intel8x0.c 92.9 KB
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/*
 *   ALSA driver for Intel ICH (i8x0) chipsets
 *
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 *	Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
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 *
 *
 *   This code also contains alpha support for SiS 735 chipsets provided
 *   by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet
 *   for SiS735, so the code is not fully functional.
 *
 *
 *   This program is free software; you can redistribute it and/or modify
 *   it under the terms of the GNU General Public License as published by
 *   the Free Software Foundation; either version 2 of the License, or
 *   (at your option) any later version.
 *
 *   This program is distributed in the hope that it will be useful,
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *   GNU General Public License for more details.
 *
 *   You should have received a copy of the GNU General Public License
 *   along with this program; if not, write to the Free Software
 *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA

 *
 */      

#include <asm/io.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
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#include <linux/module.h>
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#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/ac97_codec.h>
#include <sound/info.h>
#include <sound/initval.h>
/* for 440MX workaround */
#include <asm/pgtable.h>
#include <asm/cacheflush.h>

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#ifdef CONFIG_KVM_GUEST
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#include <linux/kvm_para.h>
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#else
#define kvm_para_available() (0)
#endif

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MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
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MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455");
MODULE_LICENSE("GPL");
MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
		"{Intel,82901AB-ICH0},"
		"{Intel,82801BA-ICH2},"
		"{Intel,82801CA-ICH3},"
		"{Intel,82801DB-ICH4},"
		"{Intel,ICH5},"
		"{Intel,ICH6},"
		"{Intel,ICH7},"
		"{Intel,6300ESB},"
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		"{Intel,ESB2},"
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		"{Intel,MX440},"
		"{SiS,SI7012},"
		"{NVidia,nForce Audio},"
		"{NVidia,nForce2 Audio},"
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		"{NVidia,nForce3 Audio},"
		"{NVidia,MCP04},"
		"{NVidia,MCP501},"
		"{NVidia,CK804},"
		"{NVidia,CK8},"
		"{NVidia,CK8S},"
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		"{AMD,AMD768},"
		"{AMD,AMD8111},"
	        "{ALI,M5455}}");

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static int index = SNDRV_DEFAULT_IDX1;	/* Index 0-MAX */
static char *id = SNDRV_DEFAULT_STR1;	/* ID for this card */
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static int ac97_clock;
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static char *ac97_quirk;
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static bool buggy_semaphore;
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static int buggy_irq = -1; /* auto-check */
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static bool xbox;
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static int spdif_aclink = -1;
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static int inside_vm = -1;
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module_param(index, int, 0444);
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MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard.");
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module_param(id, charp, 0444);
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MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard.");
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module_param(ac97_clock, int, 0444);
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MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect).");
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module_param(ac97_quirk, charp, 0444);
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MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware.");
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module_param(buggy_semaphore, bool, 0444);
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MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores.");
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module_param(buggy_irq, bint, 0444);
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MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards.");
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module_param(xbox, bool, 0444);
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MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection.");
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module_param(spdif_aclink, int, 0444);
MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link.");
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module_param(inside_vm, bint, 0444);
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MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization.");
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/* just for backward compatibility */
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static bool enable;
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module_param(enable, bool, 0444);
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static int joystick;
module_param(joystick, int, 0444);

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/*
 *  Direct registers
 */
enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };

#define ICHREG(x) ICH_REG_##x

#define DEFINE_REGSET(name,base) \
enum { \
	ICH_REG_##name##_BDBAR	= base + 0x0,	/* dword - buffer descriptor list base address */ \
	ICH_REG_##name##_CIV	= base + 0x04,	/* byte - current index value */ \
	ICH_REG_##name##_LVI	= base + 0x05,	/* byte - last valid index */ \
	ICH_REG_##name##_SR	= base + 0x06,	/* byte - status register */ \
	ICH_REG_##name##_PICB	= base + 0x08,	/* word - position in current buffer */ \
	ICH_REG_##name##_PIV	= base + 0x0a,	/* byte - prefetched index value */ \
	ICH_REG_##name##_CR	= base + 0x0b,	/* byte - control register */ \
};

/* busmaster blocks */
DEFINE_REGSET(OFF, 0);		/* offset */
DEFINE_REGSET(PI, 0x00);	/* PCM in */
DEFINE_REGSET(PO, 0x10);	/* PCM out */
DEFINE_REGSET(MC, 0x20);	/* Mic in */

/* ICH4 busmaster blocks */
DEFINE_REGSET(MC2, 0x40);	/* Mic in 2 */
DEFINE_REGSET(PI2, 0x50);	/* PCM in 2 */
DEFINE_REGSET(SP, 0x60);	/* SPDIF out */

/* values for each busmaster block */

/* LVI */
#define ICH_REG_LVI_MASK		0x1f

/* SR */
#define ICH_FIFOE			0x10	/* FIFO error */
#define ICH_BCIS			0x08	/* buffer completion interrupt status */
#define ICH_LVBCI			0x04	/* last valid buffer completion interrupt */
#define ICH_CELV			0x02	/* current equals last valid */
#define ICH_DCH				0x01	/* DMA controller halted */

/* PIV */
#define ICH_REG_PIV_MASK		0x1f	/* mask */

/* CR */
#define ICH_IOCE			0x10	/* interrupt on completion enable */
#define ICH_FEIE			0x08	/* fifo error interrupt enable */
#define ICH_LVBIE			0x04	/* last valid buffer interrupt enable */
#define ICH_RESETREGS			0x02	/* reset busmaster registers */
#define ICH_STARTBM			0x01	/* start busmaster operation */


/* global block */
#define ICH_REG_GLOB_CNT		0x2c	/* dword - global control */
#define   ICH_PCM_SPDIF_MASK	0xc0000000	/* s/pdif pcm slot mask (ICH4) */
#define   ICH_PCM_SPDIF_NONE	0x00000000	/* reserved - undefined */
#define   ICH_PCM_SPDIF_78	0x40000000	/* s/pdif pcm on slots 7&8 */
#define   ICH_PCM_SPDIF_69	0x80000000	/* s/pdif pcm on slots 6&9 */
#define   ICH_PCM_SPDIF_1011	0xc0000000	/* s/pdif pcm on slots 10&11 */
#define   ICH_PCM_20BIT		0x00400000	/* 20-bit samples (ICH4) */
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#define   ICH_PCM_246_MASK	0x00300000	/* chan mask (not all chips) */
#define   ICH_PCM_8		0x00300000      /* 8 channels (not all chips) */
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#define   ICH_PCM_6		0x00200000	/* 6 channels (not all chips) */
#define   ICH_PCM_4		0x00100000	/* 4 channels (not all chips) */
#define   ICH_PCM_2		0x00000000	/* 2 channels (stereo) */
#define   ICH_SIS_PCM_246_MASK	0x000000c0	/* 6 channels (SIS7012) */
#define   ICH_SIS_PCM_6		0x00000080	/* 6 channels (SIS7012) */
#define   ICH_SIS_PCM_4		0x00000040	/* 4 channels (SIS7012) */
#define   ICH_SIS_PCM_2		0x00000000	/* 2 channels (SIS7012) */
#define   ICH_TRIE		0x00000040	/* tertiary resume interrupt enable */
#define   ICH_SRIE		0x00000020	/* secondary resume interrupt enable */
#define   ICH_PRIE		0x00000010	/* primary resume interrupt enable */
#define   ICH_ACLINK		0x00000008	/* AClink shut off */
#define   ICH_AC97WARM		0x00000004	/* AC'97 warm reset */
#define   ICH_AC97COLD		0x00000002	/* AC'97 cold reset */
#define   ICH_GIE		0x00000001	/* GPI interrupt enable */
#define ICH_REG_GLOB_STA		0x30	/* dword - global status */
#define   ICH_TRI		0x20000000	/* ICH4: tertiary (AC_SDIN2) resume interrupt */
#define   ICH_TCR		0x10000000	/* ICH4: tertiary (AC_SDIN2) codec ready */
#define   ICH_BCS		0x08000000	/* ICH4: bit clock stopped */
#define   ICH_SPINT		0x04000000	/* ICH4: S/PDIF interrupt */
#define   ICH_P2INT		0x02000000	/* ICH4: PCM2-In interrupt */
#define   ICH_M2INT		0x01000000	/* ICH4: Mic2-In interrupt */
#define   ICH_SAMPLE_CAP	0x00c00000	/* ICH4: sample capability bits (RO) */
#define   ICH_SAMPLE_16_20	0x00400000	/* ICH4: 16- and 20-bit samples */
#define   ICH_MULTICHAN_CAP	0x00300000	/* ICH4: multi-channel capability bits (RO) */
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#define   ICH_SIS_TRI		0x00080000	/* SIS: tertiary resume irq */
#define   ICH_SIS_TCR		0x00040000	/* SIS: tertiary codec ready */
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#define   ICH_MD3		0x00020000	/* modem power down semaphore */
#define   ICH_AD3		0x00010000	/* audio power down semaphore */
#define   ICH_RCS		0x00008000	/* read completion status */
#define   ICH_BIT3		0x00004000	/* bit 3 slot 12 */
#define   ICH_BIT2		0x00002000	/* bit 2 slot 12 */
#define   ICH_BIT1		0x00001000	/* bit 1 slot 12 */
#define   ICH_SRI		0x00000800	/* secondary (AC_SDIN1) resume interrupt */
#define   ICH_PRI		0x00000400	/* primary (AC_SDIN0) resume interrupt */
#define   ICH_SCR		0x00000200	/* secondary (AC_SDIN1) codec ready */
#define   ICH_PCR		0x00000100	/* primary (AC_SDIN0) codec ready */
#define   ICH_MCINT		0x00000080	/* MIC capture interrupt */
#define   ICH_POINT		0x00000040	/* playback interrupt */
#define   ICH_PIINT		0x00000020	/* capture interrupt */
#define   ICH_NVSPINT		0x00000010	/* nforce spdif interrupt */
#define   ICH_MOINT		0x00000004	/* modem playback interrupt */
#define   ICH_MIINT		0x00000002	/* modem capture interrupt */
#define   ICH_GSCI		0x00000001	/* GPI status change interrupt */
#define ICH_REG_ACC_SEMA		0x34	/* byte - codec write semaphore */
#define   ICH_CAS		0x01		/* codec access semaphore */
#define ICH_REG_SDM		0x80
#define   ICH_DI2L_MASK		0x000000c0	/* PCM In 2, Mic In 2 data in line */
#define   ICH_DI2L_SHIFT	6
#define   ICH_DI1L_MASK		0x00000030	/* PCM In 1, Mic In 1 data in line */
#define   ICH_DI1L_SHIFT	4
#define   ICH_SE		0x00000008	/* steer enable */
#define   ICH_LDI_MASK		0x00000003	/* last codec read data input */

#define ICH_MAX_FRAGS		32		/* max hw frags */


/*
 * registers for Ali5455
 */

/* ALi 5455 busmaster blocks */
DEFINE_REGSET(AL_PI, 0x40);	/* ALi PCM in */
DEFINE_REGSET(AL_PO, 0x50);	/* Ali PCM out */
DEFINE_REGSET(AL_MC, 0x60);	/* Ali Mic in */
DEFINE_REGSET(AL_CDC_SPO, 0x70);	/* Ali Codec SPDIF out */
DEFINE_REGSET(AL_CENTER, 0x80);		/* Ali center out */
DEFINE_REGSET(AL_LFE, 0x90);		/* Ali center out */
DEFINE_REGSET(AL_CLR_SPI, 0xa0);	/* Ali Controller SPDIF in */
DEFINE_REGSET(AL_CLR_SPO, 0xb0);	/* Ali Controller SPDIF out */
DEFINE_REGSET(AL_I2S, 0xc0);	/* Ali I2S in */
DEFINE_REGSET(AL_PI2, 0xd0);	/* Ali PCM2 in */
DEFINE_REGSET(AL_MC2, 0xe0);	/* Ali Mic2 in */

enum {
	ICH_REG_ALI_SCR = 0x00,		/* System Control Register */
	ICH_REG_ALI_SSR = 0x04,		/* System Status Register  */
	ICH_REG_ALI_DMACR = 0x08,	/* DMA Control Register    */
	ICH_REG_ALI_FIFOCR1 = 0x0c,	/* FIFO Control Register 1  */
	ICH_REG_ALI_INTERFACECR = 0x10,	/* Interface Control Register */
	ICH_REG_ALI_INTERRUPTCR = 0x14,	/* Interrupt control Register */
	ICH_REG_ALI_INTERRUPTSR = 0x18,	/* Interrupt  Status Register */
	ICH_REG_ALI_FIFOCR2 = 0x1c,	/* FIFO Control Register 2   */
	ICH_REG_ALI_CPR = 0x20,		/* Command Port Register     */
	ICH_REG_ALI_CPR_ADDR = 0x22,	/* ac97 addr write */
	ICH_REG_ALI_SPR = 0x24,		/* Status Port Register      */
	ICH_REG_ALI_SPR_ADDR = 0x26,	/* ac97 addr read */
	ICH_REG_ALI_FIFOCR3 = 0x2c,	/* FIFO Control Register 3  */
	ICH_REG_ALI_TTSR = 0x30,	/* Transmit Tag Slot Register */
	ICH_REG_ALI_RTSR = 0x34,	/* Receive Tag Slot  Register */
	ICH_REG_ALI_CSPSR = 0x38,	/* Command/Status Port Status Register */
	ICH_REG_ALI_CAS = 0x3c,		/* Codec Write Semaphore Register */
	ICH_REG_ALI_HWVOL = 0xf0,	/* hardware volume control/status */
	ICH_REG_ALI_I2SCR = 0xf4,	/* I2S control/status */
	ICH_REG_ALI_SPDIFCSR = 0xf8,	/* spdif channel status register  */
	ICH_REG_ALI_SPDIFICS = 0xfc,	/* spdif interface control/status  */
};

#define ALI_CAS_SEM_BUSY	0x80000000
#define ALI_CPR_ADDR_SECONDARY	0x100
#define ALI_CPR_ADDR_READ	0x80
#define ALI_CSPSR_CODEC_READY	0x08
#define ALI_CSPSR_READ_OK	0x02
#define ALI_CSPSR_WRITE_OK	0x01

/* interrupts for the whole chip by interrupt status register finish */
 
#define ALI_INT_MICIN2		(1<<26)
#define ALI_INT_PCMIN2		(1<<25)
#define ALI_INT_I2SIN		(1<<24)
#define ALI_INT_SPDIFOUT	(1<<23)	/* controller spdif out INTERRUPT */
#define ALI_INT_SPDIFIN		(1<<22)
#define ALI_INT_LFEOUT		(1<<21)
#define ALI_INT_CENTEROUT	(1<<20)
#define ALI_INT_CODECSPDIFOUT	(1<<19)
#define ALI_INT_MICIN		(1<<18)
#define ALI_INT_PCMOUT		(1<<17)
#define ALI_INT_PCMIN		(1<<16)
#define ALI_INT_CPRAIS		(1<<7)	/* command port available */
#define ALI_INT_SPRAIS		(1<<5)	/* status port available */
#define ALI_INT_GPIO		(1<<1)
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#define ALI_INT_MASK		(ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\
				 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN)
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#define ICH_ALI_SC_RESET	(1<<31)	/* master reset */
#define ICH_ALI_SC_AC97_DBL	(1<<30)
#define ICH_ALI_SC_CODEC_SPDF	(3<<20)	/* 1=7/8, 2=6/9, 3=10/11 */
#define ICH_ALI_SC_IN_BITS	(3<<18)
#define ICH_ALI_SC_OUT_BITS	(3<<16)
#define ICH_ALI_SC_6CH_CFG	(3<<14)
#define ICH_ALI_SC_PCM_4	(1<<8)
#define ICH_ALI_SC_PCM_6	(2<<8)
#define ICH_ALI_SC_PCM_246_MASK	(3<<8)

#define ICH_ALI_SS_SEC_ID	(3<<5)
#define ICH_ALI_SS_PRI_ID	(3<<3)

#define ICH_ALI_IF_AC97SP	(1<<21)
#define ICH_ALI_IF_MC		(1<<20)
#define ICH_ALI_IF_PI		(1<<19)
#define ICH_ALI_IF_MC2		(1<<18)
#define ICH_ALI_IF_PI2		(1<<17)
#define ICH_ALI_IF_LINE_SRC	(1<<15)	/* 0/1 = slot 3/6 */
#define ICH_ALI_IF_MIC_SRC	(1<<14)	/* 0/1 = slot 3/6 */
#define ICH_ALI_IF_SPDF_SRC	(3<<12)	/* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */
#define ICH_ALI_IF_AC97_OUT	(3<<8)	/* 00 = PCM, 10 = spdif-in, 11 = i2s */
#define ICH_ALI_IF_PO_SPDF	(1<<3)
#define ICH_ALI_IF_PO		(1<<1)

/*
 *  
 */

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enum {
	ICHD_PCMIN,
	ICHD_PCMOUT,
	ICHD_MIC,
	ICHD_MIC2,
	ICHD_PCM2IN,
	ICHD_SPBAR,
	ICHD_LAST = ICHD_SPBAR
};
enum {
	NVD_PCMIN,
	NVD_PCMOUT,
	NVD_MIC,
	NVD_SPBAR,
	NVD_LAST = NVD_SPBAR
};
enum {
	ALID_PCMIN,
	ALID_PCMOUT,
	ALID_MIC,
	ALID_AC97SPDIFOUT,
	ALID_SPDIFIN,
	ALID_SPDIFOUT,
	ALID_LAST = ALID_SPDIFOUT
};
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#define get_ichdev(substream) (substream->runtime->private_data)
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struct ichdev {
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	unsigned int ichd;			/* ich device number */
	unsigned long reg_offset;		/* offset to bmaddr */
	u32 *bdbar;				/* CPU address (32bit) */
	unsigned int bdbar_addr;		/* PCI bus address (32bit) */
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	struct snd_pcm_substream *substream;
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	unsigned int physbuf;			/* physical address (32bit) */
        unsigned int size;
        unsigned int fragsize;
        unsigned int fragsize1;
        unsigned int position;
	unsigned int pos_shift;
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	unsigned int last_pos;
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        int frags;
        int lvi;
        int lvi_frag;
	int civ;
	int ack;
	int ack_reload;
	unsigned int ack_bit;
	unsigned int roff_sr;
	unsigned int roff_picb;
	unsigned int int_sta_mask;		/* interrupt status mask */
	unsigned int ali_slot;			/* ALI DMA slot */
	struct ac97_pcm *pcm;
	int pcm_open_flag;
	unsigned int page_attr_changed: 1;
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	unsigned int suspended: 1;
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};
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struct intel8x0 {
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	unsigned int device_type;

	int irq;

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	void __iomem *addr;
	void __iomem *bmaddr;
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	struct pci_dev *pci;
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	struct snd_card *card;
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	int pcm_devs;
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	struct snd_pcm *pcm[6];
	struct ichdev ichd[6];
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	unsigned multi4: 1,
		 multi6: 1,
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		 multi8 :1,
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		 dra: 1,
		 smp20bit: 1;
	unsigned in_ac97_init: 1,
		 in_sdin_init: 1;
	unsigned in_measurement: 1;	/* during ac97 clock measurement */
	unsigned fix_nocache: 1; 	/* workaround for 440MX */
	unsigned buggy_irq: 1;		/* workaround for buggy mobos */
	unsigned xbox: 1;		/* workaround for Xbox AC'97 detection */
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	unsigned buggy_semaphore: 1;	/* workaround for buggy codec semaphore */
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	unsigned inside_vm: 1;		/* enable VM optimization */
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	int spdif_idx;	/* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */
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	unsigned int sdm_saved;	/* SDM reg value */
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	struct snd_ac97_bus *ac97_bus;
	struct snd_ac97 *ac97[3];
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	unsigned int ac97_sdin[3];
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	unsigned int max_codecs, ncodecs;
	unsigned int *codec_bit;
	unsigned int codec_isr_bits;
	unsigned int codec_ready_bits;
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	spinlock_t reg_lock;
	
	u32 bdbars_count;
	struct snd_dma_buffer bdbars;
	u32 int_sta_reg;		/* interrupt status register */
	u32 int_sta_mask;		/* interrupt status mask */
};

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static DEFINE_PCI_DEVICE_TABLE(snd_intel8x0_ids) = {
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	{ PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL },	/* 82801AA */
	{ PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL },	/* 82901AB */
	{ PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL },	/* 82801BA */
	{ PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL },	/* ICH3 */
	{ PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */
	{ PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */
	{ PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */
	{ PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */
	{ PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */
	{ PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */
	{ PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL },	/* 440MX */
	{ PCI_VDEVICE(SI, 0x7012), DEVICE_SIS },	/* SI7012 */
	{ PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE },	/* NFORCE */
	{ PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE },	/* MCP04 */
	{ PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE },	/* NFORCE2 */
	{ PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE },	/* CK804 */
	{ PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE },	/* CK8 */
	{ PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE },	/* NFORCE3 */
	{ PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE },	/* CK8S */
	{ PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE },	/* MCP51 */
	{ PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL },	/* AMD8111 */
	{ PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL },	/* AMD768 */
	{ PCI_VDEVICE(AL, 0x5455), DEVICE_ALI },   /* Ali5455 */
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	{ 0, }
};

MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids);

/*
 *  Lowlevel I/O - busmaster
 */

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static inline u8 igetbyte(struct intel8x0 *chip, u32 offset)
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{
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	return ioread8(chip->bmaddr + offset);
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}

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static inline u16 igetword(struct intel8x0 *chip, u32 offset)
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{
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	return ioread16(chip->bmaddr + offset);
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}

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static inline u32 igetdword(struct intel8x0 *chip, u32 offset)
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{
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	return ioread32(chip->bmaddr + offset);
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}

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static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val)
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{
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	iowrite8(val, chip->bmaddr + offset);
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}

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static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val)
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{
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	iowrite16(val, chip->bmaddr + offset);
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}

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static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val)
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{
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	iowrite32(val, chip->bmaddr + offset);
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}

/*
 *  Lowlevel I/O - AC'97 registers
 */

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static inline u16 iagetword(struct intel8x0 *chip, u32 offset)
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{
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	return ioread16(chip->addr + offset);
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}

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static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val)
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{
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	iowrite16(val, chip->addr + offset);
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}

/*
 *  Basic I/O
 */

/*
 * access to AC97 codec via normal i/o (for ICH and SIS7012)
 */

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static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec)
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{
	int time;
	
	if (codec > 2)
		return -EIO;
	if (chip->in_sdin_init) {
		/* we don't know the ready bit assignment at the moment */
		/* so we check any */
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		codec = chip->codec_isr_bits;
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	} else {
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		codec = chip->codec_bit[chip->ac97_sdin[codec]];
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	}

	/* codec ready ? */
	if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
		return -EIO;

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	if (chip->buggy_semaphore)
		return 0; /* just ignore ... */

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	/* Anyone holding a semaphore for 1 msec should be shot... */
	time = 100;
      	do {
      		if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
      			return 0;
		udelay(10);
	} while (time--);

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	/* access to some forbidden (non existent) ac97 registers will not
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	 * reset the semaphore. So even if you don't get the semaphore, still
	 * continue the access. We don't need the semaphore anyway. */
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	snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
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			igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
	iagetword(chip, 0);	/* clear semaphore flag */
	/* I don't care about the semaphore */
	return -EBUSY;
}
 
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static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
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				     unsigned short reg,
				     unsigned short val)
{
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	struct intel8x0 *chip = ac97->private_data;
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	if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
		if (! chip->in_ac97_init)
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			snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
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	}
	iaputword(chip, reg + ac97->num * 0x80, val);
}

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static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
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					      unsigned short reg)
{
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	struct intel8x0 *chip = ac97->private_data;
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	unsigned short res;
	unsigned int tmp;

	if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) {
		if (! chip->in_ac97_init)
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			snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
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		res = 0xffff;
	} else {
		res = iagetword(chip, reg + ac97->num * 0x80);
		if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
			/* reset RCS and preserve other R/WC bits */
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			iputdword(chip, ICHREG(GLOB_STA), tmp &
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				  ~(chip->codec_ready_bits | ICH_GSCI));
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			if (! chip->in_ac97_init)
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				snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
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			res = 0xffff;
		}
	}
	return res;
}

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static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip,
						   unsigned int codec)
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{
	unsigned int tmp;

	if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) {
		iagetword(chip, codec * 0x80);
		if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
			/* reset RCS and preserve other R/WC bits */
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			iputdword(chip, ICHREG(GLOB_STA), tmp &
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				  ~(chip->codec_ready_bits | ICH_GSCI));
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		}
	}
}

/*
 * access to AC97 for Ali5455
 */
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static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask)
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{
	int count = 0;
	for (count = 0; count < 0x7f; count++) {
		int val = igetbyte(chip, ICHREG(ALI_CSPSR));
		if (val & mask)
			return 0;
	}
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	if (! chip->in_ac97_init)
		snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n");
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	return -EBUSY;
}

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static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip)
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{
	int time = 100;
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	if (chip->buggy_semaphore)
		return 0; /* just ignore ... */
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	while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY))
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		udelay(1);
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	if (! time && ! chip->in_ac97_init)
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		snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n");
	return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY);
}

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static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg)
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{
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	struct intel8x0 *chip = ac97->private_data;
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	unsigned short data = 0xffff;

	if (snd_intel8x0_ali_codec_semaphore(chip))
		goto __err;
	reg |= ALI_CPR_ADDR_READ;
	if (ac97->num)
		reg |= ALI_CPR_ADDR_SECONDARY;
	iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
	if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK))
		goto __err;
	data = igetword(chip, ICHREG(ALI_SPR));
 __err:
	return data;
}

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static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg,
					 unsigned short val)
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{
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	struct intel8x0 *chip = ac97->private_data;
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	if (snd_intel8x0_ali_codec_semaphore(chip))
		return;
	iputword(chip, ICHREG(ALI_CPR), val);
	if (ac97->num)
		reg |= ALI_CPR_ADDR_SECONDARY;
	iputword(chip, ICHREG(ALI_CPR_ADDR), reg);
	snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK);
}


/*
 * DMA I/O
 */
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static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev) 
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{
	int idx;
	u32 *bdbar = ichdev->bdbar;
	unsigned long port = ichdev->reg_offset;

	iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
	if (ichdev->size == ichdev->fragsize) {
		ichdev->ack_reload = ichdev->ack = 2;
		ichdev->fragsize1 = ichdev->fragsize >> 1;
		for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
			bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
			bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
						     ichdev->fragsize1 >> ichdev->pos_shift);
			bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
			bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
						     ichdev->fragsize1 >> ichdev->pos_shift);
		}
		ichdev->frags = 2;
	} else {
		ichdev->ack_reload = ichdev->ack = 1;
		ichdev->fragsize1 = ichdev->fragsize;
		for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
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			bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf +
						     (((idx >> 1) * ichdev->fragsize) %
						      ichdev->size));
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			bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
						     ichdev->fragsize >> ichdev->pos_shift);
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#if 0
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			printk(KERN_DEBUG "bdbar[%i] = 0x%x [0x%x]\n",
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			       idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
#endif
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		}
		ichdev->frags = ichdev->size / ichdev->fragsize;
	}
	iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
	ichdev->civ = 0;
	iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
	ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
	ichdev->position = 0;
#if 0
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	printk(KERN_DEBUG "lvi_frag = %i, frags = %i, period_size = 0x%x, "
	       "period_size1 = 0x%x\n",
	       ichdev->lvi_frag, ichdev->frags, ichdev->fragsize,
	       ichdev->fragsize1);
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#endif
	/* clear interrupts */
	iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
}

#ifdef __i386__
/*
 * Intel 82443MX running a 100MHz processor system bus has a hardware bug,
 * which aborts PCI busmaster for audio transfer.  A workaround is to set
 * the pages as non-cached.  For details, see the errata in
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 *	http://download.intel.com/design/chipsets/specupdt/24505108.pdf
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 */
static void fill_nocache(void *buf, int size, int nocache)
{
	size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
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	if (nocache)
		set_pages_uc(virt_to_page(buf), size);
	else
		set_pages_wb(virt_to_page(buf), size);
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}
#else
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#define fill_nocache(buf, size, nocache) do { ; } while (0)
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#endif

/*
 *  Interrupt handler
 */

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static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev)
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{
	unsigned long port = ichdev->reg_offset;
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	unsigned long flags;
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	int status, civ, i, step;
	int ack = 0;

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	spin_lock_irqsave(&chip->reg_lock, flags);
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	status = igetbyte(chip, port + ichdev->roff_sr);
	civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
	if (!(status & ICH_BCIS)) {
		step = 0;
	} else if (civ == ichdev->civ) {
		// snd_printd("civ same %d\n", civ);
		step = 1;
		ichdev->civ++;
		ichdev->civ &= ICH_REG_LVI_MASK;
	} else {
		step = civ - ichdev->civ;
		if (step < 0)
			step += ICH_REG_LVI_MASK + 1;
		// if (step != 1)
		//	snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
		ichdev->civ = civ;
	}

	ichdev->position += step * ichdev->fragsize1;
	if (! chip->in_measurement)
		ichdev->position %= ichdev->size;
	ichdev->lvi += step;
	ichdev->lvi &= ICH_REG_LVI_MASK;
	iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
	for (i = 0; i < step; i++) {
		ichdev->lvi_frag++;
		ichdev->lvi_frag %= ichdev->frags;
		ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1);
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#if 0
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	printk(KERN_DEBUG "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, "
	       "all = 0x%x, 0x%x\n",
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	       ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
	       ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
	       inl(port + 4), inb(port + ICH_REG_OFF_CR));
#endif
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		if (--ichdev->ack == 0) {
			ichdev->ack = ichdev->ack_reload;
			ack = 1;
		}
	}
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	spin_unlock_irqrestore(&chip->reg_lock, flags);
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	if (ack && ichdev->substream) {
		snd_pcm_period_elapsed(ichdev->substream);
	}
	iputbyte(chip, port + ichdev->roff_sr,
		 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI));
}

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static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
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{
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	struct intel8x0 *chip = dev_id;
	struct ichdev *ichdev;
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	unsigned int status;
	unsigned int i;

	status = igetdword(chip, chip->int_sta_reg);
	if (status == 0xffffffff)	/* we are not yet resumed */
		return IRQ_NONE;

	if ((status & chip->int_sta_mask) == 0) {
		if (status) {
			/* ack */
			iputdword(chip, chip->int_sta_reg, status);
			if (! chip->buggy_irq)
				status = 0;
		}
		return IRQ_RETVAL(status);
	}

	for (i = 0; i < chip->bdbars_count; i++) {
		ichdev = &chip->ichd[i];
		if (status & ichdev->int_sta_mask)
			snd_intel8x0_update(chip, ichdev);
	}

	/* ack them */
	iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
	
	return IRQ_HANDLED;
}

/*
 *  PCM part
 */

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static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
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{
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	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
	struct ichdev *ichdev = get_ichdev(substream);
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	unsigned char val = 0;
	unsigned long port = ichdev->reg_offset;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_RESUME:
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		ichdev->suspended = 0;
		/* fallthru */
	case SNDRV_PCM_TRIGGER_START:
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	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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		val = ICH_IOCE | ICH_STARTBM;
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		ichdev->last_pos = ichdev->position;
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		break;
	case SNDRV_PCM_TRIGGER_SUSPEND:
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		ichdev->suspended = 1;
		/* fallthru */
	case SNDRV_PCM_TRIGGER_STOP:
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		val = 0;
		break;
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
		val = ICH_IOCE;
		break;
	default:
		return -EINVAL;
	}
	iputbyte(chip, port + ICH_REG_OFF_CR, val);
	if (cmd == SNDRV_PCM_TRIGGER_STOP) {
		/* wait until DMA stopped */
		while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
		/* reset whole DMA things */
		iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
	}
	return 0;
}

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static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd)
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{
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	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
	struct ichdev *ichdev = get_ichdev(substream);
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	unsigned long port = ichdev->reg_offset;
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	static int fiforeg[] = {
		ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3)
	};
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	unsigned int val, fifo;

	val = igetdword(chip, ICHREG(ALI_DMACR));
	switch (cmd) {
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	case SNDRV_PCM_TRIGGER_RESUME:
		ichdev->suspended = 0;
		/* fallthru */
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	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
			/* clear FIFO for synchronization of channels */
			fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]);
			fifo &= ~(0xff << (ichdev->ali_slot % 4));  
			fifo |= 0x83 << (ichdev->ali_slot % 4); 
			iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo);
		}
		iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
		val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */
904 905
		/* start DMA */
		iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot));
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		break;
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	case SNDRV_PCM_TRIGGER_SUSPEND:
		ichdev->suspended = 1;
		/* fallthru */
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	case SNDRV_PCM_TRIGGER_STOP:
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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		/* pause */
		iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16)));
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		iputbyte(chip, port + ICH_REG_OFF_CR, 0);
		while (igetbyte(chip, port + ICH_REG_OFF_CR))
			;
		if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
			break;
		/* reset whole DMA things */
		iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
		/* clear interrupts */
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		iputbyte(chip, port + ICH_REG_OFF_SR,
			 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e);
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		iputdword(chip, ICHREG(ALI_INTERRUPTSR),
			  igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask);
		break;
	default:
		return -EINVAL;
	}
	return 0;
}

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static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
				  struct snd_pcm_hw_params *hw_params)
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{
936 937 938
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
	struct ichdev *ichdev = get_ichdev(substream);
	struct snd_pcm_runtime *runtime = substream->runtime;
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	int dbl = params_rate(hw_params) > 48000;
	int err;

	if (chip->fix_nocache && ichdev->page_attr_changed) {
		fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */
		ichdev->page_attr_changed = 0;
	}
	err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
	if (err < 0)
		return err;
	if (chip->fix_nocache) {
		if (runtime->dma_area && ! ichdev->page_attr_changed) {
			fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
			ichdev->page_attr_changed = 1;
		}
	}
	if (ichdev->pcm_open_flag) {
		snd_ac97_pcm_close(ichdev->pcm);
		ichdev->pcm_open_flag = 0;
	}
	err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params),
				params_channels(hw_params),
				ichdev->pcm->r[dbl].slots);
	if (err >= 0) {
		ichdev->pcm_open_flag = 1;
		/* Force SPDIF setting */
		if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0)
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			snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF,
					  params_rate(hw_params));
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	}
	return err;
}

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static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
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{
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	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
	struct ichdev *ichdev = get_ichdev(substream);
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	if (ichdev->pcm_open_flag) {
		snd_ac97_pcm_close(ichdev->pcm);
		ichdev->pcm_open_flag = 0;
	}
	if (chip->fix_nocache && ichdev->page_attr_changed) {
		fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0);
		ichdev->page_attr_changed = 0;
	}
	return snd_pcm_lib_free_pages(substream);
}

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static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip,
				       struct snd_pcm_runtime *runtime)
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{
	unsigned int cnt;
	int dbl = runtime->rate > 48000;
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	spin_lock_irq(&chip->reg_lock);
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	switch (chip->device_type) {
	case DEVICE_ALI:
		cnt = igetdword(chip, ICHREG(ALI_SCR));
		cnt &= ~ICH_ALI_SC_PCM_246_MASK;
		if (runtime->channels == 4 || dbl)
			cnt |= ICH_ALI_SC_PCM_4;
		else if (runtime->channels == 6)
			cnt |= ICH_ALI_SC_PCM_6;
		iputdword(chip, ICHREG(ALI_SCR), cnt);
		break;
	case DEVICE_SIS:
		cnt = igetdword(chip, ICHREG(GLOB_CNT));
		cnt &= ~ICH_SIS_PCM_246_MASK;
		if (runtime->channels == 4 || dbl)
			cnt |= ICH_SIS_PCM_4;
		else if (runtime->channels == 6)
			cnt |= ICH_SIS_PCM_6;
		iputdword(chip, ICHREG(GLOB_CNT), cnt);
		break;
	default:
		cnt = igetdword(chip, ICHREG(GLOB_CNT));
		cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT);
		if (runtime->channels == 4 || dbl)
			cnt |= ICH_PCM_4;
		else if (runtime->channels == 6)
			cnt |= ICH_PCM_6;
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		else if (runtime->channels == 8)
			cnt |= ICH_PCM_8;
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		if (chip->device_type == DEVICE_NFORCE) {
			/* reset to 2ch once to keep the 6 channel data in alignment,
			 * to start from Front Left always
			 */
			if (cnt & ICH_PCM_246_MASK) {
				iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK);
				spin_unlock_irq(&chip->reg_lock);
				msleep(50); /* grrr... */
				spin_lock_irq(&chip->reg_lock);
			}
		} else if (chip->device_type == DEVICE_INTEL_ICH4) {
			if (runtime->sample_bits > 16)
				cnt |= ICH_PCM_20BIT;
		}
		iputdword(chip, ICHREG(GLOB_CNT), cnt);
		break;
	}
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	spin_unlock_irq(&chip->reg_lock);
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}

1043
static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream)
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{
1045 1046 1047
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
	struct snd_pcm_runtime *runtime = substream->runtime;
	struct ichdev *ichdev = get_ichdev(substream);
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	ichdev->physbuf = runtime->dma_addr;
	ichdev->size = snd_pcm_lib_buffer_bytes(substream);
	ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
	if (ichdev->ichd == ICHD_PCMOUT) {
		snd_intel8x0_setup_pcm_out(chip, runtime);
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		if (chip->device_type == DEVICE_INTEL_ICH4)
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			ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1;
	}
	snd_intel8x0_setup_periods(chip, ichdev);
	return 0;
}

1061
static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
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{
1063 1064
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
	struct ichdev *ichdev = get_ichdev(substream);
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	size_t ptr1, ptr;
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	int civ, timeout = 10;
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	unsigned int position;

	spin_lock(&chip->reg_lock);
	do {
		civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
		ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
		position = ichdev->position;
		if (ptr1 == 0) {
			udelay(10);
			continue;
		}
1078 1079
		if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV))
			continue;
1080 1081 1082 1083 1084 1085 1086

		/* IO read operation is very expensive inside virtual machine
		 * as it is emulated. The probability that subsequent PICB read
		 * will return different result is high enough to loop till
		 * timeout here.
		 * Same CIV is strict enough condition to be sure that PICB
		 * is valid inside VM on emulated card. */
1087 1088 1089
		if (chip->inside_vm)
			break;
		if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
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			break;
	} while (timeout--);
1092
	ptr = ichdev->last_pos;
1093 1094 1095 1096
	if (ptr1 != 0) {
		ptr1 <<= ichdev->pos_shift;
		ptr = ichdev->fragsize1 - ptr1;
		ptr += position;
1097 1098 1099 1100 1101 1102 1103 1104 1105 1106
		if (ptr < ichdev->last_pos) {
			unsigned int pos_base, last_base;
			pos_base = position / ichdev->fragsize1;
			last_base = ichdev->last_pos / ichdev->fragsize1;
			/* another sanity check; ptr1 can go back to full
			 * before the base position is updated
			 */
			if (pos_base == last_base)
				ptr = ichdev->last_pos;
		}
1107
	}
1108
	ichdev->last_pos = ptr;
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	spin_unlock(&chip->reg_lock);
	if (ptr >= ichdev->size)
		return 0;
	return bytes_to_frames(substream->runtime, ptr);
}

1115
static struct snd_pcm_hardware snd_intel8x0_stream =
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{
	.info =			(SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
				 SNDRV_PCM_INFO_MMAP_VALID |
				 SNDRV_PCM_INFO_PAUSE |
				 SNDRV_PCM_INFO_RESUME),
	.formats =		SNDRV_PCM_FMTBIT_S16_LE,
	.rates =		SNDRV_PCM_RATE_48000,
	.rate_min =		48000,
	.rate_max =		48000,
	.channels_min =		2,
	.channels_max =		2,
	.buffer_bytes_max =	128 * 1024,
	.period_bytes_min =	32,
	.period_bytes_max =	128 * 1024,
	.periods_min =		1,
	.periods_max =		1024,
	.fifo_size =		0,
};

static unsigned int channels4[] = {
	2, 4,
};

1140
static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = {
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	.count = ARRAY_SIZE(channels4),
	.list = channels4,
	.mask = 0,
};

static unsigned int channels6[] = {
	2, 4, 6,
};

1150
static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = {
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	.count = ARRAY_SIZE(channels6),
	.list = channels6,
	.mask = 0,
};

1156 1157 1158 1159 1160 1161 1162 1163 1164 1165
static unsigned int channels8[] = {
	2, 4, 6, 8,
};

static struct snd_pcm_hw_constraint_list hw_constraints_channels8 = {
	.count = ARRAY_SIZE(channels8),
	.list = channels8,
	.mask = 0,
};

1166
static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
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{
1168 1169
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
	struct snd_pcm_runtime *runtime = substream->runtime;
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	int err;

	ichdev->substream = substream;
	runtime->hw = snd_intel8x0_stream;
	runtime->hw.rates = ichdev->pcm->rates;
	snd_pcm_limit_hw_rates(runtime);
	if (chip->device_type == DEVICE_SIS) {
		runtime->hw.buffer_bytes_max = 64*1024;
		runtime->hw.period_bytes_max = 64*1024;
	}
	if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
		return err;
	runtime->private_data = ichdev;
	return 0;
}

1186
static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream)
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{
1188 1189
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
	struct snd_pcm_runtime *runtime = substream->runtime;
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	int err;

	err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]);
	if (err < 0)
		return err;

1196 1197 1198 1199 1200 1201
	if (chip->multi8) {
		runtime->hw.channels_max = 8;
		snd_pcm_hw_constraint_list(runtime, 0,
						SNDRV_PCM_HW_PARAM_CHANNELS,
						&hw_constraints_channels8);
	} else if (chip->multi6) {
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		runtime->hw.channels_max = 6;
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		snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
					   &hw_constraints_channels6);
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	} else if (chip->multi4) {
		runtime->hw.channels_max = 4;
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		snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
					   &hw_constraints_channels4);
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	}
	if (chip->dra) {
		snd_ac97_pcm_double_rate_rules(runtime);
	}
	if (chip->smp20bit) {
		runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE;
		snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20);
	}
	return 0;
}

1220
static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream)
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{
1222
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
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	chip->ichd[ICHD_PCMOUT].substream = NULL;
	return 0;
}

1228
static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream)
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{
1230
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
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	return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]);
}

1235
static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream)
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{
1237
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
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	chip->ichd[ICHD_PCMIN].substream = NULL;
	return 0;
}

1243
static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream)
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{
1245
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
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	return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]);
}

1250
static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream)
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{
1252
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
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	chip->ichd[ICHD_MIC].substream = NULL;
	return 0;
}

1258
static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream)
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{
1260
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
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	return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]);
}

1265
static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream)
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{
1267
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
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	chip->ichd[ICHD_MIC2].substream = NULL;
	return 0;
}

1273
static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream)
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{
1275
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
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	return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]);
}

1280
static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream)
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{
1282
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
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	chip->ichd[ICHD_PCM2IN].substream = NULL;
	return 0;
}

1288
static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream)
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{
1290
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
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	int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;

	return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]);
}

1296
static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream)
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{
1298
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
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	int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR;

	chip->ichd[idx].substream = NULL;
	return 0;
}

1305
static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream)
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{
1307
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
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	unsigned int val;

	spin_lock_irq(&chip->reg_lock);
	val = igetdword(chip, ICHREG(ALI_INTERFACECR));
	val |= ICH_ALI_IF_AC97SP;
	iputdword(chip, ICHREG(ALI_INTERFACECR), val);
	/* also needs to set ALI_SC_CODEC_SPDF correctly */
	spin_unlock_irq(&chip->reg_lock);

	return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]);
}

1320
static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream)
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{
1322
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
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	unsigned int val;

	chip->ichd[ALID_AC97SPDIFOUT].substream = NULL;
	spin_lock_irq(&chip->reg_lock);
	val = igetdword(chip, ICHREG(ALI_INTERFACECR));
	val &= ~ICH_ALI_IF_AC97SP;
	iputdword(chip, ICHREG(ALI_INTERFACECR), val);
	spin_unlock_irq(&chip->reg_lock);

	return 0;
}

1335
#if 0 // NYI
1336
static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream)
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{
1338
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
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	return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]);
}

1343
static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream)
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{
1345
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
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	chip->ichd[ALID_SPDIFIN].substream = NULL;
	return 0;
}

1351
static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream)
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{
1353
	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
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	return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]);
}

1358
static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream)
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{
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	struct intel8x0 *chip = snd_pcm_substream_chip(substream);
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	chip->ichd[ALID_SPDIFOUT].substream = NULL;
	return 0;
}
#endif

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static struct snd_pcm_ops snd_intel8x0_playback_ops = {
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	.open =		snd_intel8x0_playback_open,
	.close =	snd_intel8x0_playback_close,
	.ioctl =	snd_pcm_lib_ioctl,
	.hw_params =	snd_intel8x0_hw_params,
	.hw_free =	snd_intel8x0_hw_free,
	.prepare =	snd_intel8x0_pcm_prepare,
	.trigger =	snd_intel8x0_pcm_trigger,
	.pointer =	snd_intel8x0_pcm_pointer,
};

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static struct snd_pcm_ops snd_intel8x0_capture_ops = {
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	.open =		snd_intel8x0_capture_open,
	.close =	snd_intel8x0_capture_close,
	.ioctl =	snd_pcm_lib_ioctl,
	.hw_params =	snd_intel8x0_hw_params,
	.hw_free =	snd_intel8x0_hw_free,
	.prepare =	snd_intel8x0_pcm_prepare,
	.trigger =	snd_intel8x0_pcm_trigger,
	.pointer =	snd_intel8x0_pcm_pointer,
};

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static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = {
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	.open =		snd_intel8x0_mic_open,
	.close =	snd_intel8x0_mic_close,
	.ioctl =	snd_pcm_lib_ioctl,
	.hw_params =	snd_intel8x0_hw_params,
	.hw_free =	snd_intel8x0_hw_free,
	.prepare =	snd_intel8x0_pcm_prepare,
	.trigger =	snd_intel8x0_pcm_trigger,
	.pointer =	snd_intel8x0_pcm_pointer,
};

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static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = {
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	.open =		snd_intel8x0_mic2_open,
	.close =	snd_intel8x0_mic2_close,
	.ioctl =	snd_pcm_lib_ioctl,
	.hw_params =	snd_intel8x0_hw_params,
	.hw_free =	snd_intel8x0_hw_free,
	.prepare =	snd_intel8x0_pcm_prepare,
	.trigger =	snd_intel8x0_pcm_trigger,
	.pointer =	snd_intel8x0_pcm_pointer,
};

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static struct snd_pcm_ops snd_intel8x0_capture2_ops = {
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	.open =		snd_intel8x0_capture2_open,
	.close =	snd_intel8x0_capture2_close,
	.ioctl =	snd_pcm_lib_ioctl,
	.hw_params =	snd_intel8x0_hw_params,
	.hw_free =	snd_intel8x0_hw_free,
	.prepare =	snd_intel8x0_pcm_prepare,
	.trigger =	snd_intel8x0_pcm_trigger,
	.pointer =	snd_intel8x0_pcm_pointer,
};

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static struct snd_pcm_ops snd_intel8x0_spdif_ops = {
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	.open =		snd_intel8x0_spdif_open,
	.close =	snd_intel8x0_spdif_close,
	.ioctl =	snd_pcm_lib_ioctl,
	.hw_params =	snd_intel8x0_hw_params,
	.hw_free =	snd_intel8x0_hw_free,
	.prepare =	snd_intel8x0_pcm_prepare,
	.trigger =	snd_intel8x0_pcm_trigger,
	.pointer =	snd_intel8x0_pcm_pointer,
};

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static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = {
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	.open =		snd_intel8x0_playback_open,
	.close =	snd_intel8x0_playback_close,
	.ioctl =	snd_pcm_lib_ioctl,
	.hw_params =	snd_intel8x0_hw_params,
	.hw_free =	snd_intel8x0_hw_free,
	.prepare =	snd_intel8x0_pcm_prepare,
	.trigger =	snd_intel8x0_ali_trigger,
	.pointer =	snd_intel8x0_pcm_pointer,
};

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static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = {
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	.open =		snd_intel8x0_capture_open,
	.close =	snd_intel8x0_capture_close,
	.ioctl =	snd_pcm_lib_ioctl,
	.hw_params =	snd_intel8x0_hw_params,
	.hw_free =	snd_intel8x0_hw_free,
	.prepare =	snd_intel8x0_pcm_prepare,
	.trigger =	snd_intel8x0_ali_trigger,
	.pointer =	snd_intel8x0_pcm_pointer,
};

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static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = {
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	.open =		snd_intel8x0_mic_open,
	.close =	snd_intel8x0_mic_close,
	.ioctl =	snd_pcm_lib_ioctl,
	.hw_params =	snd_intel8x0_hw_params,
	.hw_free =	snd_intel8x0_hw_free,
	.prepare =	snd_intel8x0_pcm_prepare,
	.trigger =	snd_intel8x0_ali_trigger,
	.pointer =	snd_intel8x0_pcm_pointer,
};

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static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = {
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	.open =		snd_intel8x0_ali_ac97spdifout_open,
	.close =	snd_intel8x0_ali_ac97spdifout_close,
	.ioctl =	snd_pcm_lib_ioctl,
	.hw_params =	snd_intel8x0_hw_params,
	.hw_free =	snd_intel8x0_hw_free,
	.prepare =	snd_intel8x0_pcm_prepare,
	.trigger =	snd_intel8x0_ali_trigger,
	.pointer =	snd_intel8x0_pcm_pointer,
};

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#if 0 // NYI
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static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = {
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	.open =		snd_intel8x0_ali_spdifin_open,
	.close =	snd_intel8x0_ali_spdifin_close,
	.ioctl =	snd_pcm_lib_ioctl,
	.hw_params =	snd_intel8x0_hw_params,
	.hw_free =	snd_intel8x0_hw_free,
	.prepare =	snd_intel8x0_pcm_prepare,
	.trigger =	snd_intel8x0_pcm_trigger,
	.pointer =	snd_intel8x0_pcm_pointer,
};

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static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = {
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	.open =		snd_intel8x0_ali_spdifout_open,
	.close =	snd_intel8x0_ali_spdifout_close,
	.ioctl =	snd_pcm_lib_ioctl,
	.hw_params =	snd_intel8x0_hw_params,
	.hw_free =	snd_intel8x0_hw_free,
	.prepare =	snd_intel8x0_pcm_prepare,
	.trigger =	snd_intel8x0_pcm_trigger,
	.pointer =	snd_intel8x0_pcm_pointer,
};
#endif // NYI

struct ich_pcm_table {
	char *suffix;
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	struct snd_pcm_ops *playback_ops;
	struct snd_pcm_ops *capture_ops;
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	size_t prealloc_size;
	size_t prealloc_max_size;
	int ac97_idx;
};

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static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device,
				       struct ich_pcm_table *rec)
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{
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	struct snd_pcm *pcm;
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	int err;
	char name[32];

	if (rec->suffix)
		sprintf(name, "Intel ICH - %s", rec->suffix);
	else
		strcpy(name, "Intel ICH");
	err = snd_pcm_new(chip->card, name, device,
			  rec->playback_ops ? 1 : 0,
			  rec->capture_ops ? 1 : 0, &pcm);
	if (err < 0)
		return err;

	if (rec->playback_ops)
		snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
	if (rec->capture_ops)
		snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);

	pcm->private_data = chip;
	pcm->info_flags = 0;
	if (rec->suffix)
		sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
	else
		strcpy(pcm->name, chip->card->shortname);
	chip->pcm[device] = pcm;

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	snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
					      snd_dma_pci_data(chip->pci),
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					      rec->prealloc_size, rec->prealloc_max_size);

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	if (rec->ac97_idx == ICHD_PCMOUT && rec->playback_ops) {
		struct snd_pcm_chmap *chmap;
		int chs = 2;
		if (rec->ac97_idx == ICHD_PCMOUT) {
			if (chip->multi8)
				chs = 8;
			else if (chip->multi6)
				chs = 6;
			else if (chip->multi4)
				chs = 4;
		}
		err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
					     snd_pcm_alt_chmaps, chs, 0,
					     &chmap);
		if (err < 0)
			return err;
		chmap->channel_mask = SND_PCM_CHMAP_MASK_2468;
		chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap;
	}

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	return 0;
}

static struct ich_pcm_table intel_pcms[] __devinitdata = {
	{
		.playback_ops = &snd_intel8x0_playback_ops,
		.capture_ops = &snd_intel8x0_capture_ops,
		.prealloc_size = 64 * 1024,
		.prealloc_max_size = 128 * 1024,
	},
	{
		.suffix = "MIC ADC",
		.capture_ops = &snd_intel8x0_capture_mic_ops,
		.prealloc_size = 0,
		.prealloc_max_size = 128 * 1024,
		.ac97_idx = ICHD_MIC,
	},
	{
		.suffix = "MIC2 ADC",
		.capture_ops = &snd_intel8x0_capture_mic2_ops,
		.prealloc_size = 0,
		.prealloc_max_size = 128 * 1024,
		.ac97_idx = ICHD_MIC2,
	},
	{
		.suffix = "ADC2",
		.capture_ops = &snd_intel8x0_capture2_ops,
		.prealloc_size = 0,
		.prealloc_max_size = 128 * 1024,
		.ac97_idx = ICHD_PCM2IN,
	},
	{
		.suffix = "IEC958",
		.playback_ops = &snd_intel8x0_spdif_ops,
		.prealloc_size = 64 * 1024,
		.prealloc_max_size = 128 * 1024,
		.ac97_idx = ICHD_SPBAR,
	},
};

static struct ich_pcm_table nforce_pcms[] __devinitdata = {
	{
		.playback_ops = &snd_intel8x0_playback_ops,
		.capture_ops = &snd_intel8x0_capture_ops,
		.prealloc_size = 64 * 1024,
		.prealloc_max_size = 128 * 1024,
	},
	{
		.suffix = "MIC ADC",
		.capture_ops = &snd_intel8x0_capture_mic_ops,
		.prealloc_size = 0,
		.prealloc_max_size = 128 * 1024,
		.ac97_idx = NVD_MIC,
	},
	{
		.suffix = "IEC958",
		.playback_ops = &snd_intel8x0_spdif_ops,
		.prealloc_size = 64 * 1024,
		.prealloc_max_size = 128 * 1024,
		.ac97_idx = NVD_SPBAR,
	},
};

static struct ich_pcm_table ali_pcms[] __devinitdata = {
	{
		.playback_ops = &snd_intel8x0_ali_playback_ops,
		.capture_ops = &snd_intel8x0_ali_capture_ops,
		.prealloc_size = 64 * 1024,
		.prealloc_max_size = 128 * 1024,
	},
	{
		.suffix = "MIC ADC",
		.capture_ops = &snd_intel8x0_ali_capture_mic_ops,
		.prealloc_size = 0,
		.prealloc_max_size = 128 * 1024,
		.ac97_idx = ALID_MIC,
	},
	{
		.suffix = "IEC958",
		.playback_ops = &snd_intel8x0_ali_ac97spdifout_ops,
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		/* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */
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		.prealloc_size = 64 * 1024,
		.prealloc_max_size = 128 * 1024,
		.ac97_idx = ALID_AC97SPDIFOUT,
	},
#if 0 // NYI
	{
		.suffix = "HW IEC958",
		.playback_ops = &snd_intel8x0_ali_spdifout_ops,
		.prealloc_size = 64 * 1024,
		.prealloc_max_size = 128 * 1024,
	},
#endif
};

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static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip)
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{
	int i, tblsize, device, err;
	struct ich_pcm_table *tbl, *rec;

	switch (chip->device_type) {
	case DEVICE_INTEL_ICH4:
		tbl = intel_pcms;
		tblsize = ARRAY_SIZE(intel_pcms);
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		if (spdif_aclink)
			tblsize--;
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		break;
	case DEVICE_NFORCE:
		tbl = nforce_pcms;
		tblsize = ARRAY_SIZE(nforce_pcms);
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		if (spdif_aclink)
			tblsize--;
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		break;
	case DEVICE_ALI:
		tbl = ali_pcms;
		tblsize = ARRAY_SIZE(ali_pcms);
		break;
	default:
		tbl = intel_pcms;
		tblsize = 2;
		break;
	}

	device = 0;
	for (i = 0; i < tblsize; i++) {
		rec = tbl + i;
		if (i > 0 && rec->ac97_idx) {
			/* activate PCM only when associated AC'97 codec */
			if (! chip->ichd[rec->ac97_idx].pcm)
				continue;
		}
		err = snd_intel8x0_pcm1(chip, device, rec);
		if (err < 0)
			return err;
		device++;
	}

	chip->pcm_devs = device;
	return 0;
}
	

/*
 *  Mixer part
 */

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static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
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{
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	struct intel8x0 *chip = bus->private_data;
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	chip->ac97_bus = NULL;
}

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static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
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{
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	struct intel8x0 *chip = ac97->private_data;
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	chip->ac97[ac97->num] = NULL;
}

static struct ac97_pcm ac97_pcm_defs[] __devinitdata = {
	/* front PCM */
	{
		.exclusive = 1,
		.r = {	{
				.slots = (1 << AC97_SLOT_PCM_LEFT) |
					 (1 << AC97_SLOT_PCM_RIGHT) |
					 (1 << AC97_SLOT_PCM_CENTER) |
					 (1 << AC97_SLOT_PCM_SLEFT) |
					 (1 << AC97_SLOT_PCM_SRIGHT) |
					 (1 << AC97_SLOT_LFE)
			},
			{
				.slots = (1 << AC97_SLOT_PCM_LEFT) |
					 (1 << AC97_SLOT_PCM_RIGHT) |
					 (1 << AC97_SLOT_PCM_LEFT_0) |
					 (1 << AC97_SLOT_PCM_RIGHT_0)
			}
		}
	},
	/* PCM IN #1 */
	{
		.stream = 1,
		.exclusive = 1,
		.r = {	{
				.slots = (1 << AC97_SLOT_PCM_LEFT) |
					 (1 << AC97_SLOT_PCM_RIGHT)
			}
		}
	},
	/* MIC IN #1 */
	{
		.stream = 1,
		.exclusive = 1,
		.r = {	{
				.slots = (1 << AC97_SLOT_MIC)
			}
		}
	},
	/* S/PDIF PCM */
	{
		.exclusive = 1,
		.spdif = 1,
		.r = {	{
				.slots = (1 << AC97_SLOT_SPDIF_LEFT2) |
					 (1 << AC97_SLOT_SPDIF_RIGHT2)
			}
		}
	},
	/* PCM IN #2 */
	{
		.stream = 1,
		.exclusive = 1,
		.r = {	{
				.slots = (1 << AC97_SLOT_PCM_LEFT) |
					 (1 << AC97_SLOT_PCM_RIGHT)
			}
		}
	},
	/* MIC IN #2 */
	{
		.stream = 1,
		.exclusive = 1,
		.r = {	{
				.slots = (1 << AC97_SLOT_MIC)
			}
		}
	},
};

static struct ac97_quirk ac97_quirks[] __devinitdata = {
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        {
		.subvendor = 0x0e11,
		.subdevice = 0x000e,
		.name = "Compaq Deskpro EN",	/* AD1885 */
		.type = AC97_TUNE_HP_ONLY
        },
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	{
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		.subvendor = 0x0e11,
		.subdevice = 0x008a,
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		.name = "Compaq Evo W4000",	/* AD1885 */
		.type = AC97_TUNE_HP_ONLY
	},
	{
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		.subvendor = 0x0e11,
		.subdevice = 0x00b8,
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		.name = "Compaq Evo D510C",
		.type = AC97_TUNE_HP_ONLY
	},
        {
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		.subvendor = 0x0e11,
		.subdevice = 0x0860,
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		.name = "HP/Compaq nx7010",
		.type = AC97_TUNE_MUTE_LED
        },
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	{
		.subvendor = 0x1014,
		.subdevice = 0x0534,
		.name = "ThinkPad X31",
		.type = AC97_TUNE_INV_EAPD
	},
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	{
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		.subvendor = 0x1014,
		.subdevice = 0x1f00,
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		.name = "MS-9128",
		.type = AC97_TUNE_ALC_JACK
	},
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	{
		.subvendor = 0x1014,
		.subdevice = 0x0267,
		.name = "IBM NetVista A30p",	/* AD1981B */
		.type = AC97_TUNE_HP_ONLY
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	},
	{
		.subvendor = 0x1025,
		.subdevice = 0x0082,
		.name = "Acer Travelmate 2310",
		.type = AC97_TUNE_HP_ONLY
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	},
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	{
		.subvendor = 0x1025,
		.subdevice = 0x0083,
		.name = "Acer Aspire 3003LCi",
		.type = AC97_TUNE_HP_ONLY
	},
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	{
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		.subvendor = 0x1028,
		.subdevice = 0x00d8,
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		.name = "Dell Precision 530",	/* AD1885 */
		.type = AC97_TUNE_HP_ONLY
	},
	{
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		.subvendor = 0x1028,
		.subdevice = 0x010d,
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		.name = "Dell",	/* which model?  AD1885 */
		.type = AC97_TUNE_HP_ONLY
	},
	{
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		.subvendor = 0x1028,
		.subdevice = 0x0126,
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		.name = "Dell Optiplex GX260",	/* AD1981A */
		.type = AC97_TUNE_HP_ONLY
	},
	{
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		.subvendor = 0x1028,
		.subdevice = 0x012c,
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		.name = "Dell Precision 650",	/* AD1981A */
		.type = AC97_TUNE_HP_ONLY
	},
	{
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		.subvendor = 0x1028,
		.subdevice = 0x012d,
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		.name = "Dell Precision 450",	/* AD1981B*/
		.type = AC97_TUNE_HP_ONLY
	},
	{
1878 1879
		.subvendor = 0x1028,
		.subdevice = 0x0147,
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1880 1881 1882
		.name = "Dell",	/* which model?  AD1981B*/
		.type = AC97_TUNE_HP_ONLY
	},
1883 1884 1885 1886 1887 1888
	{
		.subvendor = 0x1028,
		.subdevice = 0x0151,
		.name = "Dell Optiplex GX270",  /* AD1981B */
		.type = AC97_TUNE_HP_ONLY
	},
1889 1890 1891 1892 1893 1894
	{
		.subvendor = 0x1028,
		.subdevice = 0x014e,
		.name = "Dell D800", /* STAC9750/51 */
		.type = AC97_TUNE_HP_ONLY
	},
L
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1895
	{
1896 1897
		.subvendor = 0x1028,
		.subdevice = 0x0163,
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1898 1899 1900
		.name = "Dell Unknown",	/* STAC9750/51 */
		.type = AC97_TUNE_HP_ONLY
	},
1901 1902 1903 1904 1905
	{
		.subvendor = 0x1028,
		.subdevice = 0x016a,
		.name = "Dell Inspiron 8600",	/* STAC9750/51 */
		.type = AC97_TUNE_HP_ONLY
1906 1907 1908 1909 1910 1911
	},
	{
		.subvendor = 0x1028,
		.subdevice = 0x0182,
		.name = "Dell Latitude D610",	/* STAC9750/51 */
		.type = AC97_TUNE_HP_ONLY
1912
	},
1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924
	{
		.subvendor = 0x1028,
		.subdevice = 0x0186,
		.name = "Dell Latitude D810", /* cf. Malone #41015 */
		.type = AC97_TUNE_HP_MUTE_LED
	},
	{
		.subvendor = 0x1028,
		.subdevice = 0x0188,
		.name = "Dell Inspiron 6000",
		.type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */
	},
1925 1926 1927 1928 1929 1930
	{
		.subvendor = 0x1028,
		.subdevice = 0x0189,
		.name = "Dell Inspiron 9300",
		.type = AC97_TUNE_HP_MUTE_LED
	},
1931 1932 1933 1934 1935 1936
	{
		.subvendor = 0x1028,
		.subdevice = 0x0191,
		.name = "Dell Inspiron 8600",
		.type = AC97_TUNE_HP_ONLY
	},
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1937
	{
1938 1939
		.subvendor = 0x103c,
		.subdevice = 0x006d,
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1940 1941 1942 1943
		.name = "HP zv5000",
		.type = AC97_TUNE_MUTE_LED	/*AD1981B*/
	},
	{	/* FIXME: which codec? */
1944 1945
		.subvendor = 0x103c,
		.subdevice = 0x00c3,
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1946 1947 1948 1949
		.name = "HP xw6000",
		.type = AC97_TUNE_HP_ONLY
	},
	{
1950 1951
		.subvendor = 0x103c,
		.subdevice = 0x088c,
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1952
		.name = "HP nc8000",
1953
		.type = AC97_TUNE_HP_MUTE_LED
L
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1954 1955
	},
	{
1956 1957
		.subvendor = 0x103c,
		.subdevice = 0x0890,
L
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1958 1959 1960 1961
		.name = "HP nc6000",
		.type = AC97_TUNE_MUTE_LED
	},
	{
1962 1963
		.subvendor = 0x103c,
		.subdevice = 0x129d,
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1964 1965 1966
		.name = "HP xw8000",
		.type = AC97_TUNE_HP_ONLY
	},
1967 1968 1969 1970 1971 1972 1973 1974 1975
	{
		.subvendor = 0x103c,
		.subdevice = 0x0938,
		.name = "HP nc4200",
		.type = AC97_TUNE_HP_MUTE_LED
	},
	{
		.subvendor = 0x103c,
		.subdevice = 0x099c,
1976
		.name = "HP nx6110/nc6120",
1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990
		.type = AC97_TUNE_HP_MUTE_LED
	},
	{
		.subvendor = 0x103c,
		.subdevice = 0x0944,
		.name = "HP nc6220",
		.type = AC97_TUNE_HP_MUTE_LED
	},
	{
		.subvendor = 0x103c,
		.subdevice = 0x0934,
		.name = "HP nc8220",
		.type = AC97_TUNE_HP_MUTE_LED
	},
L
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1991
	{
1992 1993
		.subvendor = 0x103c,
		.subdevice = 0x12f1,
L
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1994 1995 1996 1997
		.name = "HP xw8200",	/* AD1981B*/
		.type = AC97_TUNE_HP_ONLY
	},
	{
1998 1999
		.subvendor = 0x103c,
		.subdevice = 0x12f2,
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2000 2001 2002 2003
		.name = "HP xw6200",
		.type = AC97_TUNE_HP_ONLY
	},
	{
2004 2005
		.subvendor = 0x103c,
		.subdevice = 0x3008,
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2006 2007 2008
		.name = "HP xw4200",	/* AD1981B*/
		.type = AC97_TUNE_HP_ONLY
	},
2009 2010 2011 2012 2013 2014
	{
		.subvendor = 0x104d,
		.subdevice = 0x8144,
		.name = "Sony",
		.type = AC97_TUNE_INV_EAPD
	},
L
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2015
	{
2016 2017
		.subvendor = 0x104d,
		.subdevice = 0x8197,
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2018 2019 2020
		.name = "Sony S1XP",
		.type = AC97_TUNE_INV_EAPD
	},
2021 2022 2023 2024 2025 2026
	{
		.subvendor = 0x104d,
		.subdevice = 0x81c0,
		.name = "Sony VAIO VGN-T350P", /*AD1981B*/
		.type = AC97_TUNE_INV_EAPD
	},
2027 2028 2029 2030 2031 2032
	{
		.subvendor = 0x104d,
		.subdevice = 0x81c5,
		.name = "Sony VAIO VGN-B1VP", /*AD1981B*/
		.type = AC97_TUNE_INV_EAPD
	},
L
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2033
 	{
2034 2035
		.subvendor = 0x1043,
		.subdevice = 0x80f3,
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2036 2037 2038 2039
		.name = "ASUS ICH5/AD1985",
		.type = AC97_TUNE_AD_SHARING
	},
	{
2040 2041
		.subvendor = 0x10cf,
		.subdevice = 0x11c3,
L
Linus Torvalds 已提交
2042 2043 2044
		.name = "Fujitsu-Siemens E4010",
		.type = AC97_TUNE_HP_ONLY
	},
T
Takashi Iwai 已提交
2045 2046 2047 2048 2049 2050
	{
		.subvendor = 0x10cf,
		.subdevice = 0x1225,
		.name = "Fujitsu-Siemens T3010",
		.type = AC97_TUNE_HP_ONLY
	},
L
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2051
	{
2052 2053
		.subvendor = 0x10cf,
		.subdevice = 0x1253,
L
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2054 2055 2056
		.name = "Fujitsu S6210",	/* STAC9750/51 */
		.type = AC97_TUNE_HP_ONLY
	},
2057 2058 2059 2060 2061 2062
	{
		.subvendor = 0x10cf,
		.subdevice = 0x127d,
		.name = "Fujitsu Lifebook P7010",
		.type = AC97_TUNE_HP_ONLY
	},
2063 2064 2065 2066 2067 2068
	{
		.subvendor = 0x10cf,
		.subdevice = 0x127e,
		.name = "Fujitsu Lifebook C1211D",
		.type = AC97_TUNE_HP_ONLY
	},
2069 2070 2071 2072 2073 2074
	{
		.subvendor = 0x10cf,
		.subdevice = 0x12ec,
		.name = "Fujitsu-Siemens 4010",
		.type = AC97_TUNE_HP_ONLY
	},
2075 2076 2077 2078 2079 2080
	{
		.subvendor = 0x10cf,
		.subdevice = 0x12f2,
		.name = "Fujitsu-Siemens Celsius H320",
		.type = AC97_TUNE_SWAP_HP
	},
L
Linus Torvalds 已提交
2081
	{
2082 2083
		.subvendor = 0x10f1,
		.subdevice = 0x2665,
L
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2084 2085 2086 2087
		.name = "Fujitsu-Siemens Celsius",	/* AD1981? */
		.type = AC97_TUNE_HP_ONLY
	},
	{
2088 2089
		.subvendor = 0x10f1,
		.subdevice = 0x2885,
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2090 2091 2092
		.name = "AMD64 Mobo",	/* ALC650 */
		.type = AC97_TUNE_HP_ONLY
	},
2093 2094 2095 2096 2097 2098
	{
		.subvendor = 0x10f1,
		.subdevice = 0x2895,
		.name = "Tyan Thunder K8WE",
		.type = AC97_TUNE_HP_ONLY
	},
2099 2100 2101 2102 2103 2104
	{
		.subvendor = 0x10f7,
		.subdevice = 0x834c,
		.name = "Panasonic CF-R4",
		.type = AC97_TUNE_HP_ONLY,
	},
L
Linus Torvalds 已提交
2105
	{
2106 2107
		.subvendor = 0x110a,
		.subdevice = 0x0056,
L
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2108 2109 2110 2111
		.name = "Fujitsu-Siemens Scenic",	/* AD1981? */
		.type = AC97_TUNE_HP_ONLY
	},
	{
2112 2113
		.subvendor = 0x11d4,
		.subdevice = 0x5375,
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2114 2115 2116 2117
		.name = "ADI AD1985 (discrete)",
		.type = AC97_TUNE_HP_ONLY
	},
	{
2118 2119
		.subvendor = 0x1462,
		.subdevice = 0x5470,
L
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2120 2121 2122
		.name = "MSI P4 ATX 645 Ultra",
		.type = AC97_TUNE_HP_ONLY
	},
2123 2124 2125 2126 2127 2128
	{
		.subvendor = 0x161f,
		.subdevice = 0x202f,
		.name = "Gateway M520",
		.type = AC97_TUNE_INV_EAPD
	},
2129 2130 2131 2132 2133 2134
	{
		.subvendor = 0x161f,
		.subdevice = 0x203a,
		.name = "Gateway 4525GZ",		/* AD1981B */
		.type = AC97_TUNE_INV_EAPD
	},
L
Linus Torvalds 已提交
2135
	{
2136 2137
		.subvendor = 0x1734,
		.subdevice = 0x0088,
L
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2138 2139 2140 2141
		.name = "Fujitsu-Siemens D1522",	/* AD1981 */
		.type = AC97_TUNE_HP_ONLY
	},
	{
2142 2143
		.subvendor = 0x8086,
		.subdevice = 0x2000,
L
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2144 2145 2146 2147 2148
		.mask = 0xfff0,
		.name = "Intel ICH5/AD1985",
		.type = AC97_TUNE_AD_SHARING
	},
	{
2149 2150
		.subvendor = 0x8086,
		.subdevice = 0x4000,
L
Linus Torvalds 已提交
2151 2152 2153 2154 2155
		.mask = 0xfff0,
		.name = "Intel ICH5/AD1985",
		.type = AC97_TUNE_AD_SHARING
	},
	{
2156 2157
		.subvendor = 0x8086,
		.subdevice = 0x4856,
L
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2158 2159 2160 2161
		.name = "Intel D845WN (82801BA)",
		.type = AC97_TUNE_SWAP_HP
	},
	{
2162 2163
		.subvendor = 0x8086,
		.subdevice = 0x4d44,
L
Linus Torvalds 已提交
2164 2165 2166 2167
		.name = "Intel D850EMV2",	/* AD1885 */
		.type = AC97_TUNE_HP_ONLY
	},
	{
2168 2169
		.subvendor = 0x8086,
		.subdevice = 0x4d56,
L
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2170 2171 2172 2173
		.name = "Intel ICH/AD1885",
		.type = AC97_TUNE_HP_ONLY
	},
	{
2174 2175
		.subvendor = 0x8086,
		.subdevice = 0x6000,
L
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2176 2177 2178 2179 2180
		.mask = 0xfff0,
		.name = "Intel ICH5/AD1985",
		.type = AC97_TUNE_AD_SHARING
	},
	{
2181 2182
		.subvendor = 0x8086,
		.subdevice = 0xe000,
L
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2183 2184 2185 2186 2187 2188
		.mask = 0xfff0,
		.name = "Intel ICH5/AD1985",
		.type = AC97_TUNE_AD_SHARING
	},
#if 0 /* FIXME: this seems wrong on most boards */
	{
2189 2190
		.subvendor = 0x8086,
		.subdevice = 0xa000,
L
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2191 2192 2193 2194 2195 2196 2197 2198
		.mask = 0xfff0,
		.name = "Intel ICH5/AD1985",
		.type = AC97_TUNE_HP_ONLY
	},
#endif
	{ } /* terminator */
};

2199 2200
static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock,
					const char *quirk_override)
L
Linus Torvalds 已提交
2201
{
2202 2203
	struct snd_ac97_bus *pbus;
	struct snd_ac97_template ac97;
L
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2204 2205 2206
	int err;
	unsigned int i, codecs;
	unsigned int glob_sta = 0;
2207 2208
	struct snd_ac97_bus_ops *ops;
	static struct snd_ac97_bus_ops standard_bus_ops = {
L
Linus Torvalds 已提交
2209 2210 2211
		.write = snd_intel8x0_codec_write,
		.read = snd_intel8x0_codec_read,
	};
2212
	static struct snd_ac97_bus_ops ali_bus_ops = {
L
Linus Torvalds 已提交
2213 2214 2215 2216 2217
		.write = snd_intel8x0_ali_codec_write,
		.read = snd_intel8x0_ali_codec_read,
	};

	chip->spdif_idx = -1; /* use PCMOUT (or disabled) */
2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230
	if (!spdif_aclink) {
		switch (chip->device_type) {
		case DEVICE_NFORCE:
			chip->spdif_idx = NVD_SPBAR;
			break;
		case DEVICE_ALI:
			chip->spdif_idx = ALID_AC97SPDIFOUT;
			break;
		case DEVICE_INTEL_ICH4:
			chip->spdif_idx = ICHD_SPBAR;
			break;
		};
	}
L
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2231 2232 2233 2234 2235 2236

	chip->in_ac97_init = 1;
	
	memset(&ac97, 0, sizeof(ac97));
	ac97.private_data = chip;
	ac97.private_free = snd_intel8x0_mixer_free_ac97;
2237
	ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE;
L
Linus Torvalds 已提交
2238 2239 2240 2241 2242
	if (chip->xbox)
		ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR;
	if (chip->device_type != DEVICE_ALI) {
		glob_sta = igetdword(chip, ICHREG(GLOB_STA));
		ops = &standard_bus_ops;
2243 2244 2245 2246 2247 2248 2249 2250 2251
		chip->in_sdin_init = 1;
		codecs = 0;
		for (i = 0; i < chip->max_codecs; i++) {
			if (! (glob_sta & chip->codec_bit[i]))
				continue;
			if (chip->device_type == DEVICE_INTEL_ICH4) {
				snd_intel8x0_codec_read_test(chip, codecs);
				chip->ac97_sdin[codecs] =
					igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK;
2252 2253
				if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3))
					chip->ac97_sdin[codecs] = 0;
2254 2255 2256
			} else
				chip->ac97_sdin[codecs] = i;
			codecs++;
L
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2257
		}
2258 2259 2260
		chip->in_sdin_init = 0;
		if (! codecs)
			codecs = 1;
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2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285
	} else {
		ops = &ali_bus_ops;
		codecs = 1;
		/* detect the secondary codec */
		for (i = 0; i < 100; i++) {
			unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR));
			if (reg & 0x40) {
				codecs = 2;
				break;
			}
			iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40);
			udelay(1);
		}
	}
	if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0)
		goto __err;
	pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
	if (ac97_clock >= 8000 && ac97_clock <= 48000)
		pbus->clock = ac97_clock;
	/* FIXME: my test board doesn't work well with VRA... */
	if (chip->device_type == DEVICE_ALI)
		pbus->no_vra = 1;
	else
		pbus->dra = 1;
	chip->ac97_bus = pbus;
2286
	chip->ncodecs = codecs;
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2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341

	ac97.pci = chip->pci;
	for (i = 0; i < codecs; i++) {
		ac97.num = i;
		if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
			if (err != -EACCES)
				snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i);
			if (i == 0)
				goto __err;
		}
	}
	/* tune up the primary codec */
	snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override);
	/* enable separate SDINs for ICH4 */
	if (chip->device_type == DEVICE_INTEL_ICH4)
		pbus->isdin = 1;
	/* find the available PCM streams */
	i = ARRAY_SIZE(ac97_pcm_defs);
	if (chip->device_type != DEVICE_INTEL_ICH4)
		i -= 2;		/* do not allocate PCM2IN and MIC2 */
	if (chip->spdif_idx < 0)
		i--;		/* do not allocate S/PDIF */
	err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs);
	if (err < 0)
		goto __err;
	chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0];
	chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1];
	chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2];
	if (chip->spdif_idx >= 0)
		chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3];
	if (chip->device_type == DEVICE_INTEL_ICH4) {
		chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4];
		chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5];
	}
	/* enable separate SDINs for ICH4 */
	if (chip->device_type == DEVICE_INTEL_ICH4) {
		struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm;
		u8 tmp = igetbyte(chip, ICHREG(SDM));
		tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK);
		if (pcm) {
			tmp |= ICH_SE;	/* steer enable for multiple SDINs */
			tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT;
			for (i = 1; i < 4; i++) {
				if (pcm->r[0].codec[i]) {
					tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT;
					break;
				}
			}
		} else {
			tmp &= ~ICH_SE; /* steer disable */
		}
		iputbyte(chip, ICHREG(SDM), tmp);
	}
	if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) {
		chip->multi4 = 1;
2342
		if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) {
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2343
			chip->multi6 = 1;
2344 2345 2346
			if (chip->ac97[0]->flags & AC97_HAS_8CH)
				chip->multi8 = 1;
		}
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2347 2348 2349 2350 2351 2352 2353 2354
	}
	if (pbus->pcms[0].r[1].rslots[0]) {
		chip->dra = 1;
	}
	if (chip->device_type == DEVICE_INTEL_ICH4) {
		if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20)
			chip->smp20bit = 1;
	}
2355
	if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
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2356 2357 2358
		/* 48kHz only */
		chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000;
	}
2359
	if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
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2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372
		/* use slot 10/11 for SPDIF */
		u32 val;
		val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK;
		val |= ICH_PCM_SPDIF_1011;
		iputdword(chip, ICHREG(GLOB_CNT), val);
		snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4);
	}
	chip->in_ac97_init = 0;
	return 0;

 __err:
	/* clear the cold-reset bit for the next chance */
	if (chip->device_type != DEVICE_ALI)
2373 2374
		iputdword(chip, ICHREG(GLOB_CNT),
			  igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
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	return err;
}


/*
 *
 */

2383
static void do_ali_reset(struct intel8x0 *chip)
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2384 2385 2386 2387 2388 2389
{
	iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET);
	iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383);
	iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383);
	iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383);
	iputdword(chip, ICHREG(ALI_INTERFACECR),
W
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2390
		  ICH_ALI_IF_PI|ICH_ALI_IF_PO);
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	iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000);
	iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000);
}

2395 2396 2397 2398 2399
#ifdef CONFIG_SND_AC97_POWER_SAVE
static struct snd_pci_quirk ich_chip_reset_mode[] = {
	SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1),
	{ } /* end */
};
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2401 2402 2403
static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip)
{
	unsigned int cnt;
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	/* ACLink on, 2 channels */
2405 2406 2407 2408

	if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
		return -EIO;

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	cnt = igetdword(chip, ICHREG(GLOB_CNT));
	cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
2411

2412 2413 2414 2415 2416 2417 2418 2419
	/* do cold reset - the full ac97 powerdown may leave the controller
	 * in a warm state but actually it cannot communicate with the codec.
	 */
	iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD);
	cnt = igetdword(chip, ICHREG(GLOB_CNT));
	udelay(10);
	iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD);
	msleep(1);
2420 2421 2422 2423
	return 0;
}
#define snd_intel8x0_ich_chip_can_cold_reset(chip) \
	(!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode))
2424
#else
2425
#define snd_intel8x0_ich_chip_cold_reset(chip)	0
2426 2427 2428 2429 2430 2431 2432 2433 2434 2435
#define snd_intel8x0_ich_chip_can_cold_reset(chip) (0)
#endif

static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip)
{
	unsigned long end_time;
	unsigned int cnt;
	/* ACLink on, 2 channels */
	cnt = igetdword(chip, ICHREG(GLOB_CNT));
	cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK);
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	/* finish cold or do warm reset */
	cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
	iputdword(chip, ICHREG(GLOB_CNT), cnt);
	end_time = (jiffies + (HZ / 4)) + 1;
	do {
		if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
2442
			return 0;
2443
		schedule_timeout_uninterruptible(1);
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2444
	} while (time_after_eq(end_time, jiffies));
2445 2446
	snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
		   igetdword(chip, ICHREG(GLOB_CNT)));
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	return -EIO;
2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470
}

static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing)
{
	unsigned long end_time;
	unsigned int status, nstatus;
	unsigned int cnt;
	int err;

	/* put logic to right state */
	/* first clear status bits */
	status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT;
	if (chip->device_type == DEVICE_NFORCE)
		status |= ICH_NVSPINT;
	cnt = igetdword(chip, ICHREG(GLOB_STA));
	iputdword(chip, ICHREG(GLOB_STA), cnt & status);

	if (snd_intel8x0_ich_chip_can_cold_reset(chip))
		err = snd_intel8x0_ich_chip_cold_reset(chip);
	else
		err = snd_intel8x0_ich_chip_reset(chip);
	if (err < 0)
		return err;
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	if (probing) {
		/* wait for any codec ready status.
		 * Once it becomes ready it should remain ready
		 * as long as we do not disable the ac97 link.
		 */
		end_time = jiffies + HZ;
		do {
2479
			status = igetdword(chip, ICHREG(GLOB_STA)) &
2480
				chip->codec_isr_bits;
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2481 2482
			if (status)
				break;
2483
			schedule_timeout_uninterruptible(1);
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2484 2485 2486
		} while (time_after_eq(end_time, jiffies));
		if (! status) {
			/* no codec is found */
2487 2488
			snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
				   igetdword(chip, ICHREG(GLOB_STA)));
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			return -EIO;
		}

		/* wait for other codecs ready status. */
		end_time = jiffies + HZ / 4;
2494 2495
		while (status != chip->codec_isr_bits &&
		       time_after_eq(end_time, jiffies)) {
2496
			schedule_timeout_uninterruptible(1);
2497 2498
			status |= igetdword(chip, ICHREG(GLOB_STA)) &
				chip->codec_isr_bits;
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		}

	} else {
		/* resume phase */
		int i;
		status = 0;
2505
		for (i = 0; i < chip->ncodecs; i++)
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			if (chip->ac97[i])
2507
				status |= chip->codec_bit[chip->ac97_sdin[i]];
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		/* wait until all the probed codecs are ready */
		end_time = jiffies + HZ;
		do {
2511
			nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
2512
				chip->codec_isr_bits;
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2513 2514
			if (status == nstatus)
				break;
2515
			schedule_timeout_uninterruptible(1);
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		} while (time_after_eq(end_time, jiffies));
	}

	if (chip->device_type == DEVICE_SIS) {
		/* unmute the output on SIS7012 */
		iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
	}
2523
	if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
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		/* enable SPDIF interrupt */
		unsigned int val;
		pci_read_config_dword(chip->pci, 0x4c, &val);
		val |= 0x1000000;
		pci_write_config_dword(chip->pci, 0x4c, val);
	}
      	return 0;
}

2533
static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing)
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2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548
{
	u32 reg;
	int i = 0;

	reg = igetdword(chip, ICHREG(ALI_SCR));
	if ((reg & 2) == 0)	/* Cold required */
		reg |= 2;
	else
		reg |= 1;	/* Warm */
	reg &= ~0x80000000;	/* ACLink on */
	iputdword(chip, ICHREG(ALI_SCR), reg);

	for (i = 0; i < HZ / 2; i++) {
		if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO))
			goto __ok;
2549
		schedule_timeout_uninterruptible(1);
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	}
	snd_printk(KERN_ERR "AC'97 reset failed.\n");
	if (probing)
		return -EIO;

 __ok:
	for (i = 0; i < HZ / 2; i++) {
		reg = igetdword(chip, ICHREG(ALI_RTSR));
		if (reg & 0x80) /* primary codec */
			break;
		iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80);
2561
		schedule_timeout_uninterruptible(1);
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	}

	do_ali_reset(chip);
	return 0;
}

2568
static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing)
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{
2570
	unsigned int i, timeout;
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	int err;
	
	if (chip->device_type != DEVICE_ALI) {
		if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0)
			return err;
		iagetword(chip, 0);	/* clear semaphore flag */
	} else {
		if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0)
			return err;
	}

	/* disable interrupts */
	for (i = 0; i < chip->bdbars_count; i++)
		iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
	/* reset channels */
	for (i = 0; i < chip->bdbars_count; i++)
		iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2588 2589 2590 2591 2592 2593 2594 2595 2596
	for (i = 0; i < chip->bdbars_count; i++) {
	        timeout = 100000;
	        while (--timeout != 0) {
        		if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0)
        		        break;
                }
                if (timeout == 0)
                        printk(KERN_ERR "intel8x0: reset of registers failed?\n");
        }
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	/* initialize Buffer Descriptor Lists */
	for (i = 0; i < chip->bdbars_count; i++)
2599 2600
		iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset,
			  chip->ichd[i].bdbar_addr);
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	return 0;
}

2604
static int snd_intel8x0_free(struct intel8x0 *chip)
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2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615
{
	unsigned int i;

	if (chip->irq < 0)
		goto __hw_end;
	/* disable interrupts */
	for (i = 0; i < chip->bdbars_count; i++)
		iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
	/* reset channels */
	for (i = 0; i < chip->bdbars_count; i++)
		iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
2616
	if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) {
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		/* stop the spdif interrupt */
		unsigned int val;
		pci_read_config_dword(chip->pci, 0x4c, &val);
		val &= ~0x1000000;
		pci_write_config_dword(chip->pci, 0x4c, val);
	}
	/* --- */
2624

L
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2625 2626
      __hw_end:
	if (chip->irq >= 0)
2627
		free_irq(chip->irq, chip);
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	if (chip->bdbars.area) {
		if (chip->fix_nocache)
			fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0);
		snd_dma_free_pages(&chip->bdbars);
	}
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	if (chip->addr)
		pci_iounmap(chip->pci, chip->addr);
	if (chip->bmaddr)
		pci_iounmap(chip->pci, chip->bmaddr);
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	pci_release_regions(chip->pci);
	pci_disable_device(chip->pci);
	kfree(chip);
	return 0;
}

2643
#ifdef CONFIG_PM_SLEEP
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/*
 * power management
 */
2647
static int intel8x0_suspend(struct device *dev)
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2648
{
2649 2650
	struct pci_dev *pci = to_pci_dev(dev);
	struct snd_card *card = dev_get_drvdata(dev);
T
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2651
	struct intel8x0 *chip = card->private_data;
L
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2652 2653
	int i;

T
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	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
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2655 2656 2657 2658 2659
	for (i = 0; i < chip->pcm_devs; i++)
		snd_pcm_suspend_all(chip->pcm[i]);
	/* clear nocache */
	if (chip->fix_nocache) {
		for (i = 0; i < chip->bdbars_count; i++) {
2660
			struct ichdev *ichdev = &chip->ichd[i];
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2661
			if (ichdev->substream && ichdev->page_attr_changed) {
2662
				struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
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				if (runtime->dma_area)
					fill_nocache(runtime->dma_area, runtime->dma_bytes, 0);
			}
		}
	}
2668
	for (i = 0; i < chip->ncodecs; i++)
T
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		snd_ac97_suspend(chip->ac97[i]);
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	if (chip->device_type == DEVICE_INTEL_ICH4)
		chip->sdm_saved = igetbyte(chip, ICHREG(SDM));
2672

2673
	if (chip->irq >= 0) {
2674
		free_irq(chip->irq, chip);
2675 2676
		chip->irq = -1;
	}
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	pci_disable_device(pci);
	pci_save_state(pci);
2679 2680 2681
	/* The call below may disable built-in speaker on some laptops
	 * after S2RAM.  So, don't touch it.
	 */
2682
	/* pci_set_power_state(pci, PCI_D3hot); */
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	return 0;
}

2686
static int intel8x0_resume(struct device *dev)
L
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2687
{
2688 2689
	struct pci_dev *pci = to_pci_dev(dev);
	struct snd_card *card = dev_get_drvdata(dev);
T
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2690
	struct intel8x0 *chip = card->private_data;
L
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2691 2692
	int i;

2693
	pci_set_power_state(pci, PCI_D0);
T
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2694
	pci_restore_state(pci);
2695 2696 2697 2698 2699 2700
	if (pci_enable_device(pci) < 0) {
		printk(KERN_ERR "intel8x0: pci_enable_device failed, "
		       "disabling device\n");
		snd_card_disconnect(card);
		return -EIO;
	}
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	pci_set_master(pci);
2702
	snd_intel8x0_chip_init(chip, 0);
2703
	if (request_irq(pci->irq, snd_intel8x0_interrupt,
2704
			IRQF_SHARED, KBUILD_MODNAME, chip)) {
2705 2706 2707 2708 2709
		printk(KERN_ERR "intel8x0: unable to grab IRQ %d, "
		       "disabling device\n", pci->irq);
		snd_card_disconnect(card);
		return -EIO;
	}
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	chip->irq = pci->irq;
2711
	synchronize_irq(chip->irq);
L
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2712

T
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2713
	/* re-initialize mixer stuff */
2714
	if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) {
T
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		/* enable separate SDINs for ICH4 */
		iputbyte(chip, ICHREG(SDM), chip->sdm_saved);
		/* use slot 10/11 for SPDIF */
		iputdword(chip, ICHREG(GLOB_CNT),
			  (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) |
			  ICH_PCM_SPDIF_1011);
	}

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2723 2724 2725 2726
	/* refill nocache */
	if (chip->fix_nocache)
		fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);

2727
	for (i = 0; i < chip->ncodecs; i++)
T
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2728
		snd_ac97_resume(chip->ac97[i]);
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2729 2730 2731 2732

	/* refill nocache */
	if (chip->fix_nocache) {
		for (i = 0; i < chip->bdbars_count; i++) {
2733
			struct ichdev *ichdev = &chip->ichd[i];
L
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2734
			if (ichdev->substream && ichdev->page_attr_changed) {
2735
				struct snd_pcm_runtime *runtime = ichdev->substream->runtime;
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				if (runtime->dma_area)
					fill_nocache(runtime->dma_area, runtime->dma_bytes, 1);
			}
		}
	}

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2742 2743
	/* resume status */
	for (i = 0; i < chip->bdbars_count; i++) {
2744
		struct ichdev *ichdev = &chip->ichd[i];
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2745 2746 2747 2748 2749 2750 2751 2752 2753 2754 2755
		unsigned long port = ichdev->reg_offset;
		if (! ichdev->substream || ! ichdev->suspended)
			continue;
		if (ichdev->ichd == ICHD_PCMOUT)
			snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime);
		iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
		iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
		iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ);
		iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
	}

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	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
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	return 0;
}
2759 2760 2761 2762 2763

static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume);
#define INTEL8X0_PM_OPS	&intel8x0_pm
#else
#define INTEL8X0_PM_OPS	NULL
2764
#endif /* CONFIG_PM_SLEEP */
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#define INTEL8X0_TESTBUF_SIZE	32768	/* enough large for one shot */

2768
static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip)
L
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2769
{
2770 2771
	struct snd_pcm_substream *subs;
	struct ichdev *ichdev;
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2772
	unsigned long port;
2773
	unsigned long pos, pos1, t;
2774
	int civ, timeout = 1000, attempt = 1;
2775
	struct timespec start_time, stop_time;
L
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	if (chip->ac97_bus->clock != 48000)
		return; /* specified in module option */

2780
      __again:
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2781 2782
	subs = chip->pcm[0]->streams[0].substream;
	if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) {
2783
		snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n");
L
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		return;
	}
	ichdev = &chip->ichd[ICHD_PCMOUT];
	ichdev->physbuf = subs->dma_buffer.addr;
2788
	ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE;
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	ichdev->substream = NULL; /* don't process interrupts */

	/* set rate */
	if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) {
		snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock);
		return;
	}
	snd_intel8x0_setup_periods(chip, ichdev);
	port = ichdev->reg_offset;
	spin_lock_irq(&chip->reg_lock);
	chip->in_measurement = 1;
	/* trigger */
	if (chip->device_type != DEVICE_ALI)
		iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM);
	else {
		iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE);
		iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot);
	}
2807
	do_posix_clock_monotonic_gettime(&start_time);
L
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2808
	spin_unlock_irq(&chip->reg_lock);
2809
	msleep(50);
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2810 2811
	spin_lock_irq(&chip->reg_lock);
	/* check the position */
2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822
	do {
		civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV);
		pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb);
		if (pos1 == 0) {
			udelay(10);
			continue;
		}
		if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) &&
		    pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb))
			break;
	} while (timeout--);
2823 2824 2825 2826 2827 2828 2829
	if (pos1 == 0) {	/* oops, this value is not reliable */
		pos = 0;
	} else {
		pos = ichdev->fragsize1;
		pos -= pos1 << ichdev->pos_shift;
		pos += ichdev->position;
	}
L
Linus Torvalds 已提交
2830
	chip->in_measurement = 0;
2831
	do_posix_clock_monotonic_gettime(&stop_time);
L
Linus Torvalds 已提交
2832 2833
	/* stop */
	if (chip->device_type == DEVICE_ALI) {
W
Wei Ni 已提交
2834
		iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16));
L
Linus Torvalds 已提交
2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845
		iputbyte(chip, port + ICH_REG_OFF_CR, 0);
		while (igetbyte(chip, port + ICH_REG_OFF_CR))
			;
	} else {
		iputbyte(chip, port + ICH_REG_OFF_CR, 0);
		while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH))
			;
	}
	iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
	spin_unlock_irq(&chip->reg_lock);

2846 2847
	if (pos == 0) {
		snd_printk(KERN_ERR "intel8x0: measure - unreliable DMA position..\n");
2848
	      __retry:
2849 2850
		if (attempt < 3) {
			msleep(300);
2851 2852 2853
			attempt++;
			goto __again;
		}
2854
		goto __end;
2855 2856
	}

2857
	pos /= 4;
L
Linus Torvalds 已提交
2858 2859
	t = stop_time.tv_sec - start_time.tv_sec;
	t *= 1000000;
2860 2861
	t += (stop_time.tv_nsec - start_time.tv_nsec) / 1000;
	printk(KERN_INFO "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos);
L
Linus Torvalds 已提交
2862
	if (t == 0) {
2863
		snd_printk(KERN_ERR "intel8x0: ?? calculation error..\n");
2864
		goto __retry;
L
Linus Torvalds 已提交
2865
	}
2866
	pos *= 1000;
L
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2867
	pos = (pos / t) * 1000 + ((pos % t) * 1000) / t;
2868
	if (pos < 40000 || pos >= 60000) {
L
Linus Torvalds 已提交
2869 2870
		/* abnormal value. hw problem? */
		printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos);
2871 2872
		goto __retry;
	} else if (pos > 40500 && pos < 41500)
2873 2874
		/* first exception - 41000Hz reference clock */
		chip->ac97_bus->clock = 41000;
2875
	else if (pos > 43600 && pos < 44600)
2876 2877
		/* second exception - 44100HZ reference clock */
		chip->ac97_bus->clock = 44100;
L
Linus Torvalds 已提交
2878 2879 2880
	else if (pos < 47500 || pos > 48500)
		/* not 48000Hz, tuning the clock.. */
		chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos;
2881
      __end:
L
Linus Torvalds 已提交
2882
	printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock);
2883
	snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0);
L
Linus Torvalds 已提交
2884 2885
}

2886 2887 2888 2889
static struct snd_pci_quirk intel8x0_clock_list[] __devinitdata = {
	SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000),
	SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100),
	SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000),
2890
	SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000),
2891 2892
	SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000),
	{ }	/* terminator */
2893 2894 2895 2896 2897
};

static int __devinit intel8x0_in_clock_list(struct intel8x0 *chip)
{
	struct pci_dev *pci = chip->pci;
2898 2899 2900 2901 2902 2903 2904 2905 2906
	const struct snd_pci_quirk *wl;

	wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list);
	if (!wl)
		return 0;
	printk(KERN_INFO "intel8x0: white list rate for %04x:%04x is %i\n",
	       pci->subsystem_vendor, pci->subsystem_device, wl->value);
	chip->ac97_bus->clock = wl->value;
	return 1;
2907 2908
}

2909
#ifdef CONFIG_PROC_FS
2910 2911
static void snd_intel8x0_proc_read(struct snd_info_entry * entry,
				   struct snd_info_buffer *buffer)
L
Linus Torvalds 已提交
2912
{
2913
	struct intel8x0 *chip = entry->private_data;
L
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2914 2915 2916 2917 2918 2919 2920 2921 2922 2923
	unsigned int tmp;

	snd_iprintf(buffer, "Intel8x0\n\n");
	if (chip->device_type == DEVICE_ALI)
		return;
	tmp = igetdword(chip, ICHREG(GLOB_STA));
	snd_iprintf(buffer, "Global control        : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT)));
	snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
	if (chip->device_type == DEVICE_INTEL_ICH4)
		snd_iprintf(buffer, "SDM                   : 0x%08x\n", igetdword(chip, ICHREG(SDM)));
2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937
	snd_iprintf(buffer, "AC'97 codecs ready    :");
	if (tmp & chip->codec_isr_bits) {
		int i;
		static const char *codecs[3] = {
			"primary", "secondary", "tertiary"
		};
		for (i = 0; i < chip->max_codecs; i++)
			if (tmp & chip->codec_bit[i])
				snd_iprintf(buffer, " %s", codecs[i]);
	} else
		snd_iprintf(buffer, " none");
	snd_iprintf(buffer, "\n");
	if (chip->device_type == DEVICE_INTEL_ICH4 ||
	    chip->device_type == DEVICE_SIS)
L
Linus Torvalds 已提交
2938 2939 2940 2941 2942 2943
		snd_iprintf(buffer, "AC'97 codecs SDIN     : %i %i %i\n",
			chip->ac97_sdin[0],
			chip->ac97_sdin[1],
			chip->ac97_sdin[2]);
}

2944
static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip)
L
Linus Torvalds 已提交
2945
{
2946
	struct snd_info_entry *entry;
L
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2947 2948

	if (! snd_card_proc_new(chip->card, "intel8x0", &entry))
2949
		snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read);
L
Linus Torvalds 已提交
2950
}
2951 2952 2953
#else
#define snd_intel8x0_proc_init(x)
#endif
L
Linus Torvalds 已提交
2954

2955
static int snd_intel8x0_dev_free(struct snd_device *device)
L
Linus Torvalds 已提交
2956
{
2957
	struct intel8x0 *chip = device->device_data;
L
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2958 2959 2960 2961 2962 2963 2964 2965
	return snd_intel8x0_free(chip);
}

struct ich_reg_info {
	unsigned int int_sta_mask;
	unsigned int offset;
};

2966 2967 2968 2969 2970 2971 2972
static unsigned int ich_codec_bits[3] = {
	ICH_PCR, ICH_SCR, ICH_TCR
};
static unsigned int sis_codec_bits[3] = {
	ICH_PCR, ICH_SCR, ICH_SIS_TCR
};

2973
static int __devinit snd_intel8x0_inside_vm(struct pci_dev *pci)
2974
{
2975 2976
	int result  = inside_vm;
	char *msg   = NULL;
2977

2978 2979 2980 2981 2982 2983 2984 2985 2986 2987
	/* check module parameter first (override detection) */
	if (result >= 0) {
		msg = result ? "enable (forced) VM" : "disable (forced) VM";
		goto fini;
	}

	/* detect KVM and Parallels virtual environments */
	result = kvm_para_available();
#ifdef X86_FEATURE_HYPERVISOR
	result = result || boot_cpu_has(X86_FEATURE_HYPERVISOR);
2988
#endif
2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002
	if (!result)
		goto fini;

	/* check for known (emulated) devices */
	if (pci->subsystem_vendor == 0x1af4 &&
	    pci->subsystem_device == 0x1100) {
		/* KVM emulated sound, PCI SSID: 1af4:1100 */
		msg = "enable KVM";
	} else if (pci->subsystem_vendor == 0x1ab8) {
		/* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */
		msg = "enable Parallels VM";
	} else {
		msg = "disable (unknown or VT-d) VM";
		result = 0;
3003 3004
	}

3005 3006 3007
fini:
	if (msg != NULL)
		printk(KERN_INFO "intel8x0: %s optimization\n", msg);
3008 3009 3010 3011

	return result;
}

3012
static int __devinit snd_intel8x0_create(struct snd_card *card,
L
Linus Torvalds 已提交
3013 3014
					 struct pci_dev *pci,
					 unsigned long device_type,
3015
					 struct intel8x0 ** r_intel8x0)
L
Linus Torvalds 已提交
3016
{
3017
	struct intel8x0 *chip;
L
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3018 3019 3020
	int err;
	unsigned int i;
	unsigned int int_sta_masks;
3021 3022
	struct ichdev *ichdev;
	static struct snd_device_ops ops = {
L
Linus Torvalds 已提交
3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061
		.dev_free =	snd_intel8x0_dev_free,
	};

	static unsigned int bdbars[] = {
		3, /* DEVICE_INTEL */
		6, /* DEVICE_INTEL_ICH4 */
		3, /* DEVICE_SIS */
		6, /* DEVICE_ALI */
		4, /* DEVICE_NFORCE */
	};
	static struct ich_reg_info intel_regs[6] = {
		{ ICH_PIINT, 0 },
		{ ICH_POINT, 0x10 },
		{ ICH_MCINT, 0x20 },
		{ ICH_M2INT, 0x40 },
		{ ICH_P2INT, 0x50 },
		{ ICH_SPINT, 0x60 },
	};
	static struct ich_reg_info nforce_regs[4] = {
		{ ICH_PIINT, 0 },
		{ ICH_POINT, 0x10 },
		{ ICH_MCINT, 0x20 },
		{ ICH_NVSPINT, 0x70 },
	};
	static struct ich_reg_info ali_regs[6] = {
		{ ALI_INT_PCMIN, 0x40 },
		{ ALI_INT_PCMOUT, 0x50 },
		{ ALI_INT_MICIN, 0x60 },
		{ ALI_INT_CODECSPDIFOUT, 0x70 },
		{ ALI_INT_SPDIFIN, 0xa0 },
		{ ALI_INT_SPDIFOUT, 0xb0 },
	};
	struct ich_reg_info *tbl;

	*r_intel8x0 = NULL;

	if ((err = pci_enable_device(pci)) < 0)
		return err;

3062
	chip = kzalloc(sizeof(*chip), GFP_KERNEL);
L
Linus Torvalds 已提交
3063 3064 3065 3066 3067 3068 3069 3070 3071
	if (chip == NULL) {
		pci_disable_device(pci);
		return -ENOMEM;
	}
	spin_lock_init(&chip->reg_lock);
	chip->device_type = device_type;
	chip->card = card;
	chip->pci = pci;
	chip->irq = -1;
3072 3073 3074 3075 3076 3077

	/* module parameters */
	chip->buggy_irq = buggy_irq;
	chip->buggy_semaphore = buggy_semaphore;
	if (xbox)
		chip->xbox = 1;
L
Linus Torvalds 已提交
3078

3079
	chip->inside_vm = snd_intel8x0_inside_vm(pci);
3080

L
Linus Torvalds 已提交
3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092
	if (pci->vendor == PCI_VENDOR_ID_INTEL &&
	    pci->device == PCI_DEVICE_ID_INTEL_440MX)
		chip->fix_nocache = 1; /* enable workaround */

	if ((err = pci_request_regions(pci, card->shortname)) < 0) {
		kfree(chip);
		pci_disable_device(pci);
		return err;
	}

	if (device_type == DEVICE_ALI) {
		/* ALI5455 has no ac97 region */
T
Takashi Iwai 已提交
3093
		chip->bmaddr = pci_iomap(pci, 0, 0);
L
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3094 3095 3096
		goto port_inited;
	}

T
Takashi Iwai 已提交
3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113
	if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
		chip->addr = pci_iomap(pci, 2, 0);
	else
		chip->addr = pci_iomap(pci, 0, 0);
	if (!chip->addr) {
		snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
		snd_intel8x0_free(chip);
		return -EIO;
	}
	if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
		chip->bmaddr = pci_iomap(pci, 3, 0);
	else
		chip->bmaddr = pci_iomap(pci, 1, 0);
	if (!chip->bmaddr) {
		snd_printk(KERN_ERR "Controller space ioremap problem\n");
		snd_intel8x0_free(chip);
		return -EIO;
L
Linus Torvalds 已提交
3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166
	}

 port_inited:
	chip->bdbars_count = bdbars[device_type];

	/* initialize offsets */
	switch (device_type) {
	case DEVICE_NFORCE:
		tbl = nforce_regs;
		break;
	case DEVICE_ALI:
		tbl = ali_regs;
		break;
	default:
		tbl = intel_regs;
		break;
	}
	for (i = 0; i < chip->bdbars_count; i++) {
		ichdev = &chip->ichd[i];
		ichdev->ichd = i;
		ichdev->reg_offset = tbl[i].offset;
		ichdev->int_sta_mask = tbl[i].int_sta_mask;
		if (device_type == DEVICE_SIS) {
			/* SiS 7012 swaps the registers */
			ichdev->roff_sr = ICH_REG_OFF_PICB;
			ichdev->roff_picb = ICH_REG_OFF_SR;
		} else {
			ichdev->roff_sr = ICH_REG_OFF_SR;
			ichdev->roff_picb = ICH_REG_OFF_PICB;
		}
		if (device_type == DEVICE_ALI)
			ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
		/* SIS7012 handles the pcm data in bytes, others are in samples */
		ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
	}

	/* allocate buffer descriptor lists */
	/* the start of each lists must be aligned to 8 bytes */
	if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
				chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
				&chip->bdbars) < 0) {
		snd_intel8x0_free(chip);
		snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n");
		return -ENOMEM;
	}
	/* tables must be aligned to 8 bytes here, but the kernel pages
	   are much bigger, so we don't care (on i386) */
	/* workaround for 440MX */
	if (chip->fix_nocache)
		fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1);
	int_sta_masks = 0;
	for (i = 0; i < chip->bdbars_count; i++) {
		ichdev = &chip->ichd[i];
3167 3168 3169 3170
		ichdev->bdbar = ((u32 *)chip->bdbars.area) +
			(i * ICH_MAX_FRAGS * 2);
		ichdev->bdbar_addr = chip->bdbars.addr +
			(i * sizeof(u32) * ICH_MAX_FRAGS * 2);
L
Linus Torvalds 已提交
3171 3172
		int_sta_masks |= ichdev->int_sta_mask;
	}
3173 3174
	chip->int_sta_reg = device_type == DEVICE_ALI ?
		ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA;
L
Linus Torvalds 已提交
3175 3176
	chip->int_sta_mask = int_sta_masks;

3177 3178
	pci_set_master(pci);

3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201
	switch(chip->device_type) {
	case DEVICE_INTEL_ICH4:
		/* ICH4 can have three codecs */
		chip->max_codecs = 3;
		chip->codec_bit = ich_codec_bits;
		chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI;
		break;
	case DEVICE_SIS:
		/* recent SIS7012 can have three codecs */
		chip->max_codecs = 3;
		chip->codec_bit = sis_codec_bits;
		chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI;
		break;
	default:
		/* others up to two codecs */
		chip->max_codecs = 2;
		chip->codec_bit = ich_codec_bits;
		chip->codec_ready_bits = ICH_PRI | ICH_SRI;
		break;
	}
	for (i = 0; i < chip->max_codecs; i++)
		chip->codec_isr_bits |= chip->codec_bit[i];

L
Linus Torvalds 已提交
3202 3203 3204 3205 3206
	if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
		snd_intel8x0_free(chip);
		return err;
	}

3207 3208
	/* request irq after initializaing int_sta_mask, etc */
	if (request_irq(pci->irq, snd_intel8x0_interrupt,
3209
			IRQF_SHARED, KBUILD_MODNAME, chip)) {
3210 3211 3212 3213 3214 3215
		snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
		snd_intel8x0_free(chip);
		return -EBUSY;
	}
	chip->irq = pci->irq;

L
Linus Torvalds 已提交
3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229 3230
	if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
		snd_intel8x0_free(chip);
		return err;
	}

	snd_card_set_dev(card, &pci->dev);

	*r_intel8x0 = chip;
	return 0;
}

static struct shortname_table {
	unsigned int id;
	const char *s;
} shortnames[] __devinitdata = {
3231 3232 3233
	{ PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" },
	{ PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" },
	{ PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" },
L
Linus Torvalds 已提交
3234
	{ PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" },
3235 3236 3237
	{ PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" },
	{ PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" },
	{ PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" },
L
Linus Torvalds 已提交
3238 3239 3240
	{ PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" },
	{ PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" },
	{ PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" },
3241
	{ PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" },
L
Linus Torvalds 已提交
3242
	{ PCI_DEVICE_ID_SI_7012, "SiS SI7012" },
3243
	{ PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" },
L
Linus Torvalds 已提交
3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255
	{ PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" },
	{ PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" },
	{ PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" },
	{ PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" },
	{ PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" },
	{ 0x003a, "NVidia MCP04" },
	{ 0x746d, "AMD AMD8111" },
	{ 0x7445, "AMD AMD768" },
	{ 0x5455, "ALi M5455" },
	{ 0, NULL },
};

3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278
static struct snd_pci_quirk spdif_aclink_defaults[] __devinitdata = {
	SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1),
	{ } /* end */
};

/* look up white/black list for SPDIF over ac-link */
static int __devinit check_default_spdif_aclink(struct pci_dev *pci)
{
	const struct snd_pci_quirk *w;

	w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults);
	if (w) {
		if (w->value)
			snd_printdd(KERN_INFO "intel8x0: Using SPDIF over "
				    "AC-Link for %s\n", w->name);
		else
			snd_printdd(KERN_INFO "intel8x0: Using integrated "
				    "SPDIF DMA for %s\n", w->name);
		return w->value;
	}
	return 0;
}

L
Linus Torvalds 已提交
3279 3280 3281
static int __devinit snd_intel8x0_probe(struct pci_dev *pci,
					const struct pci_device_id *pci_id)
{
3282 3283
	struct snd_card *card;
	struct intel8x0 *chip;
L
Linus Torvalds 已提交
3284 3285 3286
	int err;
	struct shortname_table *name;

3287 3288 3289
	err = snd_card_create(index, id, THIS_MODULE, 0, &card);
	if (err < 0)
		return err;
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	if (spdif_aclink < 0)
		spdif_aclink = check_default_spdif_aclink(pci);

	strcpy(card->driver, "ICH");
	if (!spdif_aclink) {
		switch (pci_id->driver_data) {
		case DEVICE_NFORCE:
			strcpy(card->driver, "NFORCE");
			break;
		case DEVICE_INTEL_ICH4:
			strcpy(card->driver, "ICH4");
		}
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	}

	strcpy(card->shortname, "Intel ICH");
	for (name = shortnames; name->id; name++) {
		if (pci->device == name->id) {
			strcpy(card->shortname, name->s);
			break;
		}
	}

3313 3314 3315 3316 3317 3318 3319 3320 3321 3322
	if (buggy_irq < 0) {
		/* some Nforce[2] and ICH boards have problems with IRQ handling.
		 * Needs to return IRQ_HANDLED for unknown irqs.
		 */
		if (pci_id->driver_data == DEVICE_NFORCE)
			buggy_irq = 1;
		else
			buggy_irq = 0;
	}

3323
	if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data,
3324
				       &chip)) < 0) {
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		snd_card_free(card);
		return err;
	}
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	card->private_data = chip;
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3330
	if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) {
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		snd_card_free(card);
		return err;
	}
	if ((err = snd_intel8x0_pcm(chip)) < 0) {
		snd_card_free(card);
		return err;
	}
	
	snd_intel8x0_proc_init(chip);

	snprintf(card->longname, sizeof(card->longname),
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		 "%s with %s at irq %i", card->shortname,
		 snd_ac97_get_short_name(chip->ac97[0]), chip->irq);
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3345 3346 3347 3348 3349 3350 3351 3352
	if (ac97_clock == 0 || ac97_clock == 1) {
		if (ac97_clock == 0) {
			if (intel8x0_in_clock_list(chip) == 0)
				intel8x0_measure_ac97_clock(chip);
		} else {
			intel8x0_measure_ac97_clock(chip);
		}
	}
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	if ((err = snd_card_register(card)) < 0) {
		snd_card_free(card);
		return err;
	}
	pci_set_drvdata(pci, card);
	return 0;
}

static void __devexit snd_intel8x0_remove(struct pci_dev *pci)
{
	snd_card_free(pci_get_drvdata(pci));
	pci_set_drvdata(pci, NULL);
}

3368
static struct pci_driver intel8x0_driver = {
3369
	.name = KBUILD_MODNAME,
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	.id_table = snd_intel8x0_ids,
	.probe = snd_intel8x0_probe,
	.remove = __devexit_p(snd_intel8x0_remove),
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	.driver = {
		.pm = INTEL8X0_PM_OPS,
	},
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};

3378
module_pci_driver(intel8x0_driver);