cpu-info.h 3.1 KB
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/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994 Waldorf GMBH
 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
 * Copyright (C) 1996 Paul M. Antoine
 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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 * Copyright (C) 2004  Maciej W. Rozycki
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 */
#ifndef __ASM_CPU_INFO_H
#define __ASM_CPU_INFO_H

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#include <linux/types.h>

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#include <asm/cache.h>

/*
 * Descriptor for a cache
 */
struct cache_desc {
	unsigned int waysize;	/* Bytes per way */
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	unsigned short sets;	/* Number of lines per set */
	unsigned char ways;	/* Number of ways */
	unsigned char linesz;	/* Size of line in bytes */
	unsigned char waybit;	/* Bits to select in a cache set */
	unsigned char flags;	/* Flags describing cache properties */
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};

/*
 * Flag definitions
 */
#define MIPS_CACHE_NOT_PRESENT	0x00000001
#define MIPS_CACHE_VTAG		0x00000002	/* Virtually tagged cache */
#define MIPS_CACHE_ALIASES	0x00000004	/* Cache could have aliases */
#define MIPS_CACHE_IC_F_DC	0x00000008	/* Ic can refill from D-cache */
#define MIPS_IC_SNOOPS_REMOTE	0x00000010	/* Ic snoops remote stores */
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#define MIPS_CACHE_PINDEX	0x00000020	/* Physically indexed cache */
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struct cpuinfo_mips {
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	unsigned int		udelay_val;
	unsigned int		asid_cache;
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	/*
	 * Capability and feature descriptor structure for MIPS CPU
	 */
	unsigned long		options;
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	unsigned long		ases;
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	unsigned int		processor_id;
	unsigned int		fpu_id;
	unsigned int		cputype;
	int			isa_level;
	int			tlbsize;
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	int			tlbsizevtlb;
	int			tlbsizeftlbsets;
	int			tlbsizeftlbways;
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	struct cache_desc	icache; /* Primary I-cache */
	struct cache_desc	dcache; /* Primary D or combined I/D cache */
	struct cache_desc	scache; /* Secondary cache */
	struct cache_desc	tcache; /* Tertiary/split secondary cache */
	int			srsets; /* Shadow register sets */
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	int			core;	/* physical core number */
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#ifdef CONFIG_64BIT
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	int			vmbits; /* Virtual memory size in bits */
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#endif
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#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
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	/*
	 * In the MIPS MT "SMTC" model, each TC is considered
	 * to be a "CPU" for the purposes of scheduling, but
	 * exception resources, ASID spaces, etc, are common
	 * to all TCs within the same VPE.
	 */
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	int			vpe_id;	 /* Virtual Processor number */
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#endif
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#ifdef CONFIG_MIPS_MT_SMTC
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	int			tc_id;	 /* Thread Context number */
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#endif
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	void			*data;	/* Additional data */
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	unsigned int		watch_reg_count;   /* Number that exist */
	unsigned int		watch_reg_use_cnt; /* Usable by ptrace */
#define NUM_WATCH_REGS 4
	u16			watch_reg_masks[NUM_WATCH_REGS];
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	unsigned int		kscratch_mask; /* Usable KScratch mask. */
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} __attribute__((aligned(SMP_CACHE_BYTES)));

extern struct cpuinfo_mips cpu_data[];
#define current_cpu_data cpu_data[smp_processor_id()]
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#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
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#define boot_cpu_data cpu_data[0]
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extern void cpu_probe(void);
extern void cpu_report(void);

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extern const char *__cpu_name[];
#define cpu_name_string()	__cpu_name[smp_processor_id()]

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#endif /* __ASM_CPU_INFO_H */