sky2.c 86.2 KB
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/*
 * New driver for Marvell Yukon 2 chipset.
 * Based on earlier sk98lin, and skge driver.
 *
 * This driver intentionally does not support all the features
 * of the original driver such as link fail-over and link management because
 * those should be done at higher levels.
 *
 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

/*
 * TOTEST
 *	- speed setting
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 *	- suspend/resume
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 */

#include <linux/config.h>
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#include <linux/crc32.h>
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#include <linux/kernel.h>
#include <linux/version.h>
#include <linux/module.h>
#include <linux/netdevice.h>
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#include <linux/dma-mapping.h>
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#include <linux/etherdevice.h>
#include <linux/ethtool.h>
#include <linux/pci.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/in.h>
#include <linux/delay.h>
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#include <linux/workqueue.h>
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#include <linux/if_vlan.h>
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#include <linux/prefetch.h>
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#include <linux/mii.h>
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#include <asm/irq.h>

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#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
#define SKY2_VLAN_TAG_USED 1
#endif

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#include "sky2.h"

#define DRV_NAME		"sky2"
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#define DRV_VERSION		"0.12"
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#define PFX			DRV_NAME " "

/*
 * The Yukon II chipset takes 64 bit command blocks (called list elements)
 * that are organized into three (receive, transmit, status) different rings
 * similar to Tigon3. A transmit can require several elements;
 * a receive requires one (or two if using 64 bit dma).
 */

#define is_ec_a1(hw) \
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	unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
		 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
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#define RX_LE_SIZE	    	512
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#define RX_LE_BYTES		(RX_LE_SIZE*sizeof(struct sky2_rx_le))
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#define RX_MAX_PENDING		(RX_LE_SIZE/2 - 2)
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#define RX_DEF_PENDING		RX_MAX_PENDING
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#define RX_SKB_ALIGN		8
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#define TX_RING_SIZE		512
#define TX_DEF_PENDING		(TX_RING_SIZE - 1)
#define TX_MIN_PENDING		64
#define MAX_SKB_TX_LE		(4 + 2*MAX_SKB_FRAGS)
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#define STATUS_RING_SIZE	2048	/* 2 ports * (TX + 2*RX) */
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#define STATUS_LE_BYTES		(STATUS_RING_SIZE*sizeof(struct sky2_status_le))
#define ETH_JUMBO_MTU		9000
#define TX_WATCHDOG		(5 * HZ)
#define NAPI_WEIGHT		64
#define PHY_RETRIES		1000

static const u32 default_msg =
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    NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
    | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
    | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
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static int debug = -1;		/* defaults above */
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module_param(debug, int, 0);
MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");

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static int copybreak __read_mostly = 256;
module_param(copybreak, int, 0);
MODULE_PARM_DESC(copybreak, "Receive copy threshold");

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static const struct pci_device_id sky2_id_table[] = {
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	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
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	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
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	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
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	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
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	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
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	{ 0 }
};
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MODULE_DEVICE_TABLE(pci, sky2_id_table);

/* Avoid conditionals by using array */
static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
static const unsigned rxqaddr[] = { Q_R1, Q_R2 };

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/* This driver supports yukon2 chipset only */
static const char *yukon2_name[] = {
	"XL",		/* 0xb3 */
	"EC Ultra", 	/* 0xb4 */
	"UNKNOWN",	/* 0xb5 */
	"EC",		/* 0xb6 */
	"FE",		/* 0xb7 */
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};

/* Access to external PHY */
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static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
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{
	int i;

	gma_write16(hw, port, GM_SMI_DATA, val);
	gma_write16(hw, port, GM_SMI_CTRL,
		    GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));

	for (i = 0; i < PHY_RETRIES; i++) {
		if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
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			return 0;
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		udelay(1);
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	}
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	printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
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	return -ETIMEDOUT;
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}

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static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
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{
	int i;

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	gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
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		    | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);

	for (i = 0; i < PHY_RETRIES; i++) {
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		if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
			*val = gma_read16(hw, port, GM_SMI_DATA);
			return 0;
		}

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		udelay(1);
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	}

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	return -ETIMEDOUT;
}

static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
{
	u16 v;

	if (__gm_phy_read(hw, port, reg, &v) != 0)
		printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
	return v;
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}

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static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
{
	u16 power_control;
	u32 reg1;
	int vaux;
	int ret = 0;

	pr_debug("sky2_set_power_state %d\n", state);
	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

	pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
	vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
		(power_control & PCI_PM_CAP_PME_D3cold);

	pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);

	power_control |= PCI_PM_CTRL_PME_STATUS;
	power_control &= ~(PCI_PM_CTRL_STATE_MASK);

	switch (state) {
	case PCI_D0:
		/* switch power to VCC (WA for VAUX problem) */
		sky2_write8(hw, B0_POWER_CTRL,
			    PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);

		/* disable Core Clock Division, */
		sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);

		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
			/* enable bits are inverted */
			sky2_write8(hw, B2_Y2_CLK_GATE,
				    Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
				    Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
				    Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
		else
			sky2_write8(hw, B2_Y2_CLK_GATE, 0);

		/* Turn off phy power saving */
		pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
		reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);

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		/* looks like this XL is back asswards .. */
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		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
			reg1 |= PCI_Y2_PHY1_COMA;
			if (hw->ports > 1)
				reg1 |= PCI_Y2_PHY2_COMA;
		}
		pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
		break;

	case PCI_D3hot:
	case PCI_D3cold:
		/* Turn on phy power saving */
		pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
			reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
		else
			reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
		pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);

		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
			sky2_write8(hw, B2_Y2_CLK_GATE, 0);
		else
			/* enable bits are inverted */
			sky2_write8(hw, B2_Y2_CLK_GATE,
				    Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
				    Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
				    Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);

		/* switch power to VAUX */
		if (vaux && state != PCI_D3cold)
			sky2_write8(hw, B0_POWER_CTRL,
				    (PC_VAUX_ENA | PC_VCC_ENA |
				     PC_VAUX_ON | PC_VCC_OFF));
		break;
	default:
		printk(KERN_ERR PFX "Unknown power state %d\n", state);
		ret = -1;
	}

	pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
	return ret;
}

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static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
{
	u16 reg;

	/* disable all GMAC IRQ's */
	sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
	/* disable PHY IRQs */
	gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
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	gma_write16(hw, port, GM_MC_ADDR_H1, 0);	/* clear MC hash */
	gma_write16(hw, port, GM_MC_ADDR_H2, 0);
	gma_write16(hw, port, GM_MC_ADDR_H3, 0);
	gma_write16(hw, port, GM_MC_ADDR_H4, 0);

	reg = gma_read16(hw, port, GM_RX_CTRL);
	reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
	gma_write16(hw, port, GM_RX_CTRL, reg);
}

static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
{
	struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
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	u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
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	if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
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		u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);

		ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
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			   PHY_M_EC_MAC_S_MSK);
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		ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);

		if (hw->chip_id == CHIP_ID_YUKON_EC)
			ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
		else
			ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);

		gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
	}

	ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
	if (hw->copper) {
		if (hw->chip_id == CHIP_ID_YUKON_FE) {
			/* enable automatic crossover */
			ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
		} else {
			/* disable energy detect */
			ctrl &= ~PHY_M_PC_EN_DET_MSK;

			/* enable automatic crossover */
			ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);

			if (sky2->autoneg == AUTONEG_ENABLE &&
			    hw->chip_id == CHIP_ID_YUKON_XL) {
				ctrl &= ~PHY_M_PC_DSC_MSK;
				ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
			}
		}
		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
	} else {
		/* workaround for deviation #4.88 (CRC errors) */
		/* disable Automatic Crossover */

		ctrl &= ~PHY_M_PC_MDIX_MSK;
		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);

		if (hw->chip_id == CHIP_ID_YUKON_XL) {
			/* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
			gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
			ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
			ctrl &= ~PHY_M_MAC_MD_MSK;
			ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
			gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);

			/* select page 1 to access Fiber registers */
			gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
		}
	}

	ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
	if (sky2->autoneg == AUTONEG_DISABLE)
		ctrl &= ~PHY_CT_ANE;
	else
		ctrl |= PHY_CT_ANE;

	ctrl |= PHY_CT_RESET;
	gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

	ctrl = 0;
	ct1000 = 0;
	adv = PHY_AN_CSMA;

	if (sky2->autoneg == AUTONEG_ENABLE) {
		if (hw->copper) {
			if (sky2->advertising & ADVERTISED_1000baseT_Full)
				ct1000 |= PHY_M_1000C_AFD;
			if (sky2->advertising & ADVERTISED_1000baseT_Half)
				ct1000 |= PHY_M_1000C_AHD;
			if (sky2->advertising & ADVERTISED_100baseT_Full)
				adv |= PHY_M_AN_100_FD;
			if (sky2->advertising & ADVERTISED_100baseT_Half)
				adv |= PHY_M_AN_100_HD;
			if (sky2->advertising & ADVERTISED_10baseT_Full)
				adv |= PHY_M_AN_10_FD;
			if (sky2->advertising & ADVERTISED_10baseT_Half)
				adv |= PHY_M_AN_10_HD;
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		} else		/* special defines for FIBER (88E1011S only) */
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			adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;

		/* Set Flow-control capabilities */
		if (sky2->tx_pause && sky2->rx_pause)
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			adv |= PHY_AN_PAUSE_CAP;	/* symmetric */
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		else if (sky2->rx_pause && !sky2->tx_pause)
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			adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
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		else if (!sky2->rx_pause && sky2->tx_pause)
			adv |= PHY_AN_PAUSE_ASYM;	/* local */

		/* Restart Auto-negotiation */
		ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
	} else {
		/* forced speed/duplex settings */
		ct1000 = PHY_M_1000C_MSE;

		if (sky2->duplex == DUPLEX_FULL)
			ctrl |= PHY_CT_DUP_MD;

		switch (sky2->speed) {
		case SPEED_1000:
			ctrl |= PHY_CT_SP1000;
			break;
		case SPEED_100:
			ctrl |= PHY_CT_SP100;
			break;
		}

		ctrl |= PHY_CT_RESET;
	}

	if (hw->chip_id != CHIP_ID_YUKON_FE)
		gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);

	gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
	gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

	/* Setup Phy LED's */
	ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
	ledover = 0;

	switch (hw->chip_id) {
	case CHIP_ID_YUKON_FE:
		/* on 88E3082 these bits are at 11..9 (shifted left) */
		ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;

		ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);

		/* delete ACT LED control bits */
		ctrl &= ~PHY_M_FELP_LED1_MSK;
		/* change ACT LED control to blink mode */
		ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
		gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
		break;

	case CHIP_ID_YUKON_XL:
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		pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
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		/* select page 3 to access LED control register */
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

		/* set LED Function Control register */
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		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) |	/* LINK/ACT */
							   PHY_M_LEDC_INIT_CTRL(7) |	/* 10 Mbps */
							   PHY_M_LEDC_STA1_CTRL(7) |	/* 100 Mbps */
							   PHY_M_LEDC_STA0_CTRL(7)));	/* 1000 Mbps */
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		/* set Polarity Control register */
		gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
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			     (PHY_M_POLC_LS1_P_MIX(4) |
			      PHY_M_POLC_IS0_P_MIX(4) |
			      PHY_M_POLC_LOS_CTRL(2) |
			      PHY_M_POLC_INIT_CTRL(2) |
			      PHY_M_POLC_STA1_CTRL(2) |
			      PHY_M_POLC_STA0_CTRL(2)));
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		/* restore page register */
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		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
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		break;

	default:
		/* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
		ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
		/* turn off the Rx LED (LED_RX) */
		ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
	}

	gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);

	if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
		/* turn on 100 Mbps LED (LED_LINK100) */
		ledover |= PHY_M_LED_MO_100(MO_LED_ON);
	}

	if (ledover)
		gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);

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	/* Enable phy interrupt on auto-negotiation complete (or link up) */
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	if (sky2->autoneg == AUTONEG_ENABLE)
		gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
	else
		gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
}

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/* Force a renegotiation */
static void sky2_phy_reinit(struct sky2_port *sky2)
{
	down(&sky2->phy_sema);
	sky2_phy_init(sky2->hw, sky2->port);
	up(&sky2->phy_sema);
}

493 494 495 496 497 498 499
static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
{
	struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
	u16 reg;
	int i;
	const u8 *addr = hw->dev[port]->dev_addr;

500 501
	sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
	sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
502 503 504

	sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);

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505
	if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537
		/* WA DEV_472 -- looks like crossed wires on port 2 */
		/* clear GMAC 1 Control reset */
		sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
		do {
			sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
			sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
		} while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
			 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
			 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
	}

	if (sky2->autoneg == AUTONEG_DISABLE) {
		reg = gma_read16(hw, port, GM_GP_CTRL);
		reg |= GM_GPCR_AU_ALL_DIS;
		gma_write16(hw, port, GM_GP_CTRL, reg);
		gma_read16(hw, port, GM_GP_CTRL);

		switch (sky2->speed) {
		case SPEED_1000:
			reg |= GM_GPCR_SPEED_1000;
			/* fallthru */
		case SPEED_100:
			reg |= GM_GPCR_SPEED_100;
		}

		if (sky2->duplex == DUPLEX_FULL)
			reg |= GM_GPCR_DUP_FULL;
	} else
		reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;

	if (!sky2->tx_pause && !sky2->rx_pause) {
		sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
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538 539 540
		reg |=
		    GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
	} else if (sky2->tx_pause && !sky2->rx_pause) {
541 542 543 544 545 546
		/* disable Rx flow-control */
		reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
	}

	gma_write16(hw, port, GM_GP_CTRL, reg);

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547
	sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
548

549
	down(&sky2->phy_sema);
550
	sky2_phy_init(hw, port);
551
	up(&sky2->phy_sema);
552 553 554 555 556 557

	/* MIB clear */
	reg = gma_read16(hw, port, GM_PHY_ADDR);
	gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);

	for (i = 0; i < GM_MIB_CNT_SIZE; i++)
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558
		gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
559 560 561 562 563 564 565
	gma_write16(hw, port, GM_PHY_ADDR, reg);

	/* transmit control */
	gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));

	/* receive control reg: unicast + multicast + no FCS  */
	gma_write16(hw, port, GM_RX_CTRL,
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566
		    GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
567 568 569 570 571 572 573 574 575 576 577 578 579

	/* transmit flow control */
	gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);

	/* transmit parameter */
	gma_write16(hw, port, GM_TX_PARAM,
		    TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
		    TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
		    TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
		    TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));

	/* serial mode register */
	reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
580
		GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
581

582
	if (hw->dev[port]->mtu > ETH_DATA_LEN)
583 584 585 586 587 588 589
		reg |= GM_SMOD_JUMBO_ENA;

	gma_write16(hw, port, GM_SERIAL_MODE, reg);

	/* virtual address for data */
	gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);

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590 591 592 593
	/* physical address: used for pause frames */
	gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);

	/* ignore counter overflows */
594 595 596 597 598 599
	gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
	gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
	gma_write16(hw, port, GM_TR_IRQ_MSK, 0);

	/* Configure Rx MAC FIFO */
	sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
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600
	sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
601
		     GMF_RX_CTRL_DEF);
602

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603
	/* Flush Rx MAC FIFO on any flow control or error */
604
	sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
605

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606 607
	/* Set threshold to 0xa (64 bytes)
	 *  ASF disabled so no need to do WA dev #4.30
608 609 610 611 612 613
	 */
	sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);

	/* Configure Tx MAC FIFO */
	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
	sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
614 615 616 617 618 619 620 621 622 623 624 625

	if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
		sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
		sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
		if (hw->dev[port]->mtu > ETH_DATA_LEN) {
			/* set Tx GMAC FIFO Almost Empty Threshold */
			sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
			/* Disable Store & Forward mode for TX */
			sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
		}
	}

626 627
}

628 629 630 631 632
/* Assign Ram Buffer allocation.
 * start and end are in units of 4k bytes
 * ram registers are in units of 64bit words
 */
static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
633
{
634
	u32 start, end;
635

636 637
	start = startk * 4096/8;
	end = (endk * 4096/8) - 1;
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638

639 640 641 642 643 644 645
	sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
	sky2_write32(hw, RB_ADDR(q, RB_START), start);
	sky2_write32(hw, RB_ADDR(q, RB_END), end);
	sky2_write32(hw, RB_ADDR(q, RB_WP), start);
	sky2_write32(hw, RB_ADDR(q, RB_RP), start);

	if (q == Q_R1 || q == Q_R2) {
646 647
		u32 space = (endk - startk) * 4096/8;
		u32 tp = space - space/4;
S
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648

649 650 651 652 653 654
		/* On receive queue's set the thresholds
		 * give receiver priority when > 3/4 full
		 * send pause when down to 2K
		 */
		sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
		sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
S
Stephen Hemminger 已提交
655

656 657 658
		tp = space - 2048/8;
		sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
		sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
659 660 661 662 663 664 665 666
	} else {
		/* Enable store & forward on Tx queue's because
		 * Tx FIFO is only 1K on Yukon
		 */
		sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
	}

	sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
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667
	sky2_read8(hw, RB_ADDR(q, RB_CTRL));
668 669 670
}

/* Setup Bus Memory Interface */
671
static void sky2_qset(struct sky2_hw *hw, u16 q)
672 673 674 675
{
	sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
	sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
	sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
676
	sky2_write32(hw, Q_ADDR(q, Q_WM),  BMU_WM_DEFAULT);
677 678 679 680 681
}

/* Setup prefetch unit registers. This is the interface between
 * hardware and driver list elements
 */
682
static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
683 684 685 686 687 688 689 690
				      u64 addr, u32 last)
{
	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
	sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
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Stephen Hemminger 已提交
691 692

	sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
693 694
}

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695 696 697 698 699 700 701
static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
{
	struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;

	sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
	return le;
}
702 703

/*
S
shemminger@osdl.org 已提交
704
 * This is a workaround code taken from SysKonnect sk98lin driver
S
Stephen Hemminger 已提交
705
 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
706 707 708 709
 */
static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
				u16 idx, u16 *last, u16 size)
{
710
	wmb();
711 712 713 714 715
	if (is_ec_a1(hw) && idx < *last) {
		u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));

		if (hwget == 0) {
			/* Start prefetching again */
S
Stephen Hemminger 已提交
716
			sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
717 718 719
			goto setnew;
		}

S
Stephen Hemminger 已提交
720
		if (hwget == size - 1) {
721 722 723 724 725
			/* set watermark to one list element */
			sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);

			/* set put index to first list element */
			sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
S
Stephen Hemminger 已提交
726 727 728
		} else		/* have hardware go to end of list */
			sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
				     size - 1);
729
	} else {
S
Stephen Hemminger 已提交
730
setnew:
731 732
		sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
	}
733
	*last = idx;
734
	mmiowb();
735 736
}

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737

738 739 740 741 742 743 744
static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
{
	struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
	sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
	return le;
}

745 746 747 748 749 750
/* Return high part of DMA address (could be 32 or 64 bit) */
static inline u32 high32(dma_addr_t a)
{
	return (a >> 16) >> 16;
}

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Stephen Hemminger 已提交
751
/* Build description to hardware about buffer */
752
static inline void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
753 754
{
	struct sky2_rx_le *le;
755 756
	u32 hi = high32(map);
	u16 len = sky2->rx_bufsize;
757

S
Stephen Hemminger 已提交
758
	if (sky2->rx_addr64 != hi) {
759
		le = sky2_next_rx(sky2);
S
Stephen Hemminger 已提交
760
		le->addr = cpu_to_le32(hi);
761 762
		le->ctrl = 0;
		le->opcode = OP_ADDR64 | HW_OWNER;
763
		sky2->rx_addr64 = high32(map + len);
764
	}
S
Stephen Hemminger 已提交
765

766
	le = sky2_next_rx(sky2);
767 768
	le->addr = cpu_to_le32((u32) map);
	le->length = cpu_to_le16(len);
769 770 771 772
	le->ctrl = 0;
	le->opcode = OP_PACKET | HW_OWNER;
}

S
Stephen Hemminger 已提交
773

774 775 776 777
/* Tell chip where to start receive checksum.
 * Actually has two checksums, but set both same to avoid possible byte
 * order problems.
 */
S
Stephen Hemminger 已提交
778
static void rx_set_checksum(struct sky2_port *sky2)
779 780 781 782
{
	struct sky2_rx_le *le;

	le = sky2_next_rx(sky2);
S
Stephen Hemminger 已提交
783
	le->addr = (ETH_HLEN << 16) | ETH_HLEN;
784 785
	le->ctrl = 0;
	le->opcode = OP_TCPSTART | HW_OWNER;
S
Stephen Hemminger 已提交
786 787 788 789

	sky2_write32(sky2->hw,
		     Q_ADDR(rxqaddr[sky2->port], Q_CSR),
		     sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
790 791 792

}

793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824
/*
 * The RX Stop command will not work for Yukon-2 if the BMU does not
 * reach the end of packet and since we can't make sure that we have
 * incoming data, we must reset the BMU while it is not doing a DMA
 * transfer. Since it is possible that the RX path is still active,
 * the RX RAM buffer will be stopped first, so any possible incoming
 * data will not trigger a DMA. After the RAM buffer is stopped, the
 * BMU is polled until any DMA in progress is ended and only then it
 * will be reset.
 */
static void sky2_rx_stop(struct sky2_port *sky2)
{
	struct sky2_hw *hw = sky2->hw;
	unsigned rxq = rxqaddr[sky2->port];
	int i;

	/* disable the RAM Buffer receive queue */
	sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);

	for (i = 0; i < 0xffff; i++)
		if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
		    == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
			goto stopped;

	printk(KERN_WARNING PFX "%s: receiver stop failed\n",
	       sky2->netdev->name);
stopped:
	sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);

	/* reset the Rx prefetch unit */
	sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
}
S
Stephen Hemminger 已提交
825

S
shemminger@osdl.org 已提交
826
/* Clean out receive buffer area, assumes receiver hardware stopped */
827 828 829 830 831
static void sky2_rx_clean(struct sky2_port *sky2)
{
	unsigned i;

	memset(sky2->rx_le, 0, RX_LE_BYTES);
S
Stephen Hemminger 已提交
832
	for (i = 0; i < sky2->rx_pending; i++) {
833 834 835
		struct ring_info *re = sky2->rx_ring + i;

		if (re->skb) {
S
Stephen Hemminger 已提交
836
			pci_unmap_single(sky2->hw->pdev,
837
					 re->mapaddr, sky2->rx_bufsize,
838 839 840 841 842 843 844
					 PCI_DMA_FROMDEVICE);
			kfree_skb(re->skb);
			re->skb = NULL;
		}
	}
}

845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862
/* Basic MII support */
static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
	struct mii_ioctl_data *data = if_mii(ifr);
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
	int err = -EOPNOTSUPP;

	if (!netif_running(dev))
		return -ENODEV;	/* Phy still in reset */

	switch(cmd) {
	case SIOCGMIIPHY:
		data->phy_id = PHY_ADDR_MARV;

		/* fallthru */
	case SIOCGMIIREG: {
		u16 val = 0;
863 864

		down(&sky2->phy_sema);
865
		err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
866 867
		up(&sky2->phy_sema);

868 869 870 871 872 873 874 875
		data->val_out = val;
		break;
	}

	case SIOCSMIIREG:
		if (!capable(CAP_NET_ADMIN))
			return -EPERM;

876
		down(&sky2->phy_sema);
877 878
		err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
				   data->val_in);
879
		up(&sky2->phy_sema);
880 881 882 883 884
		break;
	}
	return err;
}

885 886 887 888 889 890 891
#ifdef SKY2_VLAN_TAG_USED
static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
	u16 port = sky2->port;

892
	spin_lock(&sky2->tx_lock);
893 894 895 896 897

	sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
	sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
	sky2->vlgrp = grp;

898
	spin_unlock(&sky2->tx_lock);
899 900 901 902 903 904 905 906
}

static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
	u16 port = sky2->port;

907
	spin_lock(&sky2->tx_lock);
908 909 910 911 912 913

	sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
	sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
	if (sky2->vlgrp)
		sky2->vlgrp->vlan_devices[vid] = NULL;

914
	spin_unlock(&sky2->tx_lock);
915 916 917
}
#endif

918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937
/*
 * It appears the hardware has a bug in the FIFO logic that
 * cause it to hang if the FIFO gets overrun and the receive buffer
 * is not aligned. ALso alloc_skb() won't align properly if slab
 * debugging is enabled.
 */
static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
{
	struct sk_buff *skb;

	skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
	if (likely(skb)) {
		unsigned long p	= (unsigned long) skb->data;
		skb_reserve(skb,
			((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p);
	}

	return skb;
}

938 939 940 941 942 943
/*
 * Allocate and setup receiver buffer pool.
 * In case of 64 bit dma, there are 2X as many list elements
 * available as ring entries
 * and need to reserve one list element so we don't wrap around.
 */
944
static int sky2_rx_start(struct sky2_port *sky2)
945
{
946 947 948
	struct sky2_hw *hw = sky2->hw;
	unsigned rxq = rxqaddr[sky2->port];
	int i;
949

950
	sky2->rx_put = sky2->rx_next = 0;
951
	sky2_qset(hw, rxq);
952 953 954
	sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);

	rx_set_checksum(sky2);
S
Stephen Hemminger 已提交
955
	for (i = 0; i < sky2->rx_pending; i++) {
956 957
		struct ring_info *re = sky2->rx_ring + i;

958
		re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
959 960 961
		if (!re->skb)
			goto nomem;

962
		re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
963 964
					     sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
		sky2_rx_add(sky2, re->mapaddr);
965 966
	}

967 968 969
	/* Tell chip about available buffers */
	sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
	sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989
	return 0;
nomem:
	sky2_rx_clean(sky2);
	return -ENOMEM;
}

/* Bring up network interface. */
static int sky2_up(struct net_device *dev)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
	unsigned port = sky2->port;
	u32 ramsize, rxspace;
	int err = -ENOMEM;

	if (netif_msg_ifup(sky2))
		printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);

	/* must be power of 2 */
	sky2->tx_le = pci_alloc_consistent(hw->pdev,
S
Stephen Hemminger 已提交
990 991
					   TX_RING_SIZE *
					   sizeof(struct sky2_tx_le),
992 993 994 995
					   &sky2->tx_le_map);
	if (!sky2->tx_le)
		goto err_out;

996
	sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
997 998 999 1000 1001 1002 1003 1004 1005 1006 1007
				GFP_KERNEL);
	if (!sky2->tx_ring)
		goto err_out;
	sky2->tx_prod = sky2->tx_cons = 0;

	sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
					   &sky2->rx_le_map);
	if (!sky2->rx_le)
		goto err_out;
	memset(sky2->rx_le, 0, RX_LE_BYTES);

1008
	sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
1009 1010 1011 1012 1013 1014
				GFP_KERNEL);
	if (!sky2->rx_ring)
		goto err_out;

	sky2_mac_init(hw, port);

1015 1016 1017 1018 1019 1020 1021 1022 1023 1024
	/* Determine available ram buffer space (in 4K blocks).
	 * Note: not sure about the FE setting below yet
	 */
	if (hw->chip_id == CHIP_ID_YUKON_FE)
		ramsize = 4;
	else
		ramsize = sky2_read8(hw, B2_E_0);

	/* Give transmitter one third (rounded up) */
	rxspace = ramsize - (ramsize + 2) / 3;
1025 1026

	sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1027
	sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
1028

S
Stephen Hemminger 已提交
1029 1030 1031 1032
	/* Make sure SyncQ is disabled */
	sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
		    RB_RST_SET);

1033
	sky2_qset(hw, txqaddr[port]);
1034 1035 1036 1037
	if (hw->chip_id == CHIP_ID_YUKON_EC_U)
		sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);


1038 1039
	sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
			   TX_RING_SIZE - 1);
1040

1041
	err = sky2_rx_start(sky2);
1042 1043 1044 1045 1046 1047 1048 1049 1050
	if (err)
		goto err_out;

	/* Enable interrupts from phy/mac for port */
	hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
	sky2_write32(hw, B0_IMSK, hw->intr_mask);
	return 0;

err_out:
1051
	if (sky2->rx_le) {
1052 1053
		pci_free_consistent(hw->pdev, RX_LE_BYTES,
				    sky2->rx_le, sky2->rx_le_map);
1054 1055 1056
		sky2->rx_le = NULL;
	}
	if (sky2->tx_le) {
1057 1058 1059
		pci_free_consistent(hw->pdev,
				    TX_RING_SIZE * sizeof(struct sky2_tx_le),
				    sky2->tx_le, sky2->tx_le_map);
1060 1061 1062 1063
		sky2->tx_le = NULL;
	}
	kfree(sky2->tx_ring);
	kfree(sky2->rx_ring);
1064

1065 1066
	sky2->tx_ring = NULL;
	sky2->rx_ring = NULL;
1067 1068 1069
	return err;
}

S
Stephen Hemminger 已提交
1070 1071 1072
/* Modular subtraction in ring */
static inline int tx_dist(unsigned tail, unsigned head)
{
1073
	return (head - tail) % TX_RING_SIZE;
S
Stephen Hemminger 已提交
1074
}
1075

S
Stephen Hemminger 已提交
1076 1077
/* Number of list elements available for next tx */
static inline int tx_avail(const struct sky2_port *sky2)
1078
{
S
Stephen Hemminger 已提交
1079
	return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1080 1081
}

S
Stephen Hemminger 已提交
1082 1083
/* Estimate of number of transmit list elements required */
static inline unsigned tx_le_req(const struct sk_buff *skb)
1084
{
S
Stephen Hemminger 已提交
1085 1086 1087 1088 1089 1090 1091 1092
	unsigned count;

	count = sizeof(dma_addr_t) / sizeof(u32);
	count += skb_shinfo(skb)->nr_frags * count;

	if (skb_shinfo(skb)->tso_size)
		++count;

1093
	if (skb->ip_summed == CHECKSUM_HW)
S
Stephen Hemminger 已提交
1094 1095 1096
		++count;

	return count;
1097 1098
}

S
Stephen Hemminger 已提交
1099 1100 1101 1102 1103
/*
 * Put one packet in ring for transmit.
 * A single packet can generate multiple list elements, and
 * the number of ring elements will probably be less than the number
 * of list elements used.
1104 1105
 *
 * No BH disabling for tx_lock here (like tg3)
S
Stephen Hemminger 已提交
1106
 */
1107 1108 1109 1110
static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
1111
	struct sky2_tx_le *le = NULL;
1112
	struct tx_ring_info *re;
1113 1114 1115 1116 1117 1118
	unsigned i, len;
	dma_addr_t mapping;
	u32 addr64;
	u16 mss;
	u8 ctrl;

1119
	if (!spin_trylock(&sky2->tx_lock))
1120 1121
		return NETDEV_TX_LOCKED;

S
Stephen Hemminger 已提交
1122
	if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1123 1124 1125 1126 1127 1128 1129 1130
		/* There is a known but harmless race with lockless tx
		 * and netif_stop_queue.
		 */
		if (!netif_queue_stopped(dev)) {
			netif_stop_queue(dev);
			printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
			       dev->name);
		}
1131
		spin_unlock(&sky2->tx_lock);
1132 1133 1134 1135

		return NETDEV_TX_BUSY;
	}

S
Stephen Hemminger 已提交
1136
	if (unlikely(netif_msg_tx_queued(sky2)))
1137 1138 1139 1140 1141
		printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
		       dev->name, sky2->tx_prod, skb->len);

	len = skb_headlen(skb);
	mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1142
	addr64 = high32(mapping);
S
Stephen Hemminger 已提交
1143 1144 1145

	re = sky2->tx_ring + sky2->tx_prod;

1146 1147
	/* Send high bits if changed or crosses boundary */
	if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
S
Stephen Hemminger 已提交
1148 1149 1150 1151
		le = get_tx_le(sky2);
		le->tx.addr = cpu_to_le32(addr64);
		le->ctrl = 0;
		le->opcode = OP_ADDR64 | HW_OWNER;
1152
		sky2->tx_addr64 = high32(mapping + len);
S
Stephen Hemminger 已提交
1153
	}
1154 1155 1156

	/* Check for TCP Segmentation Offload */
	mss = skb_shinfo(skb)->tso_size;
S
Stephen Hemminger 已提交
1157
	if (mss != 0) {
1158 1159 1160
		/* just drop the packet if non-linear expansion fails */
		if (skb_header_cloned(skb) &&
		    pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
S
Stephen Hemminger 已提交
1161 1162
			dev_kfree_skb_any(skb);
			goto out_unlock;
1163 1164 1165 1166 1167
		}

		mss += ((skb->h.th->doff - 5) * 4);	/* TCP options */
		mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
		mss += ETH_HLEN;
S
Stephen Hemminger 已提交
1168
	}
1169

S
Stephen Hemminger 已提交
1170
	if (mss != sky2->tx_last_mss) {
1171 1172
		le = get_tx_le(sky2);
		le->tx.tso.size = cpu_to_le16(mss);
S
Stephen Hemminger 已提交
1173
		le->tx.tso.rsvd = 0;
1174 1175
		le->opcode = OP_LRGLEN | HW_OWNER;
		le->ctrl = 0;
S
Stephen Hemminger 已提交
1176
		sky2->tx_last_mss = mss;
1177 1178 1179
	}

	ctrl = 0;
1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195
#ifdef SKY2_VLAN_TAG_USED
	/* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
	if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
		if (!le) {
			le = get_tx_le(sky2);
			le->tx.addr = 0;
			le->opcode = OP_VLAN|HW_OWNER;
			le->ctrl = 0;
		} else
			le->opcode |= OP_VLAN;
		le->length = cpu_to_be16(vlan_tx_tag_get(skb));
		ctrl |= INS_VLAN;
	}
#endif

	/* Handle TCP checksum offload */
1196
	if (skb->ip_summed == CHECKSUM_HW) {
S
Stephen Hemminger 已提交
1197 1198
		u16 hdr = skb->h.raw - skb->data;
		u16 offset = hdr + skb->csum;
1199 1200 1201 1202 1203 1204 1205

		ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
		if (skb->nh.iph->protocol == IPPROTO_UDP)
			ctrl |= UDPTCP;

		le = get_tx_le(sky2);
		le->tx.csum.start = cpu_to_le16(hdr);
S
Stephen Hemminger 已提交
1206 1207
		le->tx.csum.offset = cpu_to_le16(offset);
		le->length = 0;	/* initial checksum value */
1208
		le->ctrl = 1;	/* one packet */
S
Stephen Hemminger 已提交
1209
		le->opcode = OP_TCPLISW | HW_OWNER;
1210 1211 1212 1213 1214 1215
	}

	le = get_tx_le(sky2);
	le->tx.addr = cpu_to_le32((u32) mapping);
	le->length = cpu_to_le16(len);
	le->ctrl = ctrl;
S
Stephen Hemminger 已提交
1216
	le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1217

S
Stephen Hemminger 已提交
1218
	/* Record the transmit mapping info */
1219
	re->skb = skb;
1220
	pci_unmap_addr_set(re, mapaddr, mapping);
1221 1222 1223

	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1224
		struct tx_ring_info *fre;
1225 1226 1227

		mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
				       frag->size, PCI_DMA_TODEVICE);
S
Stephen Hemminger 已提交
1228 1229 1230 1231 1232 1233 1234
		addr64 = (mapping >> 16) >> 16;
		if (addr64 != sky2->tx_addr64) {
			le = get_tx_le(sky2);
			le->tx.addr = cpu_to_le32(addr64);
			le->ctrl = 0;
			le->opcode = OP_ADDR64 | HW_OWNER;
			sky2->tx_addr64 = addr64;
1235 1236 1237 1238 1239 1240
		}

		le = get_tx_le(sky2);
		le->tx.addr = cpu_to_le32((u32) mapping);
		le->length = cpu_to_le16(frag->size);
		le->ctrl = ctrl;
S
Stephen Hemminger 已提交
1241
		le->opcode = OP_BUFFER | HW_OWNER;
1242

S
Stephen Hemminger 已提交
1243 1244
		fre = sky2->tx_ring
		    + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1245
		pci_unmap_addr_set(fre, mapaddr, mapping);
1246
	}
1247

S
Stephen Hemminger 已提交
1248
	re->idx = sky2->tx_prod;
1249 1250
	le->ctrl |= EOP;

S
shemminger@osdl.org 已提交
1251
	sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
1252 1253
		     &sky2->tx_last_put, TX_RING_SIZE);

1254
	if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1255
		netif_stop_queue(dev);
S
Stephen Hemminger 已提交
1256 1257

out_unlock:
1258
	spin_unlock(&sky2->tx_lock);
1259 1260 1261 1262 1263 1264

	dev->trans_start = jiffies;
	return NETDEV_TX_OK;
}

/*
S
Stephen Hemminger 已提交
1265 1266 1267
 * Free ring elements from starting at tx_cons until "done"
 *
 * NB: the hardware will tell us about partial completion of multi-part
S
shemminger@osdl.org 已提交
1268
 *     buffers; these are deferred until completion.
1269
 */
1270
static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1271
{
1272
	struct net_device *dev = sky2->netdev;
1273 1274
	struct pci_dev *pdev = sky2->hw->pdev;
	u16 nxt, put;
S
Stephen Hemminger 已提交
1275
	unsigned i;
1276

1277
	BUG_ON(done >= TX_RING_SIZE);
1278

1279
	if (unlikely(netif_msg_tx_done(sky2)))
S
shemminger@osdl.org 已提交
1280
		printk(KERN_DEBUG "%s: tx done, up to %u\n",
1281
		       dev->name, done);
1282

1283 1284 1285
	for (put = sky2->tx_cons; put != done; put = nxt) {
		struct tx_ring_info *re = sky2->tx_ring + put;
		struct sk_buff *skb = re->skb;
1286

1287 1288
  		nxt = re->idx;
		BUG_ON(nxt >= TX_RING_SIZE);
S
Stephen Hemminger 已提交
1289
		prefetch(sky2->tx_ring + nxt);
1290

S
Stephen Hemminger 已提交
1291
		/* Check for partial status */
1292 1293
		if (tx_dist(put, done) < tx_dist(put, nxt))
			break;
S
Stephen Hemminger 已提交
1294 1295

		skb = re->skb;
1296
		pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1297
				 skb_headlen(skb), PCI_DMA_TODEVICE);
S
Stephen Hemminger 已提交
1298 1299

		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1300
			struct tx_ring_info *fre;
1301 1302 1303
			fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
			pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
  				       skb_shinfo(skb)->frags[i].size,
1304
				       PCI_DMA_TODEVICE);
1305 1306 1307
		}

		dev_kfree_skb_any(skb);
S
Stephen Hemminger 已提交
1308 1309
	}

1310 1311
	spin_lock(&sky2->tx_lock);
	sky2->tx_cons = put;
S
Stephen Hemminger 已提交
1312
	if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1313 1314 1315 1316 1317
		netif_wake_queue(dev);
	spin_unlock(&sky2->tx_lock);
}

/* Cleanup all untransmitted buffers, assume transmitter not running */
1318
static void sky2_tx_clean(struct sky2_port *sky2)
1319
{
1320
	sky2_tx_complete(sky2, sky2->tx_prod);
1321 1322 1323 1324 1325 1326 1327 1328 1329 1330
}

/* Network shutdown */
static int sky2_down(struct net_device *dev)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
	unsigned port = sky2->port;
	u16 ctrl;

1331 1332 1333 1334
	/* Never really got started! */
	if (!sky2->tx_le)
		return 0;

1335 1336 1337
	if (netif_msg_ifdown(sky2))
		printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);

1338
	/* Stop more packets from being queued */
1339 1340
	netif_stop_queue(dev);

1341 1342 1343 1344 1345 1346
	/* Disable port IRQ */
	local_irq_disable();
	hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
	sky2_write32(hw, B0_IMSK, hw->intr_mask);
	local_irq_enable();

1347
	flush_scheduled_work();
1348

S
Stephen Hemminger 已提交
1349 1350
	sky2_phy_reset(hw, port);

1351 1352 1353 1354 1355
	/* Stop transmitter */
	sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
	sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));

	sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
S
Stephen Hemminger 已提交
1356
		     RB_RST_SET | RB_DIS_OP_MD);
1357 1358

	ctrl = gma_read16(hw, port, GM_GP_CTRL);
S
Stephen Hemminger 已提交
1359
	ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1360 1361 1362 1363 1364
	gma_write16(hw, port, GM_GP_CTRL, ctrl);

	sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);

	/* Workaround shared GMAC reset */
S
Stephen Hemminger 已提交
1365 1366
	if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
	      && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377
		sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);

	/* Disable Force Sync bit and Enable Alloc bit */
	sky2_write8(hw, SK_REG(port, TXA_CTRL),
		    TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);

	/* Stop Interval Timer and Limit Counter of Tx Arbiter */
	sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
	sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);

	/* Reset the PCI FIFO of the async Tx queue */
S
Stephen Hemminger 已提交
1378 1379
	sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
		     BMU_RST_SET | BMU_FIFO_RST);
1380 1381 1382 1383 1384 1385 1386

	/* Reset the Tx prefetch units */
	sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
		     PREF_UNIT_RST_SET);

	sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);

1387
	sky2_rx_stop(sky2);
1388 1389 1390 1391

	sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);

S
shemminger@osdl.org 已提交
1392
	/* turn off LED's */
1393 1394
	sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);

1395 1396
	synchronize_irq(hw->pdev->irq);

1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408
	sky2_tx_clean(sky2);
	sky2_rx_clean(sky2);

	pci_free_consistent(hw->pdev, RX_LE_BYTES,
			    sky2->rx_le, sky2->rx_le_map);
	kfree(sky2->rx_ring);

	pci_free_consistent(hw->pdev,
			    TX_RING_SIZE * sizeof(struct sky2_tx_le),
			    sky2->tx_le, sky2->tx_le_map);
	kfree(sky2->tx_ring);

1409 1410 1411 1412 1413 1414
	sky2->tx_le = NULL;
	sky2->rx_le = NULL;

	sky2->rx_ring = NULL;
	sky2->tx_ring = NULL;

1415 1416 1417 1418 1419
	return 0;
}

static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
{
S
Stephen Hemminger 已提交
1420 1421 1422
	if (!hw->copper)
		return SPEED_1000;

1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442
	if (hw->chip_id == CHIP_ID_YUKON_FE)
		return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;

	switch (aux & PHY_M_PS_SPEED_MSK) {
	case PHY_M_PS_SPEED_1000:
		return SPEED_1000;
	case PHY_M_PS_SPEED_100:
		return SPEED_100;
	default:
		return SPEED_10;
	}
}

static void sky2_link_up(struct sky2_port *sky2)
{
	struct sky2_hw *hw = sky2->hw;
	unsigned port = sky2->port;
	u16 reg;

	/* Enable Transmit FIFO Underrun */
S
Stephen Hemminger 已提交
1443
	sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459

	reg = gma_read16(hw, port, GM_GP_CTRL);
	if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
		reg |= GM_GPCR_DUP_FULL;

	/* enable Rx/Tx */
	reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
	gma_write16(hw, port, GM_GP_CTRL, reg);
	gma_read16(hw, port, GM_GP_CTRL);

	gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);

	netif_carrier_on(sky2->netdev);
	netif_wake_queue(sky2->netdev);

	/* Turn on link LED */
S
Stephen Hemminger 已提交
1460
	sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1461 1462
		    LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);

S
Stephen Hemminger 已提交
1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476
	if (hw->chip_id == CHIP_ID_YUKON_XL) {
		u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) |	/* LINK/ACT */
			     PHY_M_LEDC_INIT_CTRL(sky2->speed ==
						  SPEED_10 ? 7 : 0) |
			     PHY_M_LEDC_STA1_CTRL(sky2->speed ==
						  SPEED_100 ? 7 : 0) |
			     PHY_M_LEDC_STA0_CTRL(sky2->speed ==
						  SPEED_1000 ? 7 : 0));
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
	}

1477 1478
	if (netif_msg_link(sky2))
		printk(KERN_INFO PFX
S
shemminger@osdl.org 已提交
1479
		       "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1480 1481 1482
		       sky2->netdev->name, sky2->speed,
		       sky2->duplex == DUPLEX_FULL ? "full" : "half",
		       (sky2->tx_pause && sky2->rx_pause) ? "both" :
S
Stephen Hemminger 已提交
1483
		       sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501
}

static void sky2_link_down(struct sky2_port *sky2)
{
	struct sky2_hw *hw = sky2->hw;
	unsigned port = sky2->port;
	u16 reg;

	gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);

	reg = gma_read16(hw, port, GM_GP_CTRL);
	reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
	gma_write16(hw, port, GM_GP_CTRL, reg);
	gma_read16(hw, port, GM_GP_CTRL);	/* PCI post */

	if (sky2->rx_pause && !sky2->tx_pause) {
		/* restore Asymmetric Pause bit */
		gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
S
Stephen Hemminger 已提交
1502 1503
			     gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
			     | PHY_M_AN_ASP);
1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516
	}

	netif_carrier_off(sky2->netdev);
	netif_stop_queue(sky2->netdev);

	/* Turn on link LED */
	sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);

	if (netif_msg_link(sky2))
		printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
	sky2_phy_init(hw, port);
}

S
Stephen Hemminger 已提交
1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561
static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
{
	struct sky2_hw *hw = sky2->hw;
	unsigned port = sky2->port;
	u16 lpa;

	lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);

	if (lpa & PHY_M_AN_RF) {
		printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
		return -1;
	}

	if (hw->chip_id != CHIP_ID_YUKON_FE &&
	    gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
		printk(KERN_ERR PFX "%s: master/slave fault",
		       sky2->netdev->name);
		return -1;
	}

	if (!(aux & PHY_M_PS_SPDUP_RES)) {
		printk(KERN_ERR PFX "%s: speed/duplex mismatch",
		       sky2->netdev->name);
		return -1;
	}

	sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;

	sky2->speed = sky2_phy_speed(hw, aux);

	/* Pause bits are offset (9..8) */
	if (hw->chip_id == CHIP_ID_YUKON_XL)
		aux >>= 6;

	sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
	sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;

	if ((sky2->tx_pause || sky2->rx_pause)
	    && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
		sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
	else
		sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);

	return 0;
}
1562 1563

/*
1564
 * Interrupt from PHY are handled outside of interrupt context
1565 1566 1567
 * because accessing phy registers requires spin wait which might
 * cause excess interrupt latency.
 */
1568
static void sky2_phy_task(void *arg)
1569
{
1570
	struct sky2_port *sky2 = arg;
1571 1572 1573
	struct sky2_hw *hw = sky2->hw;
	u16 istatus, phystat;

1574
	down(&sky2->phy_sema);
S
Stephen Hemminger 已提交
1575 1576
	istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
	phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1577 1578 1579 1580 1581 1582

	if (netif_msg_intr(sky2))
		printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
		       sky2->netdev->name, istatus, phystat);

	if (istatus & PHY_M_IS_AN_COMPL) {
S
Stephen Hemminger 已提交
1583 1584 1585 1586
		if (sky2_autoneg_done(sky2, phystat) == 0)
			sky2_link_up(sky2);
		goto out;
	}
1587

S
Stephen Hemminger 已提交
1588 1589
	if (istatus & PHY_M_IS_LSP_CHANGE)
		sky2->speed = sky2_phy_speed(hw, phystat);
1590

S
Stephen Hemminger 已提交
1591 1592 1593
	if (istatus & PHY_M_IS_DUP_CHANGE)
		sky2->duplex =
		    (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1594

S
Stephen Hemminger 已提交
1595 1596
	if (istatus & PHY_M_IS_LST_CHANGE) {
		if (phystat & PHY_M_PS_LINK_UP)
1597
			sky2_link_up(sky2);
S
Stephen Hemminger 已提交
1598 1599
		else
			sky2_link_down(sky2);
1600
	}
S
Stephen Hemminger 已提交
1601
out:
1602
	up(&sky2->phy_sema);
1603 1604

	local_irq_disable();
S
Stephen Hemminger 已提交
1605
	hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1606 1607 1608 1609 1610 1611 1612
	sky2_write32(hw, B0_IMSK, hw->intr_mask);
	local_irq_enable();
}

static void sky2_tx_timeout(struct net_device *dev)
{
	struct sky2_port *sky2 = netdev_priv(dev);
1613 1614
	struct sky2_hw *hw = sky2->hw;
	unsigned txq = txqaddr[sky2->port];
1615 1616 1617 1618

	if (netif_msg_timer(sky2))
		printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);

1619 1620 1621 1622 1623 1624
	netif_stop_queue(dev);

	sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
	sky2_read32(hw, Q_ADDR(txq, Q_CSR));

	sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1625 1626

	sky2_tx_clean(sky2);
1627 1628 1629 1630 1631

	sky2_qset(hw, txq);
	sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);

	netif_wake_queue(dev);
1632 1633
}

1634 1635 1636 1637 1638 1639 1640 1641

#define roundup(x, y)   ((((x)+((y)-1))/(y))*(y))
/* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */
static inline unsigned sky2_buf_size(int mtu)
{
	return roundup(mtu + ETH_HLEN + 4, 8);
}

1642 1643
static int sky2_change_mtu(struct net_device *dev, int new_mtu)
{
1644 1645 1646 1647
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
	int err;
	u16 ctl, mode;
1648 1649 1650 1651

	if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
		return -EINVAL;

1652 1653 1654
	if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
		return -EINVAL;

1655 1656 1657 1658 1659 1660 1661
	if (!netif_running(dev)) {
		dev->mtu = new_mtu;
		return 0;
	}

	sky2_write32(hw, B0_IMSK, 0);

1662 1663 1664 1665
	dev->trans_start = jiffies;	/* prevent tx timeout */
	netif_stop_queue(dev);
	netif_poll_disable(hw->dev[0]);

1666 1667 1668 1669
	ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
	gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
	sky2_rx_stop(sky2);
	sky2_rx_clean(sky2);
1670 1671

	dev->mtu = new_mtu;
1672
	sky2->rx_bufsize = sky2_buf_size(new_mtu);
1673 1674 1675 1676 1677 1678 1679
	mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
		GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);

	if (dev->mtu > ETH_DATA_LEN)
		mode |= GM_SMOD_JUMBO_ENA;

	gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1680

1681
	sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1682

1683 1684
	err = sky2_rx_start(sky2);
	sky2_write32(hw, B0_IMSK, hw->intr_mask);
1685

1686 1687 1688 1689 1690 1691 1692 1693 1694
	if (err)
		dev_close(dev);
	else {
		gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);

		netif_poll_enable(hw->dev[0]);
		netif_wake_queue(dev);
	}

1695 1696 1697 1698 1699 1700
	return err;
}

/*
 * Receive one packet.
 * For small packets or errors, just reuse existing skb.
S
shemminger@osdl.org 已提交
1701
 * For larger packets, get new buffer.
1702
 */
1703
static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1704 1705 1706
				    u16 length, u32 status)
{
	struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1707
	struct sk_buff *skb = NULL;
1708 1709 1710

	if (unlikely(netif_msg_rx_status(sky2)))
		printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1711
		       sky2->netdev->name, sky2->rx_next, status, length);
1712

S
Stephen Hemminger 已提交
1713
	sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
S
Stephen Hemminger 已提交
1714
	prefetch(sky2->rx_ring + sky2->rx_next);
1715

1716
	if (status & GMR_FS_ANY_ERR)
1717 1718
		goto error;

1719 1720 1721
	if (!(status & GMR_FS_RX_OK))
		goto resubmit;

1722 1723 1724
	if ((status >> 16) != length || length > sky2->rx_bufsize)
		goto oversize;

1725
	if (length < copybreak) {
1726 1727
		skb = alloc_skb(length + 2, GFP_ATOMIC);
		if (!skb)
S
Stephen Hemminger 已提交
1728 1729
			goto resubmit;

1730
		skb_reserve(skb, 2);
S
Stephen Hemminger 已提交
1731 1732
		pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
					    length, PCI_DMA_FROMDEVICE);
1733
		memcpy(skb->data, re->skb->data, length);
1734 1735
		skb->ip_summed = re->skb->ip_summed;
		skb->csum = re->skb->csum;
S
Stephen Hemminger 已提交
1736 1737 1738
		pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
					       length, PCI_DMA_FROMDEVICE);
	} else {
1739 1740
		struct sk_buff *nskb;

1741
		nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
S
Stephen Hemminger 已提交
1742 1743
		if (!nskb)
			goto resubmit;
1744

S
Stephen Hemminger 已提交
1745
		skb = re->skb;
1746
		re->skb = nskb;
S
Stephen Hemminger 已提交
1747
		pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1748
				 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
S
Stephen Hemminger 已提交
1749
		prefetch(skb->data);
1750

S
Stephen Hemminger 已提交
1751
		re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1752
					     sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
S
Stephen Hemminger 已提交
1753
	}
1754

1755
	skb_put(skb, length);
S
Stephen Hemminger 已提交
1756
resubmit:
1757
	re->skb->ip_summed = CHECKSUM_NONE;
1758
	sky2_rx_add(sky2, re->mapaddr);
1759

1760 1761 1762 1763
	/* Tell receiver about new buffers. */
	sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
		     &sky2->rx_last_put, RX_LE_SIZE);

1764 1765
	return skb;

1766 1767 1768 1769
oversize:
	++sky2->net_stats.rx_over_errors;
	goto resubmit;

1770
error:
1771 1772
	++sky2->net_stats.rx_errors;

1773 1774 1775
	if (netif_msg_rx_err(sky2))
		printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
		       sky2->netdev->name, status, length);
S
Stephen Hemminger 已提交
1776 1777

	if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1778 1779 1780 1781 1782
		sky2->net_stats.rx_length_errors++;
	if (status & GMR_FS_FRAGMENT)
		sky2->net_stats.rx_frame_errors++;
	if (status & GMR_FS_CRC_ERR)
		sky2->net_stats.rx_crc_errors++;
S
Stephen Hemminger 已提交
1783 1784
	if (status & GMR_FS_RX_FF_OV)
		sky2->net_stats.rx_fifo_errors++;
1785

S
Stephen Hemminger 已提交
1786
	goto resubmit;
1787 1788
}

1789 1790
/*
 * Check for transmit complete
S
Stephen Hemminger 已提交
1791
 */
1792
#define TX_NO_STATUS	0xffff
1793

1794 1795 1796 1797 1798 1799 1800 1801
static inline void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
{
	if (last != TX_NO_STATUS) {
		struct net_device *dev = hw->dev[port];
		if (dev && netif_running(dev)) {
			struct sky2_port *sky2 = netdev_priv(dev);
			sky2_tx_complete(sky2, last);
		}
1802
	}
1803 1804 1805 1806 1807 1808
}

/*
 * Both ports share the same status interrupt, therefore there is only
 * one poll routine.
 */
1809
static int sky2_poll(struct net_device *dev0, int *budget)
1810
{
1811 1812
	struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
	unsigned int to_do = min(dev0->quota, *budget);
1813
	unsigned int work_done = 0;
S
Stephen Hemminger 已提交
1814
	u16 hwidx;
1815
	u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
1816

S
Stephen Hemminger 已提交
1817
	hwidx = sky2_read16(hw, STAT_PUT_IDX);
1818
	BUG_ON(hwidx >= STATUS_RING_SIZE);
1819
	rmb();
1820

1821 1822 1823
	while (hwidx != hw->st_idx) {
		struct sky2_status_le *le  = hw->st_le + hw->st_idx;
		struct net_device *dev;
1824
		struct sky2_port *sky2;
1825 1826 1827
		struct sk_buff *skb;
		u32 status;
		u16 length;
1828
		u8 op;
1829

1830
		le = hw->st_le + hw->st_idx;
1831
		hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1832
		prefetch(hw->st_le + hw->st_idx);
1833

1834 1835 1836 1837 1838 1839
		BUG_ON(le->link >= 2);
		dev = hw->dev[le->link];
		if (dev == NULL || !netif_running(dev))
			continue;

		sky2 = netdev_priv(dev);
1840 1841
		status = le32_to_cpu(le->status);
		length = le16_to_cpu(le->length);
1842 1843
		op = le->opcode & ~HW_OWNER;
		le->opcode = 0;
1844

1845
		switch (op) {
1846
		case OP_RXSTAT:
1847
			skb = sky2_receive(sky2, length, status);
1848 1849
			if (!skb)
				break;
1850 1851 1852 1853 1854

			skb->dev = dev;
			skb->protocol = eth_type_trans(skb, dev);
			dev->last_rx = jiffies;

1855 1856 1857 1858 1859 1860 1861
#ifdef SKY2_VLAN_TAG_USED
			if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
				vlan_hwaccel_receive_skb(skb,
							 sky2->vlgrp,
							 be16_to_cpu(sky2->rx_tag));
			} else
#endif
1862
				netif_receive_skb(skb);
1863 1864 1865

			if (++work_done >= to_do)
				goto exit_loop;
1866 1867
			break;

1868 1869 1870 1871 1872 1873 1874 1875 1876
#ifdef SKY2_VLAN_TAG_USED
		case OP_RXVLAN:
			sky2->rx_tag = length;
			break;

		case OP_RXCHKSVLAN:
			sky2->rx_tag = length;
			/* fall through */
#endif
1877
		case OP_RXCHKS:
1878 1879 1880
			skb = sky2->rx_ring[sky2->rx_next].skb;
			skb->ip_summed = CHECKSUM_HW;
			skb->csum = le16_to_cpu(status);
1881 1882 1883
			break;

		case OP_TXINDEXLE:
1884 1885 1886 1887
			/* TX index reports status for both ports */
			tx_done[0] = status & 0xffff;
			tx_done[1] = ((status >> 24) & 0xff)
				| (u16)(length & 0xf) << 8;
1888 1889 1890 1891
			break;

		default:
			if (net_ratelimit())
S
Stephen Hemminger 已提交
1892
				printk(KERN_WARNING PFX
1893
				       "unknown status opcode 0x%x\n", op);
1894 1895
			break;
		}
1896
	}
1897

1898
exit_loop:
1899
	sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
S
Stephen Hemminger 已提交
1900

1901 1902 1903
	sky2_tx_check(hw, 0, tx_done[0]);
	sky2_tx_check(hw, 1, tx_done[1]);

1904
	if (sky2_read16(hw, STAT_PUT_IDX) == hw->st_idx) {
1905
		/* need to restart TX timer */
1906 1907 1908 1909 1910
		if (is_ec_a1(hw)) {
			sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
			sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
		}

1911
		netif_rx_complete(dev0);
1912 1913
		hw->intr_mask |= Y2_IS_STAT_BMU;
		sky2_write32(hw, B0_IMSK, hw->intr_mask);
1914 1915 1916 1917 1918
		return 0;
	} else {
		*budget -= work_done;
		dev0->quota -= work_done;
		return 1;
1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962
	}
}

static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
{
	struct net_device *dev = hw->dev[port];

	printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
	       dev->name, status);

	if (status & Y2_IS_PAR_RD1) {
		printk(KERN_ERR PFX "%s: ram data read parity error\n",
		       dev->name);
		/* Clear IRQ */
		sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
	}

	if (status & Y2_IS_PAR_WR1) {
		printk(KERN_ERR PFX "%s: ram data write parity error\n",
		       dev->name);

		sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
	}

	if (status & Y2_IS_PAR_MAC1) {
		printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
		sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
	}

	if (status & Y2_IS_PAR_RX1) {
		printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
		sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
	}

	if (status & Y2_IS_TCP_TXA1) {
		printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
		sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
	}
}

static void sky2_hw_intr(struct sky2_hw *hw)
{
	u32 status = sky2_read32(hw, B0_HWE_ISRC);

S
Stephen Hemminger 已提交
1963
	if (status & Y2_IS_TIST_OV)
1964 1965 1966
		sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);

	if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
S
Stephen Hemminger 已提交
1967 1968 1969
		u16 pci_err;

		pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
1970 1971 1972 1973
		printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
		       pci_name(hw->pdev), pci_err);

		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
S
Stephen Hemminger 已提交
1974 1975
		pci_write_config_word(hw->pdev, PCI_STATUS,
				      pci_err | PCI_STATUS_ERROR_BITS);
1976 1977 1978 1979
		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
	}

	if (status & Y2_IS_PCI_EXP) {
S
shemminger@osdl.org 已提交
1980
		/* PCI-Express uncorrectable Error occurred */
S
Stephen Hemminger 已提交
1981 1982 1983
		u32 pex_err;

		pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
1984 1985 1986 1987 1988 1989

		printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
		       pci_name(hw->pdev), pex_err);

		/* clear the interrupt */
		sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
S
Stephen Hemminger 已提交
1990 1991
		pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
				       0xffffffffUL);
1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035
		sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

		if (pex_err & PEX_FATAL_ERRORS) {
			u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
			hwmsk &= ~Y2_IS_PCI_EXP;
			sky2_write32(hw, B0_HWE_IMSK, hwmsk);
		}
	}

	if (status & Y2_HWE_L1_MASK)
		sky2_hw_error(hw, 0, status);
	status >>= 8;
	if (status & Y2_HWE_L1_MASK)
		sky2_hw_error(hw, 1, status);
}

static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
{
	struct net_device *dev = hw->dev[port];
	struct sky2_port *sky2 = netdev_priv(dev);
	u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));

	if (netif_msg_intr(sky2))
		printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
		       dev->name, status);

	if (status & GM_IS_RX_FF_OR) {
		++sky2->net_stats.rx_fifo_errors;
		sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
	}

	if (status & GM_IS_TX_FF_UR) {
		++sky2->net_stats.tx_fifo_errors;
		sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
	}
}

static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
{
	struct net_device *dev = hw->dev[port];
	struct sky2_port *sky2 = netdev_priv(dev);

	hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
	sky2_write32(hw, B0_IMSK, hw->intr_mask);
2036
	schedule_work(&sky2->phy_task);
2037 2038 2039 2040 2041
}

static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
{
	struct sky2_hw *hw = dev_id;
2042
	struct net_device *dev0 = hw->dev[0];
2043 2044 2045
	u32 status;

	status = sky2_read32(hw, B0_Y2_SP_ISRC2);
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	if (status == 0 || status == ~0)
2047 2048 2049 2050 2051
		return IRQ_NONE;

	if (status & Y2_IS_HW_ERR)
		sky2_hw_intr(hw);

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	/* Do NAPI for Rx and Tx status */
2053
	if (status & Y2_IS_STAT_BMU) {
2054 2055
		hw->intr_mask &= ~Y2_IS_STAT_BMU;
		sky2_write32(hw, B0_IMSK, hw->intr_mask);
2056

2057 2058
		if (likely(__netif_rx_schedule_prep(dev0))) {
			prefetch(&hw->st_le[hw->st_idx]);
2059
			__netif_rx_schedule(dev0);
2060
		}
2061 2062
	}

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	if (status & Y2_IS_IRQ_PHY1)
2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075
		sky2_phy_intr(hw, 0);

	if (status & Y2_IS_IRQ_PHY2)
		sky2_phy_intr(hw, 1);

	if (status & Y2_IS_IRQ_MAC1)
		sky2_mac_intr(hw, 0);

	if (status & Y2_IS_IRQ_MAC2)
		sky2_mac_intr(hw, 1);

	sky2_write32(hw, B0_Y2_SP_ICR, 2);
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2076 2077 2078

	sky2_read32(hw, B0_IMSK);

2079 2080 2081 2082 2083 2084 2085 2086
	return IRQ_HANDLED;
}

#ifdef CONFIG_NET_POLL_CONTROLLER
static void sky2_netpoll(struct net_device *dev)
{
	struct sky2_port *sky2 = netdev_priv(dev);

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	sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
2088 2089 2090 2091
}
#endif

/* Chip internal frequency for clock calculations */
2092
static inline u32 sky2_mhz(const struct sky2_hw *hw)
2093
{
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2094
	switch (hw->chip_id) {
2095
	case CHIP_ID_YUKON_EC:
2096
	case CHIP_ID_YUKON_EC_U:
2097
		return 125;	/* 125 Mhz */
2098
	case CHIP_ID_YUKON_FE:
2099
		return 100;	/* 100 Mhz */
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2100
	default:		/* YUKON_XL */
2101
		return 156;	/* 156 Mhz */
2102 2103 2104
	}
}

2105
static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2106
{
2107
	return sky2_mhz(hw) * us;
2108 2109
}

2110
static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2111
{
2112
	return clk / sky2_mhz(hw);
2113 2114
}

2115

2116 2117
static int sky2_reset(struct sky2_hw *hw)
{
2118
	u32 ctst;
2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132
	u16 status;
	u8 t8, pmd_type;
	int i;

	ctst = sky2_read32(hw, B0_CTST);

	sky2_write8(hw, B0_CTST, CS_RST_CLR);
	hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
	if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
		printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
		       pci_name(hw->pdev), hw->chip_id);
		return -EOPNOTSUPP;
	}

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2133 2134 2135 2136 2137 2138
	/* ring for status responses */
	hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
					 &hw->st_dma);
	if (!hw->st_le)
		return -ENOMEM;

2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149
	/* disable ASF */
	if (hw->chip_id <= CHIP_ID_YUKON_EC) {
		sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
		sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
	}

	/* do a SW reset */
	sky2_write8(hw, B0_CTST, CS_RST_SET);
	sky2_write8(hw, B0_CTST, CS_RST_CLR);

	/* clear PCI errors, if any */
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	pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2151
	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
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2152 2153
	pci_write_config_word(hw->pdev, PCI_STATUS,
			      status | PCI_STATUS_ERROR_BITS);
2154 2155 2156 2157 2158

	sky2_write8(hw, B0_CTST, CS_MRST_CLR);

	/* clear any PEX errors */
	if (is_pciex(hw)) {
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2159 2160 2161 2162
		u16 lstat;
		pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
				       0xffffffffUL);
		pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175
	}

	pmd_type = sky2_read8(hw, B2_PMD_TYP);
	hw->copper = !(pmd_type == 'L' || pmd_type == 'S');

	hw->ports = 1;
	t8 = sky2_read8(hw, B2_Y2_HW_RES);
	if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
		if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
			++hw->ports;
	}
	hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;

2176
	sky2_set_power_state(hw, PCI_D0);
2177 2178 2179 2180 2181 2182 2183 2184

	for (i = 0; i < hw->ports; i++) {
		sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
		sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
	}

	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

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2185 2186
	/* Clear I2C IRQ noise */
	sky2_write32(hw, B2_I2C_IRQ, 1);
2187 2188 2189 2190

	/* turn off hardware timer (unused) */
	sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
	sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
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2192 2193
	sky2_write8(hw, B0_Y2LED, LED_STAT_ON);

2194 2195
	/* Turn off descriptor polling */
	sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2196 2197 2198

	/* Turn off receive timestamp */
	sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
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	sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2200 2201 2202 2203 2204 2205 2206

	/* enable the Tx Arbiters */
	for (i = 0; i < hw->ports; i++)
		sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);

	/* Initialize ram interface */
	for (i = 0; i < hw->ports; i++) {
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		sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234

		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
	}

	sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);

	for (i = 0; i < hw->ports; i++)
		sky2_phy_reset(hw, i);

	memset(hw->st_le, 0, STATUS_LE_BYTES);
	hw->st_idx = 0;

	sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
	sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);

	sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
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	sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2236 2237

	/* Set the list last index */
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2238
	sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2239

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2240
	/* These status setup values are copied from SysKonnect's driver */
2241 2242
	if (is_ec_a1(hw)) {
		/* WA for dev. #4.3 */
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2243
		sky2_write16(hw, STAT_TX_IDX_TH, 0xfff);	/* Tx Threshold */
2244 2245 2246 2247 2248

		/* set Status-FIFO watermark */
		sky2_write8(hw, STAT_FIFO_WM, 0x21);	/* WA for dev. #4.18 */

		/* set Status-FIFO ISR watermark */
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2249
		sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07);	/* WA for dev. #4.18 */
2250
		sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000));
2251
	} else {
2252 2253
		sky2_write16(hw, STAT_TX_IDX_TH, 10);
		sky2_write8(hw, STAT_FIFO_WM, 16);
2254 2255 2256

		/* set Status-FIFO ISR watermark */
		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2257 2258 2259
			sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
		else
			sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2260

2261 2262 2263
		sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
		sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
		sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2264 2265
	}

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2266
	/* enable status unit */
2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279
	sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);

	sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
	sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
	sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);

	return 0;
}

static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
{
	u32 modes;
	if (hw->copper) {
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2280 2281 2282 2283 2284
		modes = SUPPORTED_10baseT_Half
		    | SUPPORTED_10baseT_Full
		    | SUPPORTED_100baseT_Half
		    | SUPPORTED_100baseT_Full
		    | SUPPORTED_Autoneg | SUPPORTED_TP;
2285 2286 2287

		if (hw->chip_id != CHIP_ID_YUKON_FE)
			modes |= SUPPORTED_1000baseT_Half
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2288
			    | SUPPORTED_1000baseT_Full;
2289 2290
	} else
		modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
S
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2291
		    | SUPPORTED_Autoneg;
2292 2293 2294
	return modes;
}

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2295
static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2296 2297 2298 2299 2300 2301 2302 2303 2304
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;

	ecmd->transceiver = XCVR_INTERNAL;
	ecmd->supported = sky2_supported_modes(hw);
	ecmd->phy_address = PHY_ADDR_MARV;
	if (hw->copper) {
		ecmd->supported = SUPPORTED_10baseT_Half
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2305 2306 2307 2308 2309 2310
		    | SUPPORTED_10baseT_Full
		    | SUPPORTED_100baseT_Half
		    | SUPPORTED_100baseT_Full
		    | SUPPORTED_1000baseT_Half
		    | SUPPORTED_1000baseT_Full
		    | SUPPORTED_Autoneg | SUPPORTED_TP;
2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334
		ecmd->port = PORT_TP;
	} else
		ecmd->port = PORT_FIBRE;

	ecmd->advertising = sky2->advertising;
	ecmd->autoneg = sky2->autoneg;
	ecmd->speed = sky2->speed;
	ecmd->duplex = sky2->duplex;
	return 0;
}

static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	const struct sky2_hw *hw = sky2->hw;
	u32 supported = sky2_supported_modes(hw);

	if (ecmd->autoneg == AUTONEG_ENABLE) {
		ecmd->advertising = supported;
		sky2->duplex = -1;
		sky2->speed = -1;
	} else {
		u32 setting;

S
Stephen Hemminger 已提交
2335
		switch (ecmd->speed) {
2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374
		case SPEED_1000:
			if (ecmd->duplex == DUPLEX_FULL)
				setting = SUPPORTED_1000baseT_Full;
			else if (ecmd->duplex == DUPLEX_HALF)
				setting = SUPPORTED_1000baseT_Half;
			else
				return -EINVAL;
			break;
		case SPEED_100:
			if (ecmd->duplex == DUPLEX_FULL)
				setting = SUPPORTED_100baseT_Full;
			else if (ecmd->duplex == DUPLEX_HALF)
				setting = SUPPORTED_100baseT_Half;
			else
				return -EINVAL;
			break;

		case SPEED_10:
			if (ecmd->duplex == DUPLEX_FULL)
				setting = SUPPORTED_10baseT_Full;
			else if (ecmd->duplex == DUPLEX_HALF)
				setting = SUPPORTED_10baseT_Half;
			else
				return -EINVAL;
			break;
		default:
			return -EINVAL;
		}

		if ((setting & supported) == 0)
			return -EINVAL;

		sky2->speed = ecmd->speed;
		sky2->duplex = ecmd->duplex;
	}

	sky2->autoneg = ecmd->autoneg;
	sky2->advertising = ecmd->advertising;

2375 2376
	if (netif_running(dev))
		sky2_phy_reinit(sky2);
2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392

	return 0;
}

static void sky2_get_drvinfo(struct net_device *dev,
			     struct ethtool_drvinfo *info)
{
	struct sky2_port *sky2 = netdev_priv(dev);

	strcpy(info->driver, DRV_NAME);
	strcpy(info->version, DRV_VERSION);
	strcpy(info->fw_version, "N/A");
	strcpy(info->bus_info, pci_name(sky2->hw->pdev));
}

static const struct sky2_stat {
S
Stephen Hemminger 已提交
2393 2394
	char name[ETH_GSTRING_LEN];
	u16 offset;
2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430
} sky2_stats[] = {
	{ "tx_bytes",	   GM_TXO_OK_HI },
	{ "rx_bytes",	   GM_RXO_OK_HI },
	{ "tx_broadcast",  GM_TXF_BC_OK },
	{ "rx_broadcast",  GM_RXF_BC_OK },
	{ "tx_multicast",  GM_TXF_MC_OK },
	{ "rx_multicast",  GM_RXF_MC_OK },
	{ "tx_unicast",    GM_TXF_UC_OK },
	{ "rx_unicast",    GM_RXF_UC_OK },
	{ "tx_mac_pause",  GM_TXF_MPAUSE },
	{ "rx_mac_pause",  GM_RXF_MPAUSE },
	{ "collisions",    GM_TXF_SNG_COL },
	{ "late_collision",GM_TXF_LAT_COL },
	{ "aborted", 	   GM_TXF_ABO_COL },
	{ "multi_collisions", GM_TXF_MUL_COL },
	{ "fifo_underrun", GM_TXE_FIFO_UR },
	{ "fifo_overflow", GM_RXE_FIFO_OV },
	{ "rx_toolong",    GM_RXF_LNG_ERR },
	{ "rx_jabber",     GM_RXF_JAB_PKT },
	{ "rx_runt", 	   GM_RXE_FRAG },
	{ "rx_too_long",   GM_RXF_LNG_ERR },
	{ "rx_fcs_error",   GM_RXF_FCS_ERR },
};

static u32 sky2_get_rx_csum(struct net_device *dev)
{
	struct sky2_port *sky2 = netdev_priv(dev);

	return sky2->rx_csum;
}

static int sky2_set_rx_csum(struct net_device *dev, u32 data)
{
	struct sky2_port *sky2 = netdev_priv(dev);

	sky2->rx_csum = data;
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Stephen Hemminger 已提交
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2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443
	sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
		     data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);

	return 0;
}

static u32 sky2_get_msglevel(struct net_device *netdev)
{
	struct sky2_port *sky2 = netdev_priv(netdev);
	return sky2->msg_enable;
}

2444 2445 2446 2447 2448 2449 2450
static int sky2_nway_reset(struct net_device *dev)
{
	struct sky2_port *sky2 = netdev_priv(dev);

	if (sky2->autoneg != AUTONEG_ENABLE)
		return -EINVAL;

2451
	sky2_phy_reinit(sky2);
2452 2453 2454 2455

	return 0;
}

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static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2457 2458 2459 2460 2461 2462
{
	struct sky2_hw *hw = sky2->hw;
	unsigned port = sky2->port;
	int i;

	data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
S
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2463
	    | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2464
	data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
S
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2465
	    | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2466

S
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2467
	for (i = 2; i < count; i++)
2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482
		data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
}

static void sky2_set_msglevel(struct net_device *netdev, u32 value)
{
	struct sky2_port *sky2 = netdev_priv(netdev);
	sky2->msg_enable = value;
}

static int sky2_get_stats_count(struct net_device *dev)
{
	return ARRAY_SIZE(sky2_stats);
}

static void sky2_get_ethtool_stats(struct net_device *dev,
S
Stephen Hemminger 已提交
2483
				   struct ethtool_stats *stats, u64 * data)
2484 2485 2486
{
	struct sky2_port *sky2 = netdev_priv(dev);

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	sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2488 2489
}

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static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509
{
	int i;

	switch (stringset) {
	case ETH_SS_STATS:
		for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
			memcpy(data + i * ETH_GSTRING_LEN,
			       sky2_stats[i].name, ETH_GSTRING_LEN);
		break;
	}
}

/* Use hardware MIB variables for critical path statistics and
 * transmit feedback not reported at interrupt.
 * Other errors are accounted for in interrupt handler.
 */
static struct net_device_stats *sky2_get_stats(struct net_device *dev)
{
	struct sky2_port *sky2 = netdev_priv(dev);
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	u64 data[13];
2511

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	sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533

	sky2->net_stats.tx_bytes = data[0];
	sky2->net_stats.rx_bytes = data[1];
	sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
	sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
	sky2->net_stats.multicast = data[5] + data[7];
	sky2->net_stats.collisions = data[10];
	sky2->net_stats.tx_aborted_errors = data[12];

	return &sky2->net_stats;
}

static int sky2_set_mac_address(struct net_device *dev, void *p)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sockaddr *addr = p;

	if (!is_valid_ether_addr(addr->sa_data))
		return -EADDRNOTAVAIL;

	memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
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	memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
2535
		    dev->dev_addr, ETH_ALEN);
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	memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
2537
		    dev->dev_addr, ETH_ALEN);
2538 2539 2540 2541 2542

	if (netif_running(dev))
		sky2_phy_reinit(sky2);

	return 0;
2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558
}

static void sky2_set_multicast(struct net_device *dev)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
	unsigned port = sky2->port;
	struct dev_mc_list *list = dev->mc_list;
	u16 reg;
	u8 filter[8];

	memset(filter, 0, sizeof(filter));

	reg = gma_read16(hw, port, GM_RX_CTRL);
	reg |= GM_RXCR_UCF_ENA;

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	if (dev->flags & IFF_PROMISC)	/* promiscuous */
2560
		reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
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	else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16)	/* all multicast */
2562
		memset(filter, 0xff, sizeof(filter));
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	else if (dev->mc_count == 0)	/* no multicast */
2564 2565 2566 2567 2568 2569 2570
		reg &= ~GM_RXCR_MCF_ENA;
	else {
		int i;
		reg |= GM_RXCR_MCF_ENA;

		for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
			u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
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			filter[bit / 8] |= 1 << (bit % 8);
2572 2573 2574 2575
		}
	}

	gma_write16(hw, port, GM_MC_ADDR_H1,
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		    (u16) filter[0] | ((u16) filter[1] << 8));
2577
	gma_write16(hw, port, GM_MC_ADDR_H2,
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		    (u16) filter[2] | ((u16) filter[3] << 8));
2579
	gma_write16(hw, port, GM_MC_ADDR_H3,
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		    (u16) filter[4] | ((u16) filter[5] << 8));
2581
	gma_write16(hw, port, GM_MC_ADDR_H4,
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		    (u16) filter[6] | ((u16) filter[7] << 8));
2583 2584 2585 2586 2587 2588 2589

	gma_write16(hw, port, GM_RX_CTRL, reg);
}

/* Can have one global because blinking is controlled by
 * ethtool and that is always under RTNL mutex
 */
2590
static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2591
{
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	u16 pg;

	switch (hw->chip_id) {
	case CHIP_ID_YUKON_XL:
		pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
			     on ? (PHY_M_LEDC_LOS_CTRL(1) |
				   PHY_M_LEDC_INIT_CTRL(7) |
				   PHY_M_LEDC_STA1_CTRL(7) |
				   PHY_M_LEDC_STA0_CTRL(7))
			     : 0);

		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
		break;

	default:
		gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2610
		gm_phy_write(hw, port, PHY_MARV_LED_OVER,
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			     on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
			     PHY_M_LED_MO_10(MO_LED_ON) |
			     PHY_M_LED_MO_100(MO_LED_ON) |
2614
			     PHY_M_LED_MO_1000(MO_LED_ON) |
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			     PHY_M_LED_MO_RX(MO_LED_ON)
			     : PHY_M_LED_MO_DUP(MO_LED_OFF) |
			     PHY_M_LED_MO_10(MO_LED_OFF) |
			     PHY_M_LED_MO_100(MO_LED_OFF) |
2619 2620 2621
			     PHY_M_LED_MO_1000(MO_LED_OFF) |
			     PHY_M_LED_MO_RX(MO_LED_OFF));

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	}
2623 2624 2625 2626 2627 2628 2629 2630
}

/* blink LED's for finding board */
static int sky2_phys_id(struct net_device *dev, u32 data)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
	unsigned port = sky2->port;
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	u16 ledctrl, ledover = 0;
2632
	long ms;
2633
	int interrupted;
2634 2635
	int onoff = 1;

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	if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2637 2638 2639 2640 2641
		ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
	else
		ms = data * 1000;

	/* save initial values */
2642
	down(&sky2->phy_sema);
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	if (hw->chip_id == CHIP_ID_YUKON_XL) {
		u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
		ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
	} else {
		ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
		ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
	}
2652

2653 2654
	interrupted = 0;
	while (!interrupted && ms > 0) {
2655 2656 2657
		sky2_led(hw, port, onoff);
		onoff = !onoff;

2658 2659 2660 2661
		up(&sky2->phy_sema);
		interrupted = msleep_interruptible(250);
		down(&sky2->phy_sema);

2662 2663 2664 2665
		ms -= 250;
	}

	/* resume regularly scheduled programming */
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	if (hw->chip_id == CHIP_ID_YUKON_XL) {
		u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
	} else {
		gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
		gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
	}
2675
	up(&sky2->phy_sema);
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	return 0;
}

static void sky2_get_pauseparam(struct net_device *dev,
				struct ethtool_pauseparam *ecmd)
{
	struct sky2_port *sky2 = netdev_priv(dev);

	ecmd->tx_pause = sky2->tx_pause;
	ecmd->rx_pause = sky2->rx_pause;
	ecmd->autoneg = sky2->autoneg;
}

static int sky2_set_pauseparam(struct net_device *dev,
			       struct ethtool_pauseparam *ecmd)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	int err = 0;

	sky2->autoneg = ecmd->autoneg;
	sky2->tx_pause = ecmd->tx_pause != 0;
	sky2->rx_pause = ecmd->rx_pause != 0;

2700
	sky2_phy_reinit(sky2);
2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736

	return err;
}

#ifdef CONFIG_PM
static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
	struct sky2_port *sky2 = netdev_priv(dev);

	wol->supported = WAKE_MAGIC;
	wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
}

static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;

	if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
		return -EOPNOTSUPP;

	sky2->wol = wol->wolopts == WAKE_MAGIC;

	if (sky2->wol) {
		memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);

		sky2_write16(hw, WOL_CTRL_STAT,
			     WOL_CTL_ENA_PME_ON_MAGIC_PKT |
			     WOL_CTL_ENA_MAGIC_PKT_UNIT);
	} else
		sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);

	return 0;
}
#endif

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static int sky2_get_coalesce(struct net_device *dev,
			     struct ethtool_coalesce *ecmd)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;

	if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
		ecmd->tx_coalesce_usecs = 0;
	else {
		u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
		ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
	}
	ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);

	if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
		ecmd->rx_coalesce_usecs = 0;
	else {
		u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
		ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
	}
	ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);

	if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
		ecmd->rx_coalesce_usecs_irq = 0;
	else {
		u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
		ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
	}

	ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);

	return 0;
}

/* Note: this affect both ports */
static int sky2_set_coalesce(struct net_device *dev,
			     struct ethtool_coalesce *ecmd)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
	const u32 tmin = sky2_clk2us(hw, 1);
	const u32 tmax = 5000;

	if (ecmd->tx_coalesce_usecs != 0 &&
	    (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
		return -EINVAL;

	if (ecmd->rx_coalesce_usecs != 0 &&
	    (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
		return -EINVAL;

	if (ecmd->rx_coalesce_usecs_irq != 0 &&
	    (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
		return -EINVAL;

	if (ecmd->tx_max_coalesced_frames > 0xffff)
		return -EINVAL;
	if (ecmd->rx_max_coalesced_frames > 0xff)
		return -EINVAL;
	if (ecmd->rx_max_coalesced_frames_irq > 0xff)
		return -EINVAL;

	if (ecmd->tx_coalesce_usecs == 0)
		sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
	else {
		sky2_write32(hw, STAT_TX_TIMER_INI,
			     sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
		sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
	}
	sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);

	if (ecmd->rx_coalesce_usecs == 0)
		sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
	else {
		sky2_write32(hw, STAT_LEV_TIMER_INI,
			     sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
		sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
	}
	sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);

	if (ecmd->rx_coalesce_usecs_irq == 0)
		sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
	else {
		sky2_write32(hw, STAT_TX_TIMER_INI,
			     sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
		sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
	}
	sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
	return 0;
}

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static void sky2_get_ringparam(struct net_device *dev,
			       struct ethtool_ringparam *ering)
{
	struct sky2_port *sky2 = netdev_priv(dev);

	ering->rx_max_pending = RX_MAX_PENDING;
	ering->rx_mini_max_pending = 0;
	ering->rx_jumbo_max_pending = 0;
	ering->tx_max_pending = TX_RING_SIZE - 1;

	ering->rx_pending = sky2->rx_pending;
	ering->rx_mini_pending = 0;
	ering->rx_jumbo_pending = 0;
	ering->tx_pending = sky2->tx_pending;
}

static int sky2_set_ringparam(struct net_device *dev,
			      struct ethtool_ringparam *ering)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	int err = 0;

	if (ering->rx_pending > RX_MAX_PENDING ||
	    ering->rx_pending < 8 ||
	    ering->tx_pending < MAX_SKB_TX_LE ||
	    ering->tx_pending > TX_RING_SIZE - 1)
		return -EINVAL;

	if (netif_running(dev))
		sky2_down(dev);

	sky2->rx_pending = ering->rx_pending;
	sky2->tx_pending = ering->tx_pending;

2862
	if (netif_running(dev)) {
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		err = sky2_up(dev);
2864 2865
		if (err)
			dev_close(dev);
2866 2867
		else
			sky2_set_multicast(dev);
2868
	}
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	return err;
}

static int sky2_get_regs_len(struct net_device *dev)
{
2875
	return 0x4000;
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2876 2877 2878 2879
}

/*
 * Returns copy of control register region
2880
 * Note: access to the RAM address register set will cause timeouts.
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 */
static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
			  void *p)
{
	const struct sky2_port *sky2 = netdev_priv(dev);
	const void __iomem *io = sky2->hw->regs;

2888
	BUG_ON(regs->len < B3_RI_WTO_R1);
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2889
	regs->version = 1;
2890
	memset(p, 0, regs->len);
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2892 2893 2894 2895 2896
	memcpy_fromio(p, io, B3_RAM_ADDR);

	memcpy_fromio(p + B3_RI_WTO_R1,
		      io + B3_RI_WTO_R1,
		      regs->len - B3_RI_WTO_R1);
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}
2898 2899

static struct ethtool_ops sky2_ethtool_ops = {
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	.get_settings = sky2_get_settings,
	.set_settings = sky2_set_settings,
	.get_drvinfo = sky2_get_drvinfo,
	.get_msglevel = sky2_get_msglevel,
	.set_msglevel = sky2_set_msglevel,
2905
	.nway_reset   = sky2_nway_reset,
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	.get_regs_len = sky2_get_regs_len,
	.get_regs = sky2_get_regs,
	.get_link = ethtool_op_get_link,
	.get_sg = ethtool_op_get_sg,
	.set_sg = ethtool_op_set_sg,
	.get_tx_csum = ethtool_op_get_tx_csum,
	.set_tx_csum = ethtool_op_set_tx_csum,
	.get_tso = ethtool_op_get_tso,
	.set_tso = ethtool_op_set_tso,
	.get_rx_csum = sky2_get_rx_csum,
	.set_rx_csum = sky2_set_rx_csum,
	.get_strings = sky2_get_strings,
2918 2919
	.get_coalesce = sky2_get_coalesce,
	.set_coalesce = sky2_set_coalesce,
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	.get_ringparam = sky2_get_ringparam,
	.set_ringparam = sky2_set_ringparam,
2922 2923 2924
	.get_pauseparam = sky2_get_pauseparam,
	.set_pauseparam = sky2_set_pauseparam,
#ifdef CONFIG_PM
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2925 2926
	.get_wol = sky2_get_wol,
	.set_wol = sky2_set_wol,
2927
#endif
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	.phys_id = sky2_phys_id,
2929 2930
	.get_stats_count = sky2_get_stats_count,
	.get_ethtool_stats = sky2_get_ethtool_stats,
2931
	.get_perm_addr	= ethtool_op_get_perm_addr,
2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947
};

/* Initialize network device */
static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
						     unsigned port, int highmem)
{
	struct sky2_port *sky2;
	struct net_device *dev = alloc_etherdev(sizeof(*sky2));

	if (!dev) {
		printk(KERN_ERR "sky2 etherdev alloc failed");
		return NULL;
	}

	SET_MODULE_OWNER(dev);
	SET_NETDEV_DEV(dev, &hw->pdev->dev);
2948
	dev->irq = hw->pdev->irq;
2949 2950
	dev->open = sky2_up;
	dev->stop = sky2_down;
2951
	dev->do_ioctl = sky2_ioctl;
2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974
	dev->hard_start_xmit = sky2_xmit_frame;
	dev->get_stats = sky2_get_stats;
	dev->set_multicast_list = sky2_set_multicast;
	dev->set_mac_address = sky2_set_mac_address;
	dev->change_mtu = sky2_change_mtu;
	SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
	dev->tx_timeout = sky2_tx_timeout;
	dev->watchdog_timeo = TX_WATCHDOG;
	if (port == 0)
		dev->poll = sky2_poll;
	dev->weight = NAPI_WEIGHT;
#ifdef CONFIG_NET_POLL_CONTROLLER
	dev->poll_controller = sky2_netpoll;
#endif

	sky2 = netdev_priv(dev);
	sky2->netdev = dev;
	sky2->hw = hw;
	sky2->msg_enable = netif_msg_init(debug, default_msg);

	spin_lock_init(&sky2->tx_lock);
	/* Auto speed and flow control */
	sky2->autoneg = AUTONEG_ENABLE;
2975
	sky2->tx_pause = 1;
2976 2977 2978 2979
	sky2->rx_pause = 1;
	sky2->duplex = -1;
	sky2->speed = -1;
	sky2->advertising = sky2_supported_modes(hw);
2980 2981 2982 2983 2984 2985 2986

 	/* Receive checksum disabled for Yukon XL
	 * because of observed problems with incorrect
	 * values when multiple packets are received in one interrupt
	 */
	sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);

2987 2988
	INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
	init_MUTEX(&sky2->phy_sema);
S
Stephen Hemminger 已提交
2989 2990
	sky2->tx_pending = TX_DEF_PENDING;
	sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
2991
	sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
2992 2993 2994 2995 2996

	hw->dev[port] = dev;

	sky2->port = port;

2997 2998 2999
	dev->features |= NETIF_F_LLTX;
	if (hw->chip_id != CHIP_ID_YUKON_EC_U)
		dev->features |= NETIF_F_TSO;
3000 3001
	if (highmem)
		dev->features |= NETIF_F_HIGHDMA;
S
Stephen Hemminger 已提交
3002
	dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3003

3004 3005 3006 3007 3008 3009
#ifdef SKY2_VLAN_TAG_USED
	dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
	dev->vlan_rx_register = sky2_vlan_rx_register;
	dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
#endif

3010
	/* read the mac address */
S
Stephen Hemminger 已提交
3011
	memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3012
	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034

	/* device is off until link detection */
	netif_carrier_off(dev);
	netif_stop_queue(dev);

	return dev;
}

static inline void sky2_show_addr(struct net_device *dev)
{
	const struct sky2_port *sky2 = netdev_priv(dev);

	if (netif_msg_probe(sky2))
		printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
		       dev->name,
		       dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
		       dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
}

static int __devinit sky2_probe(struct pci_dev *pdev,
				const struct pci_device_id *ent)
{
S
Stephen Hemminger 已提交
3035
	struct net_device *dev, *dev1 = NULL;
3036
	struct sky2_hw *hw;
3037
	int err, pm_cap, using_dac = 0;
3038

S
Stephen Hemminger 已提交
3039 3040
	err = pci_enable_device(pdev);
	if (err) {
3041 3042 3043 3044 3045
		printk(KERN_ERR PFX "%s cannot enable PCI device\n",
		       pci_name(pdev));
		goto err_out;
	}

S
Stephen Hemminger 已提交
3046 3047
	err = pci_request_regions(pdev, DRV_NAME);
	if (err) {
3048 3049
		printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
		       pci_name(pdev));
S
Stephen Hemminger 已提交
3050
		goto err_out;
3051 3052 3053 3054
	}

	pci_set_master(pdev);

3055 3056 3057 3058 3059 3060 3061 3062 3063
	/* Find power-management capability. */
	pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
	if (pm_cap == 0) {
		printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
		       "aborting.\n");
		err = -EIO;
		goto err_out_free_regions;
	}

3064 3065 3066 3067 3068 3069 3070 3071 3072
	if (sizeof(dma_addr_t) > sizeof(u32) &&
	    !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
		using_dac = 1;
		err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
		if (err < 0) {
			printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
			       "for consistent allocations\n", pci_name(pdev));
			goto err_out_free_regions;
		}
3073

3074
	} else {
3075 3076 3077 3078 3079 3080 3081
		err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
		if (err) {
			printk(KERN_ERR PFX "%s no usable DMA configuration\n",
			       pci_name(pdev));
			goto err_out_free_regions;
		}
	}
3082

3083
#ifdef __BIG_ENDIAN
S
shemminger@osdl.org 已提交
3084
	/* byte swap descriptors in hardware */
3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110
	{
		u32 reg;

		pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
		reg |= PCI_REV_DESC;
		pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
	}
#endif

	err = -ENOMEM;
	hw = kmalloc(sizeof(*hw), GFP_KERNEL);
	if (!hw) {
		printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
		       pci_name(pdev));
		goto err_out_free_regions;
	}

	memset(hw, 0, sizeof(*hw));
	hw->pdev = pdev;

	hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
	if (!hw->regs) {
		printk(KERN_ERR PFX "%s: cannot map device registers\n",
		       pci_name(pdev));
		goto err_out_free_hw;
	}
3111
	hw->pm_cap = pm_cap;
3112 3113 3114

	err = sky2_reset(hw);
	if (err)
S
Stephen Hemminger 已提交
3115
		goto err_out_iounmap;
3116

3117 3118
	printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
	       DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
3119
	       yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
S
Stephen Hemminger 已提交
3120
	       hw->chip_id, hw->chip_rev);
3121

S
Stephen Hemminger 已提交
3122 3123
	dev = sky2_init_netdev(hw, 0, using_dac);
	if (!dev)
3124 3125
		goto err_out_free_pci;

S
Stephen Hemminger 已提交
3126 3127
	err = register_netdev(dev);
	if (err) {
3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139
		printk(KERN_ERR PFX "%s: cannot register net device\n",
		       pci_name(pdev));
		goto err_out_free_netdev;
	}

	sky2_show_addr(dev);

	if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
		if (register_netdev(dev1) == 0)
			sky2_show_addr(dev1);
		else {
			/* Failure to register second port need not be fatal */
S
Stephen Hemminger 已提交
3140 3141
			printk(KERN_WARNING PFX
			       "register of second port failed\n");
3142 3143 3144 3145 3146
			hw->dev[1] = NULL;
			free_netdev(dev1);
		}
	}

S
Stephen Hemminger 已提交
3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158
	err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
	if (err) {
		printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
		       pci_name(pdev), pdev->irq);
		goto err_out_unregister;
	}

	hw->intr_mask = Y2_IS_BASE;
	sky2_write32(hw, B0_IMSK, hw->intr_mask);

	pci_set_drvdata(pdev, hw);

3159 3160
	return 0;

S
Stephen Hemminger 已提交
3161 3162 3163 3164 3165 3166
err_out_unregister:
	if (dev1) {
		unregister_netdev(dev1);
		free_netdev(dev1);
	}
	unregister_netdev(dev);
3167 3168 3169
err_out_free_netdev:
	free_netdev(dev);
err_out_free_pci:
S
Stephen Hemminger 已提交
3170
	sky2_write8(hw, B0_CTST, CS_RST_SET);
3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184
	pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
err_out_iounmap:
	iounmap(hw->regs);
err_out_free_hw:
	kfree(hw);
err_out_free_regions:
	pci_release_regions(pdev);
	pci_disable_device(pdev);
err_out:
	return err;
}

static void __devexit sky2_remove(struct pci_dev *pdev)
{
S
Stephen Hemminger 已提交
3185
	struct sky2_hw *hw = pci_get_drvdata(pdev);
3186 3187
	struct net_device *dev0, *dev1;

S
Stephen Hemminger 已提交
3188
	if (!hw)
3189 3190 3191
		return;

	dev0 = hw->dev[0];
S
Stephen Hemminger 已提交
3192 3193 3194
	dev1 = hw->dev[1];
	if (dev1)
		unregister_netdev(dev1);
3195 3196
	unregister_netdev(dev0);

S
Stephen Hemminger 已提交
3197
	sky2_write32(hw, B0_IMSK, 0);
3198
	sky2_set_power_state(hw, PCI_D3hot);
3199
	sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
S
Stephen Hemminger 已提交
3200
	sky2_write8(hw, B0_CTST, CS_RST_SET);
3201
	sky2_read8(hw, B0_CTST);
3202 3203

	free_irq(pdev->irq, hw);
S
Stephen Hemminger 已提交
3204
	pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3205 3206
	pci_release_regions(pdev);
	pci_disable_device(pdev);
S
Stephen Hemminger 已提交
3207

3208 3209 3210 3211 3212
	if (dev1)
		free_netdev(dev1);
	free_netdev(dev0);
	iounmap(hw->regs);
	kfree(hw);
3213

3214 3215 3216 3217 3218 3219
	pci_set_drvdata(pdev, NULL);
}

#ifdef CONFIG_PM
static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
{
S
Stephen Hemminger 已提交
3220
	struct sky2_hw *hw = pci_get_drvdata(pdev);
3221
	int i;
3222 3223 3224 3225 3226

	for (i = 0; i < 2; i++) {
		struct net_device *dev = hw->dev[i];

		if (dev) {
3227 3228 3229 3230
			if (!netif_running(dev))
				continue;

			sky2_down(dev);
3231 3232 3233 3234
			netif_device_detach(dev);
		}
	}

3235
	return sky2_set_power_state(hw, pci_choose_state(pdev, state));
3236 3237 3238 3239
}

static int sky2_resume(struct pci_dev *pdev)
{
S
Stephen Hemminger 已提交
3240
	struct sky2_hw *hw = pci_get_drvdata(pdev);
3241 3242 3243 3244
	int i;

	pci_restore_state(pdev);
	pci_enable_wake(pdev, PCI_D0, 0);
3245
	sky2_set_power_state(hw, PCI_D0);
3246 3247 3248 3249 3250 3251

	sky2_reset(hw);

	for (i = 0; i < 2; i++) {
		struct net_device *dev = hw->dev[i];
		if (dev) {
3252 3253
			if (netif_running(dev)) {
				netif_device_attach(dev);
3254 3255
				if (sky2_up(dev))
					dev_close(dev);
3256
			}
3257 3258 3259 3260 3261 3262 3263
		}
	}
	return 0;
}
#endif

static struct pci_driver sky2_driver = {
S
Stephen Hemminger 已提交
3264 3265 3266 3267
	.name = DRV_NAME,
	.id_table = sky2_id_table,
	.probe = sky2_probe,
	.remove = __devexit_p(sky2_remove),
3268
#ifdef CONFIG_PM
S
Stephen Hemminger 已提交
3269 3270
	.suspend = sky2_suspend,
	.resume = sky2_resume,
3271 3272 3273 3274 3275
#endif
};

static int __init sky2_init_module(void)
{
3276
	return pci_register_driver(&sky2_driver);
3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289
}

static void __exit sky2_cleanup_module(void)
{
	pci_unregister_driver(&sky2_driver);
}

module_init(sky2_init_module);
module_exit(sky2_cleanup_module);

MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
MODULE_LICENSE("GPL");
3290
MODULE_VERSION(DRV_VERSION);