[bsp] add core-v-mcu bsp (#6705)

* add core-v-mcu bsp

* 规范bsp格式 添加readme

* 修改readme

Co-authored-by: 1516081466@qq.com <ws051000>

bsp/core-v-mcu/Libraries/Kconfig

+config SOC_RISCV_FAMILY_Core_V
+    bool
+
+config SOC_RISCV_SERIES_Core_V
+    bool
+    select ARCH_RISCV
+    select SOC_RISCV_FAMILY_Core_V

bsp/core-v-mcu/Libraries/core_v_drivers/SConscript

+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+
+src = Split("""
+source/udma_uart_driver.c
+""")
+
+if  GetDepend('SOC_RISCV_FAMILY_Core_V'):
+
+    if GetDepend('BSP_USING_UART'):
+        src += ['source/drv_usart.c']
+
+path = [
+	cwd + '/include']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/core-v-mcu/Libraries/core_v_drivers/include/camera.h

+#ifndef __CAMERA_H__
+#define __CAMERA_H__
+
+//#include <FreeRTOS.h>
+#include <queue.h>
+#include "himax.h"
+
+
+typedef struct {
+	volatile uint32_t *rx_saddr; // 0x00
+	volatile uint32_t rx_size; 	 // 0x04
+	volatile uint32_t rx_cfg;    // 0x08
+	volatile uint32_t rx_initcfg;// 0x0C
+	volatile uint32_t *tx_saddr; // 0x10
+	volatile uint32_t tx_size;   // 0x14
+	volatile uint32_t tx_cfg;    // 0x18
+	volatile uint32_t tx_initcfg;// 0x1C
+	volatile uint32_t cfg_glob;  // 0x20
+	volatile uint32_t cfg_ll;    // 0x24
+	volatile uint32_t cfg_ur;    // 0x28
+	volatile uint32_t cfg_size;  // 0x2C
+	volatile uint32_t cfg_filter;// 0x30
+	volatile uint32_t vsync_pol; // 0x34
+
+} camera_struct_t;
+
+typedef struct {
+	uint16_t addr;
+	uint8_t data;
+}reg_cfg_t;
+
+
+#endif

bsp/core-v-mcu/Libraries/core_v_drivers/include/drv_log.h

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-15     SummerGift   first version
+ */
+
+/*
+ * NOTE: DO NOT include this file on the header file.
+ */
+
+#ifndef LOG_TAG
+#define DBG_TAG               "drv"
+#else
+#define DBG_TAG               LOG_TAG
+#endif /* LOG_TAG */
+
+#ifdef DRV_DEBUG
+#define DBG_LVL               DBG_LOG
+#else
+#define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+
+#include <rtdbg.h>

bsp/core-v-mcu/Libraries/core_v_drivers/include/drv_usart.h

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-12-08     WangShun     the first version
+ */
+#ifndef __DRV_USART_H__
+#define __DRV_USART_H__
+#include <rtthread.h>
+#include "rtdevice.h"
+#include <rthw.h>
+
+/* corev config class */
+struct corev_uart_config
+{
+    const char *name;
+};
+
+/* corevs uart dirver class */
+struct corev_uart
+{
+    struct corev_uart_config *config;
+    struct rt_serial_device serial;
+};
+
+extern void uart_rx_isr (void *id);
+int rt_hw_usart_init(void);
+#endif

bsp/core-v-mcu/Libraries/core_v_drivers/include/himax.h

+/*
+ * Copyright (C) 2018 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * Copyright (C) 2018 GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __HIMAX_H__
+#define __HIMAX_H__
+
+/*
+ *  HIMAX camera macros
+ */
+// Register address
+// Read only registers
+#define         MODEL_ID_H          0x0000
+#define         MODEL_ID_L          0x0001
+#define         FRAME_COUNT         0x0005
+#define         PIXEL_ORDER         0x0006
+// R&W registers
+// Sensor mode control
+#define         MODE_SELECT         0x0100
+#define         IMG_ORIENTATION     0x0101
+#define         SW_RESET            0x0103
+#define         GRP_PARAM_HOLD      0x0104
+// Sensor exposure gain control
+#define         INTEGRATION_H       0x0202
+#define         INTEGRATION_L       0x0203
+#define         ANALOG_GAIN         0x0205
+#define         DIGITAL_GAIN_H      0x020E
+#define         DIGITAL_GAIN_L      0x020F
+// Frame timing control
+#define         FRAME_LEN_LINES_H   0x0340
+#define         FRAME_LEN_LINES_L   0x0341
+#define         LINE_LEN_PCK_H      0x0342
+#define         LINE_LEN_PCK_L      0x0343
+// Binning mode control
+#define         READOUT_X           0x0383
+#define         READOUT_Y           0x0387
+#define         BINNING_MODE        0x0390
+// Test pattern control
+#define         TEST_PATTERN_MODE   0x0601
+// Black level control
+#define         BLC_CFG             0x1000
+#define         BLC_TGT             0x1003
+#define         BLI_EN              0x1006
+#define         BLC2_TGT            0x1007
+//  Sensor reserved
+#define         DPC_CTRL            0x1008
+#define         SINGLE_THR_HOT      0x100B
+#define         SINGLE_THR_COLD     0x100C
+// VSYNC,HSYNC and pixel shift register
+#define         VSYNC_HSYNC_PIXEL_SHIFT_EN  0x1012
+// Automatic exposure gain control
+#define         AE_CTRL             0x2100
+#define         AE_TARGET_MEAN      0x2101
+#define         AE_MIN_MEAN         0x2102
+#define         CONVERGE_IN_TH      0x2103
+#define         CONVERGE_OUT_TH     0x2104
+#define         MAX_INTG_H          0x2105
+#define         MAX_INTG_L          0x2106
+#define         MIN_INTG            0x2107
+#define         MAX_AGAIN_FULL      0x2108
+#define         MAX_AGAIN_BIN2      0x2109
+#define         MIN_AGAIN           0x210A
+#define         MAX_DGAIN           0x210B
+#define         MIN_DGAIN           0x210C
+#define         DAMPING_FACTOR      0x210D
+#define         FS_CTRL             0x210E
+#define         FS_60HZ_H           0x210F
+#define         FS_60HZ_L           0x2110
+#define         FS_50HZ_H           0x2111
+#define         FS_50HZ_L           0x2112
+#define         FS_HYST_TH          0x2113
+// Motion detection control
+#define         MD_CTRL             0x2150
+#define         I2C_CLEAR           0x2153
+#define         WMEAN_DIFF_TH_H     0x2155
+#define         WMEAN_DIFF_TH_M     0x2156
+#define         WMEAN_DIFF_TH_L     0x2157
+#define         MD_THH              0x2158
+#define         MD_THM1             0x2159
+#define         MD_THM2             0x215A
+#define         MD_THL              0x215B
+//  Sensor timing control
+#define         QVGA_WIN_EN         0x3010
+#define         SIX_BIT_MODE_EN     0x3011
+#define         PMU_AUTOSLEEP_FRAMECNT  0x3020
+#define         ADVANCE_VSYNC       0x3022
+#define         ADVANCE_HSYNC       0x3023
+#define         EARLY_GAIN          0x3035
+//  IO and clock control
+#define         BIT_CONTROL         0x3059
+#define         OSC_CLK_DIV         0x3060
+#define         ANA_Register_11     0x3061
+#define         IO_DRIVE_STR        0x3062
+#define         IO_DRIVE_STR2       0x3063
+#define         ANA_Register_14     0x3064
+#define         OUTPUT_PIN_STATUS_CONTROL   0x3065
+#define         ANA_Register_17     0x3067
+#define         PCLK_POLARITY       0x3068
+
+/*
+ * Useful value of Himax registers
+ */
+#define         HIMAX_RESET         0x01
+#define         Pclk_rising_edge    0x00
+#define         Pclk_falling_edge   0x01
+
+#define         BYPASS_BIGEND       5
+
+enum{
+    HIMAX_Standby = 0x0,
+    HIMAX_Streaming = 0x1,        // I2C triggered streaming enable
+    HIMAX_Streaming2 = 0x3,       // Output N frames
+    HIMAX_Streaming3 = 0x5        // Hardware Trigger
+};
+
+#endif

bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_cam_driver.h

+/*
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef DRIVERS_INCLUDE_UDMA_CAM_DRIVER_H_
+#define DRIVERS_INCLUDE_UDMA_CAM_DRIVER_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "hal_udma_ctrl_reg_defs.h"
+#include "hal_udma_cam_reg_defs.h"
+
+typedef enum {
+		kCamReset,
+		kCamID,
+		kCamInit,
+		kCamFrame
+} udma_cam_control_type_t;
+
+typedef enum {
+	kSPIm_Cfg 	    = (0x0 << 28),
+	kSPIm_SOT	    = (0x1 << 28),
+	kSPIm_SendCmd	= (0x2 << 28),
+	kSPIm_Dummy	    = (0x4 << 28),
+	kSPIm_Wait		= (0x5 << 28),
+	kSPIm_TxData	= (0x6 << 28),
+	kSPIm_RxData  	= (0x7 << 28),
+	kSPIm_Repeat	= (0x8 << 28),
+	kSPIm_EOT		= (0x9 << 28),
+	kSPIm_RepeatEnd = (0xa << 28),
+	kSPIm_RxCheck	= (0xb << 28),
+	kSPIm_FDX 		= (0xc << 28),
+	kSPIm_UCA 		= (0xd << 28),
+	kSPIm_UCS 		= (0xe << 28)
+
+} cam_cmd_t;
+
+
+uint16_t udma_cam_control(udma_cam_control_type_t control_type, void* pparam);
+void cam_open (uint8_t cam_id);
+
+
+// helper functions
+void _himaxRegWrite(unsigned int addr, unsigned char value);
+
+#endif /* DRIVERS_INCLUDE_UDMA_CAM_DRIVER_H_ */

bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_i2cm_driver.h

+/*
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef DRIVERS_INCLUDE_UDMA_I2CM_DRIVER_H_
+#define DRIVERS_INCLUDE_UDMA_I2CM_DRIVER_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "hal_udma_ctrl_reg_defs.h"
+
+#define SEMAPHORE_WAIT_TIME_IN_MS	10
+
+typedef enum {
+		kI2cmReset
+} udma_i2cm_control_type_t;
+
+typedef enum {
+	kI2cmCmdStart 	= 0x00,
+	kI2cmCmdStop	= 0x20,
+	kI2cmCmdRdAck	= 0x40,
+	kI2cmCmdRdNack	= 0x60,
+	kI2cmCmdWr		= 0x80,
+	kI2cmCmdWait	= 0xA0,
+	kI2cmCmdRpt		= 0xC0,
+	kI2cmCmdCfg		= 0xE0,
+	kI2cmCmdWaitEvt	= 0x10,
+} i2cm_cmd_t;
+
+uint16_t udma_i2cm_open (uint8_t i2c_id, uint32_t i2c_clk_freq);
+uint16_t udma_i2cm_close (uint8_t i2c_id);
+uint16_t udma_i2cm_control(uint8_t i2c_id, udma_i2cm_control_type_t control_type, void* pparam);
+uint8_t udma_i2cm_write(uint8_t i2c_id, uint8_t i2c_addr, uint8_t reg_addr, uint16_t write_len, uint8_t* write_data, bool more_follows);
+uint8_t udma_i2cm_read(uint8_t i2c_id, uint8_t i2c_addr, uint8_t reg_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows);
+uint8_t udma_i2cm_16read8(uint8_t i2c_id, uint8_t i2c_addr, uint16_t reg_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows);
+
+
+
+// helper functions
+uint8_t _udma_i2cm_write_addr_plus_regaddr (uint8_t i2c_id, uint8_t i2c_addr, uint8_t reg_addr);
+uint8_t _udma_i2cm_write_addr_plus_reg16addr (uint8_t i2c_id, uint8_t i2c_addr, uint16_t reg_addr);
+uint8_t _udma_i2cm_read(uint8_t i2c_id, uint8_t i2c_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows);
+uint8_t _udma_i2cm_send_stop(uint8_t i2c_id);
+
+#endif /* DRIVERS_INCLUDE_UDMA_I2CM_DRIVER_H_ */
+

bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_qspi_driver.h

+/*
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef DRIVERS_INCLUDE_UDMA_QSPIM_DRIVER_H_
+#define DRIVERS_INCLUDE_UDMA_QSPIM_DRIVER_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "hal_udma_ctrl_reg_defs.h"
+
+typedef enum {
+		kQSPImReset
+} udma_qspim_control_type_t;
+
+typedef enum {
+	kSPIm_Cfg 	    = (0x0 << 28),
+	kSPIm_SOT	    = (0x1 << 28),
+	kSPIm_SendCmd	= (0x2 << 28),
+	kSPIm_Dummy	    = (0x4 << 28),
+	kSPIm_Wait		= (0x5 << 28),
+	kSPIm_TxData	= (0x6 << 28),
+	kSPIm_RxData  	= (0x7 << 28),
+	kSPIm_Repeat	= (0x8 << 28),
+	kSPIm_EOT		= (0x9 << 28),
+	kSPIm_RepeatEnd = (0xa << 28),
+	kSPIm_RxCheck	= (0xb << 28),
+	kSPIm_FDX 		= (0xc << 28),
+	kSPIm_UCA 		= (0xd << 28),
+	kSPIm_UCS 		= (0xe << 28)
+
+} spim_cmd_t;
+
+uint16_t udma_qspim_open (uint8_t qspim_id, uint32_t spi_clk_freq);
+uint16_t udma_qspim_close (uint8_t qspim_id);
+uint16_t udma_qspim_control(uint8_t qspim_id, udma_qspim_control_type_t control_type, void* pparam);
+void udma_qspim_write(uint8_t qspim_id, uint8_t cs, uint16_t write_len, uint8_t* write_data);
+void udma_qspim_read(uint8_t qspim_id,  uint8_t cs, uint16_t read_len, uint8_t* read_buffer);
+uint8_t udma_flash_erase(uint8_t qspim_id, uint8_t cs, uint32_t addr, uint8_t cmd);
+uint32_t udma_flash_readid(uint8_t qspim_id, uint8_t cs);
+void udma_flash_read(uint8_t qspim_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t read_len ) ;
+void udma_flash_write(uint8_t qspim_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t write_len ) ;
+uint32_t udma_flash_reset_enable(uint8_t qspim_id, uint8_t cs);
+uint32_t udma_flash_reset_memory(uint8_t qspim_id, uint8_t cs);
+
+// helper functions
+
+
+#endif /* DRIVERS_INCLUDE_UDMA_QSPIM_DRIVER_H_ */

bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_sdio_driver.h

+/*
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef DRIVERS_INCLUDE_UDMA_SDIO_DRIVER_H_
+#define DRIVERS_INCLUDE_UDMA_SDIO_DRIVER_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "hal_udma_ctrl_reg_defs.h"
+
+typedef enum {
+		kSDIOmReset
+} udma_sdio_control_type_t;
+/*
+typedef enum {
+	kSPIm_Cfg 	    = (0x0 << 28),
+	kSPIm_SOT	    = (0x1 << 28),
+	kSPIm_SendCmd	= (0x2 << 28),
+	kSPIm_Dummy	    = (0x4 << 28),
+	kSPIm_Wait		= (0x5 << 28),
+	kSPIm_TxData	= (0x6 << 28),
+	kSPIm_RxData  	= (0x7 << 28),
+	kSPIm_Repeat	= (0x8 << 28),
+	kSPIm_EOT		= (0x9 << 28),
+	kSPIm_RepeatEnd = (0xa << 28),
+	kSPIm_RxCheck	= (0xb << 28),
+	kSPIm_FDX 		= (0xc << 28),
+	kSPIm_UCA 		= (0xd << 28),
+	kSPIm_UCS 		= (0xe << 28)
+
+} spim_cmd_t;
+*/
+uint16_t udma_sdio_open (uint8_t sdio_id);
+uint16_t udma_sdio_close (uint8_t sdio_id);
+uint16_t udma_sdio_control(uint8_t sdio_id, udma_sdio_control_type_t control_type, void* pparam);
+uint8_t udma_sdio_sendCmd(uint8_t sdio_id, uint8_t aCmdOpCode, uint8_t aRspType, uint32_t aCmdArgument, uint32_t *aResponseBuf);
+void udma_sdio_write(uint8_t sdio_id, uint8_t cs, uint16_t write_len, uint8_t* write_data);
+void udma_sdio_read(uint8_t sdio_id,  uint8_t cs, uint16_t read_len, uint8_t* read_buffer);
+uint8_t udma_flash_erase(uint8_t sdio_id, uint8_t cs, uint32_t addr, uint8_t cmd);
+uint32_t udma_flash_readid(uint8_t sdio_id, uint8_t cs);
+void udma_flash_read(uint8_t sdio_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t read_len ) ;
+void udma_flash_write(uint8_t sdio_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t write_len ) ;
+uint32_t udma_flash_reset_enable(uint8_t sdio_id, uint8_t cs);
+uint32_t udma_flash_reset_memory(uint8_t sdio_id, uint8_t cs);
+
+uint8_t udma_sdio_readBlockData(uint8_t sdio_id, uint32_t aNumOfBlocks, uint32_t *aBuf, uint32_t aBufLen);
+uint8_t udma_sdio_writeBlockData(uint8_t sdio_id, uint32_t aNumOfBlocks, uint32_t *aBuf, uint32_t aBufLen);
+void udma_sdio_clearDataSetup(uint8_t sdio_id);
+
+// helper functions
+
+
+#endif /* DRIVERS_INCLUDE_UDMA_QSPIM_DRIVER_H_ */

bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_uart_driver.h

+/*
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+ 
+#ifndef __UDMA_UART_DRIVER_H_
+#define __UDMA_UART_DRIVER_H_
+
+#include "stdint.h"
+
+#include "hal_udma_ctrl_reg_defs.h"
+
+typedef enum {
+		kUartDataValid
+} udma_uart_control_type_t;
+
+uint16_t udma_uart_open (uint8_t uart_id, uint32_t xbaudrate);
+uint16_t udma_uart_close (uint8_t uart_id);
+uint16_t udma_uart_write(uint8_t uart_id, uint16_t write_len, uint8_t* write_buffer);
+uint16_t udma_uart_writeraw(uint8_t uart_id, uint16_t write_len, uint8_t* write_buffer);
+uint16_t udma_uart_read(uint8_t uart_id, uint16_t read_len, uint8_t* read_buffer);
+uint16_t udma_uart_readraw(uint8_t uart_id, uint16_t read_len, uint8_t* read_buffer);
+uint8_t udma_uart_getchar(uint8_t uart_id);
+uint16_t udma_uart_control(uint8_t uart_id, udma_uart_control_type_t control_type, void* pparam);
+
+#endif //__UDMA_UART_DRIVER_H_

bsp/core-v-mcu/Libraries/core_v_drivers/source/drv_usart.c

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-12-08     WangShun          the first version
+ */
+
+#include "board.h"
+#include <rtdevice.h>
+#include <drv_usart.h>
+#include "hal_udma_ctrl_reg_defs.h"
+#include "hal_udma_uart_reg_defs.h"
+#include "udma_uart_driver.h"
+#include <string.h>
+#include "core-v-mcu-config.h"
+
+#ifdef RT_USING_SERIAL
+//#define DRV_DEBUG
+#define LOG_TAG              "drv.uart"
+#include <drv_log.h>
+
+#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) && \
+    !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) 
+    #error "Please define at least one BSP_USING_UARTx"
+    /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
+#endif
+
+extern char u1buffer[128], u0buffer[128];
+extern  int u1rdptr, u1wrptr, u0rdptr,u0wrptr;
+extern UdmaUart_t *puart0 ;
+extern UdmaUart_t *puart1 ;
+
+enum
+{
+    UART1_INDEX,
+};
+
+struct corev_uart_config uart_config[1] =
+{
+   {
+     "uart1"
+   }
+};
+
+struct corev_uart uart_obj[1] = {0};
+
+static rt_err_t corev_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+     return RT_EOK;
+}
+
+static rt_err_t corev_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    return RT_EOK;
+}
+
+uint16_t rt_writeraw(uint8_t uart_id, uint16_t write_len, uint8_t* write_buffer) {
+	UdmaUart_t*				puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
+
+	while (puart->status_b.tx_busy) {
+	}
+
+	puart->tx_saddr = (uint32_t)write_buffer;
+	puart->tx_size = write_len;
+	puart->tx_cfg_b.en = 1;
+
+	return 0;
+}
+
+static int corev_putc(struct rt_serial_device *serial, char c)
+{
+	char put_data =c;
+    struct corev_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = (struct corev_uart *)serial->parent.user_data;
+    rt_writeraw(0, 1,&put_data);
+
+    return 1;
+}
+
+static int corev_getc(struct rt_serial_device *serial)
+{
+    signed char ch;
+    struct corev_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct corev_uart *)serial->parent.user_data;
+    ch = -1;
+
+	UdmaUart_t*	puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + 0 * UDMA_CH_SIZE);
+
+	if (puart->valid_b.rx_data_valid == 1) {
+		ch = puart->data_b.rx_data & 0xff;
+	}
+
+    return (int)ch;
+}
+
+rt_size_t corevdma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
+{
+    return RT_EOK;
+}
+
+ void uart_isr(struct rt_serial_device *serial)
+{
+    struct corev_uart *uart = (struct corev_uart *) serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+    rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+}
+
+static const struct rt_uart_ops corev_uart_ops =
+{
+    corev_configure,
+    corev_control,
+    corev_putc,
+    corev_getc,
+    corevdma_transmit
+};
+
+void uart_rx_isr (void *id){
+	rt_interrupt_enter();
+	if (id == 6) {
+		while (*(int*)0x1a102130) {
+			u1buffer[u1wrptr++] = puart1->data_b.rx_data & 0xff;
+			u1wrptr &= 0x7f;
+		}
+	}
+	if (id == 2) {//use this uart
+		while (puart0->valid) {
+			uart_isr(&(uart_obj[UART1_INDEX].serial));
+		}
+	}
+	rt_interrupt_leave();
+}
+
+int rt_hw_usart_init(void)
+{
+    rt_size_t obj_num = 1;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+    rt_err_t result = 0;
+
+    for (int i = 0; i < obj_num; i++)
+    {
+        /* init UART object */
+        uart_obj[i].config        = &uart_config[i];
+        uart_obj[i].serial.ops    = &corev_uart_ops;
+        uart_obj[i].serial.config = config;
+
+        /* register UART device */
+        result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
+                                       RT_DEVICE_FLAG_RDWR
+                                       | RT_DEVICE_FLAG_INT_RX
+                                       ,&uart_obj[i]);
+        RT_ASSERT(result == RT_EOK);
+    }
+    return result;
+}
+
+#endif /* RT_USING_SERIAL */

bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_cam_driver.c

+/*
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <drivers/include/camera.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdbool.h>
+//#include "FreeRTOS.h"
+#include "semphr.h"
+
+#include "target/core-v-mcu/include/core-v-mcu-config.h"
+
+#include "hal/include/hal_fc_event.h"
+#include "hal/include/hal_udma_ctrl_reg_defs.h"
+#include "hal/include/hal_udma_cam_reg_defs.h"
+
+#include <drivers/include/udma_cam_driver.h>
+#include <drivers/include/udma_i2cm_driver.h>
+
+#include "drivers/include/himax.h"
+#include "drivers/include/camera.h"
+
+reg_cfg_t himaxRegInit[] = {
+    {BLC_TGT, 0x08},            //  BLC target :8  at 8 bit mode
+    {BLC2_TGT, 0x08},           //  BLI target :8  at 8 bit mode
+    {0x3044, 0x0A},             //  Increase CDS time for settling
+    {0x3045, 0x00},             //  Make symetric for cds_tg and rst_tg
+    {0x3047, 0x0A},             //  Increase CDS time for settling
+    {0x3050, 0xC0},             //  Make negative offset up to 4x
+    {0x3051, 0x42},
+    {0x3052, 0x50},
+    {0x3053, 0x00},
+    {0x3054, 0x03},             //  tuning sf sig clamping as lowest
+    {0x3055, 0xF7},             //  tuning dsun
+    {0x3056, 0xF8},             //  increase adc nonoverlap clk
+    {0x3057, 0x29},             //  increase adc pwr for missing code
+    {0x3058, 0x1F},             //  turn on dsun
+    {0x3059, 0x1E},
+    {0x3064, 0x00},
+    {0x3065, 0x04},             //  pad pull 0
+
+    {BLC_CFG, 0x43},            //  BLC_on, IIR
+
+    {0x1001, 0x43},             //  BLC dithering en
+    {0x1002, 0x43},             //  blc_darkpixel_thd
+    {0x0350, 0x00},             //  Dgain Control
+    {BLI_EN, 0x01},             //  BLI enable
+    {0x1003, 0x00},             //  BLI Target [Def: 0x20]
+
+    {DPC_CTRL, 0x01},           //  DPC option 0: DPC off   1 : mono   3 : bayer1   5 : bayer2
+    {0x1009, 0xA0},             //  cluster hot pixel th
+    {0x100A, 0x60},             //  cluster cold pixel th
+    {SINGLE_THR_HOT, 0x90},     //  single hot pixel th
+    {SINGLE_THR_COLD, 0x40},    //  single cold pixel th
+    {0x1012, 0x00},             //  Sync. shift disable
+    {0x2000, 0x07},
+    {0x2003, 0x00},
+    {0x2004, 0x1C},
+    {0x2007, 0x00},
+    {0x2008, 0x58},
+    {0x200B, 0x00},
+    {0x200C, 0x7A},
+    {0x200F, 0x00},
+    {0x2010, 0xB8},
+    {0x2013, 0x00},
+    {0x2014, 0x58},
+    {0x2017, 0x00},
+    {0x2018, 0x9B},
+
+    {AE_CTRL,        0x01},      //Automatic Exposure Gain Control
+    {AE_TARGET_MEAN, 0x3C},      //AE target mean [Def: 0x3C]
+    {AE_MIN_MEAN,    0x0A},      //AE min target mean [Def: 0x0A]
+
+    {INTEGRATION_H,  0x00},      //Integration H [Def: 0x01]
+    {INTEGRATION_L,  0x60},      //Integration L [Def: 0x08]
+    {ANALOG_GAIN,    0x00},      //Analog Global Gain
+    {DAMPING_FACTOR, 0x20},      //Damping Factor [Def: 0x20]
+    {DIGITAL_GAIN_H, 0x01},      //Digital Gain High [Def: 0x01]
+    {DIGITAL_GAIN_L, 0x00},      //Digital Gain Low [Def: 0x00]
+
+    {0x2103, 0x03},
+
+    {0x2104, 0x05},
+    {0x2105, 0x01},
+
+    {0x2106, 0x54},
+
+    {0x2108, 0x03},
+    {0x2109, 0x04},
+
+    {0x210B, 0xC0},
+    {0x210E, 0x00}, //Flicker Control
+    {0x210F, 0x00},
+    {0x2110, 0x3C},
+    {0x2111, 0x00},
+    {0x2112, 0x32},
+
+    {0x2150, 0x30},
+    {0x0340, 0x02},
+    {0x0341, 0x16},
+    {0x0342, 0x01},
+    {0x0343, 0x78},
+    {0x3010, 0x01},
+    {0x0383, 0x01},
+    {0x0387, 0x01},
+    {0x0390, 0x00},
+    {0x3011, 0x70},
+    {0x3059, 0x02},
+    {0x3060, 0x01},
+//    {0x3060, 0x25}, //Clock gating and clock divisors
+    {0x3068, 0x20}, //PCLK0 polarity
+    {IMG_ORIENTATION, 0x01}, // change the orientation
+    {0x0104, 0x01},
+    {0x0100, 0x01},
+	//{0x0601, 0x11}	//Test pattern walking ones
+	//{0x0601, 0x01}	//Test pattern colour bar
+};
+
+SemaphoreHandle_t  cam_semaphore_rx;
+static uint8_t cam;
+static void camISR() {
+
+}
+void cam_open (uint8_t cam_id)
+{
+	int i = 0;
+	volatile UdmaCtrl_t*		pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
+
+	/* Enable reset and enable uart clock */
+	pudma_ctrl->reg_rst |= (UDMA_CTRL_CAM0_CLKEN << cam_id);
+	pudma_ctrl->reg_rst &= ~(UDMA_CTRL_CAM0_CLKEN << cam_id);
+	pudma_ctrl->reg_cg |= (UDMA_CTRL_CAM0_CLKEN << cam_id);
+
+	//psdio_regs->clk_div_b.clk_div = 5;
+	//psdio_regs->clk_div_b.valid = 1;
+	hal_setpinmux(21, 0);
+	hal_setpinmux(22, 0);
+	hal_setpinmux(25, 0);
+	for(i=0; i<8; i++ )
+	{
+		//set pin muxes to sdio functionality
+		 hal_setpinmux(29+i, 0);
+	}
+
+	/* See if already initialized */
+	if (cam_semaphore_rx != NULL ){
+		return;
+	}
+
+	/* Set semaphore */
+	SemaphoreHandle_t shSemaphoreHandle;		// FreeRTOS.h has a define for xSemaphoreHandle, so can't use that
+	shSemaphoreHandle = xSemaphoreCreateBinary();
+	configASSERT(shSemaphoreHandle);
+	xSemaphoreGive(shSemaphoreHandle);
+	cam_semaphore_rx = shSemaphoreHandle;
+
+
+	/* Set handlers. */
+	pi_fc_event_handler_set(SOC_EVENT_UDMA_CAM_RX(cam_id), camISR, cam_semaphore_rx);
+	/* Enable SOC events propagation to FC. */
+	hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_CAM_RX(cam_id));
+
+	/* configure */
+	cam = 0x48; // Himax address
+	udma_cam_control(kCamReset, NULL);
+
+	return;
+}
+uint16_t udma_cam_control(udma_cam_control_type_t control_type, void* pparam) {
+	short retval = 0;
+	uint16_t i;
+	SemaphoreHandle_t shSemaphoreHandle;
+	camera_struct_t *camera;
+	//camera = (camera_struct_t *)0x1A102300;  // Peripheral 5?
+	camera = (camera_struct_t *)(UDMA_CH_ADDR_CAM + 0 * UDMA_CH_SIZE);
+	shSemaphoreHandle = cam_semaphore_rx;
+
+	switch (control_type) {
+	case kCamReset:
+		_himaxRegWrite(SW_RESET, HIMAX_RESET);
+		break;
+	case kCamID:
+		udma_i2cm_16read8(0, cam, MODEL_ID_H, 2, &retval, 0);
+		retval = (retval >> 8) & 0xff | (retval <<8);
+		break;
+	case kCamInit:
+	    for(i=0; i<(sizeof(himaxRegInit)/sizeof(reg_cfg_t)); i++){
+	        _himaxRegWrite(himaxRegInit[i].addr, himaxRegInit[i].data);
+	    }
+	    camera->cfg_ll = 0<<16 | 0;
+	    	camera->cfg_ur = 323<<16 | 243; // 320 x 240 ?
+	    	camera->cfg_filter = (1 << 16) | (1 << 8) | 1;
+	    	camera->cfg_size = 324;
+	    	camera->vsync_pol = 1;
+	    	camera->cfg_glob = (0 << 0) | //  framedrop disabled
+	    			(000000 << 1) | // number of frames to drop
+	    			(0 << 7) | // Frame slice disabled
+	    			(004 << 8) | // Format binary 100 = ByPass little endian
+	    			(0000 << 11);  // Shift value ignored in bypass
+
+	    break;
+	case kCamFrame:
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		camera->rx_saddr = pparam;
+		camera->rx_size = (244*324);
+		camera->rx_cfg = 0x12;  // start 16-bit transfers
+    	camera->cfg_glob = camera->cfg_glob |
+    			(1 << 31) ; // enable 1 == go
+
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+    	camera->cfg_glob = camera->cfg_glob &
+    			(0x7fffffff) ; // enable 1 == go
+		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
+	}
+	return retval;
+}
+
+void _himaxRegWrite(unsigned int addr, unsigned char value){
+	uint8_t naddr;
+	uint16_t data;
+	naddr = (addr>>8) & 0xff;
+	data = (value << 8) | (addr & 0xff);
+	udma_i2cm_write (0, cam, naddr, 2, &data, 0);
+   //     i2c_16write8(cam,addr,value);
+}

bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_i2cm_driver.c

+/*
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include <stdint.h>
+#include <stdbool.h>
+//#include "FreeRTOS.h"
+#include "semphr.h"
+
+#include "target/core-v-mcu/include/core-v-mcu-config.h"
+
+#include "hal/include/hal_fc_event.h"
+#include "hal/include/hal_udma_ctrl_reg_defs.h"
+#include "hal/include/hal_udma_i2cm_reg_defs.h"
+
+#include <drivers/include/udma_i2cm_driver.h>
+
+#define  unuse_freertos_in_i2cm
+
+
+SemaphoreHandle_t  i2cm_semaphores_rx[N_I2CM];
+SemaphoreHandle_t  i2cm_semaphores_tx[N_I2CM];
+
+void i2cmTXHandler(void *arg)
+{
+	uint32_t lCounter = 0;
+
+	lCounter++;
+}
+
+void i2cmRXHandler(void *arg)
+{
+	uint32_t lCounter = 0;
+
+	lCounter++;
+}
+
+static uint8_t aucclkdiv[2];
+
+uint16_t udma_i2cm_open (uint8_t i2cm_id, uint32_t clk_freq) {
+	volatile UdmaCtrl_t*		pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
+	UdmaI2cm_t*					pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
+	uint32_t					clk_divisor;
+
+	/* See if already initialized */
+	if (i2cm_semaphores_rx[i2cm_id] != NULL || i2cm_semaphores_tx[i2cm_id] != NULL) {
+		return 1;
+	}
+	/* Enable reset and enable uart clock */
+	pudma_ctrl->reg_rst |= (UDMA_CTRL_I2CM0_CLKEN << i2cm_id);
+	pudma_ctrl->reg_rst &= ~(UDMA_CTRL_I2CM0_CLKEN << i2cm_id);
+	pudma_ctrl->reg_cg |= (UDMA_CTRL_I2CM0_CLKEN << i2cm_id);
+
+	/* Set semaphore */
+	#ifndef unuse_freertos_in_i2cm
+	SemaphoreHandle_t shSemaphoreHandle;		// FreeRTOS.h has a define for xSemaphoreHandle, so can't use that
+	shSemaphoreHandle = xSemaphoreCreateBinary();
+	configASSERT(shSemaphoreHandle);
+	xSemaphoreGive(shSemaphoreHandle);
+	i2cm_semaphores_rx[i2cm_id] = shSemaphoreHandle;
+
+	shSemaphoreHandle = xSemaphoreCreateBinary();
+	configASSERT(shSemaphoreHandle);
+	xSemaphoreGive(shSemaphoreHandle);
+	i2cm_semaphores_tx[i2cm_id] = shSemaphoreHandle;
+	#endif
+	/* Set handlers. */
+	pi_fc_event_handler_set(SOC_EVENT_UDMA_I2C_RX(i2cm_id), i2cmRXHandler/*NULL*/, i2cm_semaphores_rx[i2cm_id]);
+	pi_fc_event_handler_set(SOC_EVENT_UDMA_I2C_TX(i2cm_id), i2cmTXHandler/*NULL*/, i2cm_semaphores_tx[i2cm_id]);
+	/* Enable SOC events propagation to FC. */
+	hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_I2C_RX(i2cm_id));
+	hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_I2C_TX(i2cm_id));
+
+	/* configure */
+	clk_divisor = 5000000/clk_freq;
+	aucclkdiv[0] = (clk_divisor >> 0) & 0xFF;
+	aucclkdiv[1] = (clk_divisor >> 8) & 0xFF;
+
+	return 0;
+}
+
+uint16_t udma_i2cm_control(uint8_t i2cm_id, udma_i2cm_control_type_t control_type, void* pparam) {
+	volatile UdmaCtrl_t*		pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
+	UdmaI2cm_t*					pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
+
+	switch(control_type) {
+	case kI2cmReset:
+		pudma_ctrl->reg_rst |= (UDMA_CTRL_I2CM0_CLKEN << i2cm_id);
+		pudma_ctrl->reg_rst &= ~(UDMA_CTRL_I2CM0_CLKEN << i2cm_id);
+		break;
+	default:
+		configASSERT(0);
+	}
+	return 0;
+}
+
+static uint8_t auccmd_rx[16];
+
+uint8_t udma_i2cm_read(uint8_t i2cm_id, uint8_t i2cm_addr, uint8_t reg_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows) {
+	_udma_i2cm_write_addr_plus_regaddr(i2cm_id, i2cm_addr, reg_addr);
+	return _udma_i2cm_read(i2cm_id, i2cm_addr, read_len, read_buffer, more_follows);
+}
+uint8_t udma_i2cm_16read8(uint8_t i2cm_id, uint8_t i2cm_addr, uint16_t reg_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows) {
+	_udma_i2cm_write_addr_plus_reg16addr(i2cm_id, i2cm_addr, reg_addr);
+	return _udma_i2cm_read(i2cm_id, i2cm_addr, read_len, read_buffer, more_follows);
+}
+
+static uint8_t auccmd_tx[32];
+uint8_t udma_i2cm_write (uint8_t i2cm_id, uint8_t i2cm_addr, uint8_t reg_addr, uint16_t write_len, uint8_t *write_data,  bool more_follows) {
+	UdmaI2cm_t*					pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
+	uint8_t*					pcmd = auccmd_tx;
+	uint8_t*					pdata = write_data;
+	SemaphoreHandle_t 			shSemaphoreHandleTx = i2cm_semaphores_tx[i2cm_id];
+	uint8_t lStatus = pdFALSE;
+
+	configASSERT(write_len < 256);
+
+	if( xSemaphoreTake( shSemaphoreHandleTx, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE ) // Wait for any prior transmission to complete
+	{
+		*pcmd++ = kI2cmCmdCfg;
+		*pcmd++ = aucclkdiv[1];
+		*pcmd++ = aucclkdiv[0];
+		*pcmd++ = kI2cmCmdStart;			// Put Start transaction on I2C bus
+		*pcmd++ = kI2cmCmdRpt; 				// Set up for several writes: i2cm_CMD_RPT
+		*pcmd++ = (uint8_t)(write_len + 2);	// I@CM_ADDR + REG_ADDR + data
+		*pcmd++ = kI2cmCmdWr; 				// Command to repeat: I2C CMD_WR
+		*pcmd++ = i2cm_addr & 0xfe; 		// Clear R/WRbar bit from i2c device's address to indicate write
+		*pcmd++ = reg_addr;					// Target address for following data
+		for (int i = 0; i != write_len; i++) {
+			*pcmd++ = *pdata++;
+		}
+		pi2cm_regs->tx_saddr = auccmd_tx;
+		pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_tx);
+		pi2cm_regs->tx_cfg_b.en = 1;
+
+		// Block until UDMA transaction is completed
+		xSemaphoreTake( shSemaphoreHandleTx, SEMAPHORE_WAIT_TIME_IN_MS );
+		xSemaphoreGive( shSemaphoreHandleTx );
+
+		if (!more_follows) {
+			_udma_i2cm_send_stop(i2cm_id);
+		}
+		lStatus = pdTRUE;
+	}
+	else
+	{
+		xSemaphoreGive( shSemaphoreHandleTx );
+	}
+	return lStatus;
+}
+
+uint8_t _udma_i2cm_write_addr_plus_regaddr (uint8_t i2cm_id, uint8_t i2cm_addr, uint8_t reg_addr) {
+	UdmaI2cm_t*					pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
+	uint8_t*					pcmd = auccmd_tx;
+	uint8_t lStatus = pdFALSE;
+
+	SemaphoreHandle_t shSemaphoreHandle = i2cm_semaphores_tx[i2cm_id];
+	if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
+	{
+		pi2cm_regs->tx_cfg_b.en = 0;
+		*pcmd++ = kI2cmCmdCfg;
+		*pcmd++ = aucclkdiv[1];
+		*pcmd++ = aucclkdiv[0];
+		*pcmd++ = kI2cmCmdStart;		// Put Start transaction on I2C bus
+		*pcmd++ = kI2cmCmdWr;		// Write device's address (next byte)
+		*pcmd++ = i2cm_addr & 0xfe; 	// Clear R/WRbar bit from i2c device's address to indicate write
+		*pcmd++ = kI2cmCmdWr; 		// I2C CMD_WR
+		pi2cm_regs->tx_saddr = auccmd_tx;
+		pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_tx);
+		pi2cm_regs->tx_cfg_b.en = 1;
+
+		// Block until UDMA operation is completed
+		if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
+		{
+			//pi2cm_regs->tx_cfg_b.en = 0;
+			pcmd = auccmd_tx;
+			*pcmd++ = reg_addr;
+			pi2cm_regs->tx_saddr = auccmd_tx;
+			pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_tx);
+			pi2cm_regs->tx_cfg_b.en = 1;
+
+			// Block until UDMA operation is completed
+			xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS );
+			xSemaphoreGive( shSemaphoreHandle );
+			lStatus = pdTRUE;
+		}
+		else
+		{
+			xSemaphoreGive( shSemaphoreHandle );
+		}
+	}
+	else
+	{
+		xSemaphoreGive( shSemaphoreHandle );
+	}
+	return lStatus;
+}
+uint8_t _udma_i2cm_write_addr_plus_reg16addr (uint8_t i2cm_id, uint8_t i2cm_addr, uint16_t reg_addr) {
+	UdmaI2cm_t*					pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
+	uint8_t*					pcmd = auccmd_tx;
+	uint8_t lStatus = pdFALSE;
+
+	SemaphoreHandle_t shSemaphoreHandle = i2cm_semaphores_tx[i2cm_id];
+	if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
+	{
+		pi2cm_regs->tx_cfg_b.en = 0;
+		*pcmd++ = kI2cmCmdCfg;
+		*pcmd++ = aucclkdiv[1];
+		*pcmd++ = aucclkdiv[0];
+		*pcmd++ = kI2cmCmdStart;		// Put Start transaction on I2C bus
+		*pcmd++ = kI2cmCmdWr;		// Write device's address (next byte)
+		*pcmd++ = i2cm_addr & 0xfe; 	// Clear R/WRbar bit from i2c device's address to indicate write
+		*pcmd++ = kI2cmCmdRpt;  // 2 byte register address
+		*pcmd++ = 2;
+		*pcmd++ = kI2cmCmdWr; 		// I2C CMD_WR
+		pi2cm_regs->tx_saddr = auccmd_tx;
+		pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_tx);
+		pi2cm_regs->tx_cfg_b.en = 1;
+
+		// Block until UDMA operation is completed
+		if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
+		{
+			//pi2cm_regs->tx_cfg_b.en = 0;
+			pcmd = auccmd_tx;
+			*pcmd++ = reg_addr & 0xff;
+			*pcmd++ = (reg_addr >> 8) & 0xff;
+			pi2cm_regs->tx_saddr = auccmd_tx;
+			pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_tx);
+			pi2cm_regs->tx_cfg_b.en = 1;
+
+			// Block until UDMA operation is completed
+			xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS );
+			xSemaphoreGive( shSemaphoreHandle );
+
+			lStatus = pdTRUE;
+		}
+		else
+		{
+			xSemaphoreGive( shSemaphoreHandle );
+		}
+	}
+	else
+	{
+		xSemaphoreGive( shSemaphoreHandle );
+	}
+	return lStatus;
+}
+
+
+uint8_t _udma_i2cm_read(uint8_t i2cm_id, uint8_t i2cm_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows) {
+	UdmaI2cm_t*					pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
+	uint8_t*					pcmd = auccmd_rx;
+	uint8_t lStatus = pdFALSE;
+
+	configASSERT(read_len < 256);
+
+	SemaphoreHandle_t shSemaphoreHandle = i2cm_semaphores_rx[i2cm_id];
+	if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
+	{
+		shSemaphoreHandle = i2cm_semaphores_tx[i2cm_id];
+		if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
+		{
+			pi2cm_regs->tx_cfg_b.en = 0;
+			*pcmd++ = kI2cmCmdCfg;
+			*pcmd++ = aucclkdiv[1];
+			*pcmd++ = aucclkdiv[0];
+			*pcmd++ = kI2cmCmdStart;		// Put Start transaction on I2C bus
+			*pcmd++ = kI2cmCmdWr;		// Write device's address (next byte)
+			*pcmd++ = i2cm_addr | 0x01;	// Device's address with read bit set
+			if (read_len > 1) {				// Do len-1 reads with ACK, and follow by 1 read with NACK
+				*pcmd++ = kI2cmCmdRpt;		// Tell controller to repeat the following command
+				*pcmd++ = (uint8_t)(read_len - 1);		// len-1 times
+				*pcmd++ = kI2cmCmdRdAck;		// command to repeat is read with ack
+			}
+			*pcmd++ = kI2cmCmdRdNack;	// Read last byte with NACK to indicate the end of the read
+
+			//
+			pi2cm_regs->rx_saddr = read_buffer;
+			pi2cm_regs->rx_size = read_len;
+			pi2cm_regs->rx_cfg_b.en = 1;
+
+			pi2cm_regs->tx_saddr = auccmd_rx;
+			pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_rx);
+			pi2cm_regs->tx_cfg_b.en = 1;
+
+			// Block until UDMA operation is complete
+			shSemaphoreHandle = i2cm_semaphores_rx[i2cm_id];
+			xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS );
+			xSemaphoreGive( shSemaphoreHandle );
+
+			shSemaphoreHandle = i2cm_semaphores_tx[i2cm_id];
+
+			xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS );
+			xSemaphoreGive( shSemaphoreHandle );
+
+			if (!more_follows) {
+				_udma_i2cm_send_stop(i2cm_id);
+			}
+			lStatus = pdTRUE;
+		}
+		else
+		{
+			xSemaphoreGive( shSemaphoreHandle );
+			lStatus = pdFALSE;
+		}
+	}
+	else
+	{
+		xSemaphoreGive( shSemaphoreHandle );
+		lStatus = pdFALSE;
+	}
+	return lStatus;
+}
+
+static uint8_t auci2cm_stop_seq[] = {
+		kI2cmCmdStop,	kI2cmCmdWait, 0x0
+};
+
+uint8_t _udma_i2cm_send_stop(uint8_t i2cm_id) {
+	UdmaI2cm_t*			pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
+	SemaphoreHandle_t 	shSemaphoreHandle = i2cm_semaphores_tx[i2cm_id];
+	uint8_t lStatus = pdFALSE;
+
+	if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
+	{
+		pi2cm_regs->tx_saddr = auci2cm_stop_seq;
+		pi2cm_regs->tx_size = sizeof(auci2cm_stop_seq);
+		pi2cm_regs->tx_cfg_b.en = 1;
+
+		// Block until UDMA transaction is completed
+		xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS );
+		xSemaphoreGive( shSemaphoreHandle );
+		lStatus = pdTRUE;
+	}
+	else
+	{
+		xSemaphoreGive( shSemaphoreHandle );
+	}
+	return lStatus;
+}

bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_sdio_driver.c

+/*
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include <stdint.h>
+#include <stdbool.h>
+//#include "FreeRTOS.h"
+#include "semphr.h"
+
+#include "target/core-v-mcu/include/core-v-mcu-config.h"
+#include "hal/include/hal_fc_event.h"
+#include "hal/include/hal_udma_ctrl_reg_defs.h"
+#include "hal/include/hal_udma_sdio_reg_defs.h"
+#include <drivers/include/udma_sdio_driver.h>
+
+#define BLOCK_SIZE 512
+
+uint16_t udma_sdio_open (uint8_t sdio_id)
+{
+	int i = 0;
+	volatile UdmaCtrl_t*		pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
+	UdmaSdio_t*					psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
+
+	/* Enable reset and enable uart clock */
+	pudma_ctrl->reg_rst |= (UDMA_CTRL_SDIO0_CLKEN << sdio_id);
+	pudma_ctrl->reg_rst &= ~(UDMA_CTRL_SDIO0_CLKEN << sdio_id);
+	pudma_ctrl->reg_cg |= (UDMA_CTRL_SDIO0_CLKEN << sdio_id);
+
+	psdio_regs->clk_div_b.clk_div = 7;//5;
+	psdio_regs->clk_div_b.valid = 1;
+	//Restore pin muxes
+	for(i=0; i<6; i++ )
+	{
+		//set pin muxes to sdio functionality
+		 hal_setpinmux(37+i, 0);
+	}
+	return 0;
+}
+
+uint16_t udma_sdio_control(uint8_t sdio_id, udma_sdio_control_type_t control_type, void* pparam) {
+	volatile UdmaCtrl_t*		pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
+	UdmaSdio_t*					psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
+
+	switch(control_type) {
+	case kSDIOmReset:
+		pudma_ctrl->reg_rst |= (UDMA_CTRL_SDIO0_CLKEN << sdio_id);
+		pudma_ctrl->reg_rst &= ~(UDMA_CTRL_SDIO0_CLKEN << sdio_id);
+		break;
+	default:
+		configASSERT(0);
+	}
+	return 0;
+}
+
+void udma_sdio_clearDataSetup(uint8_t sdio_id)
+{
+	UdmaSdio_t *psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
+	psdio_regs->data_setup = 0x00000000;
+}
+uint8_t udma_sdio_writeBlockData(uint8_t sdio_id, uint32_t aNumOfBlocks, uint32_t *aBuf, uint32_t aBufLen)
+{
+	uint8_t lSts = 0;
+	uint32_t lData = 0;
+	UdmaSdio_t *psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
+
+	psdio_regs->tx_cfg_b.clr = 1;
+	psdio_regs->tx_cfg_b.en = 0;
+	psdio_regs->tx_cfg_b.datasize = 2;
+
+	psdio_regs->tx_saddr = aBuf;
+	psdio_regs->tx_size = aBufLen;
+
+	lData = 0;
+	psdio_regs->data_setup = 0x00000000;
+	lData |= 1 << 0;	//Data Enable - Enable data transfer for current command
+	lData |= 0 << 1;	//RWN: Set transfer direction 1 read; 0 write
+	lData |= 1 << 2;	//QUAD mode: Use quad mode.
+	lData |= ( aNumOfBlocks - 1 ) << 8; //Number of blocks
+	lData |= ( BLOCK_SIZE - 1 ) << 16; //Block size
+
+	psdio_regs->data_setup = lData;
+
+	psdio_regs->tx_cfg_b.en = 1;
+}
+
+uint8_t udma_sdio_readBlockData(uint8_t sdio_id, uint32_t aNumOfBlocks, uint32_t *aBuf, uint32_t aBufLen)
+{
+	uint8_t lSts = 0;
+	uint32_t lData = 0;
+	UdmaSdio_t *psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
+
+	psdio_regs->rx_cfg_b.clr = 1;
+	psdio_regs->rx_cfg_b.en = 0;
+	psdio_regs->rx_cfg_b.datasize = 2;
+
+	psdio_regs->rx_saddr = aBuf;
+	psdio_regs->rx_size = aBufLen;
+
+	lData = 0;
+	psdio_regs->data_setup = 0x00000000;
+	lData |= 1 << 0;	//Data Enable - Enable data transfer for current command
+	lData |= 1 << 1;	//RWN: Set transfer direction 1 read; 0 write
+	lData |= 1 << 2;	//QUAD mode: Use quad mode.
+	lData |= ( aNumOfBlocks - 1 ) << 8; //Number of blocks
+	lData |= ( BLOCK_SIZE - 1 ) << 16; //Block size
+
+	psdio_regs->data_setup = lData;
+
+	psdio_regs->rx_cfg_b.en = 1;
+
+}
+
+uint8_t udma_sdio_sendCmd(uint8_t sdio_id, uint8_t aCmdOpCode, uint8_t aRspType, uint32_t aCmdArgument, uint32_t *aResponseBuf)
+{
+	uint8_t lSts = 0;
+	uint32_t lData = 0;
+	uint32_t lLoopCounter = 0;
+	UdmaSdio_t *psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
+
+	lData |= (aRspType & REG_CMD_OP_CMD_RSP_TYPE_MASK ) << REG_CMD_OP_CMD_RSP_TYPE_LSB;
+	lData |= ( aCmdOpCode & REG_CMD_OP_CMD_OP_MASK ) << REG_CMD_OP_CMD_OP_LSB;
+	psdio_regs->cmd_op = lData;
+
+	//psdio_regs->cmd_op_b.cmd_op = ( aCmdOpCode & 0x3F );
+	//psdio_regs->cmd_op_b.cmd_rsp_type = ( aRspType & 0x07 );
+	psdio_regs->cmd_arg = aCmdArgument;
+
+	psdio_regs->start = 1;
+
+	while( ( ( psdio_regs->status & ( REG_STATUS_EOT_MASK << REG_STATUS_EOT_LSB ) ) >> REG_STATUS_EOT_LSB ) == 0 )
+	{
+		if( ( ( psdio_regs->status & ( REG_STATUS_ERROR_MASK << REG_STATUS_ERROR_LSB ) ) >> REG_STATUS_ERROR_LSB ) == 1 )
+		{
+			lSts = (psdio_regs->status & ( REG_STATUS_CMD_ERR_STATUS_MASK << REG_STATUS_CMD_ERR_STATUS_LSB ) ) >> REG_STATUS_CMD_ERR_STATUS_LSB;
+			break;
+		}
+		else
+		{
+			if(++lLoopCounter >= 0x00010000 )
+			{
+				lSts = 5;
+				break;
+			}
+		}
+	}
+
+	psdio_regs->status_b.eot = 1;	//Write 1 to EOT bit to clear it.
+
+
+	if( aResponseBuf )
+	{
+		aResponseBuf[0] = psdio_regs->rsp0;
+		aResponseBuf[1] = psdio_regs->rsp1;
+		aResponseBuf[2] = psdio_regs->rsp2;
+		aResponseBuf[3] = psdio_regs->rsp3;
+
+	}
+	return lSts;
+}
+#if 0
+static uint32_t auccmd[16];
+
+void udma_qspim_read(uint8_t qspim_id, uint8_t cs, uint16_t read_len, uint8_t* read_buffer) {
+	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
+	uint32_t*	pcmd = auccmd;
+
+		configASSERT(read_len < 256);
+
+		SemaphoreHandle_t shSemaphoreHandle = qspim_semaphores_rx[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+
+		pqspim_regs->rx_cfg_b.en = 0;
+		pqspim_regs->tx_cfg_b.en = 0;
+		pqspim_regs->cmd_cfg_b.en = 0;
+
+		*pcmd++ = kSPIm_Cfg | aucclkdiv;
+		*pcmd++ = kSPIm_SOT | cs;  //cs 1
+		*pcmd++ = kSPIm_RxData | (0x00470000 | (read_len-1)) ; // 4 words recieved
+		*pcmd++ = kSPIm_EOT  | 1; // generate event
+
+		pqspim_regs->rx_saddr = read_buffer;
+		pqspim_regs->rx_size = read_len;
+		pqspim_regs->rx_cfg_b.en = 1;
+
+		pqspim_regs->cmd_saddr = auccmd;
+		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+		pqspim_regs->cmd_cfg_b.en = 1;
+
+		// Block until UDMA operation is complete
+		shSemaphoreHandle = qspim_semaphores_rx[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
+}
+
+
+void udma_qspim_write (uint8_t qspim_id, uint8_t cs, uint16_t write_len, uint8_t *write_data) {
+	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
+	uint32_t*	pcmd = auccmd;
+	uint32_t tmp_size;
+		configASSERT(write_len < 256);
+
+		SemaphoreHandle_t shSemaphoreHandle = qspim_semaphores_tx[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+
+		pqspim_regs->rx_cfg_b.clr = 1;
+		pqspim_regs->tx_cfg_b.clr = 1;
+		pqspim_regs->cmd_cfg_b.clr = 1;
+
+		*pcmd++ = kSPIm_Cfg | aucclkdiv;
+		*pcmd++ = kSPIm_SOT | cs;
+		*pcmd++ = kSPIm_TxData | 0x0470000 | write_len -1;
+		*pcmd++ = kSPIm_EOT | 1; // generate event
+
+
+		pqspim_regs->tx_saddr = write_data;
+		pqspim_regs->tx_size = write_len-1;
+		pqspim_regs->tx_cfg_b.datasize = 2;
+		pqspim_regs->tx_cfg_b.en = 1;
+
+		pqspim_regs->cmd_saddr = auccmd;
+		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+		pqspim_regs->cmd_cfg_b.en = 1;
+
+
+
+
+
+		// Block until UDMA operation is complete
+		shSemaphoreHandle = qspim_semaphores_tx[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
+}
+
+#endif

bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_uart_driver.c

+/*
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "core-v-mcu-config.h"
+#include <string.h>
+#include "hal_fc_event.h"
+#include "hal_udma_ctrl_reg_defs.h"
+#include "hal_udma_uart_reg_defs.h"
+#include <drv_usart.h>
+#include <stdint.h>
+//#include "FreeRTOS.h"
+//#include "semphr.h"
+#include "core-v-mcu-config.h"
+#include "udma_uart_driver.h"
+#include "rtthread.h"
+//#include <ringbuffer.h>
+//#include "ipc/ringbuffer.h" 
+#include "rtdevice.h" 
+#define  unuse_freertos_in_uart
+
+
+//SemaphoreHandle_t  uart_semaphores_rx[N_UART];
+//SemaphoreHandle_t  uart_semaphores_tx[N_UART];
+char u1buffer[128], u0buffer[128];
+int u1rdptr, u1wrptr, u0rdptr,u0wrptr;
+UdmaUart_t *puart0 = (UdmaUart_t*)(UDMA_CH_ADDR_UART);
+UdmaUart_t *puart1 = (UdmaUart_t*)(UDMA_CH_ADDR_UART + UDMA_CH_SIZE);
+
+uint16_t outdata(uint8_t uart_id, uint16_t write_len, uint8_t* write_buffer) {
+	UdmaUart_t*				puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
+
+	while (puart->status_b.tx_busy) {  // ToDo: Why is this necessary?  Thought the semaphore should have protected
+	}
+
+	puart->tx_saddr = (uint32_t)write_buffer;
+	puart->tx_size = write_len;
+	puart->tx_cfg_b.en = 1; //enable the transfer
+
+	return 0;
+}
+
+// ringbuffer  
+#define UART_RX_BUFFER_LEN 16
+rt_uint8_t uart_rxbuffer[UART_RX_BUFFER_LEN]={0};
+struct rt_ringbuffer uart_rxTCB;
+struct rt_semaphore  shell_rx_semaphore;
+
+// extern struct ch32_uart_config uart_config[];
+// extern void uart_isr(struct rt_serial_device *serial);
+// extern struct ch32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] ;
+// extern UART1_INDEX;
+char n_data[]="\r\n";
+// void uart_rx_isr (void *id){
+// 	rt_interrupt_enter();
+// 	if (id == 6) {
+// 		while (*(int*)0x1a102130) {
+// 			u1buffer[u1wrptr++] = puart1->data_b.rx_data & 0xff;
+// 			u1wrptr &= 0x7f;
+// 		}
+// 	}
+// 	if (id == 2) {
+// 		while (puart0->valid) {
+// 			//u0buffer[u0wrptr++] = puart0->data_b.rx_data & 0xff;
+// 			//u0wrptr &= 0x7f;
+// 			//outdata(0,sizeof(u0buffer),u0buffer);
+// 			//outdata(0,sizeof(n_data),n_data);
+// 			//rt_ringbuffer_putchar(&uart_rxTCB,puart0->data_b.rx_data & 0xff);
+// 			//u0wrptr=0;
+// 			uart_isr(&(uart_obj[UART1_INDEX].serial));
+// 		}
+// 		//rt_sem_release(&shell_rx_semaphore);
+// 	}
+// 	rt_interrupt_leave();
+// }
+uint8_t uart_getchar (uint8_t id) {
+	uint8_t retval;
+	if (id == 1) {
+		while (u1rdptr == u1wrptr) ;
+		retval = u1buffer[u1rdptr++];
+		u1rdptr &= 0x7f;
+	}
+	if (id == 0) {
+		while (u0rdptr == u0wrptr) ;
+		retval = u0buffer[u0rdptr++];
+		u0rdptr &= 0x7f;
+	}
+	return retval;
+}
+
+void uart_rx_isr (void *id);
+uint16_t udma_uart_open (uint8_t uart_id, uint32_t xbaudrate) {
+	UdmaUart_t*				puart;
+	volatile UdmaCtrl_t*		pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
+
+	/* See if already initialized */
+	pudma_ctrl->reg_rst |= (UDMA_CTRL_UART0_CLKEN << uart_id);
+	pudma_ctrl->reg_rst &= ~(UDMA_CTRL_UART0_CLKEN << uart_id);
+	pudma_ctrl->reg_cg |= (UDMA_CTRL_UART0_CLKEN << uart_id);
+
+
+	user_pi_fc_event_handler_set(SOC_EVENT_UART_RX(uart_id), uart_rx_isr);
+
+
+	/* Enable SOC events propagation to FC. */
+	hal_soc_eu_set_fc_mask(SOC_EVENT_UART_RX(uart_id));
+	hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_UART_TX(uart_id));
+
+	/* configure */
+	puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
+	puart->uart_setup_b.div = (uint16_t)(5000000/xbaudrate);
+	puart->uart_setup_b.bits = 3; // 8-bits
+
+	puart->irq_en_b.rx_irq_en = 1;
+	puart->uart_setup_b.en_tx = 1;
+	puart->uart_setup_b.en_rx = 1;
+	puart->uart_setup_b.rx_clean_fifo = 1;
+	
+	if (uart_id == 1) {
+		 u1rdptr = 0;
+	 	 u1wrptr = 0;
+	}
+	if (uart_id == 0) {
+		 u0rdptr = 0;
+	 	 u0wrptr = 0;
+	}
+
+	return 0;
+}
+
+uint16_t udma_uart_writeraw(uint8_t uart_id, uint16_t write_len, uint8_t* write_buffer) {
+	UdmaUart_t*				puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
+
+	// SemaphoreHandle_t shSemaphoreHandle = uart_semaphores_tx[uart_id];
+	// if( xSemaphoreTake( shSemaphoreHandle, 1000000 ) != pdTRUE ) {
+	// 	return 1;
+	// }
+
+	while (puart->status_b.tx_busy) {  // ToDo: Why is this necessary?  Thought the semaphore should have protected
+	}
+
+	puart->tx_saddr = (uint32_t)write_buffer;
+	puart->tx_size = write_len;
+	puart->tx_cfg_b.en = 1; //enable the transfer
+
+	return 0;
+}
+
+uint16_t udma_uart_read(uint8_t uart_id, uint16_t read_len, uint8_t* read_buffer) {
+	uint16_t ret = 0;
+	uint8_t last_char = 0;
+	UdmaUart_t*				puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
+
+
+	while ( (ret < (read_len - 2)) && (last_char != 0xd)) {
+		if (puart->valid_b.rx_data_valid == 1) {
+			last_char = (uint8_t)(puart->data_b.rx_data & 0xff);
+			if (last_char == 0xd)  // if cr add
+				read_buffer[ret++] = 0xa;  // linefeed
+			read_buffer[ret++] = last_char;
+		}
+	}
+	read_buffer[ret] = '\0';
+	return ret--;
+}
+
+uint16_t udma_uart_readraw(uint8_t uart_id, uint16_t read_len, uint8_t* read_buffer) {
+	uint16_t ret = 0;
+	uint8_t last_char = 0;
+	UdmaUart_t*				puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
+
+	while ( ret < read_len ) {
+		if (puart->valid_b.rx_data_valid == 1) {
+			last_char = (uint8_t)(puart->data_b.rx_data & 0xff);
+			read_buffer[ret++] = last_char;
+		}
+	}
+	return ret--;
+}
+
+uint8_t udma_uart_getchar(uint8_t uart_id) {
+	UdmaUart_t*				puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
+
+	while (puart->valid_b.rx_data_valid == 0) {
+	}
+	return (puart->data_b.rx_data & 0xff);
+}
+
+uint16_t udma_uart_control(uint8_t uart_id, udma_uart_control_type_t control_type, void* pparam) {
+	UdmaUart_t*				puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
+
+	switch(control_type) {
+	case kUartDataValid:
+		if (uart_id == 0)
+			return !(u0rdptr == u0wrptr);
+		if (uart_id == 1)
+			return !(u1rdptr == u1wrptr);
+		return puart->valid_b.rx_data_valid;
+	default:
+		return 0xFFFF;
+	}
+	return 0;
+}

bsp/core-v-mcu/Libraries/core_v_hal_libraries/SConscript

+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+src = Split("""
+core_v_hal/source/hal_apb_i2cs.c
+core_v_hal/source/hal_fc_event.c
+core_v_hal/source/hal_fll.c
+core_v_hal/source/hal_fll_pi.c
+core_v_hal/source/hal_gpio.c
+core_v_hal/source/hal_gpio_pulp.c
+core_v_hal/source/hal_irq.c
+core_v_hal/source/hal_pinmux.c
+core_v_hal/source/hal_pinmux1.c
+core_v_hal/source/hal_soc_eu.c
+core_v_hal/source/hal_timer_irq.c
+bmsis/core-v-mcu/source/core-v-mcu.c
+bmsis/core-v-mcu/source/crt0.S
+bmsis/core-v-mcu/source/vectors.S
+""")
+
+path = [
+	cwd + '/bmsis/core-v-mcu/include',
+    cwd + '/core_v_hal/include']
+
+group = DefineGroup('core_v_hal_lib', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/bits.h

+/*
+ * Copyright (c) 2011-2014, Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __BITS_H
+#define __BITS_H
+
+#include <stdbool.h>
+
+/* Helper to pass a int as a pointer or vice-versa. */
+#define POINTER_TO_UINT(x) ((uintptr_t) (x))
+#define UINT_TO_POINTER(x) ((void *) (uintptr_t) (x))
+#define POINTER_TO_INT(x)  ((intptr_t) (x))
+#define INT_TO_POINTER(x)  ((void *) (intptr_t) (x))
+
+#if !(defined (__CHAR_BIT__) && defined (__SIZEOF_LONG__))
+#	error Missing required predefined macros for BITS_PER_LONG calculation
+#endif
+
+#define BITS_PER_LONG	(__CHAR_BIT__ * __SIZEOF_LONG__)
+/* Create a contiguous bitmask starting at bit position @l and ending at
+ * position @h.
+ */
+#define GENMASK(h, l) \
+	(((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
+
+/* KB, MB, GB */
+#define KB(x) ((x) << 10)
+#define MB(x) (KB(x) << 10)
+#define GB(x) (MB(x) << 10)
+
+/* KHZ, MHZ */
+#define KHZ(x) ((x) * 1000)
+#define MHZ(x) (KHZ(x) * 1000)
+
+#ifndef BIT
+#if defined(_ASMLANGUAGE)
+#define BIT(n)  (1 << (n))
+#else
+#define BIT(n)  (1UL << (n))
+#endif
+#endif
+
+/**
+ * @brief Macro sets or clears bit depending on boolean value
+ *
+ * @param var Variable to be altered
+ * @param bit Bit number
+ * @param set Value 0 clears bit, any other value sets bit
+ */
+#define WRITE_BIT(var, bit, set) \
+	((var) = (set) ? ((var) | BIT(bit)) : ((var) & ~BIT(bit)))
+
+#define BIT_MASK(n) (BIT(n) - 1)
+
+#endif

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-config.h

+/*
+ * This is a generated file
+ * 
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __CORE_V_MCU_CONFIG_H_
+#define __CORE_V_MCU_CONFIG_H_
+#define NEW_BIT_FILE	1
+#define OLD_BIT_FILE	0
+
+#if (NEW_BIT_FILE == 1 )
+#define BUILD_DATE 0x20220127
+#define BUILD_TIME 0x00215431
+
+#define FAKE_PLL		0
+#define PERCEPTIA_PLL	1
+//  SOC options
+#define N_IO                 48
+#define N_SYSIO              3
+#define N_GPIO               32  
+#define N_APBIO              51
+#define NBIT_PADCFG          6
+#define NBIT_PADMUX          2
+#define N_UART               2
+#define N_QSPIM              2      // two QSPI  master 
+#define N_I2CM               2          // two I2C master  
+#define N_I2SC               0
+#define N_CSI2               0
+#define N_HYPER              0
+#define N_SDIO               1
+#define N_CAM                1
+#define N_JTAG               0
+#define N_MRAM               0
+#define N_FILTER             1
+#define N_FPGA               0
+#define N_EXT_PER            0
+#define N_EFPGA_TCDM_PORTS   4
+#define N_FPGAIO             43
+#define N_EFPGA_EVENTS       16
+
+//  UDMA configuration information
+#define UDMA_START_ADDR         0x1A102000
+#define UDMA_CH_SIZE            (0x80)
+//  peripheral channel definitions
+#define UDMA_CH_ADDR_CTRL       (0x1A102000)
+#define UDMA_CH_ADDR_UART       (0x1A102000 + 1 * 0x80)
+#define UDMA_UART_ID(id)        (0 + id)
+#define UDMA_CH_ADDR_UART0      (0x1A102000 + 1 * 0x80)
+#define UDMA_CH_ADDR_UART1      (0x1A102000 + 2 * 0x80)
+#define UDMA_CH_ADDR_QSPIM      (0x1A102000 + 3 * 0x80)
+#define UDMA_QSPIM_ID(id)       (2 + id)
+#define UDMA_CH_ADDR_QSPIM0     (0x1A102000 + 3 * 0x80)
+#define UDMA_CH_ADDR_QSPIM1     (0x1A102000 + 4 * 0x80)
+#define UDMA_CH_ADDR_I2CM       (0x1A102000 + 5 * 0x80)
+#define UDMA_I2CM_ID(id)        (4 + id)
+#define UDMA_CH_ADDR_I2CM0      (0x1A102000 + 5 * 0x80)
+#define UDMA_CH_ADDR_I2CM1      (0x1A102000 + 6 * 0x80)
+#define UDMA_CH_ADDR_I2SC       (0x1A102000 + 7 * 0x80)
+#define UDMA_I2SC_ID(id)        (6 + id)
+#define UDMA_CH_ADDR_I2SC0      (0x1A102000 + 7 * 0x80)
+#define UDMA_CH_ADDR_CSI2       (0x1A102000 + 7 * 0x80)
+#define UDMA_CSI2_ID(id)        (6 + id)
+#define UDMA_CH_ADDR_CSI20      (0x1A102000 + 7 * 0x80)
+#define UDMA_CH_ADDR_HYPER      (0x1A102000 + 7 * 0x80)
+#define UDMA_HYPER_ID(id)       (6 + id)
+#define UDMA_CH_ADDR_HYPER0     (0x1A102000 + 7 * 0x80)
+#define UDMA_CH_ADDR_SDIO       (0x1A102000 + 7 * 0x80)
+#define UDMA_SDIO_ID(id)        (6 + id)
+#define UDMA_CH_ADDR_SDIO0      (0x1A102000 + 7 * 0x80)
+#define UDMA_CH_ADDR_CAM        (0x1A102000 + 8 * 0x80)
+#define UDMA_CAM_ID(id)         (7 + id)
+#define UDMA_CH_ADDR_CAM0       (0x1A102000 + 8 * 0x80)
+#define UDMA_CH_ADDR_JTAG       (0x1A102000 + 9 * 0x80)
+#define UDMA_JTAG_ID(id)        (8 + id)
+#define UDMA_CH_ADDR_JTAG0      (0x1A102000 + 9 * 0x80)
+#define UDMA_CH_ADDR_MRAM       (0x1A102000 + 9 * 0x80)
+#define UDMA_MRAM_ID(id)        (8 + id)
+#define UDMA_CH_ADDR_MRAM0      (0x1A102000 + 9 * 0x80)
+#define UDMA_CH_ADDR_FILTER     (0x1A102000 + 9 * 0x80)
+#define UDMA_FILTER_ID(id)      (8 + id)
+#define UDMA_CH_ADDR_FILTER0    (0x1A102000 + 9 * 0x80)
+#define UDMA_CH_ADDR_FPGA       (0x1A102000 + 10 * 0x80)
+#define UDMA_FPGA_ID(id)        (9 + id)
+#define UDMA_CH_ADDR_FPGA0      (0x1A102000 + 10 * 0x80)
+#define UDMA_CH_ADDR_EXT_PER    (0x1A102000 + 10 * 0x80)
+#define UDMA_EXT_PER_ID(id)     (9 + id)
+#define UDMA_CH_ADDR_EXT_PER0   (0x1A102000 + 10 * 0x80)
+
+//  Peripheral clock enable masks
+#define UDMA_CTRL_UART0_CLKEN      (1 << 0)
+#define UDMA_CTRL_UART1_CLKEN      (1 << 1)
+#define UDMA_CTRL_QSPIM0_CLKEN     (1 << 2)
+#define UDMA_CTRL_QSPIM1_CLKEN     (1 << 3)
+#define UDMA_CTRL_I2CM0_CLKEN      (1 << 4)
+#define UDMA_CTRL_I2CM1_CLKEN      (1 << 5)
+#define UDMA_CTRL_I2SC0_CLKEN      (1 << 6)
+#define UDMA_CTRL_CSI20_CLKEN      (1 << 6)
+#define UDMA_CTRL_HYPER0_CLKEN     (1 << 6)
+#define UDMA_CTRL_SDIO0_CLKEN      (1 << 6)
+#define UDMA_CTRL_CAM0_CLKEN       (1 << 7)
+#define UDMA_CTRL_JTAG0_CLKEN      (1 << 8)
+#define UDMA_CTRL_MRAM0_CLKEN      (1 << 8)
+#define UDMA_CTRL_FILTER0_CLKEN    (1 << 8)
+#define UDMA_CTRL_FPGA0_CLKEN      (1 << 9)
+#define UDMA_CTRL_EXT_PER0_CLKEN   (1 << 9)
+
+//  FLL configuration information
+#define FLL1_START_ADDR 0x1A100000
+
+#define FLL2_START_ADDR 0x1A100020
+
+#define FLL3_START_ADDR 0x1A100040
+
+
+//  GPIO configuration information
+#define GPIO_START_ADDR 0x1A101000
+
+#define SOC_EVENT_GEN_START_ADDR 0x1A106000
+//  I2C Slave configuration information
+#define I2CS_START_ADDR 0x1A107000
+
+//  EFPGAIO configuration information
+#define EFPGAIO_START_ADDR 0x1A300000
+
+//  SOC controller configuration information
+#define SOC_CTRL_START_ADDR 0x1A104000
+
+//  Event Unit (Interrupts) configuration information
+#define EU_START_ADDR 0x1A109000
+
+//  Timer configuration information
+#define TIMER_START_ADDR 0x1A10B000
+
+//  AdvTimer configuration information
+#define ADV_TIMER_START_ADDR 0x1A105000
+
+//  EFPGA configuration information (FCB)
+#define EFPGA_CONFIG_START_ADDR 0x1A200000
+
+#elif (OLD_BIT_FILE == 1)
+
+#define BUILD_DATE 0x20210623
+#define BUILD_TIME 0x00111431
+
+#define FAKE_PLL		0
+#define PERCEPTIA_PLL	1
+
+//  SOC options
+#define N_IO                 48
+#define N_SYSIO              3
+#define N_GPIO               32
+#define N_APBIO              50
+#define NBIT_PADCFG          6
+#define NBIT_PADMUX          2
+#define N_UART               2
+#define N_QSPIM              1
+#define N_I2CM               2
+#define N_I2SC               0
+#define N_CSI2               0
+#define N_HYPER              0
+#define N_SDIO               1
+#define N_CAM                1
+#define N_JTAG               0
+#define N_MRAM               0
+#define N_FILTER             1
+#define N_FPGA               1
+#define N_EXT_PER            0
+#define N_EFPGA_TCDM_PORTS   4
+#define N_FPGAIO             43
+#define N_EFPGA_EVENTS       16
+
+//  UDMA configuration information
+#define UDMA_START_ADDR         0x1A102000
+#define UDMA_CH_SIZE            (0x80)
+//  peripheral channel definitions
+#define UDMA_CH_ADDR_CTRL       (0x1A102000)
+#define UDMA_CH_ADDR_UART       (0x1A102000 + 1 * 0x80)
+#define UDMA_UART_ID(id)        (0 + id)
+#define UDMA_CH_ADDR_UART0      (0x1A102000 + 1 * 0x80)
+#define UDMA_CH_ADDR_UART1      (0x1A102000 + 2 * 0x80)
+#define UDMA_CH_ADDR_QSPIM      (0x1A102000 + 3 * 0x80)
+#define UDMA_QSPIM_ID(id)       (2 + id)
+#define UDMA_CH_ADDR_QSPIM0     (0x1A102000 + 3 * 0x80)
+#define UDMA_CH_ADDR_I2CM       (0x1A102000 + 4 * 0x80)
+#define UDMA_I2CM_ID(id)        (3 + id)
+#define UDMA_CH_ADDR_I2CM0      (0x1A102000 + 4 * 0x80)
+#define UDMA_CH_ADDR_I2CM1      (0x1A102000 + 5 * 0x80)
+#define UDMA_CH_ADDR_I2SC       (0x1A102000 + 6 * 0x80)
+#define UDMA_I2SC_ID(id)        (5 + id)
+#define UDMA_CH_ADDR_I2SC0      (0x1A102000 + 6 * 0x80)
+#define UDMA_CH_ADDR_CSI2       (0x1A102000 + 6 * 0x80)
+#define UDMA_CSI2_ID(id)        (5 + id)
+#define UDMA_CH_ADDR_CSI20      (0x1A102000 + 6 * 0x80)
+#define UDMA_CH_ADDR_HYPER      (0x1A102000 + 6 * 0x80)
+#define UDMA_HYPER_ID(id)       (5 + id)
+#define UDMA_CH_ADDR_HYPER0     (0x1A102000 + 6 * 0x80)
+#define UDMA_CH_ADDR_SDIO       (0x1A102000 + 6 * 0x80)
+#define UDMA_SDIO_ID(id)        (5 + id)
+#define UDMA_CH_ADDR_SDIO0      (0x1A102000 + 6 * 0x80)
+#define UDMA_CH_ADDR_CAM        (0x1A102000 + 7 * 0x80)
+#define UDMA_CAM_ID(id)         (6 + id)
+#define UDMA_CH_ADDR_CAM0       (0x1A102000 + 6 * 0x80)
+#define UDMA_CH_ADDR_JTAG       (0x1A102000 + 7 * 0x80)
+#define UDMA_JTAG_ID(id)        (6 + id)
+#define UDMA_CH_ADDR_JTAG0      (0x1A102000 + 7 * 0x80)
+#define UDMA_CH_ADDR_MRAM       (0x1A102000 + 7 * 0x80)
+#define UDMA_MRAM_ID(id)        (6 + id)
+#define UDMA_CH_ADDR_MRAM0      (0x1A102000 + 7 * 0x80)
+#define UDMA_CH_ADDR_FILTER     (0x1A102000 + 7 * 0x80)
+#define UDMA_FILTER_ID(id)      (6 + id)
+#define UDMA_CH_ADDR_FILTER0    (0x1A102000 + 7 * 0x80)
+#define UDMA_CH_ADDR_FPGA       (0x1A102000 + 8 * 0x80)
+#define UDMA_FPGA_ID(id)        (7 + id)
+#define UDMA_CH_ADDR_FPGA0      (0x1A102000 + 8 * 0x80)
+#define UDMA_CH_ADDR_EXT_PER    (0x1A102000 + 9 * 0x80)
+#define UDMA_EXT_PER_ID(id)     (8 + id)
+#define UDMA_CH_ADDR_EXT_PER0   (0x1A102000 + 9 * 0x80)
+
+//  Peripheral clock enable masks
+#define UDMA_CTRL_UART0_CLKEN      (1 << 0)
+#define UDMA_CTRL_UART1_CLKEN      (1 << 1)
+#define UDMA_CTRL_QSPIM0_CLKEN     (1 << 2)
+#define UDMA_CTRL_I2CM0_CLKEN      (1 << 3)
+#define UDMA_CTRL_I2CM1_CLKEN      (1 << 4)
+#define UDMA_CTRL_I2SC0_CLKEN      (1 << 5)
+#define UDMA_CTRL_CSI20_CLKEN      (1 << 5)
+#define UDMA_CTRL_HYPER0_CLKEN     (1 << 5)
+#define UDMA_CTRL_SDIO0_CLKEN      (1 << 5)
+#define UDMA_CTRL_CAM0_CLKEN       (1 << 6)
+#define UDMA_CTRL_JTAG0_CLKEN      (1 << 6)
+#define UDMA_CTRL_MRAM0_CLKEN      (1 << 6)
+#define UDMA_CTRL_FILTER0_CLKEN    (1 << 6)
+#define UDMA_CTRL_FPGA0_CLKEN      (1 << 7)
+#define UDMA_CTRL_EXT_PER0_CLKEN   (1 << 8)
+
+//  FLL configuration information
+#define FLL1_START_ADDR 0x1A100000
+
+#define FLL2_START_ADDR 0x1A100020
+
+#define FLL3_START_ADDR 0x1A100040
+
+//  GPIO configuration information
+#define GPIO_START_ADDR 0x1A101000
+
+#define SOC_EVENT_GEN_START_ADDR 0x1A106000
+//  I2C Slave configuration information
+#define I2CS_START_ADDR 0x1A107000
+
+//  EFPGAIO configuration information
+#define EFPGAIO_START_ADDR 0x1A300000
+
+//  SOC controller configuration information
+#define SOC_CTRL_START_ADDR 0x1A104000
+
+//  Event Unit (Interrupts) configuration information
+#define EU_START_ADDR 0x1A109000
+
+//  Timer configuration information
+#define TIMER_START_ADDR 0x1A10B000
+
+//  AdvTimer configuration information
+#define ADV_TIMER_START_ADDR 0x1A105000
+
+//  EFPGA configuration information (FCB)
+#define EFPGA_CONFIG_START_ADDR 0x1A200000
+#endif
+
+#endif //__CORE_V_MCU_CONFIG_H_

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-events.h

+/*
+ * Copyright (C) 2019 ETH Zurich, University of Bologna and GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_EVENTS_H_
+#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_EVENTS_H_
+
+
+
+#include "core-v-mcu-properties.h"
+
+/* Events offsets. */
+#define UDMA_EVENT_OFFSET_RX            (0U)
+#define UDMA_EVENT_OFFSET_TX            (1U)
+#define EVENT_UART_RX            (2U)
+#define EVENT_UART_ERR            (3U)
+
+#define UDMA_EVENT_OFFSET_SPI_CMD       (2)
+#define UDMA_EVENT_OFFSET_SPI_EOT       (3)
+
+/* Number of events per peripheral. */
+#define UDMA_CHANNEL_NB_EVENTS_LOG2     (2)
+#define UDMA_CHANNEL_NB_EVENTS          (1 << UDMA_CHANNEL_NB_EVENTS_LOG2)
+
+/* Number of SW events. */
+#define NB_SW_EVENTS                    (8)
+
+/*! @brief FC events (aka IRQ lines)*/
+#define FC_EVENT_SW(id)                 (id & (NB_SW_EVENTS - 1))
+#define FC_EVENT_DMA_EVT                (8)
+#define FC_EVENT_DMA                    (9)
+#define FC_EVENT_TIMER0                 (10) /* Timer low.  */
+#define SYSTICK_IRQN                    FC_EVENT_TIMER0
+#define FC_EVENT_TIMER1                 (11) /* Timer high. */
+/* #define FC_EVENT_EU_HWCE                (12) */
+
+/*
+ * SoC event unit events: Many events get implicitely muxed into this interrupt.
+ * A user that gets such an interrupt has to check the event unit's registers to
+ * see what happened
+ */
+#define FC_EVENT_SOC_EVENT              (27)
+/* #define FC_EVENT_MPU_ERROR              (28) */
+/*
+ * Event queue error: If we don't process event unit events quickly enough
+ * internal fifos can overflow and we get this error interrupt
+ */
+#define FC_EVENT_FC_QUEUE_ERROR         (29)
+#define FC_EVENT_HP0                runn     (30)
+#define FC_EVENT_HP1                    (31)
+
+/*! @name SoC events  */
+/*! @brief Number of FC_Events. */
+#define SOC_EU_NB_FC_EVENTS             (168)
+
+/*! @brief UDMA events */
+/* SPIM */
+#define SOC_EVENT_UDMA_SPIM_RX(id)      ((UDMA_QSPIM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX)
+#define SOC_EVENT_UDMA_SPIM_TX(id)      ((UDMA_QSPIM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX)
+#define SOC_EVENT_UDMA_SPIM_CMD(id)     ((UDMA_QSPIM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_SPI_CMD)
+#define SOC_EVENT_UDMA_SPIM_EOT(id)     ((UDMA_QSPIM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_SPI_EOT)
+/* HYPER */
+/* #define SOC_EVENT_UDMA_HYPER_RX(id)     ((UDMA_HYPER_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX) */
+/* #define SOC_EVENT_UDMA_HYPER_TX(id)     ((UDMA_HYPER_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX) */
+/* UART */
+#define SOC_EVENT_UDMA_UART_RX(id)      ((UDMA_UART_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX)
+#define SOC_EVENT_UDMA_UART_TX(id)      ((UDMA_UART_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX)
+#define SOC_EVENT_UART_RX(id)           ((UDMA_UART_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + EVENT_UART_RX)
+#define SOC_EVENT_UART_ERR(id)           ((UDMA_UART_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + EVENT_UART_ERR)
+/* I2C */
+#define SOC_EVENT_UDMA_I2C_RX(id)       ((UDMA_I2CM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX)
+#define SOC_EVENT_UDMA_I2C_TX(id)       ((UDMA_I2CM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX)
+/* DMACPY */
+/* #define SOC_EVENT_UDMA_DMACPY_RX(id)    ((UDMA_DMACPY_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX) */
+/* #define SOC_EVENT_UDMA_DMACPY_TX(id)    ((UDMA_DMACPY_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX) */
+/* I2S */
+#define SOC_EVENT_UDMA_I2S_RX(id)       ((UDMA_I2S_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX)
+#define SOC_EVENT_UDMA_I2S_TX(id)       ((UDMA_I2S_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX)
+/* CPI */
+#define SOC_EVENT_UDMA_CAM_RX(id)       ((UDMA_CAM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX)
+
+/* UDMA EOT & error events. */
+//#define SOC_EVENT_UDMA_I2C_ERROR(id)  (26 + id)
+
+/*! @brief PMU events, no pmu*/
+/* #define SOC_EVENT_PMU_CLUSTER_POWER     (31) */
+/* #define SOC_EVENT_PMU_CLUSTER_CG        (35) */
+/* #define SOC_EVENT_PMU_DLC_BRIDGE_PICL   (36) */
+/* #define SOC_EVENT_PMU_DLC_BRIDGE_SCU    (37) */
+/* #define SOC_EVENT_PWM(id)               (38 + id) */
+#define SOC_EVENT_GPIO                  (139)
+#define SOC_EVENT_HWPE0                 (140)
+#define SOC_EVENT_HWPE1                 (141)
+/* #define SOC_EVENT_RTC_APB               (43) */
+/* #define SOC_EVENT_RTC                   (44) */
+
+#define SOC_EVENT_SW(id)                (160 + (id & (NB_SW_EVENTS - 1)))
+#define SOC_EVENT_REF32K_CLK_RISE       (168)
+
+/* @brief Cluster events */
+#define CL_EVENT_SW(id)                 (id & (NB_SW_EVENTS - 1))
+#define CL_EVENT_DMA0                   (8)
+#define CL_EVENT_DMA1                   (9)
+#define CL_EVENT_TIMER0_LO              (10)
+#define CL_EVENT_TIMER0_HI              (11)
+#define CL_EVENT_ACC0                   (12)
+#define CL_EVENT_ACC1                   (13)
+#define CL_EVENT_ACC2                   (14)
+#define CL_EVENT_ACC3                   (15)
+#define CL_EVENT_BAR                    (16)
+#define CL_EVENT_MUTEX                  (17)
+#define CL_EVENT_DISPATCH               (18)
+/* #define CL_EVENT_CLUSTER0               (22) */
+/* #define CL_EVENT_CLUSTER1               (23) */
+#define CL_EVENT_SOC_EVT                (30) /* adapted */
+
+#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_EVENTS_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-memory-map.h

+/*
+ * Copyright (C) 2019 ETH Zurich, University of Bologna and GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_MEMORY_MAP_H_
+#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_MEMORY_MAP_H_
+
+#include "core-v-mcu-properties.h"
+/* Memories */
+/* FC memory. */
+#define FC_TCDM_ADDR                                (0x1B000000)
+#if (ARCHI_HAS_FC_ALIAS)
+#define FC_TCDM_ADDR_ALIAS                          (0x00000000)
+#endif  /* ARCHI_HAS_FC_ALIAS */
+
+/* L2 memory */
+#define L2_SHARED_ADDR                              (0x1C000000)
+#if (ARCHI_HAS_L2_ALIAS)
+#define L2_SHARED_ADDR_ALIAS                        (0x00000000)
+#endif  /* ARCHI_HAS_L2_ALIAS */
+
+/* L1 cluster memory */
+#define CL_L1_ADDR                                  (0x10000000)
+#if (ARCHI_HAS_CL_L1_ALIAS)
+#define CL_L1_ADDR_ALIAS                            (0x00000000)
+#endif  /* ARCHI_HAS_CL_L1_ALIAS */
+
+/* L1 cluster TS */
+#if (ARCHI_HAS_CL_L1_TS)
+#define L2_PRIV0_TS_ADDR                            (0x10100000)
+#endif  /* ARCHI_HAS_CL_L1_TS */
+
+/* ROM memory (8 KiB)*/
+#define ROM_ADDR                                    (0x1A000000)
+#define ROM_SIZE                                    (0x00002000)
+
+/* Cluster */
+#define ARCHI_CLUSTER_ADDR                          (0x00000000)
+#define ARCHI_CLUSTER_SIZE                          (0x00400000)
+#define ARCHI_CLUSTER_GLOBAL_ADDR(cid)              (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE)
+#define ARCHI_CLUSTER_PERIPHERALS_OFFSET            (0x00200000)
+
+/* Cluster peripherals */
+#define ARCHI_TIMER_SIZE                            (0x00000800)
+
+#define ARCHI_CLUSTER_CTRL_OFFSET                   (0x00000000)
+#define ARCHI_TIMER_OFFSET                          (0x00000400)
+#define ARCHI_EU_OFFSET                             (0x00000800)
+#define ARCHI_HWCE_OFFSET                           (0x00001000)
+#define ARCHI_ICACHE_CTRL_OFFSET                    (0x00001400)
+#define ARCHI_MCHAN_EXT_OFFSET                      (0x00001800)
+
+#define ARCHI_CLUSTER_PERIPHERALS_ADDR              (ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET)
+#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid)  (ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET)
+
+#define ARCHI_CLUSTER_CTRL_ADDR                     (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_CLUSTER_CTRL_OFFSET)
+#define ARCHI_CLUSTER_TIMER_ADDR                    (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_TIMER_OFFSET)
+#define ARCHI_ICACHE_CTRL_ADDR                      (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_ICACHE_CTRL_OFFSET)
+#define ARCHI_EU_ADDR                               (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_EU_OFFSET)
+#define ARCHI_HWCE_ADDR                             (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_HWCE_OFFSET)
+#define ARCHI_MCHAN_EXT_ADDR                        (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_MCHAN_EXT_OFFSET)
+
+#define ARCHI_DEMUX_PERIPHERALS_OFFSET        (0x204000)
+#define ARCHI_EU_DEMUX_OFFSET                 (0x00000)
+#define ARCHI_MCHAN_DEMUX_OFFSET              (0x00400)
+
+#define ARCHI_DEMUX_PERIPHERALS_ADDR          (ARCHI_CLUSTER_GLOBAL_ADDR(0) + ARCHI_DEMUX_PERIPHERALS_OFFSET)
+#define ARCHI_EU_DEMUX_ADDR                   (ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_EU_DEMUX_OFFSET)
+#define ARCHI_MCHAN_DEMUX_ADDR                (ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET)
+
+
+/* SoC peripherals */
+#define SOC_PERIPHERALS_ADDR                        (0x1A100000)
+
+#define SOC_FLL_OFFSET                              (0x00000000)
+#define CL_FLL_OFFSET                               (0x00000800)
+#define GPIO_OFFSET                                 (0x00001000)
+#define UDMA_OFFSET                                 (0x00002000)
+#define APB_SOC_CTRL_OFFSET                         (0x00004000)
+#define ADV_TIMER_OFFSET                            (0x00005000) /* PWM. */
+#define SOC_EU_OFFSET                               (0x00006000)
+#define FC_IRQ_OFFSET                               (0x00009800)
+/* #define FC_IRQ_OFFSET                               (0x00009000) */ /* valid mirror address */
+#define FC_TIMER_OFFSET                             (0x0000B000)
+#define FC_HWPE_OFFSET                              (0x0000C000)
+#define STDOUT_OFFSET                               (0x0000F000)
+#define DEBUG_OFFSET                                (0x00010000)
+
+#define SOC_FLL_ADDR                                (SOC_PERIPHERALS_ADDR + SOC_FLL_OFFSET)
+#define CL_FLL_ADDR                                 (SOC_PERIPHERALS_ADDR + CL_FLL_OFFSET)
+#define GPIO_ADDR                                   (SOC_PERIPHERALS_ADDR + GPIO_OFFSET)
+#define UDMA_CTRL_ADDR                              (SOC_PERIPHERALS_ADDR + UDMA_OFFSET)
+#define APB_SOC_CTRL_ADDR                           (SOC_PERIPHERALS_ADDR + APB_SOC_CTRL_OFFSET)
+#define ADV_TIMER_ADDR                              (SOC_PERIPHERALS_ADDR + ADV_TIMER_OFFSET)
+#define SOC_EU_ADDR                                 (SOC_PERIPHERALS_ADDR + SOC_EU_OFFSET)
+#define FC_IRQ_ADDR                                 (SOC_PERIPHERALS_ADDR + FC_IRQ_OFFSET)
+#define FC_TIMER_ADDR                               (SOC_PERIPHERALS_ADDR + FC_TIMER_OFFSET)
+#define FC_HWPE_ADDR                                (SOC_PERIPHERALS_ADDR + FC_HWPE_OFFSET)
+#define STDOUT_ADDR                                 (SOC_PERIPHERALS_ADDR + STDOUT_OFFSET)
+#define DEBUG_ADDR                                  (SOC_PERIPHERALS_ADDR + DEBUG_OFFSET)
+
+/* UDMA peripherals */
+/* #define UDMA_GC_ADDR                                (UDMA_CTRL_ADDR + 0x780) */
+/* UDMA base peripheral addr = UDMA base address + UDMA ctrl. */
+#define UDMA_PERIPH_BASE_ADDR                       (UDMA_CTRL_ADDR + 0x80)
+#define UDMA_SPIM(id)                               (UDMA_PERIPH_BASE_ADDR + (UDMA_SPIM_ID(id) << UDMA_PERIPH_SIZE_LOG2))
+#define UDMA_HYPER(id)                              (UDMA_PERIPH_BASE_ADDR + (UDMA_HYPER_ID(id) << UDMA_PERIPH_SIZE_LOG2))
+#define UDMA_UART(id)                               (UDMA_PERIPH_BASE_ADDR + (UDMA_UART_ID(id) << UDMA_PERIPH_SIZE_LOG2))
+#define UDMA_I2C(id)                                (UDMA_PERIPH_BASE_ADDR + (UDMA_I2C_ID(id) << UDMA_PERIPH_SIZE_LOG2))
+#define UDMA_DMACPY(id)                             (UDMA_PERIPH_BASE_ADDR + (UDMA_DMACPY_ID(id) << UDMA_PERIPH_SIZE_LOG2))
+#define UDMA_I2S(id)                                (UDMA_PERIPH_BASE_ADDR + (UDMA_I2S_ID(id) << UDMA_PERIPH_SIZE_LOG2))
+#define UDMA_CPI(id)                                (UDMA_PERIPH_BASE_ADDR + (UDMA_CPI_ID(id) << UDMA_PERIPH_SIZE_LOG2))
+
+
+#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_MEMORY_MAP_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-pmsis-rtos-os.h

+/*
+ * Copyright 2020 GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_RTOS_OS_H_
+#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_RTOS_OS_H_
+
+
+//#include "pmsis/rtos/os_frontend_api/os.h"
+//#include "pmsis/backend/implementation_specific_defines.h"
+//#include "pmsis/backend/pmsis_backend_native_task_api.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function declaration
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API implementation
+ ******************************************************************************/
+
+//static inline int pmsis_kickoff(void *arg)
+//{
+//    return __os_native_kickoff(arg);
+//}
+
+//static inline void pmsis_exit(int err)
+//{
+//    __os_native_exit(err);
+//}
+
+//static inline void *pmsis_task_create(void (*entry)(void*),
+//        void *arg,
+//        char *name,
+//        int priority)
+//{
+//    return __os_native_api_create_task(entry, arg, name, priority);
+//}
+
+//static inline void pmsis_task_suspend(void *task_handler)
+//{
+//    __os_native_task_t *task = (__os_native_task_t *) task_handler;
+//    __os_native_task_suspend(task);
+//}
+
+//static inline void pi_yield()
+//{
+//    __os_native_yield();
+//}
+
+//static inline int disable_irq(void)
+//{
+//    hal_compiler_barrier();
+//    return __os_native_api_disable_irq();
+//}
+
+//static inline void restore_irq(int irq_enable)
+//{
+//    hal_compiler_barrier();
+//    __os_native_api_restore_irq(irq_enable);
+//}
+//
+//static inline int pi_sem_init(pi_sem_t *sem)
+//{
+//    hal_compiler_barrier();
+//    return  __os_native_api_sem_init(sem);
+//}
+//
+//static inline int pi_sem_deinit(pi_sem_t *sem)
+//{
+//    hal_compiler_barrier();
+//    return  __os_native_api_sem_deinit(sem);
+//}
+//
+//static inline void pi_sem_take(pi_sem_t *sem)
+//{
+//    hal_compiler_barrier();
+//    sem->take(sem->sem_object);
+//}
+//
+//static inline void pi_sem_give(pi_sem_t *sem)
+//{
+//    sem->give(sem->sem_object);
+//    hal_compiler_barrier();
+//}
+
+//static inline void pmsis_mutex_take(pmsis_mutex_t *mutex)
+//{
+//    hal_compiler_barrier();
+//#ifdef __NO_NATIVE_MUTEX__
+//    int irq_enabled;
+//    volatile int mutex_free=0;
+//    while (!mutex_free)
+//    {
+//        irq_enabled = disable_irq();
+//        hal_compiler_barrier();
+//        mutex_free = !((volatile uint32_t)mutex->mutex_object);
+//        hal_compiler_barrier();
+//        restore_irq(irq_enabled);
+//    }
+//    irq_enabled = disable_irq();
+//    mutex->mutex_object = (void*)1;
+//    restore_irq(irq_enabled);
+//#else
+//    mutex->take(mutex->mutex_object);
+//#endif
+//}
+//
+//static inline void pmsis_mutex_release(pmsis_mutex_t *mutex)
+//{
+//    hal_compiler_barrier();
+//#ifdef __NO_NATIVE_MUTEX__
+//    int irq_enabled = disable_irq();
+//    hal_compiler_barrier();
+//    mutex->mutex_object = (void*)0;
+//    hal_compiler_barrier();
+//    restore_irq(irq_enabled);
+//#else
+//    mutex->release(mutex->mutex_object);
+//    hal_compiler_barrier();
+//#endif
+//}
+//
+//static inline int pmsis_mutex_init(pmsis_mutex_t *mutex)
+//{
+//    hal_compiler_barrier();
+//#ifdef __NO_NATIVE_MUTEX__
+//    mutex->mutex_object = (void*)0;
+//    return 0;
+//#else
+//    return  __os_native_api_mutex_init(mutex);
+//#endif
+//}
+//
+//static inline int pmsis_mutex_deinit(pmsis_mutex_t *mutex)
+//{
+//    hal_compiler_barrier();
+//#ifdef __NO_NATIVE_MUTEX__
+//    mutex->mutex_object = (void*)0;
+//    return 0;
+//#else
+//    return  __os_native_api_mutex_deinit(mutex);
+//#endif
+//}
+//
+//static inline void pmsis_spinlock_init(pmsis_spinlock_t *spinlock)
+//{
+//    hal_compiler_barrier();
+//    spinlock->lock = 0;
+//}
+//
+//static inline void pmsis_spinlock_take(pmsis_spinlock_t *spinlock)
+//{
+//    int irq_enabled = disable_irq();
+//    hal_compiler_barrier();
+//    spinlock->lock = 1;
+//    hal_compiler_barrier();
+//    restore_irq(irq_enabled);
+//}
+//
+//static inline void pmsis_spinlock_release(pmsis_spinlock_t *spinlock)
+//{
+//    int irq_enabled = disable_irq();
+//    hal_compiler_barrier();
+//    spinlock->lock = 0;
+//    hal_compiler_barrier();
+//    restore_irq(irq_enabled);
+//}
+
+
+#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_RTOS_OS_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-pmsis.h

+/*
+ * Copyright 2019 GreenWaves Technologies
+ * Copyright 2020 ETH Zurich
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_H_
+#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_H_
+
+#include <stddef.h>
+#include <inttypes.h>
+
+/* Debug helper. */
+#ifdef DEBUG
+#define DEBUG_PRINTF printf
+#else
+#define DEBUG_PRINTF(...) ((void) 0)
+#endif  /* DEBUG */
+
+#if (!defined(HW_VERIF_ONLY))
+
+/* Backend includes. */
+//#include "pmsis/backend/implementation_specific_defines.h"
+//#include "hal/include/hal_target.h"
+/* pmsis_api includes. */
+//#include "pmsis/device.h"
+//#include "pmsis/task.h"
+//#include "pmsis_types.h"
+//#include "../../../pmsis_api/include/pmsis/rtos/rtos-orig.h"
+//#include "pmsis/rtos/assert.h"
+//#include "pmsis/mem_slab.h"
+
+/* PMSIS includes. */
+//#include "pmsis/implem/debug.h"
+//#include "pmsis/implem/drivers/drivers_data.h"
+//#include "hal/include/hal_pmsis_drivers.h"
+	#include "hal_fc_event.h"
+	#include "hal_fll_pi.h"
+	#include "hal_i2c_internal.h"
+	#include "hal_uart_internal.h"
+//#include "pmsis/rtos/os/pmsis_task.h"
+//#include "pmsis/rtos/os/pmsis_freq.h"
+//#include "target/core-v-mcu/include/core-v-mcu-pmsis-rtos-os.h"
+//#include "hal/include/hal_native_task_api.h"
+#if defined(FEATURE_CLUSTER)
+//#include "pmsis/implem/cluster/cluster.h"
+#endif  /* FEATURE_CLUSTER */
+
+#endif  /* HW_VERIF_ONLY */
+
+/* Hal includes. */
+//#include "pmsis/implem/hal/hal.h"
+
+#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-properties.h

+/*
+ * Copyright (C) 2019 ETH Zurich, University of Bologna and GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PROPERTIES_H_
+#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PROPERTIES_H_
+
+
+/* PULP defs */
+#define PULP
+
+#define ARCHI_FPGA_FREQUENCY 5000000
+
+/* hardware modules */
+#define ARCHI_NUM_TIMER 1
+#define ARCHI_NUM_FLL 2
+
+#define ARCHI_REF_CLOCK_LOG2 15
+#define ARCHI_REF_CLOCK	(1 << ARCHI_REF_CLOCK_LOG2)
+
+#define ARCHI_NB_FLL	  3
+
+#define __RT_FLL_CL	2
+#define __RT_FLL_PERIPH 1
+#define __RT_FLL_FC	0
+
+#define __RT_FREQ_DOMAIN_FC	0
+#define __RT_FREQ_DOMAIN_CL	2
+#define __RT_FREQ_DOMAIN_PERIPH 1
+#define RT_FREQ_NB_DOMAIN	3
+
+/* Cores & cluster */
+/* FC */
+#define ARCHI_FC_CID                (32)
+
+/* Cluster */
+#define ARCHI_HAS_CLUSTER           (1)
+#define ARCHI_CL_CID(id)            (id)
+#define ARCHI_CLUSTER_NB_PE         (8) /* Processing elements. */
+
+/* Memories */
+/* FC memory */
+#define ARCHI_HAS_FC_TCDM           (1)
+#define ARCHI_HAS_FC_ALIAS          (1)
+#define FC_TCDM_SIZE                (0x00004000) /* 16kB. */
+
+/* L2 memory */
+#define ARCHI_HAS_L2_ALIAS          (0)
+#define L2_SHARED_SIZE              (0x00080000) /* 512kB. */
+
+/* L1 cluster memory */
+#define ARCHI_HAS_CL_L1_ALIAS       (1)
+#define CL_L1_SIZE                  (0x00010000) /* 64kB. */
+
+/* L1 cluster TS */
+#define ARCHI_HAS_CL_L1_TS          (1)
+
+
+
+/* TODO: fix this table */
+/* UDMA peripherals */
+// #define UDMA_HAS_SPIM               (1)
+// #define UDMA_HAS_HYPER              (0)
+// #define UDMA_HAS_UART               (1)
+// #define UDMA_HAS_I2C                (1)
+// #define UDMA_HAS_DMACPY             (0)
+// #define UDMA_HAS_I2S                (1)
+// #define UDMA_HAS_CPI                (1)
+
+/* TODO: fix this table */
+/* Number of UDMA peripherals */
+// #define UDMA_NB_SPIM                (2)
+// #define UDMA_NB_HYPER               (0)
+// #define UDMA_NB_UART                (1)
+// #define UDMA_NB_I2C                 (2)
+// #define UDMA_NB_DMACPY              (0)
+// #define UDMA_NB_I2S                 (1)
+// #define UDMA_NB_CPI                 (1)
+
+/* TODO: fix this table */
+/* #define UDMA_NB_PERIPH              ((UDMA_HAS_SPIM ? UDMA_NB_SPIM) + \ */
+/*                                      (UDMA_HAS_HYPER ? UDMA_NB_HYPER) + \ */
+/*                                      (UDMA_HAS_UART ? UDMA_NB_UART) + \ */
+/*                                      (UDMA_HAS_I2C ? UDMA_NB_I2C) + \ */
+/*                                      (UDMA_HAS_DMACPY ? UDMA_NB_DMACPY) + \ */
+/*                                      (UDMA_HAS_I2S ? UDMA_NB_I2S) + \ */
+/*                                      (UDMA_HAS_CPI ? UDMA_NB_CPI)) */
+#define UDMA_NB_PERIPH              (10)
+/* Size of each UDMA peripheral */
+#define UDMA_PERIPH_SIZE_LOG2       (7)
+#define UDMA_PERIPH_SIZE            (1 << UDMA_PERIPH_SIZE_LOG2)
+
+/* UDMA peripherals ID, this maps to PER_ID_* in udma_subsystem.sv */
+//#define UDMA_SPIM_ID(id)            (1   + (id))
+/* #define UDMA_HYPER_ID(id)           (3   + (id)) */
+//#define UDMA_UART_ID(id)            (0   + (id))
+//#define UDMA_I2C_ID(id)             (2   + (id))
+/* #define UDMA_DMACPY_ID(id)          (7   + (id)) */
+//#define ARCHI_UDMA_FILTER_ID(id)          (7  + (id))
+////#define UDMA_I2S_ID(id)             (5  + (id))
+//#define UDMA_CPI_ID(id)             (6  + (id))
+//#define UDMA_SDIO_ID(id)            (4   + (id))
+
+
+/* Pads & GPIO. */
+// #define ARCHI_NB_PAD                (48)
+// #define ARCHI_NB_GPIO               (32)
+
+/* PWM. */
+/* #define ARCHI_NB_PWM                (4) */
+
+#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PROPERTIES_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-pulp-mem-map.h

+/*
+ * Copyright (C) 2019 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * Author: Robert Balas (balasr@iis.ee.ethz.ch)
+ */
+
+#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PULP_MEM_MAP_H_
+#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PULP_MEM_MAP_H_
+
+
+
+/*
+ * SOC PERIPHERALS
+ */
+
+#define PULP_SOC_PERIPHERALS_ADDR 0x1A100000
+
+#define PULP_FC_TIMER_SIZE 0x00000800
+
+#define PULP_FLL_OFFSET		 0x00000000
+#define PULP_GPIO_OFFSET	 0x00001000
+#define PULP_UDMA_OFFSET	 0x00002000
+#define PULP_APB_SOC_CTRL_OFFSET 0x00004000
+#define PULP_ADV_TIMER_OFFSET	 0x00005000
+#define PULP_SOC_EU_OFFSET	 0x00006000
+#define PULP_FC_IRQ_OFFSET	 0x00009800
+/* #define PULP_FC_IRQ_OFFSET	 0x00009000 */ /* this is a mirror of above */
+#define PULP_FC_TIMER_OFFSET 0x0000B000
+#define PULP_FC_HWPE_OFFSET  0x0000C000
+#define PULP_STDOUT_OFFSET   0x0000F000
+#define PULP_DEBUG_OFFSET    0x00010000
+
+#define PULP_FLL_ADDR  (PULP_SOC_PERIPHERALS_ADDR + PULP_FLL_OFFSET)
+#define PULP_GPIO_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_GPIO_OFFSET)
+#define PULP_UDMA_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_UDMA_OFFSET)
+#define PULP_APB_SOC_CTRL_ADDR                                                 \
+	(PULP_SOC_PERIPHERALS_ADDR + PULP_APB_SOC_CTRL_OFFSET)
+#define PULP_ADV_TIMER_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_ADV_TIMER_OFFSET)
+#define PULP_SOC_EU_ADDR    (PULP_SOC_PERIPHERALS_ADDR + PULP_SOC_EU_OFFSET)
+#define PULP_FC_IRQ_ADDR    (PULP_SOC_PERIPHERALS_ADDR + PULP_FC_IRQ_OFFSET)
+/* #define PULP_FC_ITC_ADDR   (PULP_SOC_PERIPHERALS_ADDR + PULP_FC_ITC_OFFSET) */
+#define PULP_FC_TIMER_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_FC_TIMER_OFFSET)
+#define PULP_FC_HWPE_ADDR  (PULP_SOC_PERIPHERALS_ADDR + PULP_FC_HWPE_OFFSET)
+#define PULP_STDOUT_ADDR   (PULP_SOC_PERIPHERALS_ADDR + PULP_STDOUT_OFFSET)
+
+#define PULP_FLL_AREA_SIZE 0x00000010
+
+/*
+ * CLUSTER
+ */
+
+#define PULP_CLUSTER_ADDR	      0x00000000
+#define PULP_CLUSTER_SIZE	      0x00400000
+#define PULP_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*PULP_CLUSTER_SIZE)
+
+/*
+ * CLUSTER PERIPHERALS
+ */
+
+#define PULP_CLUSTER_PERIPHERALS_OFFSET 0x00200000
+
+#define PULP_TIMER_OFFSET 0x00000400
+
+#define PULP_CLUSTER_PERIPHERALS_ADDR                                          \
+	(PULP_CLUSTER_ADDR + PULP_CLUSTER_PERIPHERALS_OFFSET)
+#define PULP_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid)                              \
+	(PULP_CLUSTER_GLOBAL_ADDR(cid) + PULP_CLUSTER_PERIPHERALS_OFFSET)
+
+#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PULP_MEM_MAP_H_ */