1. 03 6月, 2013 4 次提交
  2. 31 5月, 2013 5 次提交
  3. 30 5月, 2013 6 次提交
  4. 29 5月, 2013 7 次提交
  5. 27 5月, 2013 1 次提交
  6. 26 5月, 2013 8 次提交
  7. 25 5月, 2013 6 次提交
  8. 24 5月, 2013 1 次提交
    • G
      add rm48x50 bsp and libcpu · f51bce3f
      Grissiom 提交于
      We currently only support building with CCS and SCons is not using.
      bsp/rm48x50/HALCoGen/HALCoGen.{hcg,dil} is the HALCoGen project file.
      You may need to regenerate the source file as you like, providing that:
      
          1, IRQ is in Dispatch Mode and the table entry is IRQ_Handler. The
          channel 5 in enabled and connected to IRQ.
      
          2, RTI driver is enabled and compare3 source is selected to counter1
          and the compare3 will generate tick in the period of 10ms. This
          value is coresponding with RT_TICK_PER_SECOND in rtconfig.h.
      
      In CCS, you need to create a new CCS project and create link folders
      pointing at bsp/rm48x50, libcpu/arm/rm48x50 and src/, include/. Remember
      to add the include path to the Build Properties.
      f51bce3f
  9. 23 5月, 2013 2 次提交