[bsp] add new bsp for lpc824

bsp/lpc824/Libraries/SConscript

+# RT-Thread building script for component
+
+Import('rtconfig')
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+
+src  = Glob('peri_driver/*/*.c')
+src += Glob('common/board/*.c')
+src += Glob('common/chip/*.c')
+
+# add for startup script 
+if rtconfig.CROSS_TOOL == 'gcc':
+    print "not gcc startup file"
+    exit(0)
+elif rtconfig.CROSS_TOOL == 'keil':
+    src += [cwd + '/common/startup/keil_startup_lpc82x.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src += [cwd + '/common/startup/iar_startup_lpc82x.s']
+
+CPPPATH = [ cwd + '/peri_driver', cwd + '/common/board', 
+			cwd + '/common/chip', cwd + '/common/CMSIS']
+			
+if GetDepend(['RT_USING_BSP_CMSIS']):
+    CPPPATH += [cwd + '/common/CMSIS/']
+elif GetDepend(['RT_USING_RTT_CMSIS']):
+    CPPPATH += [RTT_ROOT + '/components/CMSIS/Include']
+			
+CPPDEFINES = ['CORE_M0PLUS']
+
+group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
+
+Return('group')

bsp/lpc824/Libraries/common/CMSIS/core_cmFunc.h

+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */

bsp/lpc824/Libraries/common/CMSIS/core_cmInstr.h

+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

bsp/lpc824/Libraries/common/board/board_api.h

+/*
+ * @brief Common board API functions
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2013
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __BOARD_API_H_
+#define __BOARD_API_H_
+
+#include "lpc_types.h"
+#include <stdio.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup BOARD_COMMON_API BOARD: Common board functions
+ * @ingroup BOARD_Common
+ * This file contains common board definitions that are shared across
+ * boards and devices. All of these functions do not need to be
+ * implemented for a specific board, but if they are implemented, they
+ * should use this API standard.
+ * @{
+ */
+
+/**
+ * @brief	Setup and initialize hardware prior to call to main()
+ * @return	None
+ * @note	Board_SystemInit() is called prior to the application and sets up system
+ * clocking, memory, and any resources needed prior to the application
+ * starting.
+ */
+void Board_SystemInit(void);
+
+/**
+ * @brief	Setup pin multiplexer per board schematics
+ * @return	None
+ * @note	Board_SetupMuxing() should be called from SystemInit() prior to application
+ * main() is called. So that the PINs are set in proper state.
+ */
+void Board_SetupMuxing(void);
+
+/**
+ * @brief	Setup system clocking
+ * @return	None
+ * @note	This sets up board clocking.
+ */
+void Board_SetupClocking(void);
+
+/**
+ * @brief	Setup external system memory
+ * @return	None
+ * @note	This function is typically called after pin mux setup and clock setup and
+ * sets up any external memory needed by the system (DRAM, SRAM, etc.). Not all
+ * boards need this function.
+ */
+void Board_SetupExtMemory(void);
+
+/**
+ * @brief	Set up and initialize all required blocks and functions related to the board hardware.
+ * @return	None
+ */
+void Board_Init(void);
+
+/**
+ * @brief	Initializes board UART for output, required for printf redirection
+ * @return	None
+ */
+void Board_Debug_Init(void);
+
+/**
+ * @brief	Sends a single character on the UART, required for printf redirection
+ * @param	ch	: character to send
+ * @return	None
+ */
+void Board_UARTPutChar(char ch);
+
+/**
+ * @brief	Sends a single character on the UART, automatic process '\n' -> '\r\n'
+ * @param	ch	: character to send
+ * @return	None
+ */
+void Board_UARTPutTextChar(char ch);
+
+
+/**
+ * @brief	Classic implementation of itoa -- integer to ASCII
+ * @param	value	: value to convert
+ * @param	result	: result string
+ * @param	base	: output radix
+ * @return	result string or NULL
+ */
+char *Board_itoa(int value, char *result, int base);
+
+/**
+ * @brief	Get a single character from the UART, required for scanf input
+ * @return	EOF if not character was received, or character value
+ */
+int Board_UARTGetChar(void);
+
+/**
+ * @brief	Prints a string to the UART
+ * @param	str	: Terminated string to output
+ * @return	None
+ */
+void Board_UARTPutSTR(const char *str);
+
+/**
+ * @brief	Get if a key is down
+ * @param	keyIndex : The index of the key to detect
+ * @return	1 = key is down , 0 = key is up
+ */
+uint32_t Board_Key_GetKeyDown(uint32_t keyIndex);
+
+/**
+ * @brief	Sets the state of a board LED to on or off
+ * @param	LEDNumber	: LED number to set state for
+ * @param	State		: true for on, false for off
+ * @return	None
+ */
+void Board_LED_Set(uint8_t LEDNumber, bool State);
+
+/**
+ * @brief	Returns the current state of a board LED
+ * @param	LEDNumber	: LED number to set state for
+ * @return	true if the LED is on, otherwise false
+ */
+bool Board_LED_Test(uint8_t LEDNumber);
+
+/**
+ * @brief	Toggles the current state of a board LED
+ * @param	LEDNumber	: LED number to change state for
+ * @return	None
+ */
+void Board_LED_Toggle(uint8_t LEDNumber);
+
+/**
+ * @brief	Turn on Board LCD Backlight
+ * @param	Intensity	: Backlight intensity (0 = off, >=1 = on)
+ * @return	None
+ * @note	On boards where a GPIO is used to control backlight on/off state, a '0' or '1'
+ * value will turn off or on the backlight. On some boards, a non-0 value will
+ * control backlight intensity via a PWN. For PWM systems, the intensity value
+ * is a percentage value between 0 and 100%.
+ */
+void Board_SetLCDBacklight(uint8_t Intensity);
+
+/**
+ * @brief Function prototype for a MS delay function. Board layers or example code may
+ *        define this function as needed.
+ */
+typedef void (*p_msDelay_func_t)(uint32_t);
+
+/* The DEBUG* functions are selected based on system configuration.
+   Code that uses the DEBUG* functions will have their I/O routed to
+   the UART, semihosting, or nowhere. */
+#if defined(DEBUG_ENABLE)
+#if defined(DEBUG_SEMIHOSTING)
+#define DEBUGINIT()
+#define DEBUGOUT(...) printf(__VA_ARGS__)
+#define DEBUGSTR(str) printf(str)
+#define DEBUGIN() (int) EOF
+
+#else
+#define DEBUGINIT() Board_Debug_Init()
+#define DEBUGOUT(...) printf(__VA_ARGS__)
+#define DEBUGSTR(str) Board_UARTPutSTR(str)
+#define DEBUGIN() Board_UARTGetChar()
+#endif /* defined(DEBUG_SEMIHOSTING) */
+
+#else
+#define DEBUGINIT()
+#define DEBUGOUT(...)
+#define DEBUGSTR(str)
+#define DEBUGIN() (int) EOF
+#endif /* defined(DEBUG_ENABLE) */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOARD_API_H_ */

bsp/lpc824/Libraries/common/board/board_lpc.c

+
+/*
+ * @brief NXP LPCXpresso LPC824 board file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2013
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+ 
+// Must define _BOARD_C_ before ANY include
+#define _BOARD_C_
+
+#include "board_lpc.h"
+#include "string.h"
+#include <stdint.h>
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+#define BOARD_LED_CNT 8
+
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+
+/* System oscillator rate and clock rate on the CLKIN pin */
+const uint32_t OscRateIn = MAIN_OSC_XTAL_FREQ_HZ;
+const uint32_t ExtRateIn = EXT_CLOCK_IN_FREQ_HZ;
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+static void Board_Key_Init(void)
+{
+	int i;
+	LPC_IOCON_T *pIOCON = LPC_IOCON;
+	for (i = 0; i < BOARD_KEY_CNT; i++) {
+		Chip_GPIO_PinSetDIR(LPC_GPIO_PORT, 0, cs_keyBits[i], 0);
+		pIOCON->PIO0[cs_keyIoConNdce[i]] = 0x80;	// weak pUp
+	}
+}
+
+/* Initialize the LEDs on the NXP LPC824 LPCXpresso Board */
+static void Board_LED_Init(void)
+{
+	int i;
+
+	for (i = 0; i < BOARD_LED_CNT; i++) {
+		Chip_GPIO_PinSetDIR(LPC_GPIO_PORT, 0, ledBits[i], 1);
+		Chip_GPIO_PinSetState(LPC_GPIO_PORT, 0, ledBits[i], true);
+	}
+}
+
+uint32_t Board_Key_GetKeyDown(uint32_t keyNdx)
+{
+	LPC_GPIO_T *pGP = LPC_GPIO_PORT;
+ 	return pGP->W[0][cs_keyBits[keyNdx]] == 0 ? 1 : 0;
+}
+
+/* Board Debug UART Initialisation function */
+STATIC void Board_UART_Init(void)
+{
+	/* Enable the clock to the Switch Matrix */
+	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM);
+
+	/* Connect the TXD_O and RXD_I signals to port pins(P0.4, P0.0) */
+	//Chip_SWM_DisableFixedPin(SWM_FIXED_XTALIN);
+	//Chip_SWM_DisableFixedPin(SWM_FIXED_XTALOUT);
+	
+	Chip_SWM_DisableFixedPin(SWM_FIXED_ACMP_I1);
+	Chip_SWM_DisableFixedPin(SWM_FIXED_ADC11);
+
+	/* Enable UART Divider clock, divided by 1 */
+	Chip_Clock_SetUARTClockDiv(1);
+
+	/* Divided by 1 */
+	if (DEBUG_UART == LPC_USART0) {
+
+		Chip_SWM_MovablePinAssign(SWM_U0_TXD_O, 4);
+		Chip_SWM_MovablePinAssign(SWM_U0_RXD_I, 0);
+	} else if (DEBUG_UART == LPC_USART1) {
+		Chip_SWM_MovablePinAssign(SWM_U1_TXD_O, 4);
+		Chip_SWM_MovablePinAssign(SWM_U1_RXD_I, 0);
+	} else {
+		Chip_SWM_MovablePinAssign(SWM_U2_TXD_O, 4);
+		Chip_SWM_MovablePinAssign(SWM_U2_RXD_I, 0);
+	}
+
+	/* Disable the clock to the Switch Matrix to save power */
+	Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SWM);
+}
+
+/* Initializes pin muxing for SPI1 interface - note that SystemInit() may
+   already setup your pin muxing at system startup */
+static void Init_SPI_PinMux(void)
+{
+
+	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM);
+	Chip_SWM_MovablePinAssign(SWM_SPI1_SSEL0_IO, 15);
+	Chip_SWM_MovablePinAssign(SWM_SPI1_SCK_IO, 24);
+	Chip_SWM_MovablePinAssign(SWM_SPI1_MISO_IO, 25);
+	Chip_SWM_MovablePinAssign(SWM_SPI1_MOSI_IO, 26);
+	Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SWM);
+
+}
+
+/* Initializes pin muxing for I2C interface */
+static void Init_I2C_PinMux(void)
+{
+	/* Enable the clock to the Switch Matrix */
+	Chip_Clock_EnablePeriphClock(SYSCTL_CLOCK_SWM);
+	Chip_SWM_EnableFixedPin(SWM_FIXED_I2C0_SDA);
+	Chip_SWM_EnableFixedPin(SWM_FIXED_I2C0_SCL);
+
+	/* Enable Fast Mode Plus for I2C pins */
+	Chip_IOCON_PinSetI2CMode(LPC_IOCON, IOCON_PIO10, PIN_I2CMODE_FASTPLUS);
+	Chip_IOCON_PinSetI2CMode(LPC_IOCON, IOCON_PIO11, PIN_I2CMODE_FASTPLUS);
+
+	/* Disable the clock to the Switch Matrix to save power */
+	Chip_Clock_DisablePeriphClock(SYSCTL_CLOCK_SWM);
+}
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/* Set the LED to the state of "On" */
+void Board_LED_Set(uint8_t LEDNumber, bool On)
+{
+	if (LEDNumber < BOARD_LED_CNT) {
+		Chip_GPIO_PinSetState(LPC_GPIO_PORT, 0, ledBits[LEDNumber], (bool) !On);
+	}
+}
+
+/* Return the state of LEDNumber */
+bool Board_LED_Test(uint8_t LEDNumber)
+{
+	bool state = false;
+
+	if (LEDNumber < BOARD_LED_CNT) {
+		state = (bool) !Chip_GPIO_PinGetState(LPC_GPIO_PORT, 0, ledBits[LEDNumber]);
+	}
+
+	return state;
+}
+
+/* Toggles the current state of a board LED */
+void Board_LED_Toggle(uint8_t LEDNumber)
+{
+	if (LEDNumber < BOARD_LED_CNT) {
+		Chip_GPIO_PinToggleState(LPC_GPIO_PORT, 0, ledBits[LEDNumber]);
+	}
+}
+
+/*  Classic implementation of itoa -- integer to ASCII */
+char *Board_itoa(int value, char *result, int base)
+{
+    char* ptr = result, *ptr1 = result, tmp_char;
+    int tmp_value;
+
+    if (base < 2 || base > 36) { *result = '\0'; return result; }
+    do {
+        tmp_value = value;
+        value /= base;
+        *ptr++ = "zyxwvutsrqponmlkjihgfedcba9876543210123456789abcdefghijklmnopqrstuvwxyz" [35 + (tmp_value - value * base)];
+    } while ( value );
+
+    if (tmp_value < 0) *ptr++ = '-';
+    *ptr-- = '\0';
+    while (ptr1 < ptr) {
+        tmp_char = *ptr;
+        *ptr--= *ptr1;
+        *ptr1++ = tmp_char;
+    }
+    return result;
+}
+
+/* Sends a character on the UART */
+void Board_UARTPutChar(char ch)
+{
+#if defined(DEBUG_UART)
+	Chip_UART_SendBlocking(DEBUG_UART, &ch, 1);
+#endif
+}
+
+void Board_UARTPutTextChar(char ch)
+{
+#if defined(DEBUG_UART)
+	static char prevChar = 0;
+	if (ch == '\n' && prevChar != '\r')
+	{
+		prevChar = '\r';
+		Chip_UART_SendBlocking(DEBUG_UART, &prevChar, 1);
+		Chip_UART_SendBlocking(DEBUG_UART, &ch, 1);
+	} else {
+		Chip_UART_SendBlocking(DEBUG_UART, &ch, 1);
+		prevChar = ch;
+	}
+#endif
+}
+
+
+/* Gets a character from the UART, returns EOF if no character is ready */
+int Board_UARTGetChar(void)
+{
+#if defined(DEBUG_UART)
+	uint8_t data;
+
+	if (Chip_UART_ReadBlocking(DEBUG_UART, &data, 1) == 1) {
+		Board_UARTPutChar(data);	// echo back the char
+		return (int) data;
+	}
+#endif
+	return EOF;
+}
+
+/* Outputs a string on the debug UART */
+void Board_UARTPutSTR(const char *str)
+{
+#if defined(DEBUG_UART)
+	while (*str != '\0') {
+		Board_UARTPutTextChar(*str++);
+	}
+#endif
+}
+
+/* Initialize debug output via UART for board */
+void Board_Debug_Init(void)
+{
+#if defined(DEBUG_UART)
+	Board_UART_Init();
+	Chip_UART_Init(DEBUG_UART);
+	Chip_UART_ConfigData(DEBUG_UART, UART_CFG_DATALEN_8 | UART_CFG_PARITY_NONE | UART_CFG_STOPLEN_1);
+	Chip_Clock_SetUSARTNBaseClockRate((115200 * 6 * 16), true);
+	Chip_UART_SetBaud(DEBUG_UART, 115200);
+	Chip_UART_Enable(DEBUG_UART);
+	Chip_UART_TXEnable(DEBUG_UART);
+#endif
+}
+
+/* Set up and initialize all required blocks and functions related to the
+   board hardware */
+void Board_Init(void)
+{
+	LPC_SWM_T *pSWM = LPC_SWM;
+	/* Sets up DEBUG UART */
+	#if defined(DEBUG_ENABLE)
+	DEBUGINIT();
+	//pSWM->PINENABLE0 |= ~(1UL<<SWM_FIXED_SWCLK | 1UL<<SWM_FIXED_SWDIO | 1UL<<SWM_FIXED_RST);
+	#ifdef USE_IRC_AS_ROOT_CLOCK
+		pSWM->PINENABLE0 |= 1UL<<SWM_FIXED_XTALIN | 1UL<<SWM_FIXED_XTALOUT;
+	#endif
+	#endif
+	/* Initialize GPIO */
+	Chip_GPIO_Init(LPC_GPIO_PORT);
+
+	/* Initialize the LEDs */
+	Board_LED_Init();
+	//Board_Key_Init();
+	Init_SPI_PinMux();
+	Init_I2C_PinMux();
+}

bsp/lpc824/Libraries/common/board/board_lpc.h

+/*
+ * @brief NXP LPCXpresso LPC824 board file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __BOARD_H_
+#define __BOARD_H_
+
+#include "chip.h"
+/* board_api.h is included at the bottom of this file after DEBUG setup */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup BOARD_NXP_LPCXPRESSO_824 NXP LPC824 LPCXpresso board support software API functions
+ * @ingroup LPCOPEN_8XX_BOARD_LPCXPRESSO_824
+ * The board support software API functions provide some simple abstracted
+ * functions used across multiple LPCOpen board examples. See @ref BOARD_COMMON_API
+ * for the functions defined by this board support layer.<br>
+ * @{
+ */
+
+/** @defgroup LPCOPEN_8XX_BOARD_LPCXPRESSO_824_OPTIONS BOARD: LPC824 LPCXpresso board build options
+ * This board has options that configure its operation at build-time.<br>
+ * @{
+ */
+
+/** Define the frequency in Hz, of the main oscillator (from Xtal) 
+ * Note that it only takes effect if main oscillator is selected as clock source
+ */
+#define MAIN_OSC_XTAL_FREQ_HZ		12000000
+/** Define the frequency in Hz, of the external clock input.
+ * Note that it only takes effect if external clock is selected as clock source
+ */
+#define EXT_CLOCK_IN_FREQ_HZ		0
+
+//#define USE_IRC_AS_ROOT_CLOCK /*注释掉使用外部晶体 打开定义则是使用内部IRC*/
+
+#define BOARD_LED_CNT 8
+#define BOARD_KEY_CNT 3
+
+typedef enum _enum_boardKeys
+{
+	BOARD_KEY_0 = 0,
+	BOARD_KEY_1 = 1,
+	BOARD_KEY_2 = 2,
+}enum_boardKeys;
+
+// define LED bits (bit <--> pin on port 0) only if in board.c file
+#ifdef  _BOARD_C_
+static const uint8_t ledBits[BOARD_LED_CNT] = {7, 13, 16, 17, 19, 27, 28, 18};
+static const uint8_t cs_keyBits[BOARD_KEY_CNT] = {12, 4 , 1};
+static const uint8_t cs_keyIoConNdce[BOARD_KEY_CNT] = {IOCON_PIO12, IOCON_PIO4, IOCON_PIO1};
+#endif
+ 
+/** Define DEBUG_ENABLE to enable IO via the DEBUGSTR, DEBUGOUT, and
+    DEBUGIN macros. If not defined, DEBUG* functions will be optimized
+	out of the code at build time.
+ */
+#define DEBUG_ENABLE
+
+/** Define DEBUG_SEMIHOSTING along with DEBUG_ENABLE to enable IO support
+    via semihosting. You may need to use a C library that supports
+	semihosting with this option.
+ */
+//#define DEBUG_SEMIHOSTING
+
+/** Board UART used for debug output and input using the DEBUG* macros. This
+    is also the port used for Board_UARTPutChar, Board_UARTGetChar, and
+	Board_UARTPutSTR functions. Although you can setup multiple UARTs here,
+	the board code only supoprts UART0 in the Board_UART_Init() fucntion,
+	so be sure to change it there too if not using UART0.
+ */
+#define DEBUG_UART LPC_USART1
+
+/**
+ * @}
+ */
+
+/* Board name */
+#define BOARD_NXP_LPCXPRESSO_824
+
+
+#include "board_api.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __BOARD_H_ */

bsp/lpc824/Libraries/common/chip/chip.h

+/*
+ * @brief LPC8xx basic chip inclusion file
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2013
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licensor disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+
+#ifndef __CHIP_H_
+#define __CHIP_H_
+
+#include "lpc_types.h"
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef CORE_M0PLUS
+#error CORE_M0PLUS is not defined for the LPC8xx architecture
+#error CORE_M0PLUS should be defined as part of your compiler define list
+#endif
+
+#ifndef CHIP_LPC8XX
+#error The LPC8XX Chip include path is used for this build, but
+#error CHIP_LPC8XX is not defined!
+#endif
+
+/** @defgroup PERIPH_8XX_BASE CHIP: LPC8xx Peripheral addresses and register set declarations
+ * @ingroup CHIP_8XX_Drivers
+ * @{
+ */
+
+/* Base addresses */
+#define LPC_FLASH_BASE        (0x00000000UL)
+#define LPC_RAM_BASE          (0x10000000UL)
+#define LPC_ROM_BASE          (0x1FFF0000UL)
+#define LPC_APB0_BASE         (0x40000000UL)
+#define LPC_AHB_BASE          (0x50000000UL)
+
+/* APB0 peripherals */
+#define LPC_WWDT_BASE         (0x40000000UL)
+#define LPC_MRT_BASE          (0x40004000UL)
+#define LPC_WKT_BASE          (0x40008000UL)
+#define LPC_SWM_BASE          (0x4000C000UL)
+#define LPC_ADC_BASE          (0x4001C000UL)  /* Available only on LPC82x */
+#define LPC_PMU_BASE          (0x40020000UL)
+#define LPC_CMP_BASE          (0x40024000UL)
+#define LPC_DMATIRGMUX_BASE   (0x40028000UL)  /* Available only on LPC82x */
+#define LPC_INMUX_BASE        (0x4002C000UL)  /* Available only on LPC82x */
+
+#define LPC_FMC_BASE          (0x40040000UL)
+#define LPC_IOCON_BASE        (0x40044000UL)
+#define LPC_SYSCTL_BASE       (0x40048000UL)
+#define LPC_I2C0_BASE         (0x40050000UL)
+#define LPC_I2C1_BASE         (0x40054000UL)  /* Available only on LPC82x */
+#define LPC_SPI0_BASE         (0x40058000UL)
+#define LPC_SPI1_BASE         (0x4005C000UL)
+#define LPC_USART0_BASE       (0x40064000UL)
+#define LPC_USART1_BASE       (0x40068000UL)
+#define LPC_USART2_BASE       (0x4006C000UL)
+#define LPC_I2C2_BASE         (0x40070000UL)  /* Available only on LPC82x */
+#define LPC_I2C3_BASE         (0x40074000UL)  /* Available only on LPC82x */
+
+/* AHB peripherals */
+#define LPC_CRC_BASE          (0x50000000UL)
+#define LPC_SCT_BASE          (0x50004000UL)
+#define LPC_DMA_BASE          (0x50008000UL)  /* Available only on LPC82x */
+
+#define LPC_GPIO_PORT_BASE    (0xA0000000UL)
+#define LPC_PIN_INT_BASE      (0xA0004000UL)
+
+#define LPC_WWDT            ((LPC_WWDT_T     *) LPC_WWDT_BASE)
+#define LPC_SPI0            ((LPC_SPI_T      *) LPC_SPI0_BASE)
+#define LPC_SPI1            ((LPC_SPI_T      *) LPC_SPI1_BASE)
+#define LPC_USART0          ((LPC_USART_T    *) LPC_USART0_BASE)
+#define LPC_USART1          ((LPC_USART_T    *) LPC_USART1_BASE)
+#define LPC_USART2          ((LPC_USART_T    *) LPC_USART2_BASE)
+#define LPC_WKT             ((LPC_WKT_T         *) LPC_WKT_BASE)
+#define LPC_PMU             ((LPC_PMU_T         *) LPC_PMU_BASE)
+#define LPC_CRC             ((LPC_CRC_T         *) LPC_CRC_BASE)
+#define LPC_SCT             ((LPC_SCT_T         *) LPC_SCT_BASE)
+#define LPC_GPIO_PORT       ((LPC_GPIO_T        *) LPC_GPIO_PORT_BASE)
+#define LPC_PININT          ((LPC_PININT_T     *) LPC_PIN_INT_BASE)
+#define LPC_IOCON           ((LPC_IOCON_T       *) LPC_IOCON_BASE)
+#define LPC_SWM             ((LPC_SWM_T         *) LPC_SWM_BASE)
+#define LPC_SYSCTL          ((LPC_SYSCTL_T      *) LPC_SYSCTL_BASE)
+#define LPC_CMP             ((LPC_CMP_T         *) LPC_CMP_BASE)
+#define LPC_FMC             ((LPC_FMC_T         *) LPC_FMC_BASE)
+#define LPC_MRT             ((LPC_MRT_T         *) LPC_MRT_BASE)
+#define LPC_I2C0            ((LPC_I2C_T         *) LPC_I2C0_BASE)
+
+#ifdef CHIP_LPC82X
+/* Peripherals available only on LPC82x */
+#define LPC_ADC             ((LPC_ADC_T         *) LPC_ADC_BASE)
+#define LPC_I2C1            ((LPC_I2C_T         *) LPC_I2C1_BASE)
+#define LPC_I2C2            ((LPC_I2C_T         *) LPC_I2C2_BASE)
+#define LPC_I2C3            ((LPC_I2C_T         *) LPC_I2C3_BASE)
+#define LPC_DMA             ((LPC_DMA_T         *) LPC_DMA_BASE)
+#define LPC_DMATRIGMUX      ((LPC_DMATRIGMUX_T  *) LPC_DMATIRGMUX_BASE)
+#define LPC_INMUX           ((LPC_INMUX_T       *) LPC_INMUX_BASE)
+#endif
+
+/* Base address Alias list */
+#define LPC_I2C_BASE         LPC_I2C0_BASE
+#define LPC_I2C              LPC_I2C0
+#define LPC_SYSCON           LPC_SYSCTL
+
+/* IRQ Handler alias list */
+#ifdef CHIP_LPC82X
+#define I2C_IRQHandler       I2C0_IRQHandler
+#define PININT0_IRQHandler   PIN_INT0_IRQHandler
+#define PININT1_IRQHandler   PIN_INT1_IRQHandler
+#define PININT2_IRQHandler   PIN_INT2_IRQHandler
+#define PININT3_IRQHandler   PIN_INT3_IRQHandler
+#define PININT4_IRQHandler   PIN_INT4_IRQHandler
+#define PININT5_IRQHandler   PIN_INT5_IRQHandler
+#define PININT6_IRQHandler   PIN_INT6_IRQHandler
+#define PININT7_IRQHandler   PIN_INT7_IRQHandler
+#endif
+
+/**
+ * @}
+ */
+
+/** @ingroup CHIP_8XX_DRIVER_OPTIONS
+ * @{
+ */
+
+/**
+ * @brief	System oscillator rate
+ * This value is defined externally to the chip layer and contains
+ * the value in Hz for the external oscillator for the board. If using the
+ * internal oscillator, this rate can be 0.
+ */
+extern const uint32_t OscRateIn;
+
+/**
+ * @brief	Clock rate on the CLKIN pin
+ * This value is defined externally to the chip layer and contains
+ * the value in Hz for the CLKIN pin for the board. If this pin isn't used,
+ * this rate can be 0.
+ */
+extern const uint32_t ExtRateIn;
+
+/**
+ * @}
+ */
+
+/* Include order is important! */
+#include "syscon_8xx.h"
+#include "clock_8xx.h"
+#include "fmc_8xx.h"
+#include "ioswm_8xx.h"
+
+#ifndef _CHIP_COMMON_
+#include "../../peri_driver/peri_driver.h"
+#endif
+
+/** @defgroup SUPPORT_8XX_FUNC CHIP: LPC8xx support functions
+ * @ingroup CHIP_8XX_Drivers
+ * @{
+ */
+
+/**
+ * @brief	Current system clock rate, mainly used for sysTick
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief	Update system core clock rate, should be called if the
+ *			system has a clock rate change
+ * @return	None
+ */
+void SystemCoreClockUpdate(void);
+
+/**
+ * @brief	Set up and initialize hardware prior to call to main()
+ * @return	None
+ * @note	Chip_SystemInit() is called prior to the application and sets up
+ * system clocking prior to the application starting.
+ */
+void Chip_SystemInit(void);
+
+/**
+ * @brief	Clock and PLL initialization based on the external oscillator
+ * @return	None
+ * @note	This function assumes an external crystal oscillator
+ * frequency of 12MHz.
+ */
+void Chip_SetupXtalClocking(void);
+
+/**
+ * @brief	Clock and PLL initialization based on the internal oscillator
+ * @return	None
+ */
+void Chip_SetupIrcClocking(void);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CHIP_H_ */

bsp/lpc824/Libraries/common/chip/clock_8xx.c

+/*
+ * @brief LPC8xx clock driver
+ *
+ * @note
+ * Copyright(C) NXP Semiconductors, 2012
+ * All rights reserved.
+ *
+ * @par
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * LPC products.  This software is supplied "AS IS" without any warranties of
+ * any kind, and NXP Semiconductors and its licenser disclaim any and
+ * all warranties, express or implied, including all implied warranties of
+ * merchantability, fitness for a particular purpose and non-infringement of
+ * intellectual property rights.  NXP Semiconductors assumes no responsibility
+ * or liability for the use of the software, conveys no license or rights under any
+ * patent, copyright, mask work right, or any other intellectual property rights in
+ * or to any products. NXP Semiconductors reserves the right to make changes
+ * in the software without notification. NXP Semiconductors also makes no
+ * representation or warranty that such application will be suitable for the
+ * specified use without further testing or modification.
+ *
+ * @par
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation is hereby granted, under NXP Semiconductors' and its
+ * licensor's relevant copyrights in the software, without fee, provided that it
+ * is used in conjunction with NXP Semiconductors microcontrollers.  This
+ * copyright, permission, and disclaimer notice must appear in all copies of
+ * this code.
+ */
+#define _CHIP_COMMON_
+#include "chip.h"
+
+
+/*****************************************************************************
+ * Private types/enumerations/variables
+ ****************************************************************************/
+
+/* Inprecise clock rates for the watchdog oscillator */
+static const uint32_t wdtOSCRate[WDTLFO_OSC_4_60 + 1] = {
+	0,					/* WDT_OSC_ILLEGAL */
+	600000,				/* WDT_OSC_0_60 */
+	1050000,			/* WDT_OSC_1_05 */
+	1400000,			/* WDT_OSC_1_40 */
+	1750000,			/* WDT_OSC_1_75 */
+	2100000,			/* WDT_OSC_2_10 */
+	2400000,			/* WDT_OSC_2_40 */
+	2700000,			/* WDT_OSC_2_70 */
+	3000000,			/* WDT_OSC_3_00 */
+	3250000,			/* WDT_OSC_3_25 */
+	3500000,			/* WDT_OSC_3_50 */
+	3750000,			/* WDT_OSC_3_75 */
+	4000000,			/* WDT_OSC_4_00 */
+	4200000,			/* WDT_OSC_4_20 */
+	4400000,			/* WDT_OSC_4_40 */
+	4600000				/* WDT_OSC_4_60 */
+};
+
+ typedef struct {
+	uint16_t	freq_main;			//	main clock frequency in MHz
+	uint16_t	freq_sys;			//	system (CPU) clock frequency in MHz
+	uint16_t	freq_fcco;			//	FCCO clock frequency in MHz
+	uint16_t	msel;				//	MSEL (pre-decremented)
+	uint16_t	psel;				//	PSEL (pre-decremented)
+	uint16_t	divider;			//	SYSAHBCLKDIV
+} LPC_8XX_PLL_T;
+ 
+/*
+ *	This table contains all useful PLL configurations
+ *	for "integer" MHZ (e.g. 1MHz, 2MHz, etc.) frequencies.
+ *
+ *	This table has two inputs:
+ *	- freq_main: This is the main frequency.
+ *	- freq_sys: This is the system (CPU) frequency.
+ *	These are used to select which table entry to use.
+ *
+ *	There are many ways to get some frequencies. For example,
+ *	there are eight ways to make the CPU run at 12MHZ. If the peripheral bus
+ *	needs to run very fast, it's possible to set the main clock
+ *	up to 96MHz. If low power is a requirement, it's possible to set the main
+ *	clock to 12MHz.
+ *
+ *	All the rest of the table entries are outputs.
+ *	- freq_fcco is simply an FYI value. It is not used for programming.
+ *	- MSEL / PSEL / divider are used to program the PLL.
+ */
+static const LPC_8XX_PLL_T config_tab[] = {
+	{	  12,   12,  192,    0,    3,    1	},		// 12.0000MHz
+	{	  12,    6,  192,    0,    3,    2	},		//  6.0000MHz
+	{	  12,    4,  192,    0,    3,    3	},		//  4.0000MHz
+	{	  12,    3,  192,    0,    3,    4	},		//  3.0000MHz
+	{	  12,    2,  192,    0,    3,    6	},		//  2.0000MHz
+	{	  12,    1,  192,    0,    3,   12	},		//  1.0000MHz
+	{	  24,   24,  192,    1,    2,    1	},		// 24.0000MHz
+	{	  24,   12,  192,    1,    2,    2	},		// 12.0000MHz
+	{	  24,    8,  192,    1,    2,    3	},		//  8.0000MHz
+	{	  24,    6,  192,    1,    2,    4	},		//  6.0000MHz
+	{	  24,    4,  192,    1,    2,    6	},		//  4.0000MHz
+	{	  24,    3,  192,    1,    2,    8	},		//  3.0000MHz
+	{	  24,    2,  192,    1,    2,   12	},		//  2.0000MHz
+	{	  24,    1,  192,    1,    2,   24	},		//  1.0000MHz
+	{	  36,   18,  288,    2,    2,    2	},		// 18.0000MHz
+	{	  36,   12,  288,    2,    2,    3	},		// 12.0000MHz
+	{	  36,    9,  288,    2,    2,    4	},		//  9.0000MHz
+	{	  36,    6,  288,    2,    2,    6	},		//  6.0000MHz
+	{	  36,    4,  288,    2,    2,    9	},		//  4.0000MHz
+	{	  36,    3,  288,    2,    2,   12	},		//  3.0000MHz
+	{	  36,    2,  288,    2,    2,   18	},		//  2.0000MHz
+	{	  36,    1,  288,    2,    2,   36	},		//  1.0000MHz
+	{	  48,   24,  192,    3,    1,    2	},		// 24.0000MHz
+	{	  48,   16,  192,    3,    1,    3	},		// 16.0000MHz
+	{	  48,   12,  192,    3,    1,    4	},		// 12.0000MHz
+	{	  48,    8,  192,    3,    1,    6	},		//  8.0000MHz
+	{	  48,    6,  192,    3,    1,    8	},		//  6.0000MHz
+	{	  48,    4,  192,    3,    1,   12	},		//  4.0000MHz
+	{	  48,    3,  192,    3,    1,   16	},		//  3.0000MHz
+	{	  48,    2,  192,    3,    1,   24	},		//  2.0000MHz
+	{	  48,    1,  192,    3,    1,   48	},		//  1.0000MHz
+	{	  60,   30,  240,    4,    1,    2	},		// 30.0000MHz
+	{	  60,   20,  240,    4,    1,    3	},		// 20.0000MHz
+	{	  60,   15,  240,    4,    1,    4	},		// 15.0000MHz
+	{	  60,   12,  240,    4,    1,    5	},		// 12.0000MHz
+	{	  60,   10,  240,    4,    1,    6	},		// 10.0000MHz
+	{	  60,    6,  240,    4,    1,   10	},		//  6.0000MHz
+	{	  60,    5,  240,    4,    1,   12	},		//  5.0000MHz
+	{	  60,    4,  240,    4,    1,   15	},		//  4.0000MHz
+	{	  60,    3,  240,    4,    1,   20	},		//  3.0000MHz
+	{	  60,    2,  240,    4,    1,   30	},		//  2.0000MHz
+	{	  60,    1,  240,    4,    1,   60	},		//  1.0000MHz
+	{	  72,   24,  288,    5,    1,    3	},		// 24.0000MHz
+	{	  72,   18,  288,    5,    1,    4	},		// 18.0000MHz
+	{	  72,   12,  288,    5,    1,    6	},		// 12.0000MHz
+	{	  72,    9,  288,    5,    1,    8	},		//  9.0000MHz
+	{	  72,    8,  288,    5,    1,    9	},		//  8.0000MHz
+	{	  72,    6,  288,    5,    1,   12	},		//  6.0000MHz
+	{	  72,    4,  288,    5,    1,   18	},		//  4.0000MHz
+	{	  72,    3,  288,    5,    1,   24	},		//  3.0000MHz
+	{	  72,    2,  288,    5,    1,   36	},		//  2.0000MHz
+	{	  72,    1,  288,    5,    1,   72	},		//  1.0000MHz
+	{	  84,   28,  168,    6,    0,    3	},		// 28.0000MHz
+	{	  84,   21,  168,    6,    0,    4	},		// 21.0000MHz
+	{	  84,   14,  168,    6,    0,    6	},		// 14.0000MHz
+	{	  84,   12,  168,    6,    0,    7	},		// 12.0000MHz
+	{	  84,    7,  168,    6,    0,   12	},		//  7.0000MHz
+	{	  84,    6,  168,    6,    0,   14	},		//  6.0000MHz
+	{	  84,    4,  168,    6,    0,   21	},		//  4.0000MHz
+	{	  84,    3,  168,    6,    0,   28	},		//  3.0000MHz
+	{	  84,    2,  168,    6,    0,   42	},		//  2.0000MHz
+	{	  84,    1,  168,    6,    0,   84	},		//  1.0000MHz
+	{	  96,   24,  192,    7,    0,    4	},		// 24.0000MHz
+	{	  96,   16,  192,    7,    0,    6	},		// 16.0000MHz
+	{	  96,   12,  192,    7,    0,    8	},		// 12.0000MHz
+	{	  96,    8,  192,    7,    0,   12	},		//  8.0000MHz
+	{	  96,    6,  192,    7,    0,   16	},		//  6.0000MHz
+	{	  96,    4,  192,    7,    0,   24	},		//  4.0000MHz
+	{	  96,    3,  192,    7,    0,   32	},		//  3.0000MHz
+	{	  96,    2,  192,    7,    0,   48	},		//  2.0000MHz
+	{	  96,    1,  192,    7,    0,   96	},		//  1.0000MHz
+};
+static const uint16_t config_tab_ct = sizeof(config_tab) / sizeof(LPC_8XX_PLL_T);
+static uint16_t config_tab_idx = 0;
+/*****************************************************************************
+ * Public types/enumerations/variables
+ ****************************************************************************/
+/* System Clock Frequency (Core Clock) */
+uint32_t SystemCoreClock;
+
+/*****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+static void pll_config(const LPC_8XX_PLL_T* pll_cfg)
+{
+	Chip_SYSCTL_PowerUp(SYSCTL_SLPWAKE_IRC_PD);									/* turn on the IRC by clearing the power down bit */
+	Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_IRC);						/* select PLL input to be IRC */
+	Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_IRC);
+	Chip_FMC_SetFLASHAccess(FLASHTIM_30MHZ_CPU);								/* setup FLASH access to 2 clocks (up to 30MHz) */
+	Chip_SYSCTL_PowerDown(SYSCTL_SLPWAKE_SYSPLL_PD);							/* power down PLL to change the PLL divider ratio */
+	Chip_Clock_SetupSystemPLL(pll_cfg->msel, pll_cfg->psel);					/* configure the PLL */
+	Chip_SYSCTL_PowerUp(SYSCTL_SLPWAKE_SYSPLL_PD);								/* turn on the PLL by clearing the power down bit */
+	while (!Chip_Clock_IsSystemPLLLocked()) {}									/* wait for PLL to lock */
+	Chip_Clock_SetSysClockDiv(pll_cfg->divider);								/* load the divider */
+	Chip_Clock_SetMainClockSource(SYSCTL_MAINCLKSRC_PLLOUT);					/* enable the new Frequency */
+}
+
+/* Compute a WDT or LFO rate */
+static uint32_t Chip_Clock_GetWDTLFORate(uint32_t reg)
+{
+	uint32_t div;
+	CHIP_WDTLFO_OSC_T clk;
+
+	/* Get WDT oscillator settings */
+	clk = (CHIP_WDTLFO_OSC_T) ((reg >> 5) & 0xF);
+	div = reg & 0x1F;
+
+	/* Compute clock rate and divided by divde value */
+	return wdtOSCRate[clk] / ((div + 1) << 1);
+}
+
+/* Compute PLL frequency */
+static uint32_t Chip_Clock_GetPLLFreq(uint32_t PLLReg, uint32_t inputRate)
+{
+	uint32_t m_val = ((PLLReg & 0x1F) + 1);
+
+	return (inputRate * m_val);
+}
+
+/*****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+bool Chip_IRC_SetFreq(uint32_t main, uint32_t sys)
+{
+	uint16_t	freq_m = main/1000000;											/* main frequency in MHz */
+	uint16_t	freq_s = sys/1000000;											/* system frequency in MHz */
+	bool		found = false;													/* frequencies found */
+	uint32_t	i = 0;
+
+	if (freq_s > 30)															/* if system frequency is higher than 30MHz... */
+		return false;															/* ...don't attempt to set it */
+	if (freq_m > 96)															/* if main frequency is higher than 96MHz... */
+		return false;															/* ...don't attempt to set it */
+	
+	for (i=0; i<config_tab_ct; i++) {											/* loop through table */
+		if ((freq_m == config_tab[i].freq_main) && (freq_s == config_tab[i].freq_sys)) {	/* attempt to find a match */
+			config_tab_idx = i;													/* save the data for later */
+			found = true;														/* set state to found */
+			break;																/* go config the PLL */
+		}
+	}
+	if (found == true) {														/* if a match has been found */
+		pll_config(&config_tab[config_tab_idx]);								/* configure the PLL */
+	}
+
+	return found;																/* return operation status */
+}
+
+// Open this API only if ROM headers are included
+#ifdef LPC_PWRD_API
+void Chip_IRC_SetFreq_ROM(uint32_t sys)
+{
+	uint32_t cmd[4], resp[2];
+
+	Chip_SYSCTL_PowerUp(SYSCTL_SLPWAKE_IRC_PD);									/* Turn on the IRC by clearing the power down bit */
+	Chip_Clock_SetSystemPLLSource(SYSCTL_PLLCLKSRC_IRC);						/* Select PLL input to be IRC */
+	Chip_FMC_SetFLASHAccess(FLASHTIM_30MHZ_CPU);								/* Setup FLASH access to 2 clocks (up to 30MHz) */
+	
+	cmd[0] = Chip_Clock_GetIntOscRate() / 1000;									/* in KHz */
+	cmd[1] = sys / 1000;														/* system clock rate in kHz */
+	cmd[2] = CPU_FREQ_EQU;
+	cmd[3] = sys / 10000;														/* Timeout. See UM10601, section 23.4.1.3 for details */
+	LPC_PWRD_API->set_pll(cmd, resp);											/* Attempt to set the PLL */
+
+	while (resp[0] != PLL_CMD_SUCCESS) {}										/* Dead loop on fail */
+}
+#else
+
+#endif
+
+/* Update system core clock rate, should be called if the system has
+   a clock rate change */
+void SystemCoreClockUpdate(void)
+{
+	/* CPU core speed */
+	SystemCoreClock = Chip_Clock_GetSystemClockRate();
+}
+/* Set System PLL clock source */
+void Chip_Clock_SetSystemPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src)
+{
+	LPC_SYSCTL->SYSPLLCLKSEL  = (uint32_t) src;
+    
+    /* sequnce a 0 followed by 1 to update PLL source selection */
+	LPC_SYSCTL->SYSPLLCLKUEN  = 0;  
+	LPC_SYSCTL->SYSPLLCLKUEN  = 1;  
+}
+
+/* Bypass System Oscillator and set oscillator frequency range */
+void Chip_Clock_SetPLLBypass(bool bypass, bool highfr)
+{
+	uint32_t ctrl = 0;
+
+	if (bypass) {
+		ctrl |= (1 << 0);
+	}
+	if (highfr) {
+		ctrl |= (1 << 1);
+	}
+
+	LPC_SYSCTL->SYSOSCCTRL = ctrl;
+}
+
+/* Set main system clock source */
+void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src)
+{
+	LPC_SYSCTL->MAINCLKSEL  = (uint32_t) src;
+    
+    /* sequnce a 0 followed by 1 to update MAINCLK source selection */
+	LPC_SYSCTL->MAINCLKUEN  = 0;
+	LPC_SYSCTL->MAINCLKUEN  = 1;
+}
+
+/* Set CLKOUT clock source and divider */
+void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div)
+{
+	LPC_SYSCTL->CLKOUTSEL = (uint32_t) src;
+    
+    /* sequnce a 0 followed by 1 to update CLKOUT source selection */
+	LPC_SYSCTL->CLKOUTUEN = 0;
+	LPC_SYSCTL->CLKOUTUEN = 1;
+	LPC_SYSCTL->CLKOUTDIV = div;
+}
+
+/* Return estimated watchdog oscillator rate */
+uint32_t Chip_Clock_GetWDTOSCRate(void)
+{
+	return Chip_Clock_GetWDTLFORate(LPC_SYSCTL->WDTOSCCTRL & ~SYSCTL_WDTOSCCTRL_RESERVED);
+}
+
+/* Return System PLL input clock rate */
+uint32_t Chip_Clock_GetSystemPLLInClockRate(void)
+{
+	uint32_t clkRate;
+
+	switch ((CHIP_SYSCTL_PLLCLKSRC_T) (LPC_SYSCTL->SYSPLLCLKSEL & 0x3)) {
+	case SYSCTL_PLLCLKSRC_IRC:
+		clkRate = Chip_Clock_GetIntOscRate();
+		break;
+
+	case SYSCTL_PLLCLKSRC_SYSOSC:
+		clkRate = Chip_Clock_GetMainOscRate();
+		break;
+
+	case SYSCTL_PLLCLKSRC_EXT_CLKIN:
+		clkRate = Chip_Clock_GetExtClockInRate();
+		break;
+
+	default:
+		clkRate = 0;
+	}
+
+	return clkRate;
+}
+
+/* Return System PLL output clock rate */
+uint32_t Chip_Clock_GetSystemPLLOutClockRate(void)
+{
+	return Chip_Clock_GetPLLFreq((LPC_SYSCTL->SYSPLLCTRL & ~SYSCTL_SYSPLLCTRL_RESERVED),
+								 Chip_Clock_GetSystemPLLInClockRate());
+}
+
+/* Return main clock rate */
+uint32_t Chip_Clock_GetMainClockRate(void)
+{
+	uint32_t clkRate = 0;
+
+	switch ((CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL & 0x3)) {
+	case SYSCTL_MAINCLKSRC_IRC:
+		clkRate = Chip_Clock_GetIntOscRate();
+		break;
+
+	case SYSCTL_MAINCLKSRC_PLLIN:
+		clkRate = Chip_Clock_GetSystemPLLInClockRate();
+		break;
+
+	case SYSCTL_MAINCLKSRC_WDTOSC:
+		clkRate = Chip_Clock_GetWDTOSCRate();
+		break;
+
+	case SYSCTL_MAINCLKSRC_PLLOUT:
+		clkRate = Chip_Clock_GetSystemPLLOutClockRate();
+		break;
+	}
+
+	return clkRate;
+}
+
+/* Return system clock rate */
+uint32_t Chip_Clock_GetSystemClockRate(void)
+{
+	/* No point in checking for divide by 0 */
+	return Chip_Clock_GetMainClockRate() / (LPC_SYSCTL->SYSAHBCLKDIV & ~SYSCTL_SYSAHBCLKDIV_RESERVED);
+}
+
+/* Get USART 0/1/2 UART base rate */
+uint32_t Chip_Clock_GetUSARTNBaseClockRate(void)
+{
+	uint64_t inclk;
+	uint32_t div;
+
+	div = (uint32_t) Chip_Clock_GetUARTClockDiv();
+	if (div == 0) {
+		/* Divider is 0 so UART clock is disabled */
+		inclk = 0;
+	}
+	else {
+		uint32_t mult, divf;
+
+		/* Input clock into FRG block is the divided main system clock */
+		inclk = (uint64_t) (Chip_Clock_GetMainClockRate() / div);
+
+		divf = Chip_SYSCTL_GetUSARTFRGDivider();
+		if (divf == 0xFF) {
+			/* Fractional part is enabled, get multiplier */
+			mult = (uint32_t) Chip_SYSCTL_GetUSARTFRGMultiplier();
+
+			/* Get fractional error */
+			inclk = (inclk * 256) / (uint64_t) (256 + mult);
+		}
+	}
+
+	return (uint32_t) inclk;
+}
+
+/* Set USART 0/1/2 UART base rate */
+uint32_t Chip_Clock_SetUSARTNBaseClockRate(uint32_t rate, bool fEnable)
+{
+	uint32_t div, inclk;
+
+	/* Input clock into FRG block is the main system clock */
+	inclk = Chip_Clock_GetMainClockRate();
+
+	/* Get integer divider for coarse rate */
+	div = inclk / rate;
+	if (div == 0) {
+		div = 1;
+	}
+
+	/* Approximated rate with only integer divider */
+	Chip_Clock_SetUARTClockDiv((uint8_t) div);
+
+	if (fEnable) {
+		uint32_t uart_fra_multiplier;
+
+		/* Reset FRG */
+		Chip_SYSCTL_PeriphReset(RESET_UARTFBRG);
+
+		/* Enable fractional divider */
+		Chip_SYSCTL_SetUSARTFRGDivider(0xFF);
+
+		/* Compute the fractional divisor (the lower byte is the
+		   fractional portion) */
+		uart_fra_multiplier = ((inclk / div) * 256) / rate;
+
+		/* ...just the fractional portion (the lower byte) */
+		Chip_SYSCTL_SetUSARTFRGMultiplier((uint8_t) uart_fra_multiplier);
+	}
+	else {
+		/* Disable fractional generator and use integer divider only */
+		Chip_SYSCTL_SetUSARTFRGDivider(0);
+	}
+
+	return Chip_Clock_GetUSARTNBaseClockRate();
+}
+
+/* Get the IOCONCLKDIV clock rate */
+uint32_t Chip_Clock_GetIOCONCLKDIVClockRate(CHIP_PIN_CLKDIV_T reg)
+{
+	uint32_t div = LPC_SYSCTL->IOCONCLKDIV[reg] & ~SYSCTL_IOCONCLKDIV_RESERVED;
+	uint32_t main_clk = Chip_Clock_GetMainClockRate();
+	
+	return (div == 0) ? 0 : (main_clk / div);
+}
+
+void Chip_Clock_SetIOCONCLKDIV(CHIP_PIN_CLKDIV_T reg, uint8_t div)
+{
+	int t_reg = IOCONCLK_MAX-reg;
+	LPC_SYSCTL->IOCONCLKDIV[t_reg] = div;
+}

bsp/lpc824/SConscript

+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/lpc824/applications/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')