add t-head smart-evb bsp, and risc-v cpu e906

bsp/thead-smart/.config

+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=512
+# CONFIG_RT_USING_TIMER_SOFT is not set
+# CONFIG_RT_DEBUG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x40003
+
+#
+# RT-Thread CPU arch and features
+#
+# CONFIG_ARCH_CSKY is not set
+
+#
+# risc-v arch
+#
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_RISCV_32=y
+# CONFIG_ARCH_RISCV_64 is not set
+CONFIG_ARCH_RISCV_FPU=y
+CONFIG_ARCH_RISCV_FPU_S=y
+# CONFIG_ARCH_RISCV_FPU_D is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=1
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=2048
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+CONFIG_FINSH_USING_MSH_ONLY=y
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+# CONFIG_RT_USING_LIBC is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_LIBC_USING_TIME is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_NUCLEI_SDK is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+CONFIG_SOC_THEAD_SMART=y
+CONFIG_RT_USING_UART1=y

bsp/thead-smart/Kconfig

+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+# you can change the RTT_ROOT default "../.." to your rtthread_root,
+# example : default "F:/git_repositories/rt-thread"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_THEAD_SMART
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+if RT_USING_SERIAL
+
+    config RT_USING_UART1
+        bool "Using uart1"
+        default y 
+
+endif

bsp/thead-smart/README.md

+# T-HEAD SMART-EVB Introduction
+SMART-EVB is a development board provided by T-HEAD, based on FPGA to provide implementation, integrating T-HEAD's RISC-V CPU (eg. E902/E906/C906) and C-SKY CPU (eg. E805/E804/E803/E802 ), integrates basic peripheral resources such as GPIO/TIMER/UART/RAM.
+
+##The main resources on board are as follows:
+1. SMART-EVB for E906/E906F/E906FD
+| res | description |
+| -- | -- |
+|ISA | RISCV |
+|CPU | E906  |
+|FREQ| 20MHz |
+|SRAM| 768KB |
+
+
+2. SMART-EVB for E804/E804F/E804D
+| res | description |
+| -- | -- |
+|ISA | C-SKY |
+|CPU | E804  |
+|FREQ| 20MHz |
+|SRAM| 768KB |
+
+
+# Compile T-HEAD BSP
+SMART-EVB BSP supports GCC compiler, the version information is:
+1. SMART-EVB for E906/E906F/E906FD
+| IDE/Compiler| version|
+| - | - |
+| GCC | gcc version 8.4.0 (C-SKY RISCV Tools V1.9.6 B20200616) |
+
+# run smart-evb bsp
+1. Connect JTAG
+2. Connect the serial port
+3. riscv64-unknown-elf-gdb rtthread-e906f.elf
+
+run log as follows:
+```
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.3 build Sep  2 2020
+ 2006 - 2020 Copyright by rt-thread team
+msh >
+```
+
+
+

bsp/thead-smart/SConscript

+# for module compiling
+import os
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/thead-smart/SConstruct

+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-' + rtconfig.CPU + '.' + rtconfig.TARGET_EXT
+
+env  = Environment(tools = ['mingw'],
+AS   = rtconfig.AS,   ASFLAGS   = rtconfig.AFLAGS,
+CC   = rtconfig.CC,   CCFLAGS   = rtconfig.CFLAGS,
+CXX  = rtconfig.CXX,  CXXFLAGS  = rtconfig.CXXFLAGS,
+AR   = rtconfig.AR,   ARFLAGS   = '-rc',
+LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+# add --start-group and --end-group for GNU GCC
+env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group'
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/thead-smart/applications/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = GetCurrentDir()
+
+CCFLAGS = ' -c -ffunction-sections'
+
+group   = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CCFLAGS=CCFLAGS)
+
+Return('group')

bsp/thead-smart/applications/main.c

+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      first version
+ */
+
+#include <rtthread.h>
+
+int main(void)
+{
+    
+    return 0;
+}
+
+/*@}*/

bsp/thead-smart/drivers/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+
+# add the general drivers.
+src     = Glob("*.c") + Glob("*.cpp") + Glob("*.S")
+
+CPPPATH = [cwd]
+group   = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/thead-smart/drivers/board.c

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      add T-HEAD header file csi_core.h
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "csi_core.h"
+#include "drv_usart.h"
+
+extern int __bss_end__;
+#define SYS_HEAP_BEGIN    (&__bss_end__)
+
+#include "core_rv32.h"
+
+
+extern usart_handle_t console_handle;
+extern void ioreuse_initial(void);
+
+
+/**
+ * This function will initial smartl-evb(e906) board.
+ */
+void rt_hw_board_init(void)
+{
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+    /* initialize hardware usart */
+    rt_hw_usart_init();
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *)SYS_HEAP_BEGIN, (void *)E906FD_IRAM_END);
+#endif
+}
+
+/*@}*/

bsp/thead-smart/drivers/board.h

+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      add E906 ram size
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#define APB_DEFAULT_FREQ         20000000   /* Hz */
+#define E906FD_IRAM_SIZE         128
+#define E906FD_IRAM_END          (0x20000000 + E906FD_IRAM_SIZE * 1024)
+
+#endif /* __BOARD_H__ */

bsp/thead-smart/drivers/board_uart.c

+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      first implementation
+ */
+
+#include <rtthread.h>
+
+#ifdef RT_USING_CONSOLE
+
+#include <rthw.h>
+#include <rtdevice.h>
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdbool.h>
+
+#include "board.h"
+#include "soc.h"
+#include "ck_usart.h"
+#include "drv_usart.h"
+#include "pin_name.h"
+
+
+
+__attribute__((isr)) void ck_usart0_irqhandler(void);
+
+struct
+{
+    uint32_t base;
+    uint32_t irq;
+    void *handler;
+} 
+const sg_usart_config[CONFIG_USART_NUM] =
+{
+    {CSKY_UART_BASE, UART_IRQn, ck_usart0_irqhandler},
+};
+
+
+int32_t target_usart_init(int32_t idx, uint32_t *base, uint32_t *irq, void **handler)
+{
+    if (idx >= CONFIG_USART_NUM) 
+    {
+        return -1;
+    }
+
+    if (base != NULL) 
+    {
+        *base = sg_usart_config[idx].base;
+    }
+
+    if (irq != NULL) 
+    {
+        *irq = sg_usart_config[idx].irq;
+    }
+
+    if (handler != NULL) 
+    {
+        *handler = sg_usart_config[idx].handler;
+    }
+
+    return idx;
+}
+
+
+#ifdef RT_USING_UART1
+#define UART_TXD1     PA10_TXD1_PWM1_XX_SIROUT1
+#define UART_RXD1     PA11_RXD1_PWM2_XX_SIRIN1
+
+static  usart_handle_t uart1_handle;
+static struct rt_serial_device  serial1;
+
+__attribute__((isr)) void ck_usart0_irqhandler(void)
+{
+    rt_hw_serial_isr(&serial1,RT_SERIAL_EVENT_RX_IND);
+}
+#endif
+
+/*
+ * UART interface
+ */
+static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    int ret;
+    usart_handle_t uart;
+
+    uint32_t bauds;
+    usart_mode_e mode;
+    usart_parity_e parity;
+    usart_stop_bits_e stopbits;
+    usart_data_bits_e databits;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (usart_handle_t)serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+
+    /* set baudrate parity...*/
+    bauds = cfg->baud_rate;
+    mode = USART_MODE_ASYNCHRONOUS;
+
+    if (cfg->parity == PARITY_EVEN)
+        parity = USART_PARITY_EVEN;
+    else if (cfg->parity == PARITY_ODD)
+        parity = USART_PARITY_ODD;
+    else
+        parity = USART_PARITY_NONE;
+
+    stopbits = USART_STOP_BITS_1 ;
+    databits = USART_DATA_BITS_8;
+
+    ret = csi_usart_config(uart, bauds, USART_MODE_ASYNCHRONOUS, parity, stopbits, databits);
+
+    if (ret < 0)
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    usart_handle_t uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (usart_handle_t)serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* Disable the UART Interrupt */
+        ck_usart_clr_int_flag(uart,IER_RDA_INT_ENABLE);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* Enable the UART Interrupt */
+        ck_usart_set_int_flag(uart,IER_RDA_INT_ENABLE);
+        break;
+    }
+
+    return (RT_EOK);
+}
+
+static int uart_putc(struct rt_serial_device *serial, char c)
+{
+    usart_handle_t uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (usart_handle_t)serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+    csi_usart_putchar(uart,c);
+
+    return (1);
+}
+
+static int uart_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    usart_handle_t uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (usart_handle_t)serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+
+
+    ch = csi_uart_getchar(uart);
+
+    return ch;
+}
+
+const struct rt_uart_ops _uart_ops =
+{
+    uart_configure,
+    uart_control,
+    uart_putc,
+    uart_getc,
+};
+
+
+int rt_hw_usart_init(void)
+{
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+#ifdef RT_USING_UART1
+    serial1.ops                 = & _uart_ops;
+    serial1.config              = config;
+    serial1.config.bufsz        = 2048;
+    serial1.config.baud_rate    = 115200;
+
+    uart1_handle = csi_usart_initialize(0, NULL);
+
+    rt_hw_serial_register(&serial1,
+                          "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart1_handle);
+#endif
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_usart_init);
+#endif

bsp/thead-smart/drivers/ck_irq.c

+
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      CSI Source File for IRQ Driver
+ */
+
+#include <stdint.h>
+#include <soc.h>
+#include <csi_core.h>
+#include <csi_config.h>
+
+extern void Default_Handler(void);
+extern void (*g_irqvector[])(void);
+extern void (*g_nmivector)(void);
+
+/**
+  \brief       enable irq.
+  \param[in]   irq_num Number of IRQ.
+  \return      None.
+*/
+void drv_irq_enable(uint32_t irq_num)
+{
+    if (NMI_EXPn != irq_num) 
+    {
+    #ifdef CONFIG_SYSTEM_SECURE
+        csi_vic_enable_sirq(irq_num);
+    #else
+        csi_vic_enable_irq(irq_num);
+    #endif
+    }
+}
+
+/**
+  \brief       disable irq.
+  \param[in]   irq_num Number of IRQ.
+  \return      None.
+*/
+void drv_irq_disable(uint32_t irq_num)
+{
+    if (NMI_EXPn != irq_num) 
+    {
+    #ifdef CONFIG_SYSTEM_SECURE
+        csi_vic_disable_sirq(irq_num);
+    #else
+        csi_vic_disable_irq(irq_num);
+    #endif
+    }
+}
+
+/**
+  \brief       register irq handler.
+  \param[in]   irq_num Number of IRQ.
+  \param[in]   irq_handler IRQ Handler.
+  \return      None.
+*/
+void drv_irq_register(uint32_t irq_num, void *irq_handler)
+{
+    if (NMI_EXPn != irq_num) 
+    {
+        g_irqvector[irq_num] = irq_handler;
+    } 
+    else 
+    {
+        g_nmivector = irq_handler;
+    }
+}
+
+/**
+  \brief       unregister irq handler.
+  \param[in]   irq_num Number of IRQ.
+  \return      None.
+*/
+void drv_irq_unregister(uint32_t irq_num)
+{
+    if (NMI_EXPn != irq_num) 
+    {
+        g_irqvector[irq_num] = (void *)Default_Handler;
+    } 
+    else 
+    {
+        g_nmivector = (void *)Default_Handler;
+    }
+}

bsp/thead-smart/drivers/ck_usart.h

+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      header file for usart driver
+ */
+
+#ifndef __CK_USART_H
+#define __CK_USART_H
+
+#include <stdio.h>
+#include "errno.h"
+#include "soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BAUDRATE_DEFAULT	19200
+#define UART_BUSY_TIMEOUT       1000000
+#define UART_RECEIVE_TIMEOUT    1000
+#define UART_TRANSMIT_TIMEOUT   1000
+#define UART_MAX_FIFO	        0x10
+/* UART register bit definitions */
+
+#define USR_UART_BUSY           0x01
+#define USR_UART_TFE            0x04
+#define USR_UART_RFNE           0x08
+#define LSR_DATA_READY          0x01
+#define LSR_THR_EMPTY           0x20
+#define IER_RDA_INT_ENABLE      0x01
+#define IER_THRE_INT_ENABLE     0x02
+#define IIR_RECV_LINE_ENABLE    0x04
+#define IIR_NO_ISQ_PEND         0x01
+
+#define LCR_SET_DLAB            0x80   /* enable r/w DLR to set the baud rate */
+#define LCR_PARITY_ENABLE       0x08   /* parity enabled */
+#define LCR_PARITY_EVEN         0x10   /* Even parity enabled */
+#define LCR_PARITY_ODD          0xef   /* Odd parity enabled */
+#define LCR_WORD_SIZE_5         0xfc   /* the data length is 5 bits */
+#define LCR_WORD_SIZE_6         0x01   /* the data length is 6 bits */
+#define LCR_WORD_SIZE_7         0x02   /* the data length is 7 bits */
+#define LCR_WORD_SIZE_8         0x03   /* the data length is 8 bits */
+#define LCR_STOP_BIT1           0xfb   /* 1 stop bit */
+#define LCR_STOP_BIT2           0x04   /* 1.5 stop bit */
+
+#define DW_LSR_PFE              0x80
+#define DW_LSR_TEMT             0x40
+#define DW_LSR_THRE             0x40
+#define DW_LSR_BI               0x10
+#define DW_LSR_FE               0x08
+#define DW_LSR_PE               0x04
+#define DW_LSR_OE               0x02
+#define DW_LSR_DR               0x01
+#define DW_LSR_TRANS_EMPTY      0x20
+
+#define DW_IIR_THR_EMPTY        0x02    /* threshold empty */
+#define DW_IIR_RECV_DATA        0x04    /* received data available */
+#define DW_IIR_RECV_LINE        0x06    /* receiver line status */
+#define DW_IIR_CHAR_TIMEOUT     0x0c    /* character timeout */
+
+typedef struct
+{
+    union 
+    {
+        __IM uint32_t RBR;           /* Offset: 0x000 (R/ )  Receive buffer register */
+        __OM uint32_t THR;           /* Offset: 0x000 ( /W)  Transmission hold register */
+        __IOM uint32_t DLL;          /* Offset: 0x000 (R/W)  Clock frequency division low section register */
+    };
+    union 
+    {
+        __IOM uint32_t DLH;          /* Offset: 0x004 (R/W)  Clock frequency division high section register */
+        __IOM uint32_t IER;          /* Offset: 0x004 (R/W)  Interrupt enable register */
+    };
+    __IM uint32_t IIR;             /* Offset: 0x008 (R/ )  Interrupt indicia register */
+    __IOM uint32_t LCR;            /* Offset: 0x00C (R/W)  Transmission control register */
+    uint32_t RESERVED0;
+    __IM uint32_t LSR;             /* Offset: 0x014 (R/ )  Transmission state register */
+    __IM uint32_t MSR;             /* Offset: 0x018 (R/ )  Modem state register */
+    uint32_t RESERVED1[24];
+    __IM uint32_t USR;             /* Offset: 0x07c (R/ )  UART state register */
+} ck_usart_reg_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CK_USART_H */
+

bsp/thead-smart/drivers/csi_config.h

+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      config file
+ */
+
+/* csi_config.h -- Autogenerated! Do not edit. */
+
+#ifndef __CSI_CONFIG_H
+#define __CSI_CONFIG_H
+
+#define CONFIG_ARCH_RV32 1
+#define CONFIG_CPU_E906FD 1
+#define CONFIG_RV32_CORETIM 1
+#define CONFIG_CHIP_SMARTL_RV32 1
+#define CONFIG_BOARD_SMARTL_E906_EVB 1
+#define CONFIG_BOARD_NAME_STR "smartl_e906_evb"
+#define CONFIG_SUPPORT_TSPEND 1
+#define CONFIG_ARCH_INTERRUPTSTACK 4096
+#define CONFIG_NEWLIB_WRAP 1
+#define CONFIG_USER_DEFINED_LD_DIR_STR ""
+
+#define CONFIG_KERNEL_RTTHREAD 1
+#endif /* __CONFIG_H */
+

bsp/thead-smart/drivers/csi_core.h

+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      CSI Core Layer Header File
+ */
+
+
+#ifndef _CORE_H_
+#define _CORE_H_
+
+#include <stdint.h>
+
+#if defined(__CK801__) || defined(__E801__)
+#include <core_801.h>
+#elif defined(__CK802__) || defined(__E802__) || defined(__E802T__) || defined(__S802__) || defined(__S802T__)
+#include <core_802.h>
+#elif defined(__CK804__) || defined(__E804D__) || defined(__E804DT__) || defined(__E804F__)  || defined(__E804FT__) || defined (__E804DF__) || defined(__E804DFT__)
+#include <core_804.h>
+#elif defined(__CK803__) || defined(__E803__) || defined(__E803T__) || defined(__S803__) || defined(__S803T__)
+#include <core_803.h>
+#elif defined(__CK805__) || defined(__I805__) || defined(__I805F__)
+#include <core_805.h>
+#elif defined(__CK610__)
+#include <core_ck610.h>
+#elif defined(__CK810__) || defined(__C810__) || defined(__C810T__) || defined(__C810V__) || defined(__C810VT__)
+#include <core_810.h>
+#elif defined(__CK807__) || defined(__C807__) || defined(__C807F__) || defined(__C807FV__) || defined(__R807__)
+#include <core_807.h>
+#elif defined(__riscv) && defined(CONFIG_CSKY_CORETIM)
+#include <core_rv32_old.h>
+#elif defined(__riscv)
+#include <core_rv32.h>
+#endif
+
+#ifdef __riscv
+#include <csi_rv32_gcc.h>
+#else
+#include <csi_gcc.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CORE_H_ */

bsp/thead-smart/drivers/drv_common.h

+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      Header File for Common Driver
+ */
+
+#ifndef _DRV_COMMON_H_
+#define _DRV_COMMON_H_
+
+#include <stdint.h>
+#include <drv_errno.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/// \details driver handle
+typedef void *drv_handle_t;
+
+#ifndef CONFIG_PARAM_NOT_CHECK
+#define HANDLE_PARAM_CHK(para, err)                                                                \
+    do {                                                                                           \
+        if ((int32_t)para == (int32_t)NULL) {                                                      \
+            return (err);                                                                          \
+        }                                                                                          \
+    } while (0)
+
+#define HANDLE_PARAM_CHK_NORETVAL(para, err)                                                          \
+    do {                                                                                           \
+        if ((int32_t)para == (int32_t)NULL) {                                                      \
+            return;                                                                                \
+        }                                                                                          \
+    } while (0)
+#else
+#define HANDLE_PARAM_CHK(para, err)
+#define HANDLE_PARAM_CHK_NORETVAL(para, err)
+#endif
+
+/**
+\brief General power states
+*/
+typedef enum  
+{
+    DRV_POWER_OFF,                        ///< Power off: no operation possible
+    DRV_POWER_LOW,                        ///< Low Power mode: retain state, detect and signal wake-up events
+    DRV_POWER_FULL,                       ///< Power on: full operation at maximum performance
+    DRV_POWER_SUSPEND,                    ///< Power suspend: power saving operation
+} csi_power_stat_e;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DRV_COMMON_H */
+

bsp/thead-smart/drivers/drv_errno.h

+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      header file for error num
+ */
+
+
+#ifndef _DRV_ERRNO_H_
+#define _DRV_ERRNO_H_
+
+#include <errno.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ERRNO_DRV_START 0X80
+
+/* driver General error codes */
+typedef enum
+{
+    DRV_ERROR = ERRNO_DRV_START,   ///< Unspecified error
+    DRV_ERROR_BUSY,                ///< Driver is busy
+    DRV_ERROR_TIMEOUT,             ///< Timeout occurred
+    DRV_ERROR_UNSUPPORTED,         ///< Operation not supported
+    DRV_ERROR_PARAMETER,           ///< Parameter error
+    DRV_ERROR_SPECIFIC             ///< Start of driver specific errors
+} drv_err_e;
+
+
+/** Get error type */
+#define GET_ERROR_TYPE(errno) \
+    (error & 0xFF000000 >> 24)
+/** Get error module */
+#define GET_ERROR_MODULE(error) \
+    (error & 0x00FF0000 >> 16)
+/** Get error API */
+#define GET_ERROR_API(error) \
+    (error & 0x0000FF00 >> 8)
+/** Get errno */
+#define GET_ERROR_NUM(error) \
+    (error & 0x000000FF)
+
+#ifndef CSI_DRV_ERRNO_BASE
+#define CSI_DRV_ERRNO_BASE                  0x81000000
+#endif
+
+/** driver module id definition*/
+#define CSI_DRV_ERRNO_GPIO_BASE             0x81010000
+#define CSI_DRV_ERRNO_USART_BASE            0x81020000
+#define CSI_DRV_ERRNO_SPI_BASE              0x81030000
+#define CSI_DRV_ERRNO_IIC_BASE              0x81040000
+#define CSI_DRV_ERRNO_PWM_BASE              0x81050000
+#define CSI_DRV_ERRNO_RTC_BASE              0x81060000
+#define CSI_DRV_ERRNO_TIMER_BASE            0x81070000
+#define CSI_DRV_ERRNO_WDT_BASE              0x81080000
+#define CSI_DRV_ERRNO_AES_BASE              0x81090000
+#define CSI_DRV_ERRNO_CRC_BASE              0x810A0000
+#define CSI_DRV_ERRNO_RSA_BASE              0x810B0000
+#define CSI_DRV_ERRNO_SHA_BASE              0x810C0000
+#define CSI_DRV_ERRNO_TRNG_BASE             0x810D0000
+#define CSI_DRV_ERRNO_EFLASH_BASE           0x810E0000
+#define CSI_DRV_ERRNO_DMA_BASE              0x810F0000
+#define CSI_DRV_ERRNO_NORFLASH_BASE         0x81100000
+#define CSI_DRV_ERRNO_INTC_BASE             0x81110000
+#define CSI_DRV_ERRNO_SPU_BASE              0x81120000
+#define CSI_DRV_ERRNO_ADC_BASE              0x81130000
+#define CSI_DRV_ERRNO_PMU_BASE              0x81140000
+#define CSI_DRV_ERRNO_BMU_BASE              0x81150000
+#define CSI_DRV_ERRNO_ETB_BASE              0x81160000
+#define CSI_DRV_ERRNO_I2S_BASE              0x81170000
+#define CSI_DRV_ERRNO_USI_BASE              0x81180000
+#define CSI_DRV_ERRNO_SPIFLASH_BASE         0x81190000
+#define CSI_DRV_ERRNO_ACMP_BASE             0x811A0000
+#define CSI_DRV_ERRNO_MAILBOX_BASE          0x811B0000
+#define CSI_DRV_ERRNO_EFUSEC_BASE           0x811C0000
+#define CSI_DRV_ERRNO_CODEC_BASE            0x811D0000
+#define CSI_DRV_ERRNO_DPU_BASE              0x811E0000
+#define CSI_DRV_ERRNO_VPU_BASE              0x811F0000
+#define CSI_DRV_ERRNO_CAMERA_BASE           0x81200000
+#define CSI_DRV_ERRNO_MIPI_CSI_BASE         0x81210000
+#define CSI_DRV_ERRNO_MIPI_CSI_READER_BASE  0x81220000
+#define CSI_DRV_ERRNO_GMAC_BASE             0x81230000
+#define CSI_DRV_ERRNO_ETHPHY_BASE           0x81240000
+#define CSI_DRV_ERRNO_QW_EFUSE_BASE         0x81250000
+#define CSI_DRV_ERRNO_RESET_BASE            0x81260000
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CSI_DRV_ERRNO_H */

bsp/thead-smart/drivers/drv_gpio.h

+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      header file for gpio driver
+ */
+
+#ifndef _CSI_GPIO_H_
+#define _CSI_GPIO_H_
+
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <drv_common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/// definition for gpio pin handle.
+typedef void *gpio_pin_handle_t;
+
+/****** GPIO specific error codes *****/
+typedef enum
+{
+    GPIO_ERROR_MODE  = (DRV_ERROR_SPECIFIC + 1),      ///< Specified Mode not supported
+    GPIO_ERROR_DIRECTION,                        ///< Specified direction not supported
+    GPIO_ERROR_IRQ_MODE,                         ///< Specified irq mode not supported
+} gpio_error_e;
+
+/*----- GPIO Control Codes: Mode -----*/
+typedef enum
+{
+    GPIO_MODE_PULLNONE         = 0,    ///< pull none for input
+    GPIO_MODE_PULLUP,                  ///< pull up for input
+    GPIO_MODE_PULLDOWN,                ///< pull down for input
+    GPIO_MODE_OPEN_DRAIN,              ///< open drain mode for output
+    GPIO_MODE_PUSH_PULL,               ///< push-pull mode for output
+} gpio_mode_e;
+
+/*----- GPIO Control Codes: Mode Parameters: Data Bits -----*/
+typedef enum
+{
+    GPIO_DIRECTION_INPUT             = 0,    ///< gpio as input
+    GPIO_DIRECTION_OUTPUT,                   ///< gpio as output
+} gpio_direction_e;
+
+/*----- GPIO Control Codes: Mode Parameters: Parity -----*/
+typedef enum
+{
+    GPIO_IRQ_MODE_RISING_EDGE     = 0,       ///< interrupt mode for rising edge
+    GPIO_IRQ_MODE_FALLING_EDGE,              ///< interrupt mode for falling edge
+    GPIO_IRQ_MODE_DOUBLE_EDGE,               ///< interrupt mode for double edge
+    GPIO_IRQ_MODE_LOW_LEVEL,                 ///< interrupt mode for low level
+    GPIO_IRQ_MODE_HIGH_LEVEL,                ///< interrupt mode for high level
+} gpio_irq_mode_e;
+
+typedef void (*gpio_event_cb_t)(int32_t idx);   ///< gpio Event call back.
+
+/**
+  \brief       Initialize GPIO handle.
+  \param[in]   gpio_pin    gpio pin idx.
+  \param[in]   cb_event  event callback function \ref gpio_event_cb_t
+  \return      gpio_pin_handle
+*/
+gpio_pin_handle_t csi_gpio_pin_initialize(int32_t gpio_pin, gpio_event_cb_t cb_event);
+
+/**
+  \brief       De-initialize GPIO pin handle.stops operation and releases the software resources used by the handle.
+  \param[in]   handle    gpio pin handle to operate.
+  \return      error code
+*/
+int32_t csi_gpio_pin_uninitialize(gpio_pin_handle_t handle);
+
+/**
+  \brief       control gpio power.
+  \param[in]   handle  gpio handle to operate.
+  \param[in]   state   power state.\ref csi_power_stat_e.
+  \return      error code
+*/
+int32_t csi_gpio_power_control(gpio_pin_handle_t handle, csi_power_stat_e state);
+
+/**
+  \brief       config pin mode
+  \param[in]   pin       gpio pin handle to operate.
+  \param[in]   mode      \ref gpio_mode_e
+  \return      error code
+*/
+int32_t csi_gpio_pin_config_mode(gpio_pin_handle_t handle,
+                                 gpio_mode_e mode);
+
+/**
+  \brief       config pin direction
+  \param[in]   pin       gpio pin handle to operate.
+  \param[in]   dir       \ref gpio_direction_e
+  \return      error code
+*/
+int32_t csi_gpio_pin_config_direction(gpio_pin_handle_t handle,
+                                      gpio_direction_e dir);
+
+/**
+  \brief       config pin
+  \param[in]   pin       gpio pin handle to operate.
+  \param[in]   mode      \ref gpio_mode_e
+  \param[in]   dir       \ref gpio_direction_e
+  \return      error code
+*/
+int32_t csi_gpio_pin_config(gpio_pin_handle_t handle,
+                            gpio_mode_e mode,
+                            gpio_direction_e dir);
+
+/**
+  \brief       Set one or zero to the selected GPIO pin.
+  \param[in]   pin       gpio pin handle to operate.
+  \param[in]   value     value to be set
+  \return      error code
+*/
+int32_t csi_gpio_pin_write(gpio_pin_handle_t handle, bool value);
+
+/**
+  \brief       Get the value of  selected GPIO pin.
+  \param[in]   pin       gpio pin handle to operate.
+  \param[out]  value     buffer to store the pin value
+  \return      error code
+*/
+int32_t csi_gpio_pin_read(gpio_pin_handle_t handle, bool *value);
+
+/**
+  \brief       set GPIO interrupt mode.
+  \param[in]   pin       gpio pin handle to operate.
+  \param[in]   mode      irq mode to be set
+  \param[in]   enable    enable flag
+  \return      error code
+*/
+int32_t csi_gpio_pin_set_irq(gpio_pin_handle_t handle, gpio_irq_mode_e mode, bool enable);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CSI_GPIO_H_ */

bsp/thead-smart/drivers/drv_irq.h

+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      header File for IRQ Driver
+ */
+
+#include <stdint.h>
+
+/**
+  \brief       enable irq.
+  \param[in]   irq_num Number of IRQ.
+  \return      None.
+*/
+void drv_irq_enable(uint32_t irq_num);
+
+/**
+  \brief       disable irq.
+  \param[in]   irq_num Number of IRQ.
+  \return      None.
+*/
+void drv_irq_disable(uint32_t irq_num);
+
+/**
+  \brief       register irq handler.
+  \param[in]   irq_num Number of IRQ.
+  \param[in]   irq_handler IRQ Handler.
+  \return      None.
+*/
+void drv_irq_register(uint32_t irq_num, void *irq_handler);
+
+/**
+  \brief       unregister irq handler.
+  \param[in]   irq_num Number of IRQ.
+  \param[in]   irq_handler IRQ Handler.
+  \return      None.
+*/
+void drv_irq_unregister(uint32_t irq_num);

bsp/thead-smart/drivers/drv_timer.h

+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      timer driver header file
+ */
+
+/******************************************************************************
+ * @file     drv_timer.h
+ * @brief    header file for timer driver
+ * @version  V1.0
+ * @date     02. June 2017
+ * @model    timer
+ ******************************************************************************/
+
+#ifndef _CSI_TIMER_H_
+#define _CSI_TIMER_H_
+
+
+#include <stdint.h>
+#include <drv_common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/// definition for timer handle.
+typedef void *timer_handle_t;
+
+/*----- TIMER Control Codes: Mode -----*/
+typedef enum
+{
+    TIMER_MODE_FREE_RUNNING                 = 0,   ///< free running mode
+    TIMER_MODE_RELOAD                              ///< reload mode
+} timer_mode_e;
+
+/**
+\brief TIMER Status
+*/
+typedef struct
+{
+    uint32_t active   : 1;                        ///< timer active flag
+    uint32_t timeout  : 1;                        ///< timeout flag
+} timer_status_t;
+
+/**
+\brief TIMER Event
+*/
+typedef enum
+{
+    TIMER_EVENT_TIMEOUT  = 0   ///< time out event
+} timer_event_e;
+
+typedef void (*timer_event_cb_t)(int32_t idx, timer_event_e event);   ///< Pointer to \ref timer_event_cb_t : TIMER Event call back.
+
+/**
+  \brief       Initialize TIMER Interface. 1. Initializes the resources needed for the TIMER interface 2.registers event callback function
+  \param[in]   idx  timer index
+  \param[in]   cb_event  event call back function \ref timer_event_cb_t
+  \param[in]   cb_arg    arguments of cb_event
+  \return      pointer to timer instance
+*/
+timer_handle_t csi_timer_initialize(int32_t idx, timer_event_cb_t cb_event);
+
+/**
+  \brief       De-initialize TIMER Interface. stops operation and releases the software resources used by the interface
+  \param[in]   handle timer handle to operate.
+  \return      error code
+*/
+int32_t csi_timer_uninitialize(timer_handle_t handle);
+
+/**
+  \brief       control timer power.
+  \param[in]   handle  timer handle to operate.
+  \param[in]   state   power state.\ref csi_power_stat_e.
+  \return      error code
+*/
+int32_t csi_timer_power_control(timer_handle_t handle, csi_power_stat_e state);
+
+/**
+  \brief       config timer mode.
+  \param[in]   handle timer handle to operate.
+  \param[in]   mode      \ref timer_mode_e
+  \return      error code
+*/
+int32_t csi_timer_config(timer_handle_t handle, timer_mode_e mode);
+
+/**
+  \brief       Set timeout just for the reload mode.
+  \param[in]   handle timer handle to operate.
+  \param[in]   timeout the timeout value in microseconds(us).
+  \return      error code
+*/
+int32_t csi_timer_set_timeout(timer_handle_t handle, uint32_t timeout);
+
+/**
+  \brief       Start timer.
+  \param[in]   handle timer handle to operate.
+  \return      error code
+*/
+int32_t csi_timer_start(timer_handle_t handle);
+
+/**
+  \brief       Stop timer.
+  \param[in]   handle timer handle to operate.
+  \return      error code
+*/
+int32_t csi_timer_stop(timer_handle_t handle);
+
+/**
+  \brief       suspend timer.
+  \param[in]   handle timer handle to operate.
+  \return      error code
+*/
+int32_t csi_timer_suspend(timer_handle_t handle);
+
+/**
+  \brief       resume timer.
+  \param[in]   handle timer handle to operate.
+  \return      error code
+*/
+int32_t csi_timer_resume(timer_handle_t handle);
+
+/**
+  \brief       get timer current value
+  \param[in]   handle timer handle to operate.
+  \param[out]   value     timer current value
+  \return      error code
+*/
+int32_t csi_timer_get_current_value(timer_handle_t handle, uint32_t *value);
+
+/**
+  \brief       Get TIMER status.
+  \param[in]   handle timer handle to operate.
+  \return      TIMER status \ref timer_status_t
+*/
+timer_status_t csi_timer_get_status(timer_handle_t handle);
+
+/**
+  \brief       get timer reload value
+  \param[in]   handle timer handle to operate.
+  \param[out]   value    timer reload value
+  \return      error code
+*/
+int32_t csi_timer_get_load_value(timer_handle_t handle, uint32_t *value);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CSI_TIMER_H_ */
+

bsp/thead-smart/drivers/drv_usart.h

+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      header file for usart driver
+ */
+
+#ifndef _CSI_USART_H_
+#define _CSI_USART_H_
+
+
+#include <drv_common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/// definition for usart handle.
+typedef void *usart_handle_t;
+
+/****** USART specific error codes *****/
+typedef enum
+{
+    USART_ERROR_MODE  = (DRV_ERROR_SPECIFIC + 1),      ///< Specified Mode not supported
+    USART_ERROR_BAUDRATE,                         ///< Specified baudrate not supported
+    USART_ERROR_DATA_BITS,                        ///< Specified number of Data bits not supported
+    USART_ERROR_PARITY,                           ///< Specified Parity not supported
+    USART_ERROR_STOP_BITS,                        ///< Specified number of Stop bits not supported
+    USART_ERROR_FLOW_CONTROL,                     ///< Specified Flow Control not supported
+    USART_ERROR_CPOL,                             ///< Specified Clock Polarity not supported
+    USART_ERROR_CPHA                              ///< Specified Clock Phase not supported
+} usart_error_e;
+
+/*----- USART Control Codes: Mode -----*/
+typedef enum
+{
+    USART_MODE_ASYNCHRONOUS         = 0,   ///< USART (Asynchronous)
+    USART_MODE_SYNCHRONOUS_MASTER,         ///< Synchronous Master
+    USART_MODE_SYNCHRONOUS_SLAVE,          ///< Synchronous Slave (external clock signal)
+    USART_MODE_SINGLE_WIRE,                 ///< USART Single-wire (half-duplex)
+    USART_MODE_SINGLE_IRDA,                 ///< UART IrDA
+    USART_MODE_SINGLE_SMART_CARD,           ///< UART Smart Card
+} usart_mode_e;
+
+/*----- USART Control Codes: Mode Parameters: Data Bits -----*/
+typedef enum
+{
+    USART_DATA_BITS_5             = 0,    ///< 5 Data bits
+    USART_DATA_BITS_6,                    ///< 6 Data bit
+    USART_DATA_BITS_7,                    ///< 7 Data bits
+    USART_DATA_BITS_8,                    ///< 8 Data bits (default)
+    USART_DATA_BITS_9                     ///< 9 Data bits
+} usart_data_bits_e;
+
+/*----- USART Control Codes: Mode Parameters: Parity -----*/
+typedef enum
+{
+    USART_PARITY_NONE            = 0,       ///< No Parity (default)
+    USART_PARITY_EVEN,                      ///< Even Parity
+    USART_PARITY_ODD,                       ///< Odd Parity
+    USART_PARITY_1,                         ///< Parity forced to 1
+    USART_PARITY_0                          ///< Parity forced to 0
+} usart_parity_e;
+
+/*----- USART Control Codes: Mode Parameters: Stop Bits -----*/
+typedef enum
+{
+    USART_STOP_BITS_1            = 0,    ///< 1 Stop bit (default)
+    USART_STOP_BITS_2,                   ///< 2 Stop bits
+    USART_STOP_BITS_1_5,                 ///< 1.5 Stop bits
+    USART_STOP_BITS_0_5                  ///< 0.5 Stop bits
+} usart_stop_bits_e;
+
+/*----- USART Control Codes: Mode Parameters: Clock Polarity (Synchronous mode) -----*/
+typedef enum
+{
+    USART_CPOL0                  = 0,    ///< CPOL = 0 (default). data are captured on rising edge (low->high transition)
+    USART_CPOL1                          ///< CPOL = 1. data are captured on falling edge (high->lowh transition)
+} usart_cpol_e;
+
+/*----- USART Control Codes: Mode Parameters: Clock Phase (Synchronous mode) -----*/
+typedef enum
+{
+    USART_CPHA0                  = 0,   ///< CPHA = 0 (default). sample on first (leading) edge
+    USART_CPHA1                         ///< CPHA = 1. sample on second (trailing) edge
+} usart_cpha_e;
+
+/*----- USART Control Codes: flush data type-----*/
+typedef enum
+{
+    USART_FLUSH_WRITE,
+    USART_FLUSH_READ
+} usart_flush_type_e;
+
+/*----- USART Control Codes: flow control type-----*/
+typedef enum
+{
+    USART_FLOWCTRL_NONE,
+    USART_FLOWCTRL_CTS,
+    USART_FLOWCTRL_RTS,
+    USART_FLOWCTRL_CTS_RTS
+} usart_flowctrl_type_e;
+
+/*----- USART Modem Control -----*/
+typedef enum
+{
+    USART_RTS_CLEAR,                  ///< Deactivate RTS
+    USART_RTS_SET,                    ///< Activate RTS
+    USART_DTR_CLEAR,                  ///< Deactivate DTR
+    USART_DTR_SET                     ///< Activate DTR
+} usart_modem_ctrl_e;
+
+/*----- USART Modem Status -----*/
+typedef struct
+{
+    uint32_t cts : 1;                     ///< CTS state: 1=Active, 0=Inactive
+    uint32_t dsr : 1;                     ///< DSR state: 1=Active, 0=Inactive
+    uint32_t dcd : 1;                     ///< DCD state: 1=Active, 0=Inactive
+    uint32_t ri  : 1;                     ///< RI  state: 1=Active, 0=Inactive
+} usart_modem_stat_t;
+
+/*----- USART Control Codes: on-off intrrupte type-----*/
+typedef enum
+{
+    USART_INTR_WRITE,
+    USART_INTR_READ
+} usart_intr_type_e;
+
+/**
+\brief USART Status
+*/
+typedef struct  {
+    uint32_t tx_busy          : 1;        ///< Transmitter busy flag
+    uint32_t rx_busy          : 1;        ///< Receiver busy flag
+    uint32_t tx_underflow     : 1;        ///< Transmit data underflow detected (cleared on start of next send operation)(Synchronous Slave)
+    uint32_t rx_overflow      : 1;        ///< Receive data overflow detected (cleared on start of next receive operation)
+    uint32_t rx_break         : 1;        ///< Break detected on receive (cleared on start of next receive operation)
+    uint32_t rx_framing_error : 1;        ///< Framing error detected on receive (cleared on start of next receive operation)
+    uint32_t rx_parity_error  : 1;        ///< Parity error detected on receive (cleared on start of next receive operation)
+    uint32_t tx_enable        : 1;        ///< Transmitter enable flag
+    uint32_t rx_enable        : 1;        ///< Receiver enbale flag
+} usart_status_t;
+
+/****** USART Event *****/
+typedef enum
+{
+    USART_EVENT_SEND_COMPLETE       = 0,  ///< Send completed; however USART may still transmit data
+    USART_EVENT_RECEIVE_COMPLETE    = 1,  ///< Receive completed
+    USART_EVENT_TRANSFER_COMPLETE   = 2,  ///< Transfer completed
+    USART_EVENT_TX_COMPLETE         = 3,  ///< Transmit completed (optional)
+    USART_EVENT_TX_UNDERFLOW        = 4,  ///< Transmit data not available (Synchronous Slave)
+    USART_EVENT_RX_OVERFLOW         = 5,  ///< Receive data overflow
+    USART_EVENT_RX_TIMEOUT          = 6,  ///< Receive character timeout (optional)
+    USART_EVENT_RX_BREAK            = 7,  ///< Break detected on receive
+    USART_EVENT_RX_FRAMING_ERROR    = 8,  ///< Framing error detected on receive
+    USART_EVENT_RX_PARITY_ERROR     = 9,  ///< Parity error detected on receive
+    USART_EVENT_CTS                 = 10, ///< CTS state changed (optional)
+    USART_EVENT_DSR                 = 11, ///< DSR state changed (optional)
+    USART_EVENT_DCD                 = 12, ///< DCD state changed (optional)
+    USART_EVENT_RI                  = 13, ///< RI  state changed (optional)
+    USART_EVENT_RECEIVED            = 14, ///< Data Received, only in usart fifo, call receive()/transfer() get the data
+} usart_event_e;
+
+typedef void (*usart_event_cb_t)(int32_t idx, usart_event_e event);   ///< Pointer to \ref usart_event_cb_t : USART Event call back.
+
+/**
+\brief USART Driver Capabilities.
+*/
+typedef struct  {
+    uint32_t asynchronous       : 1;      ///< supports UART (Asynchronous) mode
+    uint32_t synchronous_master : 1;      ///< supports Synchronous Master mode
+    uint32_t synchronous_slave  : 1;      ///< supports Synchronous Slave mode
+    uint32_t single_wire        : 1;      ///< supports UART Single-wire mode
+    uint32_t irda               : 1;      ///< supports UART IrDA mode
+    uint32_t smart_card         : 1;      ///< supports UART Smart Card mode
+    uint32_t smart_card_clock   : 1;      ///< Smart Card Clock generator available
+    uint32_t flow_control_rts   : 1;      ///< RTS Flow Control available
+    uint32_t flow_control_cts   : 1;      ///< CTS Flow Control available
+    uint32_t event_tx_complete  : 1;      ///< Transmit completed event: \ref USART_EVENT_TX_COMPLETE
+    uint32_t event_rx_timeout   : 1;      ///< Signal receive character timeout event: \ref USART_EVENT_RX_TIMEOUT
+    uint32_t rts                : 1;      ///< RTS Line: 0=not available, 1=available
+    uint32_t cts                : 1;      ///< CTS Line: 0=not available, 1=available
+    uint32_t dtr                : 1;      ///< DTR Line: 0=not available, 1=available
+    uint32_t dsr                : 1;      ///< DSR Line: 0=not available, 1=available
+    uint32_t dcd                : 1;      ///< DCD Line: 0=not available, 1=available
+    uint32_t ri                 : 1;      ///< RI Line: 0=not available, 1=available
+    uint32_t event_cts          : 1;      ///< Signal CTS change event: \ref USART_EVENT_CTS
+    uint32_t event_dsr          : 1;      ///< Signal DSR change event: \ref USART_EVENT_DSR
+    uint32_t event_dcd          : 1;      ///< Signal DCD change event: \ref USART_EVENT_DCD
+    uint32_t event_ri           : 1;      ///< Signal RI change event: \ref USART_EVENT_RI
+} usart_capabilities_t;
+
+/**
+  \brief       Initialize USART Interface. 1. Initializes the resources needed for the USART interface 2.registers event callback function
+  \param[in]   idx usart index
+  \param[in]   cb_event  event call back function \ref usart_event_cb_t
+  \return      return usart handle if success
+*/
+usart_handle_t csi_usart_initialize(int32_t idx, usart_event_cb_t cb_event);
+
+/**
+  \brief       De-initialize USART Interface. stops operation and releases the software resources used by the interface
+  \param[in]   handle  usart handle to operate.
+  \return      error code
+*/
+int32_t csi_usart_uninitialize(usart_handle_t handle);
+/**
+  \brief       Get driver capabilities.
+  \param[in]   idx usart index
+  \return      \ref usart_capabilities_t
+*/
+usart_capabilities_t csi_usart_get_capabilities(int32_t idx);
+
+/**
+  \brief       config usart mode.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   baud      baud rate.
+  \param[in]   mode      \ref usart_mode_e .
+  \param[in]   parity    \ref usart_parity_e .
+  \param[in]   stopbits  \ref usart_stop_bits_e .
+  \param[in]   bits      \ref usart_data_bits_e .
+  \return      error code
+*/
+int32_t csi_usart_config(usart_handle_t handle,
+                         uint32_t baud,
+                         usart_mode_e mode,
+                         usart_parity_e parity,
+                         usart_stop_bits_e stopbits,
+                         usart_data_bits_e bits);
+
+
+/**
+  \brief       Start sending data to USART transmitter,(received data is ignored).
+               This function is non-blocking,\ref usart_event_e is signaled when operation completes or error happens.
+               \ref csi_usart_get_status can get operation status.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   data  Pointer to buffer with data to send to USART transmitter. data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
+  \param[in]   num   Number of data items to send
+  \return      error code
+*/
+int32_t csi_usart_send(usart_handle_t handle, const void *data, uint32_t num);
+
+/**
+  \brief       Abort Send data to USART transmitter
+  \param[in]   handle  usart handle to operate.
+  \return      error code
+*/
+int32_t csi_usart_abort_send(usart_handle_t handle);
+
+/**
+  \brief       Start receiving data from USART receiver. \n
+               This function is non-blocking,\ref usart_event_e is signaled when operation completes or error happens.
+               \ref csi_usart_get_status can get operation status.
+  \param[in]   handle  usart handle to operate.
+  \param[out]  data  Pointer to buffer for data to receive from USART receiver.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
+  \param[in]   num   Number of data items to receive
+  \return      error code
+*/
+int32_t csi_usart_receive(usart_handle_t handle, void *data, uint32_t num);
+
+/**
+  \brief       query data from UART receiver FIFO.
+  \param[in]   handle  usart handle to operate.
+  \param[out]  data  Pointer to buffer for data to receive from UART receiver
+  \param[in]   num   Number of data items to receive
+  \return      fifo data num to receive
+*/
+int32_t csi_usart_receive_query(usart_handle_t handle, void *data, uint32_t num);
+
+/**
+  \brief       Abort Receive data from USART receiver
+  \param[in]   handle  usart handle to operate.
+  \return      error code
+*/
+int32_t csi_usart_abort_receive(usart_handle_t handle);
+
+/**
+  \brief       Start synchronously sends data to the USART transmitter and receives data from the USART receiver. used in synchronous mode
+               This function is non-blocking,\ref usart_event_e is signaled when operation completes or error happens.
+               \ref csi_usart_get_status can get operation status.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   data_out  Pointer to buffer with data to send to USART transmitter.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
+  \param[out]  data_in   Pointer to buffer for data to receive from USART receiver.data_type is : uint8_t for 5..8 data bits, uint16_t for 9 data bits
+  \param[in]   num       Number of data items to transfer
+  \return      error code
+*/
+int32_t csi_usart_transfer(usart_handle_t handle, const void *data_out, void *data_in, uint32_t num);
+
+/**
+  \brief       abort sending/receiving data to/from USART transmitter/receiver.
+  \param[in]   handle  usart handle to operate.
+  \return      error code
+*/
+int32_t csi_usart_abort_transfer(usart_handle_t handle);
+
+/**
+  \brief       Get USART status.
+  \param[in]   handle  usart handle to operate.
+  \return      USART status \ref usart_status_t
+*/
+usart_status_t csi_usart_get_status(usart_handle_t handle);
+
+/**
+  \brief       flush receive/send data.
+  \param[in]   handle usart handle to operate.
+  \param[in]   type \ref usart_flush_type_e .
+  \return      error code
+*/
+int32_t csi_usart_flush(usart_handle_t handle, usart_flush_type_e type);
+
+/**
+  \brief       set interrupt mode.
+  \param[in]   handle usart handle to operate.
+  \param[in]   type \ref usart_intr_type_e.
+  \param[in]   flag 0-OFF, 1-ON.
+  \return      error code
+*/
+int32_t csi_usart_set_interrupt(usart_handle_t handle, usart_intr_type_e type, int32_t flag);
+
+/**
+  \brief       set the baud rate of usart.
+  \param[in]   baud  usart base to operate.
+  \param[in]   baudrate baud rate
+  \return      error code
+*/
+int32_t csi_usart_config_baudrate(usart_handle_t handle, uint32_t baud);
+
+/**
+  \brief       config usart mode.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   mode    \ref usart_mode_e
+  \return      error code
+*/
+int32_t csi_usart_config_mode(usart_handle_t handle, usart_mode_e mode);
+
+/**
+  \brief       config usart parity.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   parity    \ref usart_parity_e
+  \return      error code
+*/
+int32_t csi_usart_config_parity(usart_handle_t handle, usart_parity_e parity);
+
+/**
+  \brief       config usart stop bit number.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   stopbits  \ref usart_stop_bits_e
+  \return      error code
+*/
+int32_t csi_usart_config_stopbits(usart_handle_t handle, usart_stop_bits_e stopbit);
+
+/**
+  \brief       config usart data length.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   databits      \ref usart_data_bits_e
+  \return      error code
+*/
+int32_t csi_usart_config_databits(usart_handle_t handle, usart_data_bits_e databits);
+
+/**
+  \brief       get character in query mode.
+  \param[in]   handle  usart handle to operate.
+  \param[out]  ch the pointer to the received character.
+  \return      error code
+*/
+int32_t csi_usart_getchar(usart_handle_t handle, uint8_t *ch);
+
+/**
+  \brief       transmit character in query mode.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   ch  the input character
+  \return      error code
+*/
+int32_t csi_usart_putchar(usart_handle_t handle, uint8_t ch);
+
+/**
+  \brief       Get usart send data count.
+  \param[in]   handle  usart handle to operate.
+  \return      number of currently transmitted data bytes
+*/
+uint32_t csi_usart_get_tx_count(usart_handle_t handle);
+
+/**
+  \brief       Get usart received data count.
+  \param[in]   handle  usart handle to operate.
+  \return      number of currently received data bytes
+*/
+uint32_t csi_usart_get_rx_count(usart_handle_t handle);
+
+/**
+  \brief       control usart power.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   state   power state.\ref csi_power_stat_e.
+  \return      error code
+*/
+int32_t csi_usart_power_control(usart_handle_t handle, csi_power_stat_e state);
+
+/**
+  \brief       config usart flow control type.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   flowctrl_type   flow control type.\ref usart_flowctrl_type_e.
+  \return      error code
+*/
+int32_t csi_usart_config_flowctrl(usart_handle_t handle,
+                                  usart_flowctrl_type_e flowctrl_type);
+
+/**
+  \brief       config usart clock Polarity and Phase.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   cpol    Clock Polarity.\ref usart_cpol_e.
+  \param[in]   cpha    Clock Phase.\ref usart_cpha_e.
+  \return      error code
+*/
+int32_t csi_usart_config_clock(usart_handle_t handle, usart_cpol_e cpol, usart_cpha_e cpha);
+
+/**
+  \brief       control the transmitter.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   enable  1 - enable the transmitter. 0 - disable the transmitter
+  \return      error code
+*/
+int32_t csi_usart_control_tx(usart_handle_t handle, uint32_t enable);
+
+/**
+  \brief       control the receiver.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   enable  1 - enable the receiver. 0 - disable the receiver
+  \return      error code
+*/
+int32_t csi_usart_control_rx(usart_handle_t handle, uint32_t enable);
+
+/**
+  \brief       control the break.
+  \param[in]   handle  usart handle to operate.
+  \param[in]   enable  1- Enable continuous Break transmission,0 - disable continuous Break transmission
+  \return      error code
+*/
+int32_t csi_usart_control_break(usart_handle_t handle, uint32_t enable);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _CSI_USART_H_ */

bsp/thead-smart/drivers/dw_gpio.c

+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-08-20     zx.chen      gpio driver
+ */
+
+/******************************************************************************
+ * @file     dw_gpio.c
+ * @brief    CSI Source File for GPIO Driver
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+
+#include <csi_config.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <drv_irq.h>
+#include <drv_gpio.h>
+#include <dw_gpio.h>
+#include <csi_core.h>
+#include <pin_name.h>
+
+extern int32_t drv_pin_config_mode(port_name_e port, uint8_t offset, gpio_mode_e pin_mode);
+
+#define ERR_GPIO(errno) (CSI_DRV_ERRNO_GPIO_BASE | errno)
+#define GPIO_NULL_PARAM_CHK(para)    HANDLE_PARAM_CHK(para, ERR_GPIO(DRV_ERROR_PARAMETER))
+
+typedef void *gpio_port_handle_t;
+
+typedef struct 
+{
+#ifdef CONFIG_LPM
+    uint8_t gpio_power_status;
+    uint32_t gpio_regs_saved[7];
+#endif
+    uint32_t base;              ///< handle register base
+    uint32_t irq;               ///< irq of this handle
+    uint32_t pin_num;           ///< pin number of this handle
+    gpio_mode_e mode;           ///< gpio mode
+    gpio_direction_e dir;       ///< gpio direction
+    uint32_t mask;              ///< gpio mask bit
+    uint32_t value;             ///< gpio value
+} dw_gpio_priv_t;
+
+typedef struct 
+{
+    uint8_t     portidx;
+    uint8_t     idx;
+    uint8_t     offset;
+    gpio_event_cb_t cb;
+} dw_gpio_pin_priv_t;
+
+extern int32_t target_gpio_port_init(port_name_e port, uint32_t *base, uint32_t *irq, void **handler, uint32_t *pin_num);
+extern int32_t target_gpio_pin_init(int32_t gpio_pin, uint32_t *port_idx);
+
+static dw_gpio_priv_t gpio_handle[CONFIG_GPIO_NUM];
+static dw_gpio_pin_priv_t gpio_pin_handle[CONFIG_GPIO_PIN_NUM];
+
+//
+// Functions
+//
+static int32_t gpio_set_direction(
+    void *port,
+    gpio_direction_e direction
+)
+{
+    dw_gpio_priv_t *gpio_priv = port;
+    dw_gpio_reg_t *gpio_reg = (dw_gpio_reg_t *)(gpio_priv->base);
+
+    if (direction == GPIO_DIRECTION_INPUT) 
+    {
+        gpio_reg->SWPORT_DDR &= (~gpio_priv->mask);
+    } else if (direction == GPIO_DIRECTION_OUTPUT) 
+    {
+        gpio_reg->SWPORT_DDR |= gpio_priv->mask;
+    } else 
+    {
+        return ERR_GPIO(GPIO_ERROR_DIRECTION);
+    }
+
+    return 0;
+}
+
+/*
+ * Read the statu of the Port choosed.
+ * Parameters:
+ *   port:  use to choose a I/O port among Port A, B, or C.
+ * return: the value of the corresponding Port.
+ */
+
+static int32_t gpio_read(void *port, uint32_t *value)
+{
+    dw_gpio_priv_t *gpio_priv = port;
+    dw_gpio_control_reg_t *gpio_control_reg = (dw_gpio_control_reg_t *)(gpio_priv->base + 0x30);
+    *value = gpio_control_reg->EXT_PORTA;
+    return 0;
+}
+
+
+/*
+ * Write an output value to corresponding Port.
+ * Parameters:
+ *   port:  use to choose a I/O port among Port A, B, or C.
+ *   output: value that will be written to the corresponding Port.
+ * return: SUCCESS
+ */
+
+static int32_t gpio_write(void *port, uint32_t mask)
+{
+    dw_gpio_priv_t *gpio_priv = port;
+    dw_gpio_reg_t *gpio_reg = (dw_gpio_reg_t *)(gpio_priv->base);
+
+    uint32_t value = gpio_reg->SWPORT_DR;
+
+    value &= ~(mask);
+    value |= gpio_priv->value;
+    gpio_reg->SWPORT_DR = value;
+    return 0;
+}
+
+/**
+ * Configure a GPIO gpio_set_irq_mode.
+ * @param[in]   pin         the addr store the pin num.
+ * @param[in]   _irqmode    the irqmode of gpio
+ * @return      zero on success. -1 on falure.
+ */
+static int32_t gpio_set_irq_mode(gpio_pin_handle_t pin, gpio_irq_mode_e irq_mode)
+{
+    dw_gpio_pin_priv_t *gpio_pin_priv = pin;
+
+    /* convert portidx to port handle */
+    dw_gpio_priv_t *port_handle = &gpio_handle[gpio_pin_priv->portidx];
+
+    dw_gpio_control_reg_t *gpio_control_reg = (dw_gpio_control_reg_t *)(port_handle->base + 0x30);
+    uint32_t offset = gpio_pin_priv->idx;
+    uint32_t mask = 1 << offset;
+
+    switch (irq_mode) 
+    {
+        /* rising edge interrupt mode */
+        case GPIO_IRQ_MODE_RISING_EDGE:
+            gpio_control_reg->INTTYPE_LEVEL |= mask;
+            gpio_control_reg->INT_POLARITY |= mask;
+            break;
+
+        /* falling edge interrupt mode */
+        case GPIO_IRQ_MODE_FALLING_EDGE:
+            gpio_control_reg->INTTYPE_LEVEL |= mask;
+            gpio_control_reg->INT_POLARITY &= (~mask);
+            break;
+
+        /* low level interrupt mode */
+        case GPIO_IRQ_MODE_LOW_LEVEL:
+            gpio_control_reg->INTTYPE_LEVEL &= (~mask);
+            gpio_control_reg->INT_POLARITY &= (~mask);
+            break;
+
+        /* high level interrupt mode */
+        case GPIO_IRQ_MODE_HIGH_LEVEL:
+            gpio_control_reg->INTTYPE_LEVEL &= (~mask);
+            gpio_control_reg->INT_POLARITY |= mask;
+            break;
+
+        /* double edge interrupt mode */
+        case GPIO_IRQ_MODE_DOUBLE_EDGE:
+            return ERR_GPIO(DRV_ERROR_UNSUPPORTED);
+
+        default:
+            return ERR_GPIO(GPIO_ERROR_IRQ_MODE);
+    }
+
+    return 0;
+}
+
+/*
+ * Clear one or more interrupts of PortA.
+ * Parameters:
+ *   pinno:
+ * return: SUCCESS.
+ */
+
+static void gpio_irq_clear(gpio_pin_handle_t pin, uint32_t idx)
+{
+    dw_gpio_pin_priv_t *gpio_pin_priv = pin;
+
+    /* convert portidx to port handle */
+    dw_gpio_priv_t *port_handle = &gpio_handle[gpio_pin_priv->portidx];
+
+    dw_gpio_control_reg_t *gpio_control_reg = (dw_gpio_control_reg_t *)(port_handle->base + 0x30);
+
+    gpio_control_reg->PORTA_EOI = idx;
+}
+
+
+/*
+ * Enable one or more interrupts of PortA.
+ * Parameters:
+ *   pinno:
+ * return: SUCCESS.
+ */
+static void gpio_irq_enable(gpio_pin_handle_t pin)
+{
+    dw_gpio_pin_priv_t *gpio_pin_priv = pin;
+
+    /* convert portidx to port handle */
+    dw_gpio_priv_t *port_handle = &gpio_handle[gpio_pin_priv->portidx];
+
+    dw_gpio_control_reg_t *gpio_control_reg = (dw_gpio_control_reg_t *)(port_handle->base + 0x30);
+    uint32_t offset = gpio_pin_priv->idx;
+    uint32_t val = gpio_control_reg->INTEN;
+    val |= (1 << offset);
+    gpio_control_reg->INTEN = val;
+}
+
+
+/*
+ * Disable one or more interrupts of PortA.
+ * Parameters:
+ *   pinno:
+ * return: SUCCESS.
+ */
+
+static void gpio_irq_disable(gpio_pin_handle_t pin)
+{
+    dw_gpio_pin_priv_t *gpio_pin_priv = pin;
+    uint32_t offset = gpio_pin_priv->idx;
+
+    /* convert portidx to port handle */
+    dw_gpio_priv_t *port_handle = &gpio_handle[gpio_pin_priv->portidx];
+
+    dw_gpio_control_reg_t *gpio_control_reg = (dw_gpio_control_reg_t *)(port_handle->base + 0x30);
+    uint32_t val = gpio_control_reg->INTEN;
+    val &= ~(1 << offset);
+    gpio_control_reg->INTEN = val;
+}
+
+void dw_gpio_irqhandler(int idx)
+{
+    if (idx >= CONFIG_GPIO_NUM) 
+    {
+        return;
+    }
+
+    dw_gpio_control_reg_t *gpio_control_reg = (dw_gpio_control_reg_t *)(gpio_handle[idx].base + 0x30);
+
+    uint32_t value = gpio_control_reg->INTSTATUS;
+    uint8_t i;
+
+    /* find the interrput pin */
+    for (i = 0; i < 32; i++) 
+    {
+        if (value & (1U << i)) 
+        {
+            uint32_t pin_idx = i;
+
+#ifndef CONFIG_CHIP_DANICA
+            uint8_t j;
+
+            if (idx > 0) 
+            {
+                for (j = 0; j < idx; j++) 
+                {
+                    pin_idx += gpio_handle[j].pin_num;
+                }
+            }
+
+            if (pin_idx >= CONFIG_GPIO_PIN_NUM) 
+            {
+                return;
+            }
+
+#endif
+            dw_gpio_pin_priv_t *gpio_pin_priv = (dw_gpio_pin_priv_t *)&gpio_pin_handle[pin_idx];
+
+            gpio_irq_clear(gpio_pin_priv, (1 << i));  //clear the gpio interrupt
+
+            /* execute the callback function */
+            if ((gpio_event_cb_t)(gpio_pin_priv->cb)) 
+            {
+                ((gpio_event_cb_t)(gpio_pin_priv->cb))(gpio_pin_priv->offset);
+            }
+        }
+    }
+}
+
+/**
+  \brief       Initialize GPIO module. 1. Initializes the resources needed for the GPIO handle 2.registers event callback function
+                3.get gpio_port_handle
+  \param[in]   port      port_name.
+  \return      gpio_port_handle
+*/
+gpio_port_handle_t csi_gpio_port_initialize(int32_t port)
+{
+    dw_gpio_priv_t *gpio_priv = NULL;
+
+    /* obtain the gpio port information */
+    uint32_t base = 0u;
+    uint32_t pin_num;
+    uint32_t irq;
+    void *handler;
+    int32_t idx = target_gpio_port_init(port, &base, &irq, &handler, &pin_num);
+
+    if (idx < 0 || idx >= CONFIG_GPIO_NUM) 
+    {
+        return NULL;
+    }
+
+    gpio_priv = &gpio_handle[idx];
+
+    gpio_priv->base = base;
+    gpio_priv->irq  = irq;
+    gpio_priv->pin_num  = pin_num;
+
+#ifdef CONFIG_LPM
+    csi_gpio_power_control(gpio_priv, DRV_POWER_FULL);
+#endif
+
+    drv_irq_register(gpio_priv->irq, handler);
+    drv_irq_enable(gpio_priv->irq);
+
+    return (gpio_port_handle_t)gpio_priv;
+}
+
+/**
+  \brief       De-initialize GPIO handle. stops operation and releases the software resources used by the handle
+  \param[in]   handle   gpio port handle to operate.
+  \return      error code
+*/
+int32_t csi_gpio_port_uninitialize(gpio_port_handle_t handle)
+{
+    GPIO_NULL_PARAM_CHK(handle);
+
+    dw_gpio_priv_t *gpio_priv = handle;
+
+    drv_irq_disable(gpio_priv->irq);
+    drv_irq_unregister(gpio_priv->irq);
+
+#ifdef CONFIG_LPM
+    csi_gpio_power_control(gpio_priv, DRV_POWER_OFF);
+#endif
+
+    return 0;
+}
+
+#ifdef CONFIG_LPM
+static void manage_clock(gpio_pin_handle_t handle, uint8_t enable)
+{
+    dw_gpio_pin_priv_t *gpio_pin_priv = (dw_gpio_pin_priv_t *)handle;
+    uint8_t device[] = {CLOCK_MANAGER_GPIO0, CLOCK_MANAGER_GPIO1};
+
+    drv_clock_manager_config(device[gpio_pin_priv->portidx], enable);
+}
+
+static void do_prepare_sleep_action(void *handle)
+{
+    dw_gpio_priv_t *gpio_handle = handle;
+    uint32_t *gbase = (uint32_t *)(gpio_handle->base);
+    uint32_t *control_base = (uint32_t *)(gpio_handle->base + 0x30);
+    registers_save(gpio_handle->gpio_regs_saved, gbase, 3);
+    registers_save(&gpio_handle->gpio_regs_saved[3], control_base, 4);
+}
+
+static void do_wakeup_sleep_action(void *handle)
+{
+    dw_gpio_priv_t *gpio_handle = handle;
+    uint32_t *gbase = (uint32_t *)(gpio_handle->base);
+    uint32_t *control_base = (uint32_t *)(gpio_handle->base + 0x30);
+    registers_restore(gbase, gpio_handle->gpio_regs_saved, 3);
+    registers_restore(control_base, &gpio_handle->gpio_regs_saved[3], 4);
+}
+#endif
+
+/**
+  \brief       Initialize GPIO handle.
+  \param[in]   gpio_pin    Pointer to the int32_t.
+  \param[in]   cb_event    Pointer to \ref gpio_event_cb_t.
+  \param[in]   arg    Pointer to \ref arg used for the callback.
+  \return      gpio_pin_handle
+*/
+gpio_pin_handle_t csi_gpio_pin_initialize(int32_t gpio_pin, gpio_event_cb_t cb_event)
+{
+
+    if (gpio_pin < 0 || gpio_pin >= CONFIG_GPIO_PIN_NUM) 
+    {
+        return NULL;
+    }
+
+    uint32_t i;
+
+    for (i = 0; i < CONFIG_GPIO_NUM; i++) 
+    {
+        csi_gpio_port_initialize(i);
+    }
+
+    /* obtain the gpio pin information */
+    uint32_t port_idx;
+    int32_t pin_idx = target_gpio_pin_init(gpio_pin, &port_idx);
+
+    if (pin_idx < 0) 
+    {
+        return NULL;
+    }
+
+    int32_t idx = pin_idx;
+
+    for (i = 0; i < port_idx; i++) 
+    {
+        idx += (gpio_handle[i].pin_num);
+    }
+
+    dw_gpio_pin_priv_t *gpio_pin_priv = &(gpio_pin_handle[idx]);
+    gpio_pin_priv->portidx = port_idx;
+
+
+    gpio_pin_priv->idx = pin_idx;
+    gpio_pin_priv->cb = cb_event;
+    gpio_pin_priv->offset = gpio_pin;
+
+    return (gpio_pin_handle_t)gpio_pin_priv;
+}
+
+/**
+  \brief       De-initialize GPIO pin handle. stops operation and releases the software resources used by the handle
+  \param[in]   handle   gpio pin handle to operate.
+  \return      error code
+*/
+int32_t csi_gpio_pin_uninitialize(gpio_pin_handle_t handle)
+{
+    if (handle == NULL) 
+    {
+        return ERR_GPIO(DRV_ERROR_PARAMETER);
+    }
+
+    dw_gpio_pin_priv_t *gpio_pin_priv = (dw_gpio_pin_priv_t *)handle;
+    gpio_pin_priv->cb = NULL;
+
+    gpio_irq_disable(handle);
+
+    return 0;
+}
+
+/**
+  \brief       control gpio power.
+  \param[in]   idx  gpio index.
+  \param[in]   state   power state.\ref csi_power_stat_e.
+  \return      error code
+*/
+int32_t csi_gpio_power_control(gpio_pin_handle_t handle, csi_power_stat_e state)
+{
+    GPIO_NULL_PARAM_CHK(handle);
+
+#ifdef CONFIG_LPM
+    dw_gpio_pin_priv_t *gpio_pin_priv = (dw_gpio_pin_priv_t *)handle;
+    power_cb_t callback = 
+    {
+        .wakeup = do_wakeup_sleep_action,
+        .sleep = do_prepare_sleep_action,
+        .manage_clock = manage_clock
+    };
+    return drv_soc_power_control(&gpio_handle[gpio_pin_priv->portidx], state, &callback);
+#else
+    return ERR_GPIO(DRV_ERROR_UNSUPPORTED);
+#endif
+}
+
+/**
+  \brief       config pin mode
+  \param[in]   pin       gpio pin handle to operate.
+  \param[in]   mode      \ref gpio_mode_e
+  \return      error code
+*/
+int32_t csi_gpio_pin_config_mode(gpio_pin_handle_t handle,
+                                 gpio_mode_e mode)
+{
+    GPIO_NULL_PARAM_CHK(handle);
+
+    /* config the gpio pin mode direction mask bits */
+    dw_gpio_pin_priv_t *gpio_pin_priv = handle;
+
+    uint8_t offset = gpio_pin_priv->idx;
+
+    int32_t ret = drv_pin_config_mode(gpio_pin_priv->portidx, offset, mode);
+
+    return ret;
+}
+/**
+  \brief       config pin direction
+  \param[in]   pin       gpio pin handle to operate.
+  \param[in]   dir       \ref gpio_direction_e
+  \return      error code
+*/
+int32_t csi_gpio_pin_config_direction(gpio_pin_handle_t handle,
+                                      gpio_direction_e dir)
+{
+    GPIO_NULL_PARAM_CHK(handle);
+
+    /* config the gpio pin mode direction mask bits */
+    dw_gpio_pin_priv_t *gpio_pin_priv = handle;
+
+    /* convert portidx to port handle */
+    dw_gpio_priv_t *gpio_priv = &gpio_handle[gpio_pin_priv->portidx];
+
+    gpio_priv->dir = dir;
+    gpio_priv->mask = 1 << gpio_pin_priv->idx;
+
+    uint32_t ret = gpio_set_direction(gpio_priv, dir);
+
+    if (ret) 
+    {
+        return ret;
+    }
+
+    return 0;
+}
+
+/**
+  \brief       config pin
+  \param[in]   handle       gpio pin handle to operate.
+  \param[in]   mode      \ref gpio_mode_e
+  \param[in]   dir       \ref gpio_direction_e
+  \return      error code
+*/
+int32_t csi_gpio_pin_config(gpio_pin_handle_t handle,
+                            gpio_mode_e mode,
+                            gpio_direction_e dir)
+{
+    GPIO_NULL_PARAM_CHK(handle);
+
+    /* config the gpio pin mode direction mask bits */
+    dw_gpio_pin_priv_t *gpio_pin_priv = handle;
+
+    /* convert portidx to port handle */
+    dw_gpio_priv_t *gpio_priv = &gpio_handle[gpio_pin_priv->portidx];
+
+    gpio_priv->mode = mode;
+    gpio_priv->dir = dir;
+    gpio_priv->mask = 1 << gpio_pin_priv->idx;
+
+    uint32_t ret = gpio_set_direction(gpio_priv, dir);
+
+    if (ret) 
+    {
+        return ret;
+    }
+
+    return 0;
+
+}
+
+/**
+  \brief       Set one or zero to the selected GPIO pin.
+  \param[in]   handle       gpio pin handle to operate.
+  \param[in]   value     the value to be set
+  \return      error code
+*/
+int32_t csi_gpio_pin_write(gpio_pin_handle_t handle, bool value)
+{
+    GPIO_NULL_PARAM_CHK(handle);
+
+    dw_gpio_pin_priv_t *gpio_pin_priv = handle;
+
+    /* convert portidx to port handle */
+    dw_gpio_priv_t *port_handle = &gpio_handle[gpio_pin_priv->portidx];
+
+    uint8_t offset = gpio_pin_priv->idx;
+    uint32_t port_value = value << offset;
+
+    port_handle->value = port_value;
+    gpio_write(port_handle, (1 << offset));
+
+    return 0;
+
+}
+
+/**
+  \brief       Get the value of  selected GPIO pin.
+  \param[in]   handle       gpio pin handle to operate.
+  \param[out]  value     buf to store the pin value
+  \return      error code
+*/
+int32_t csi_gpio_pin_read(gpio_pin_handle_t handle, bool *value)
+{
+    GPIO_NULL_PARAM_CHK(handle);
+    GPIO_NULL_PARAM_CHK(value);
+
+    dw_gpio_pin_priv_t *gpio_pin_priv = handle;
+    uint32_t port_value;
+    uint8_t offset = gpio_pin_priv->idx;
+
+    /* convert portidx to port handle */
+    dw_gpio_priv_t *port_handle = &gpio_handle[gpio_pin_priv->portidx];
+
+    gpio_read(port_handle, &port_value);
+    *value = (port_value & (1 << offset)) >> offset;
+
+    return 0;
+}
+
+/**
+  \brief       set GPIO interrupt mode.
+  \param[in]   handle       gpio pin handle to operate.
+  \param[in]   mode      the irq mode to be set
+  \param[in]   enable    the enable flag
+  \return      error code
+*/
+int32_t csi_gpio_pin_set_irq(gpio_pin_handle_t handle, gpio_irq_mode_e mode, bool enable)
+{
+    GPIO_NULL_PARAM_CHK(handle);
+
+    uint32_t ret = 0;
+
+    if (enable) 
+    {
+        ret = gpio_set_irq_mode(handle, mode);
+
+        if (ret) 
+        {
+            return ret;
+        }
+
+        gpio_irq_enable(handle);
+
+    } else 
+    {
+        gpio_irq_disable(handle);
+
+    }
+
+    return ret;
+}
+

libcpu/risc-v/SConscript

@@ -10,10 +10,17 @@ group = []
 list  = os.listdir(cwd)
 
 # add common code files
-if rtconfig.CPU != "nuclei":
-    group = group + SConscript(os.path.join('common', 'SConscript'))
+if   rtconfig.VENDOR == "t-head" :
+    group = group
+elif rtconfig.CPU == "nuclei" :
+    group = group
+else :
+    group = group + SConscript(os.path.join(cwd, 'common', 'SConscript'))
 
 # cpu porting code files
-group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
+if  rtconfig.VENDOR == "t-head" :
+    group = group + SConscript(os.path.join(cwd, rtconfig.VENDOR, rtconfig.CPU, 'SConscript'))
+else :
+    group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript'))
 
 Return('group')