Merge branch 'master' of https://github.com/RT-Thread/rt-thread

.travis.yml

@@ -13,8 +13,6 @@ before_script:
   - "[ $RTT_TOOL_CHAIN = 'atmel-avr32' ] && curl -s http://www.atmel.com/images/avr32-gnu-toolchain-3.4.1.348-linux.any.x86.tar.gz | sudo tar xzf - -C /opt && export RTT_EXEC_PATH=/opt/avr32-gnu-toolchain-linux_x86/bin && /opt/avr32-gnu-toolchain-linux_x86/bin/avr32-gcc --version && curl -sO http://www.atmel.com/images/avr-headers-3.2.3.970.zip && unzip -qq avr-headers-3.2.3.970.zip -d bsp/$RTT_BSP || true"
   - export RTT_ROOT=`pwd`
   - "[ x$RTT_CC == x ] && export RTT_CC='gcc' || true"
-  - git clone --depth 1 https://github.com/RT-Thread/RTGUI.git $HOME/RTGUI
-  - export RTT_RTGUI=$HOME/RTGUI/components/rtgui
 
 script:
   - scons -C bsp/$RTT_BSP

bsp/beaglebone/AM335x_sk_DDR3.mac

+// -----------------------------------------------------------------------
+// This file contains the initial set up configuration for the AM335x.
+//-------------------------------------------------------------------------
+
+__var clk_in;
+
+CHGBIT (addr, mask, data)
+{
+__var reg;
+	reg  = __readMemory32(addr, "Memory");
+	reg &= ~mask;
+	reg |=  data;
+  __writeMemory32(reg, addr, "Memory");
+}
+
+CLRBIT (addr, mask)
+{
+__var reg;
+	reg  = __readMemory32(addr, "Memory");
+	reg &= ~mask;
+  __writeMemory32(reg, addr, "Memory");
+}
+
+SETBIT (addr, mask)
+{
+__var reg;
+	reg  = __readMemory32(addr, "Memory");
+	reg |= mask;
+  __writeMemory32(reg, addr, "Memory");
+}
+
+TESTBIT (addr, mask)
+{
+	return(__readMemory32(addr, "Memory") & mask);
+}
+
+
+get_input_clock_frequency()
+{
+	__var temp;
+	
+	temp = __readMemory32(((0x44E10000) + 0x40), "Memory");
+	temp = temp >> 22;
+        temp = temp & 0x3;
+
+	if(temp == 0)
+	{	
+		clk_in = 19;  //19.2MHz
+		__message "Input Clock Read from SYSBOOT[15:14]:  19.2MHz\n";
+	}	
+	if(temp == 1)
+	{
+		clk_in = 24;  //24MHz
+		__message "Input Clock Read from SYSBOOT[15:14]:  24MHz\n";
+	}	
+	if(temp == 2)
+	{
+		clk_in = 25;  //25MHz
+		__message "Input Clock Read from SYSBOOT[15:14]:  25MHz\n";
+	}	
+	if(temp == 3)
+	{ 
+		clk_in = 26;  //26MHz
+		__message "Input Clock Read from SYSBOOT[15:14]:  26MHz\n";
+	}	
+}
+
+mpu_pll_config( clk_in,  N,  M,  M2)
+{
+	__var ref_clk,clk_out;
+	__var clkmode,clksel,div_m2,idlest_dpll;
+	__var temp,i;
+
+	ref_clk     = clk_in/(N+1);
+	clk_out     = (ref_clk*M)/M2;
+
+	clkmode=__readMemory32((0x44E00000 + 0x488), "Memory");
+	clksel= __readMemory32((0x44E00000 + 0x42C), "Memory");
+	div_m2= __readMemory32((0x44E00000 + 0x4A8), "Memory");
+
+	__message "****  Going to Bypass... \n";
+
+	//put the DPLL in bypass mode
+	__writeMemory32(0x4, (0x44E00000 + 0x488), "Memory");
+
+	while(((__readMemory32((0x44E00000 + 0x420), "Memory") & 0x101) != 0x00000100)); //wait for bypass status
+
+	__message "****  Bypassed, changing values... \n";
+
+	//set multiply and divide values
+	clksel = clksel & (~0x7FFFF);
+	clksel = clksel | ((M <<0x8) | N);
+	__writeMemory32(clksel, (0x44E00000 + 0x42C), "Memory");
+	div_m2 = div_m2 & ~0x1F;
+	div_m2 = div_m2 | M2;  
+	__writeMemory32(div_m2, (0x44E00000 + 0x4A8), "Memory");
+
+	__message "****  Locking ARM PLL\n";
+
+	//now lock the DPLL
+	clkmode = clkmode | 0x7;  //enables lock mode
+	__writeMemory32(clkmode, (0x44E00000 + 0x488), "Memory");
+	while(((__readMemory32((0x44E00000 + 0x420), "Memory") & 0x101) != 0x1)); //wait for lock
+}
+
+
+core_pll_config( clk_in,  N,  M,  M4,  M5,  M6)
+{
+	__var ref_clk,clk_out4,clk_out5,clk_out6;
+	__var clkmode,clksel,div_m4,div_m5,div_m6,idlest_dpll;
+
+	ref_clk     = clk_in/(N+1);
+	clk_out4     = (ref_clk*M)/M4;  //M4=200MHz
+	clk_out5     = (ref_clk*M)/M5;  //M5=250MHz
+	clk_out6     = (ref_clk*M)/M6;  //M6=500MHz
+
+	clkmode= __readMemory32((0x44E00000 + 0x490), "Memory");
+	clksel= __readMemory32((0x44E00000 + 0x468), "Memory");
+	div_m4= __readMemory32((0x44E00000 + 0x480), "Memory"); 
+	div_m5= __readMemory32((0x44E00000 + 0x484), "Memory"); 
+	div_m6= __readMemory32((0x44E00000 + 0x4D8), "Memory"); 
+
+	//put DPLL in bypass mode
+	clkmode = (clkmode & 0xfffffff8)|0x00000004;
+	__writeMemory32(clkmode, (0x44E00000 + 0x490), "Memory");
+	while((__readMemory32((0x44E00000 + 0x45C),  "Memory") & 0x00000100 )!=0x00000100); //wait for bypass status
+
+	__message "****  Core Bypassed\n";
+
+	//set multiply and divide values
+	clksel = clksel & (~0x7FFFF);
+	clksel = clksel | ((M <<0x8) | N);
+	__writeMemory32(clksel, (0x44E00000 + 0x468), "Memory");
+	div_m4= M4;   //200MHz
+	__writeMemory32(div_m4, (0x44E00000 + 0x480), "Memory");
+	div_m5=  M5;  //250MHz
+	__writeMemory32(div_m5, (0x44E00000 + 0x484), "Memory");
+	div_m6=  M6;  //500MHz
+	__writeMemory32(div_m6, (0x44E00000 + 0x4D8), "Memory");
+
+	__message "****  Now locking Core...\n";
+
+	//now lock the PLL
+	clkmode =(clkmode&0xfffffff8)|0x00000007;
+	__writeMemory32(clkmode, (0x44E00000 + 0x490), "Memory");
+
+	while((__readMemory32((0x44E00000 + 0x45C), "Memory") & 0x00000001 )!=0x00000001);
+	__message "****  Core locked\n";
+}
+
+ddr_pll_config( clk_in,  N,  M,  M2)
+{
+	__var ref_clk,clk_out ;
+	__var clkmode,clksel,div_m2,idlest_dpll;                
+
+	ref_clk     = clk_in/(N+1);
+	clk_out     = (ref_clk*M)/M2;
+
+	clkmode=__readMemory32((0x44E00000 + 0x494), "Memory");
+	clksel= __readMemory32((0x44E00000 + 0x440), "Memory");
+	div_m2= __readMemory32((0x44E00000 + 0x4A0), "Memory");
+
+	clkmode =(clkmode&0xfffffff8)|0x00000004;
+	__writeMemory32(clkmode, (0x44E00000 + 0x494), "Memory");
+	while((__readMemory32((0x44E00000 + 0x434), "Memory") & 0x00000100 )!=0x00000100);
+
+	__message "****  DDR DPLL Bypassed\n";
+
+	clksel = clksel & (~0x7FFFF);
+	clksel = clksel | ((M <<0x8) | N);
+	__writeMemory32(clksel, (0x44E00000 + 0x440), "Memory");
+	div_m2 = __readMemory32((0x44E00000 + 0x4A0), "Memory");
+	div_m2 = (div_m2&0xFFFFFFE0) | M2;
+	__writeMemory32(div_m2, (0x44E00000 + 0x4A0), "Memory");
+	clkmode =(clkmode&0xfffffff8)|0x00000007;
+	__writeMemory32(clkmode, (0x44E00000 + 0x494), "Memory");
+
+	while((__readMemory32((0x44E00000 + 0x434), "Memory") & 0x00000001 )!=0x00000001);
+
+	__message "****  DDR DPLL Locked\n";
+}
+
+per_pll_config( clk_in,  N,  M,  M2)
+{
+	__var ref_clk,clk_out;
+	__var clkmode,clksel,div_m2,idlest_dpll;
+
+	ref_clk     = clk_in/(N+1);
+	clk_out     = (ref_clk*M)/M2;
+
+	clkmode=__readMemory32((0x44E00000 + 0x48C), "Memory");
+	clksel= __readMemory32((0x44E00000 + 0x49C), "Memory");
+	div_m2= __readMemory32((0x44E00000 + 0x4AC), "Memory");
+
+	clkmode =(clkmode&0xfffffff8)|0x00000004;
+	__writeMemory32(clkmode, (0x44E00000 + 0x48C), "Memory");
+	while((__readMemory32((0x44E00000 + 0x470), "Memory") & 0x00000100 )!=0x00000100);
+
+	__message "****  PER DPLL Bypassed\n";
+
+	clksel = clksel & (~0x7FFFF);
+	clksel = clksel | ((M <<0x8) | N);
+	__writeMemory32(clksel, (0x44E00000 + 0x49C), "Memory");
+	div_m2= 0xFFFFFF80 | M2;
+	__writeMemory32(div_m2, (0x44E00000 + 0x4AC), "Memory");
+	clkmode =(clkmode&0xfffffff8)|0x00000007;
+	__writeMemory32(clkmode,(0x44E00000 + 0x48C), "Memory");
+
+	while((__readMemory32((0x44E00000 + 0x470), "Memory") & 0x00000001 )!=0x00000001);
+
+	__message "****  PER DPLL Locked\n";
+}
+
+disp_pll_config( clk_in,  N,  M,  M2)
+{
+	__var ref_clk,clk_out;
+	__var clkmode,clksel,div_m2,idlest_dpll;
+
+	__message "****  DISP PLL Config is in progress .......... \n";	
+
+	ref_clk     = clk_in/(N+1);
+	clk_out     = (ref_clk*M)/M2;
+
+	clkmode=__readMemory32((0x44E00000 + 0x498), "Memory");
+	clksel= __readMemory32((0x44E00000 + 0x454), "Memory");
+	div_m2= __readMemory32((0x44E00000 + 0x4A4), "Memory");
+
+	clkmode =(clkmode&0xfffffff8)|0x00000004;
+	__writeMemory32(clkmode, (0x44E00000 + 0x498), "Memory");
+	while((__readMemory32((0x44E00000 + 0x448), "Memory") & 0x00000100 )!=0x00000100);
+
+	clksel = clksel & (~0x7FFFF);
+	clksel = clksel | ((M <<0x8) | N);
+	__writeMemory32(clksel, (0x44E00000 + 0x454), "Memory");
+	div_m2= 0xFFFFFFE0 | M2;
+	__writeMemory32(div_m2, (0x44E00000 + 0x4A4), "Memory");
+	clkmode =(clkmode&0xfffffff8)|0x00000007;
+	__writeMemory32(clkmode, (0x44E00000 + 0x498), "Memory");
+
+	while((__readMemory32((0x44E00000 + 0x448), "Memory") & 0x00000001 )!=0x00000001);
+
+	__message "****  DISP PLL Config is DONE .......... \n";
+}
+
+arm_opp120_config()
+{
+	__message "****  Subarctic ALL ADPLL Config for OPP == OPP100 is In Progress ......... \n";
+    get_input_clock_frequency();
+
+    if (clk_in == 24)
+	{
+		mpu_pll_config(clk_in, 23, 550, 1);
+		core_pll_config(clk_in, 23, 1000, 10, 8, 4);
+		ddr_pll_config(clk_in, 23, 303, 1);
+		per_pll_config(clk_in, 23, 960, 5);
+		disp_pll_config(clk_in, 23, 48, 1);
+		__message "****  Subarctic ALL ADPLL Config for OPP == OPP100 is Done ......... \n";
+	}
+    else
+    {
+		__message "****  Subarctic PLL Config failed!!  Check SYSBOOT[15:14] for proper input freq config \n";
+    }
+
+}
+
+
+emif_prcm_clk_enable()
+{
+	   __message "EMIF PRCM is in progress ....... \n";
+
+   	   __writeMemory32(0x2, (0x44E00000 + 0x0D0), "Memory");
+       __writeMemory32(0x2, (0x44E00000 + 0x028), "Memory");
+   	   while(__readMemory32((0x44E00000 + 0x028), "Memory")!= 0x02);
+
+	   __message "EMIF PRCM Done \n";
+}
+
+vtp_enable()
+{
+      /* Write 1 to enable VTP */
+      __writeMemory32((__readMemory32(((0x44E10000) + 0x0E0C), "Memory") | 0x00000040),((0x44E10000) + 0x0E0C) , "Memory");
+      /* Write 0 to CLRZ bit */
+	  __writeMemory32((__readMemory32(((0x44E10000) + 0x0E0C), "Memory") & 0xFFFFFFFE),((0x44E10000) + 0x0E0C) ,"Memory");
+      /* Write 1 to CLRZ bit */
+      __writeMemory32((__readMemory32(((0x44E10000) + 0x0E0C), "Memory") | 0x00000001),((0x44E10000) + 0x0E0C) , "Memory");
+	  __message "Waiting for VTP Ready .......\n";
+	  while((__readMemory32(((0x44E10000) + 0x0E0C), "Memory") & 0x00000020) != 0x00000020);	 
+
+           __message "VTP Enable Done \n";
+}
+
+cmd_macro_config( REG_PHY_CTRL_SLAVE_RATIO_value, CMD_REG_PHY_CTRL_SLAVE_FORCE_value, CMD_REG_PHY_CTRL_SLAVE_DELAY_value, PHY_DLL_LOCK_DIFF_value, CMD_PHY_INVERT_CLKOUT_value)
+{
+	   __message "\DDR PHY CMD0 Register configuration is in progress ....... \n";
+
+	   __writeMemory32(REG_PHY_CTRL_SLAVE_RATIO_value, (0x01C + (0x44E12000)), "Memory");		     	
+       __writeMemory32(CMD_REG_PHY_CTRL_SLAVE_FORCE_value, (0x020 + (0x44E12000)), "Memory");                   	
+       __writeMemory32(CMD_REG_PHY_CTRL_SLAVE_DELAY_value, (0x024 + (0x44E12000)), "Memory");                   	
+	   __writeMemory32(PHY_DLL_LOCK_DIFF_value, (0x028 + (0x44E12000)), "Memory");   	             	
+	   __writeMemory32(CMD_PHY_INVERT_CLKOUT_value, (0x02C + (0x44E12000)), "Memory");
+
+	   __message "\DDR PHY CMD1 Register configuration is in progress ....... \n";
+
+	   __writeMemory32(REG_PHY_CTRL_SLAVE_RATIO_value, (0x050 + (0x44E12000)), "Memory");		     	
+       __writeMemory32(CMD_REG_PHY_CTRL_SLAVE_FORCE_value, (0x054 + (0x44E12000)), "Memory");                   	
+       __writeMemory32(CMD_REG_PHY_CTRL_SLAVE_DELAY_value, (0x058 + (0x44E12000)), "Memory");                   	
+	   __writeMemory32(PHY_DLL_LOCK_DIFF_value, (0x05C + (0x44E12000)), "Memory");   	             	
+	   __writeMemory32(CMD_PHY_INVERT_CLKOUT_value, (0x060 + (0x44E12000)), "Memory");
+
+	   __message "\DDR PHY CMD2 Register configuration is in progress ....... \n";
+
+	   __writeMemory32(REG_PHY_CTRL_SLAVE_RATIO_value, (0x084 + (0x44E12000)), "Memory");		     	
+       __writeMemory32(CMD_REG_PHY_CTRL_SLAVE_FORCE_value, (0x088 + (0x44E12000)), "Memory");                   	
+       __writeMemory32(CMD_REG_PHY_CTRL_SLAVE_DELAY_value, (0x08C + (0x44E12000)), "Memory");                   	
+	   __writeMemory32(PHY_DLL_LOCK_DIFF_value, (0x090 + (0x44E12000)), "Memory");   	             	
+	   __writeMemory32(CMD_PHY_INVERT_CLKOUT_value, (0x094 + (0x44E12000)), "Memory"); 	             	
+}
+
+data_macro_config( dataMacroNum, PHY_RD_DQS_SLAVE_RATIO_value, PHY_WR_DQS_SLAVE_RATIO_value, REG_PHY_WRLVL_INIT_RATIO_value,
+		   REG_PHY_GATELVL_INIT_RATIO_value, REG_PHY_FIFO_WE_SLAVE_RATIO_value, REG_PHY_WR_DATA_SLAVE_RATIO_value)
+{
+        __var offset;
+	if(dataMacroNum == 0)
+	{
+		offset = 0x00;
+		__message "DDR PHY DATA0 Register configuration is in progress ....... \n";
+	}
+	else if(dataMacroNum == 1)
+	{
+		offset = 0xA4;
+		__message "DDR PHY DATA1 Register configuration is in progress ....... \n";
+	}	  
+	
+	__writeMemory32(((PHY_RD_DQS_SLAVE_RATIO_value<<30)|(PHY_RD_DQS_SLAVE_RATIO_value<<20)|(PHY_RD_DQS_SLAVE_RATIO_value<<10)|(PHY_RD_DQS_SLAVE_RATIO_value<<0)), ((0x0C8 + (0x44E12000)) + offset), "Memory");
+	__writeMemory32(PHY_RD_DQS_SLAVE_RATIO_value>>2, ((0x0CC + (0x44E12000)) + offset), "Memory");
+
+    __writeMemory32(((PHY_WR_DQS_SLAVE_RATIO_value<<30)|(PHY_WR_DQS_SLAVE_RATIO_value<<20)|(PHY_WR_DQS_SLAVE_RATIO_value<<10)|(PHY_WR_DQS_SLAVE_RATIO_value<<0)), ((0x0DC + (0x44E12000)) + offset), "Memory");
+	__writeMemory32(PHY_WR_DQS_SLAVE_RATIO_value>>2, ((0x0E0 + (0x44E12000)) + offset), "Memory");
+
+	__writeMemory32(((REG_PHY_WRLVL_INIT_RATIO_value<<30)|(REG_PHY_WRLVL_INIT_RATIO_value<<20)|(REG_PHY_WRLVL_INIT_RATIO_value<<10)|(REG_PHY_WRLVL_INIT_RATIO_value<<0)), ((0x0F0 + (0x44E12000)) + offset), "Memory");
+	__writeMemory32(REG_PHY_WRLVL_INIT_RATIO_value>>2, ((0x0F4 + (0x44E12000)) + offset), "Memory");
+
+    __writeMemory32(((REG_PHY_GATELVL_INIT_RATIO_value<<30)|(REG_PHY_GATELVL_INIT_RATIO_value<<20)|(REG_PHY_GATELVL_INIT_RATIO_value<<10)|(REG_PHY_GATELVL_INIT_RATIO_value<<0)), ((0x0FC + (0x44E12000)) + offset), "Memory");
+	__writeMemory32(REG_PHY_GATELVL_INIT_RATIO_value>>2, ((0x100 + (0x44E12000)) + offset), "Memory");
+
+	__writeMemory32(((REG_PHY_FIFO_WE_SLAVE_RATIO_value<<30)|(REG_PHY_FIFO_WE_SLAVE_RATIO_value<<20)|(REG_PHY_FIFO_WE_SLAVE_RATIO_value<<10)|(REG_PHY_FIFO_WE_SLAVE_RATIO_value<<0)), ((0x108 + (0x44E12000)) + offset), "Memory");
+	__writeMemory32(REG_PHY_FIFO_WE_SLAVE_RATIO_value>>2,((0x10C + (0x44E12000)) + offset), "Memory");
+
+	__writeMemory32(((REG_PHY_WR_DATA_SLAVE_RATIO_value<<30)|(REG_PHY_WR_DATA_SLAVE_RATIO_value<<20)|(REG_PHY_WR_DATA_SLAVE_RATIO_value<<10)|(REG_PHY_WR_DATA_SLAVE_RATIO_value<<0)),((0x120 + (0x44E12000)) + offset), "Memory");
+	__writeMemory32(REG_PHY_WR_DATA_SLAVE_RATIO_value>>2, ((0x124 + (0x44E12000)) + offset), "Memory");	  
+	__writeMemory32(0x0,((0x138 + (0x44E12000)) + offset), "Memory");	  
+}
+
+
+emif_mmr_config( Read_Latency, Timing1, Timing2, Timing3, Sdram_Config, Ref_Ctrl)
+{
+	__var i;
+
+	__message "emif Timing register configuration is in progress ....... \n";
+	 
+	__writeMemory32(Read_Latency, (0x4C000000 + 0x0E4), "Memory");
+	__writeMemory32(Read_Latency, (0x4C000000 + 0x0E8), "Memory");
+	__writeMemory32(Read_Latency, (0x4C000000 + 0x0EC), "Memory");
+
+	__writeMemory32(Timing1, (0x4C000000 + 0x018), "Memory");
+	__writeMemory32(Timing1, (0x4C000000 + 0x01C), "Memory");
+
+	__writeMemory32(Timing2, (0x4C000000 + 0x020), "Memory");
+	__writeMemory32(Timing2, (0x4C000000 + 0x024), "Memory");
+
+	__writeMemory32(Timing3, (0x4C000000 + 0x028), "Memory");
+	__writeMemory32(Timing3, (0x4C000000 + 0x02C), "Memory");
+
+	__writeMemory32(Sdram_Config, (0x4C000000 + 0x008), "Memory");
+	__writeMemory32(Sdram_Config, (0x4C000000 + 0x00C), "Memory");
+	__writeMemory32(0x00004650, (0x4C000000 + 0x010), "Memory");
+	__writeMemory32(0x00004650, (0x4C000000 + 0x014), "Memory"); 
+
+	for(i=0;i<5000;i++)
+    {
+    }
+
+	__writeMemory32(Ref_Ctrl, (0x4C000000 + 0x010), "Memory");
+	__writeMemory32(Ref_Ctrl, (0x4C000000 + 0x014), "Memory"); 
+
+	__writeMemory32(Sdram_Config, (0x4C000000 + 0x008), "Memory");
+	__writeMemory32(Sdram_Config, (0x4C000000 + 0x00C), "Memory");
+
+	__message "emif Timing register configuration is done ....... \n";
+}
+
+gpio_module_clk_config()
+{
+   __var buff;
+
+   buff = __readMemory32((0x400 + 0x44E00000 + 0x8), "Memory");
+
+   buff |= 0x2;
+
+   __writeMemory32(buff, (0x400 + 0x44E00000 + 0x8), "Memory");
+
+   while((__readMemory32((0x400 + 0x44E00000 + 0x8), "Memory") & 0x3) != 0x2); 
+
+   buff = __readMemory32((0x400 + 0x44E00000 + 0x8), "Memory");
+
+   buff |= 0x00040000;
+
+   __writeMemory32(buff, (0x400 + 0x44E00000 + 0x8), "Memory");
+
+   while((__readMemory32((0x400 + 0x44E00000 + 0x8), "Memory") & 0x00040000) != 0x00040000);
+
+   while((__readMemory32((0x400 + 0x44E00000 + 0x8), "Memory") & 0x00030000) != 0x0);
+
+   while((__readMemory32((0x400 + 0x44E00000), "Memory") & 0x00000100) != 0x00000100);
+
+   __message "GPIO module clock configuration is done ....... \n";
+
+}
+
+phy_config_cmd()
+{
+    __var i;
+
+    for(i = 0; i < 3; i++)
+    {
+        __message "DDR PHY CMD Register configuration is in progress ....... \n";
+ 
+        __writeMemory32(0x40, ((0x44E12000 + 0x01c) + (i * 0x34)), "Memory");
+
+        __writeMemory32(0x1, ((0x44E12000 + 0x02c) + (i * 0x34)), "Memory");
+
+    }
+
+}
+
+phy_config_data()
+{
+    __var i;
+
+    for(i = 0; i < 2; i++)
+    {
+        __message "DDR PHY Data Register configuration is in progress ....... \n";
+
+        __writeMemory32(0x3B, ((0x44E12000 + 0x0c8) + (i * 0xA4)), "Memory");
+
+        __writeMemory32(0x85, ((0x44E12000 + 0x0DC) + (i * 0xA4)), "Memory");
+
+        __writeMemory32(0x100, ((0x44E12000 + 0x108) + (i * 0xA4)), "Memory");
+
+        __writeMemory32(0xC1, ((0x44E12000 + 0x120) + (i * 0xA4)), "Memory");
+
+    }
+
+}
+
+ddr3_emif_config()
+{
+        __message "****  AM335x OPP120 DDR3 EMIF and PHY configuration is in progress......... \n";
+
+	emif_prcm_clk_enable();
+
+	__message "DDR PHY Configuration In progress \n";
+
+        /* Perform GPIO module clock configuration. */
+        gpio_module_clk_config();
+
+        __writeMemory32(0x00000067, (0x44E10000 + 0x964), "Memory");
+
+        __writeMemory32((__readMemory32((0x44E07000 + 0x130), "Memory") & 0xFFFFFFFE), (0x44E07000 + 0x130), "Memory");
+
+        __writeMemory32((__readMemory32((0x44E07000 + 0x10), "Memory") | 0x02), (0x44E07000 + 0x10), "Memory");
+
+        /* Wait until GPIO module is reset. */
+
+        while(!(__readMemory32((0x44E07000 + 0x114), "Memory") & 0x01));
+
+        __writeMemory32((__readMemory32((0x44E07000 + 0x134), "Memory") & ~(1 << 7)), (0x44E07000 + 0x134), "Memory");
+
+        __writeMemory32((1 << 7), (0x44E07000 + 0x194), "Memory");
+
+        __writeMemory32((__readMemory32((0x44E10000 + 0x0E0C), "Memory") & 0xFFFFFFFE), (0x44E10000 + 0x0E0C), "Memory");
+
+        __writeMemory32((__readMemory32((0x44E10000 + 0x0E0C), "Memory") | 0x00000001), (0x44E10000 + 0x0E0C), "Memory");
+
+	vtp_enable(); 
+
+        phy_config_cmd();
+
+        phy_config_data();	
+
+        __writeMemory32(0x18B, (0x1404 + 0x44E10000), "Memory");
+        __writeMemory32(0x18B, (0x1408 + 0x44E10000), "Memory");
+        __writeMemory32(0x18B, (0x140C + 0x44E10000), "Memory");
+        __writeMemory32(0x18B, (0x1440 + 0x44E10000), "Memory");
+        __writeMemory32(0x18B, (0x1444 + 0x44E10000), "Memory");
+
+        __writeMemory32((__readMemory32((0x0E04 + 0x44E10000), "Memory") & ~0x10000000), (0x0E04 + 0x44E10000), "Memory");
+
+        __writeMemory32((__readMemory32((0x131C + 0x44E10000), "Memory") | 0x00000001), (0x131C + 0x44E10000), "Memory");
+
+        __message "EMIF Timing register configuration is in progress ....... \n";
+
+        __writeMemory32(0x06, (0x0E4 + 0x4C000000), "Memory");
+        __writeMemory32(0x06, (0x0E8 + 0x4C000000), "Memory");
+        __writeMemory32(0x06, (0x0EC + 0x4C000000), "Memory");
+
+        __writeMemory32(0x0888A39B, (0x018 + 0x4C000000), "Memory");
+        __writeMemory32(0x0888A39B, (0x01C + 0x4C000000), "Memory");
+
+        __writeMemory32(0x26337FDA, (0x020 + 0x4C000000), "Memory");
+        __writeMemory32(0x26337FDA, (0x024 + 0x4C000000), "Memory");
+
+        __writeMemory32(0x501F830F, (0x028 + 0x4C000000), "Memory");
+        __writeMemory32(0x501F830F, (0x02C + 0x4C000000), "Memory");
+
+        __writeMemory32(0x0000093B, (0x010 + 0x4C000000), "Memory");
+        __writeMemory32(0x0000093B, (0x014 + 0x4C000000), "Memory");
+
+        __writeMemory32(0x50074BE4, (0x0C8 + 0x4C000000), "Memory");
+
+        __writeMemory32(0x61C04AB2, (0x008 + 0x4C000000), "Memory");
+
+        __message "EMIF Timing register configuration is done ....... \n";
+
+        if((__readMemory32((0x4C000000 + 0x004), "Memory") & 0x4) == 0x4)
+        {
+            __message "PHY is READY!!\n";
+        }
+
+        __message "DDR PHY Configuration done \n";
+
+        __message "****  AM335x OPP120 DDR3 EMIF and PHY configuration is done......... \n";
+}
+
+am335x_evm_initialization()
+{
+__var psc_base;
+__var reg;
+__var module_offest;
+
+  __message " AM335x EVM-SK Initialization is in progress .......... \n";
+  arm_opp120_config();
+  ddr3_emif_config();
+  __message " AM335x EVM-SK Initialization is done .......... \n";
+}
+
+execUserPreload()
+{
+	am335x_evm_initialization();
+}
+

bsp/beaglebone/am335x_DDR.icf

+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x82000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x82000000;
+define symbol __ICFEDIT_region_ROM_end__     = 0x87FFFFFF;
+define symbol __ICFEDIT_region_RAM_start__   = 0x88000000;
+define symbol __ICFEDIT_region_RAM_end__     = 0x8FFFFFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__   = 0x100;
+define symbol __ICFEDIT_size_svcstack__ = 0x1000;
+define symbol __ICFEDIT_size_irqstack__ = 0x100;
+define symbol __ICFEDIT_size_fiqstack__ = 0x100;
+define symbol __ICFEDIT_size_undstack__ = 0x100;
+define symbol __ICFEDIT_size_abtstack__ = 0x100;
+define symbol __ICFEDIT_size_heap__     = 0x400;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+keep { section FSymTab };
+keep { section VSymTab };
+keep { section .rti_fn* };
+
+place at address mem :__ICFEDIT_intvec_start__ {readonly section .intvec};
+
+place in ROM_region  { readonly };
+place in RAM_region  { readwrite,
+                        block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
+                        block UND_STACK, block ABT_STACK, block HEAP };

bsp/beaglebone/am335x_sk.eww

+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\am335x_sk.ewp</path>
+  </project>
+</workspace>
+
+

bsp/beaglebone/applications/startup.c

@@ -10,6 +10,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2012-12-05     Bernard      the first version
+ * 2015-11-11     zchong     support iar compiler
  */
 
 #include <rthw.h>
@@ -18,7 +19,9 @@
 #include <board.h>
 
 extern int  rt_application_init(void);
-
+#ifdef __ICCARM__
+#pragma section="HEAP"
+#endif
 /**
  * This function will startup RT-Thread RTOS.
  */
@@ -34,7 +37,11 @@ void rtthread_startup(void)
 
 	/* initialize memory system */
 #ifdef RT_USING_HEAP
+#ifdef __ICCARM__
+rt_system_heap_init(__segment_end("HEAP"), (void*)0x8FFFFFFF);
+#else
     rt_system_heap_init(HEAP_BEGIN, HEAP_END);
+#endif
 #endif
 
 	/* initialize scheduler system */

bsp/beaglebone/drivers/serial.c → bsp/beaglebone/drivers/uart.c

@@ -19,8 +19,8 @@
 
 #include <am33xx.h>
 #include <interrupt.h>
-#include "serial.h"
-#include "serial_reg.h"
+#include "uart.h"
+#include "uart_reg.h"
 
 struct am33xx_uart
 {

bsp/beaglebone/rtconfig.h

@@ -127,7 +127,7 @@
 // <bool name="RT_USING_LIBC" description="Using C library" default="true" />
 #define RT_USING_LIBC
 // <bool name="RT_USING_PTHREADS" description="Using POSIX threads library" default="true" />
-#define RT_USING_PTHREADS
+//#define RT_USING_PTHREADS
 // </section>
 
 // <section name="RT_USING_DFS" description="Device file system" default="true" >

bsp/dm365/rtconfig.py

@@ -33,7 +33,7 @@ if PLATFORM == 'gcc':
     DEVICE = ' -mcpu=arm926ej-s'
     CFLAGS = DEVICE
     AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + ' -DTEXT_BASE=' + TextBase
-    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread_dm365.map,-cref,-u,_start -T dm365_ram.ld' + ' -Ttext ' + TextBase
+    LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread_dm365.map,-cref,-u,_start -T dm365_ram.ld' + ' -Ttext ' + TextBase
 
     CPATH = ''
     LPATH = ''

bsp/lpc176x/drivers/uart.c

@@ -60,7 +60,8 @@ void UART0_IRQHandler(void)
 {
     rt_ubase_t level, iir;
     struct rt_uart_lpc *uart = &uart_device;
-
+	/* enter interrupt */ 
+ 	rt_interrupt_enter();
     /* read IIR and clear it */
     iir = LPC_UART->IIR;
 
@@ -94,7 +95,8 @@ void UART0_IRQHandler(void)
     {
         iir = LPC_UART->LSR;    //oe pe fe oe read for clear interrupt
     }
-
+	/* leave interrupt */ 
+ 	rt_interrupt_leave();
     return;
 }
 

bsp/nrf51822/applications/startup.c

@@ -28,13 +28,13 @@ extern int  rt_application_init(void);
 
 #ifdef __CC_ARM
 extern int Image$$RW_IRAM1$$ZI$$Limit;
-#define NRF_SRAM_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
+#define NRF_HEAP_BEGIN    (&Image$$RW_IRAM1$$ZI$$Limit)
 #elif __ICCARM__
 #pragma section="HEAP"
-#define NRF_SRAM_BEGIN    (__segment_end("HEAP"))
+#define NRF_HEAP_BEGIN    (__segment_end("HEAP"))
 #else
 extern int __bss_end;
-#define NRF_SRAM_BEGIN    (&__bss_end)
+#define NRF_HEAP_BEGIN    (&__bss_end)
 #endif
 
 /**
@@ -58,7 +58,7 @@ void rtthread_startup(void)
     rt_system_timer_init();
 
 #ifdef RT_USING_HEAP
-    rt_system_heap_init((void*)NRF_SRAM_BEGIN, (void*)NRF_SRAM_END);
+    rt_system_heap_init((void*)NRF_HEAP_BEGIN, (void*)NRF_SRAM_END);
 #endif
 
     /* init scheduler system */

bsp/nrf51822/drivers/board.h

@@ -12,6 +12,12 @@
 #ifndef __BOARD_H__
 #define __BOARD_H__
 
+// <o> Internal SRAM memory size[Kbytes] <16 or 32>
+//  <i>Default: 16
+#define NRF_SRAM_BEGIN	(0x20000000)
+#define NRF_SRAM_SIZE	(16 * 1024)
+#define NRF_SRAM_END	(NRF_SRAM_BEGIN + NRF_SRAM_SIZE)
+//#endif
 
 
 void rt_hw_board_init(void);

bsp/nrf51822/rtconfig.h

@@ -49,10 +49,10 @@
 
 /* SECTION: Memory Management */
 /* Using Memory Pool Management*/
-/* #define RT_USING_MEMPOOL */
+#define RT_USING_MEMPOOL
 
 /* Using Dynamic Heap Management */
-//#define RT_USING_HEAP
+#define RT_USING_HEAP
 
 /* Using Small MM */
 #define RT_USING_SMALL_MEM

bsp/nrf52832/Libraries/CMSIS/Include/arm_common_tables.h

+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. October 2015
+* $Revision: 	V.1.4.5 a
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_common_tables.h
+*
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+/* extern const q31_t realCoefAQ31[1024]; */
+/* extern const q31_t realCoefBQ31[1024]; */
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20  )
+#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48  )
+#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
+#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12  )
+#define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24  )
+#define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56  )
+#define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
+#define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
+#define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */

bsp/nrf52832/Libraries/CMSIS/Include/arm_const_structs.h

+/* ----------------------------------------------------------------------
+* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
+*
+* $Date:        19. March 2015
+* $Revision: 	V.1.4.5
+*
+* Project: 	    CMSIS DSP Library
+* Title:	    arm_const_structs.h
+*
+* Description:	This file has constant structs that are initialized for
+*              user convenience.  For example, some can be given as
+*              arguments to the arm_cfft_f32() function.
+*
+* Target Processor: Cortex-M4/Cortex-M3
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*   - Redistributions of source code must retain the above copyright
+*     notice, this list of conditions and the following disclaimer.
+*   - Redistributions in binary form must reproduce the above copyright
+*     notice, this list of conditions and the following disclaimer in
+*     the documentation and/or other materials provided with the
+*     distribution.
+*   - Neither the name of ARM LIMITED nor the names of its contributors
+*     may be used to endorse or promote products derived from this
+*     software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+* -------------------------------------------------------------------- */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif

bsp/nrf52832/Libraries/CMSIS/Include/core_cmFunc.h

+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+#endif /* __CORE_CMFUNC_H */

bsp/nrf52832/Libraries/CMSIS/Include/core_cmInstr.h

+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */

bsp/nrf52832/Libraries/CMSIS/Include/core_cmSimd.h

+/**************************************************************************//**
+ * @file     core_cmSimd.h
+ * @brief    CMSIS Cortex-M SIMD Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CMSIMD_H
+#define __CORE_CMSIMD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+/*------------------ RealView Compiler -----------------*/
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+/*------------------ ARM Compiler V6 -------------------*/
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armcc_V6.h"
+
+/*------------------ GNU Compiler ----------------------*/
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+/*------------------ ICC Compiler ----------------------*/
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iar.h>
+
+/*------------------ TI CCS Compiler -------------------*/
+#elif defined ( __TMS470__ )
+  #include <cmsis_ccs.h>
+
+/*------------------ TASKING Compiler ------------------*/
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+/*------------------ COSMIC Compiler -------------------*/
+#elif defined ( __CSMC__ )
+  #include <cmsis_csm.h>
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CMSIMD_H */

bsp/nrf52832/Libraries/SConscript

+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+src = Split("""
+nrf52832/Source/templates/system_nrf52.c
+""")
+
+#add for Startup script 
+if rtconfig.CROSS_TOOL == 'gcc':
+     src = src + ['nrf52832/Source/templates/arm/gcc_startup_nrf52.s']
+elif rtconfig.CROSS_TOOL == 'keil':
+     src = src + ['nrf52832/Source/templates/arm/arm_startup_nrf52.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+     src = src + ['nrf52832/Source/templates/arm/iar_startup_nrf52.s']
+
+path = [cwd + '/CMSIS/Include',
+        cwd + '/nrf52832/Include']
+
+CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'NRF52']
+group = DefineGroup('Startup Code', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/nrf52832/Libraries/nrf52832/Include/nrf.h

+/* Copyright (c) 2015, Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright notice, this
+ *     list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright notice,
+ *     this list of conditions and the following disclaimer in the documentation
+ *     and/or other materials provided with the distribution.
+ *
+ *   * Neither the name of Nordic Semiconductor ASA nor the names of its
+ *     contributors may be used to endorse or promote products derived from
+ *     this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef NRF_H
+#define NRF_H
+
+#if defined(_WIN32)         
+    /* Do not include nrf51 specific files when building for PC host */
+#elif defined(__unix)       
+    /* Do not include nrf51 specific files when building for PC host */
+#elif defined(__APPLE__)    
+    /* Do not include nrf51 specific files when building for PC host */
+#else
+
+    /* Family selection for family includes. */
+    #if defined (NRF51)
+        #include "nrf51.h"
+        #include "nrf51_bitfields.h"
+        #include "nrf51_deprecated.h"
+    #elif defined (NRF52)
+        #include "nrf52.h"
+        #include "nrf52_bitfields.h"
+        #include "nrf51_to_nrf52.h"
+    #else
+        #error "Device family must be defined. See nrf.h."
+    #endif /* NRF51, NRF52 */
+
+    #include "compiler_abstraction.h"
+
+#endif /* _WIN32 || __unix || __APPLE__ */
+
+#endif /* NRF_H */
+

bsp/nrf52832/applications/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/nrf52832/drivers/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+src	= Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

libcpu/arm/am335x/cpu.c

@@ -92,6 +92,8 @@ rt_inline void cache_disable(rt_uint32_t bit)
 }
 #endif
 
+
+#if defined(__CC_ARM)|(__GNUC__)
 /**
  * enable I-Cache
  *
@@ -145,6 +147,7 @@ rt_base_t rt_hw_cpu_dcache_status()
 {
 	return (cp15_rd() & DCACHE_MASK);
 }
+#endif
 
 /**
  *  shutdown CPU