add LPC1114 support

bsp/lpc1114/.config

+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+# CONFIG_RT_USING_OVERFLOW_CHECK is not set
+# CONFIG_RT_USING_HOOK is not set
+# CONFIG_RT_USING_IDLE_HOOK is not set
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+# CONFIG_RT_DEBUG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
+CONFIG_RT_VER_NUM=0x40001
+CONFIG_ARCH_ARM=y
+CONFIG_ARCH_ARM_CORTEX_M=y
+CONFIG_ARCH_ARM_CORTEX_M0=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=512
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+# CONFIG_RT_USING_FINSH is not set
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=128
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_MTD is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+
+#
+# Using WiFi
+#
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+CONFIG_RT_USING_LIBC=y
+# CONFIG_RT_USING_PTHREADS is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# Modbus master and slave stack
+#
+# CONFIG_RT_USING_MODBUS is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_LWP is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+
+#
+# sample package
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# example package: hello
+#
+# CONFIG_PKG_USING_HELLO is not set
+CONFIG_SOC_LPC1114=y

bsp/lpc1114/Kconfig

+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+# you can change the RTT_ROOT default "../.." to your rtthread_root,
+# example : default "F:/git_repositories/rt-thread"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_LPC1114
+    bool 
+    select ARCH_ARM_CORTEX_M0
+    default y
+
+#source "$BSP_DIR/drivers/Kconfig"

bsp/lpc1114/SConscript

+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/lpc1114/SConstruct

+import os
+import sys
+import rtconfig
+
+from rtconfig import RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CC, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/lpc1114/applications/SConscript

+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/lpc1114/applications/main.c

+/*
+ * Copyright (c) 2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-05-05     jg1uaa       the first version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+
+/* for Z111xP board (LED is connected to PIO3_5, low=ON) */
+#define IOCON_PIO3_5    HWREG32(0x40044048)
+#define GPIO3DIR        HWREG32(0x50038000)
+#define GPIO3DATA_5     HWREG32(0x50030080)
+
+static void led_off(void)
+{
+    GPIO3DATA_5 = 0x20;
+}
+
+static void led_on(void)
+{
+    GPIO3DATA_5 = 0x00;
+}
+
+static void led_setup(void)
+{
+    IOCON_PIO3_5 = 0xd0;        // (default)
+    GPIO3DIR = 0x20;            // select output
+    led_off();
+}
+
+static void led_demo(void)
+{
+    led_setup();
+
+    while (1) {
+        led_on();
+        rt_thread_delay(50);    // 500msec, tick@100Hz
+        led_off();
+        rt_thread_delay(50);
+    }
+}
+
+int main(int argc, char **argv)
+{
+    rt_kprintf("Hello, world!\n");
+
+    led_demo();
+
+    /* NOTREACHED */
+    return 0;
+}

bsp/lpc1114/driver/SConscript

+from building import *
+
+cwd  = GetCurrentDir()
+src  = Glob('*.[cs]')
+list = os.listdir(cwd)
+CPPPATH = [cwd]
+objs = []
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+objs = objs + group
+Return('objs')

bsp/lpc1114/driver/board.c

+/*
+ * Copyright (c) 2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-05-05     jg1uaa       the first version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "board.h"
+#include "drv_uart.h"
+
+#define SYSCON_BASE     0x40048000
+#define MEMMAP          HWREG32(SYSCON_BASE + 0x000)
+#define SYSPLLCTRL      HWREG32(SYSCON_BASE + 0x008)
+#define SYSPLLSTAT      HWREG32(SYSCON_BASE + 0x00c)
+#define SYSPLLCLKSEL    HWREG32(SYSCON_BASE + 0x040)
+#define SYSPLLCLKUEN    HWREG32(SYSCON_BASE + 0x044)
+#define MAINCLKSEL      HWREG32(SYSCON_BASE + 0x070)
+#define MAINCLKUEN      HWREG32(SYSCON_BASE + 0x074)
+#define AHBCLKCTRL      HWREG32(SYSCON_BASE + 0x080)
+#define PDRUNCFG        HWREG32(SYSCON_BASE + 0x238)
+
+#define SCB_BASE        0xe000e000
+#define SYST_CSR        HWREG32(SCB_BASE + 0x010)
+#define SYST_RVR        HWREG32(SCB_BASE + 0x014)
+#define NVIC_ISER       HWREG32(SCB_BASE + 0x100)
+#define NVIC_ICER       HWREG32(SCB_BASE + 0x180)
+#define NVIC_ISPR       HWREG32(SCB_BASE + 0x200)
+#define NVIC_ICPR       HWREG32(SCB_BASE + 0x280)
+#define NVIC_IPR(irqno) HWREG32(SCB_BASE + 0x400 + (((irqno) / 4) << 2))
+#define SCB_SHPR3       HWREG32(SCB_BASE + 0xd20) 
+
+extern unsigned char __bss_end__[];
+extern unsigned char _ram_end[];
+
+/**
+ * This is the timer interrupt service routine.
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void os_clock_init(void)
+{
+    /* bump up system clock 12MHz to 48MHz, using IRC (internal RC) osc. */
+
+    MAINCLKSEL = 0;             // main clock: IRC @12MHz (default, for safety)
+    MAINCLKUEN = 0;
+    MAINCLKUEN = 1;
+
+    PDRUNCFG &= ~0x80;           // power up System PLL
+
+    SYSPLLCLKSEL = 0;           // PLL clock source: IRC osc
+    SYSPLLCLKUEN = 0;
+    SYSPLLCLKUEN = 1;
+
+    SYSPLLCTRL = 0x23;          // Fcco = 2 x P x FCLKOUT
+                                //  192MHz = 2 x 2 x 48MHz
+                                // M = FCLKOUT / FCLKIN
+                                //  4 = 48MHz / 12MHz
+
+    while (!(SYSPLLSTAT & 1));  // wait for lock PLL
+
+    MAINCLKSEL = 3;             // main clock: system PLL
+    MAINCLKUEN = 0;
+    MAINCLKUEN = 1;
+
+    AHBCLKCTRL |= (1 << 16);    // power up IOCON
+}
+
+void SysTick_init(void)
+{
+    rt_uint32_t shpr3;
+
+    /* set SysTick interrupt priority */
+    shpr3 = SCB_SHPR3;
+    shpr3 &= ~0xff000000;
+    shpr3 |= 0x40 << 24;
+    SCB_SHPR3 = shpr3;
+
+    /* start SysTick */
+    SYST_CSR = 0x06;    // Clock source:Core, SysTick Exception:enable
+    SYST_RVR = (CPU_CLOCK / RT_TICK_PER_SECOND) - 1;
+    SYST_CSR = 0x07;    // Counter:enable
+}
+
+/**
+ * This function initializes LPC1114 SoC.
+ */
+void rt_hw_board_init(void)
+{
+    os_clock_init();
+
+    /* init SysTick */
+    SysTick_init();
+
+#ifdef RT_USING_HEAP
+    /* initialize system heap */
+    rt_system_heap_init((void *)&__bss_end__, (void *)&_ram_end);
+#endif
+    /* initialize uart */
+    rt_hw_uart_init();
+
+#ifdef RT_USING_CONSOLE
+    /* set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+/**
+ * Enable External Interrupt
+ */
+void NVIC_EnableIRQ(rt_int32_t irqno)
+{
+    NVIC_ISER = 1UL << (irqno & 0x1f);
+}
+
+/**
+ * Disable External Interrupt
+ */
+void NVIC_DisableIRQ(rt_int32_t irqno)
+{
+    NVIC_ICER = 1UL << (irqno & 0x1f);
+}
+
+/**
+ * Get Pending Interrupt
+ *      Different from CMSIS implementation,
+ *      returns zero/non-zero, not zero/one.
+ */
+rt_uint32_t NVIC_GetPendingIRQ(rt_int32_t irqno)
+{
+    return NVIC_ISPR & (1UL << (irqno & 0x1f));
+}
+
+/**
+ * Set Pending Interrupt
+ */
+void NVIC_SetPendingIRQ(rt_int32_t irqno)
+{
+    NVIC_ISPR = 1UL << (irqno & 0x1f);
+}
+
+/**
+ * Clear Pending Interrupt
+ */
+void NVIC_ClearPendingIRQ(rt_int32_t irqno)
+{
+    NVIC_ICPR = 1UL << (irqno & 0x1f);
+}
+
+/**
+ * Set Interrupt Priority
+ *      Different from CMSIS implementation,
+ *      this code supports only external (device specific) interrupt.
+ */
+void NVIC_SetPriority(rt_int32_t irqno, rt_uint32_t priority)
+{
+    rt_uint32_t shift, ipr;
+
+    shift = (irqno % 4) * 8;
+    ipr = NVIC_IPR(irqno);
+    ipr &= ~(0xffUL << shift);
+    ipr |= (priority & 0xff) << shift;
+    NVIC_IPR(irqno) = ipr;
+}

bsp/lpc1114/driver/board.h

+/*
+ * Copyright (c) 2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-05-05     jg1uaa       the first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#define CPU_CLOCK       48000000        // Hz
+
+void rt_hw_board_init(void);
+
+void NVIC_EnableIRQ(rt_int32_t irqno);
+void NVIC_DisableIRQ(rt_int32_t irqno);
+rt_uint32_t NVIC_GetPendingIRQ(rt_int32_t irqno);
+void NVIC_SetPendingIRQ(rt_int32_t irqno);
+void NVIC_ClearPendingIRQ(rt_int32_t irqno);
+void NVIC_SetPriority(rt_int32_t irqno, rt_uint32_t priority);
+
+#endif /* __BOARD_H__ */

bsp/lpc1114/driver/drv_uart.c

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-05-18     Bernard      The first version for LPC40xx
+ * 2019-05-05     jg1uaa       port to LPC1114
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include "board.h"      // CPU_CLOCK
+#include "drv_uart.h"
+
+#ifdef RT_USING_SERIAL
+
+#define UART_BASE       0x40008000              // UART (only one)
+#define UART_IRQ        21
+#define UART_CLOCK      (CPU_CLOCK / 1)         // Hz
+
+#define URBR            HWREG32(UART_BASE + 0x00)       // R-
+#define UTHR            HWREG32(UART_BASE + 0x00)       // -W
+#define UIER            HWREG32(UART_BASE + 0x04)       // RW
+#define UIIR            HWREG32(UART_BASE + 0x08)       // R-
+#define UFCR            HWREG32(UART_BASE + 0x08)       // -W
+#define ULCR            HWREG32(UART_BASE + 0x0c)       // RW
+#define UMCR            HWREG32(UART_BASE + 0x10)       // RW
+#define ULSR            HWREG32(UART_BASE + 0x14)       // R-
+#define UMSR            HWREG32(UART_BASE + 0x18)       // R-
+
+#define UDLL            HWREG32(UART_BASE + 0x00)       // RW
+#define UDLM            HWREG32(UART_BASE + 0x04)       // RW
+
+#define IOCONFIG_BASE   0x40044000
+#define IOCON_PIO1_6    HWREG32(IOCONFIG_BASE + 0xa4)
+#define IOCON_PIO1_7    HWREG32(IOCONFIG_BASE + 0xa8)
+
+#define SYSCON_BASE     0x40048000
+#define AHBCLKCTRL      HWREG32(SYSCON_BASE + 0x80)
+#define UARTCLKDIV      HWREG32(SYSCON_BASE + 0x98)
+
+static rt_err_t lpc_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    rt_uint32_t Fdiv = 0;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    /* Initialize UART Configuration parameter structure to default state:
+     * Baudrate = 115200 bps
+     * 8 data bit
+     * 1 Stop bit
+     * None parity
+     */
+    /* set DLAB=1 */
+    ULCR |= 0x80;
+    /* config uart baudrate */
+    Fdiv = UART_CLOCK / (cfg->baud_rate * 16);
+    UDLM = Fdiv / 256;
+    UDLL = Fdiv % 256;
+    /* set DLAB=0 */
+    ULCR &= ~0x80;
+    /* config to 8 data bit,1 Stop bit,None parity */
+    ULCR |= 0x03;
+
+    /*enable and reset FIFO*/
+    UFCR = 0x07;
+
+    return RT_EOK;
+}
+
+static rt_err_t lpc_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    RT_ASSERT(serial != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        UIER &= ~0x01;
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        UIER |= 0x01;
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int lpc_putc(struct rt_serial_device *serial, char c)
+{
+    while (!(ULSR & 0x20));
+    UTHR = c;
+
+    return 1;
+}
+
+static int lpc_getc(struct rt_serial_device *serial)
+{
+    if (ULSR & 0x01)
+        return URBR;
+    else
+        return -1;
+}
+
+static const struct rt_uart_ops lpc_uart_ops =
+{
+    lpc_configure,
+    lpc_control,
+    lpc_putc,
+    lpc_getc,
+};
+
+struct rt_serial_device serial;
+
+void UART_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    switch (UIIR & 0x0e)
+    {
+    case 0x04:
+    case 0x0C:
+        rt_hw_serial_isr(&serial, RT_SERIAL_EVENT_RX_IND);
+        break;
+    case 0x06:
+        (void)ULSR;
+        break;
+    default:
+        (void)ULSR;
+        break;
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+int rt_hw_uart_init(void)
+{
+    rt_err_t ret = RT_EOK;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+    serial.ops    = &lpc_uart_ops;
+    serial.config = config;
+    serial.parent.user_data = NULL;
+
+    /*
+     * Initialize UART pin connect
+     * P1.6: U0_RXD
+     * P1.7: U0_TXD
+     */
+    IOCON_PIO1_6 = 0xc1;
+    IOCON_PIO1_7 = 0xc1;
+
+    /* setup the uart power and clock */
+    UARTCLKDIV = 0x01;          // UART PCLK = system clock / 1
+    AHBCLKCTRL |= (1 << 12);    // UART power-up
+
+    /* priority = 1 */
+    NVIC_SetPriority(UART_IRQ, 0x01 << 6);
+
+    /* Enable Interrupt for UART channel */
+    NVIC_EnableIRQ(UART_IRQ);
+
+    /* register UART device */
+    ret = rt_hw_serial_register(&serial, "uart",
+                                RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+                                NULL);
+
+    return ret;
+}
+INIT_BOARD_EXPORT(rt_hw_uart_init);
+
+#endif /* RT_USING_SERIAL */

bsp/lpc1114/driver/drv_uart.h

+/*
+ * Copyright (c) 2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-05-05     jg1uaa       the first version
+ */
+
+#ifndef __DRV_UART_H__
+#define __DRV_UART_H__
+
+int rt_hw_uart_init(void);
+
+#endif

bsp/lpc1114/driver/startup_gcc.s

+/*
+ * Copyright (c) 2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-05-05     jg1uaa       the first version
+ */
+
+#include "../rtconfig.h"
+
+/* Interrupt Vectors */
+        .section .isr_vector
+        .thumb
+        .align 0
+
+        .long   _estack                 // MSP default value
+        .long   Reset_Handler + 1       //  1: Reset
+        .long   default_handler + 1     //  2: NMI
+        .long   HardFault_Handler + 1   //  3: HardFault
+        .long   default_handler + 1     //  4: reserved
+        .long   default_handler + 1     //  5: reserved
+        .long   default_handler + 1     //  6: reserved
+        .long   default_handler + 1     //  7: reserved
+        .long   default_handler + 1     //  8: reserved
+        .long   default_handler + 1     //  9: reserved
+        .long   default_handler + 1     // 10: reserved
+        .long   default_handler + 1     // 11: SVCall
+        .long   default_handler + 1     // 12: reserved
+        .long   default_handler + 1     // 13: reserved
+        .long   PendSV_Handler + 1     // 14: PendSV
+        .long   SysTick_Handler + 1     // 15: SysTick
+        .long   default_handler + 1     // 16: External Interrupt(0)
+        .long   default_handler + 1     // 17: External Interrupt(1)
+        .long   default_handler + 1     // 18: External Interrupt(2)
+        .long   default_handler + 1     // 19: External Interrupt(3)
+        .long   default_handler + 1     // 20: External Interrupt(4)
+        .long   default_handler + 1     // 21: External Interrupt(5)
+        .long   default_handler + 1     // 22: External Interrupt(6)
+        .long   default_handler + 1     // 23: External Interrupt(7)
+        .long   default_handler + 1     // 24: External Interrupt(8)
+        .long   default_handler + 1     // 25: External Interrupt(9)
+        .long   default_handler + 1     // 26: External Interrupt(10)
+        .long   default_handler + 1     // 27: External Interrupt(11)
+        .long   default_handler + 1     // 28: External Interrupt(12)
+        .long   default_handler + 1     // 29: External Interrupt(13) C_CAN
+        .long   default_handler + 1     // 30: External Interrupt(14) SPI/SSP1
+        .long   default_handler + 1     // 31: External Interrupt(15) I2C
+        .long   default_handler + 1     // 32: External Interrupt(16) CT16B0
+        .long   default_handler + 1     // 33: External Interrupt(17) CT16B1
+        .long   default_handler + 1     // 34: External Interrupt(18) CT32B0
+        .long   default_handler + 1     // 35: External Interrupt(19) CT32B1
+        .long   default_handler + 1     // 36: External Interrupt(20) SPI/SSP0
+        .long   UART_IRQHandler + 1     // 37: External Interrupt(21) UART
+        .long   default_handler + 1     // 38: External Interrupt(22)
+        .long   default_handler + 1     // 39: External Interrupt(23)
+        .long   default_handler + 1     // 40: External Interrupt(24) ADC
+        .long   default_handler + 1     // 41: External Interrupt(25) WDT
+        .long   default_handler + 1     // 42: External Interrupt(26) BOD
+        .long   default_handler + 1     // 43: External Interrupt(27)
+        .long   default_handler + 1     // 44: External Interrupt(28) PIO_3
+        .long   default_handler + 1     // 45: External Interrupt(29) PIO_2
+        .long   default_handler + 1     // 46: External Interrupt(30) PIO_1
+        .long   default_handler + 1     // 47: External Interrupt(31) PIO_0
+        .long   default_handler + 1     // 48: External Interrupt(32)
+        .long   default_handler + 1     // 49: External Interrupt(33)
+        .long   default_handler + 1     // 50: External Interrupt(34)
+        .long   default_handler + 1     // 51: External Interrupt(35)
+        .long   default_handler + 1     // 52: External Interrupt(36)
+        .long   default_handler + 1     // 53: External Interrupt(37)
+        .long   default_handler + 1     // 54: External Interrupt(38)
+        .long   default_handler + 1     // 55: External Interrupt(39)
+        .long   default_handler + 1     // 56: External Interrupt(40)
+        .long   default_handler + 1     // 57: External Interrupt(41)
+        .long   default_handler + 1     // 58: External Interrupt(42)
+        .long   default_handler + 1     // 59: External Interrupt(43)
+        .long   default_handler + 1     // 60: External Interrupt(44)
+        .long   default_handler + 1     // 61: External Interrupt(45)
+        .long   default_handler + 1     // 62: External Interrupt(46)
+        .long   default_handler + 1     // 63: External Interrupt(47)
+
+/* startup */
+        .section .text
+        .thumb
+        .align 0
+        .global Reset_Handler
+Reset_Handler:
+
+        /* initialize .data */
+data_init:
+        ldr     r1, =_sidata
+        ldr     r2, =_sdata
+        ldr     r3, =_edata
+        cmp     r2, r3
+        beq     bss_init
+data_loop:
+        ldrb    r0, [r1]
+        add     r1, r1, #1
+        strb    r0, [r2]
+        add     r2, r2, #1
+        cmp     r2, r3
+        bne     data_loop
+
+        /* initialize .bss */
+bss_init:
+        mov     r0, #0
+        ldr     r2, =_sbss      // sbss/ebss is 4byte aligned by link.lds
+        ldr     r3, =_ebss
+        cmp     r2, r3
+        beq     start_main
+bss_loop:
+        str     r0, [r2]
+        add     r2, r2, #4
+        cmp     r2, r3
+        bne     bss_loop
+
+        /* launch main() */
+start_main:
+#ifdef RT_USING_USER_MAIN
+        bl      entry
+#else
+        bl      main
+#endif
+
+default_handler:
+die:
+        b       die
+
+        .pool

bsp/lpc1114/link.lds

+/* Program Entry, set to mark it as "used" and avoid gc */
+MEMORY
+{
+    CODE (rx) : ORIGIN = 0x00000000, LENGTH = 32k /* 32KB flash */
+    DATA (rw) : ORIGIN = 0x10000000, LENGTH =  4k /* 4K sram */
+}
+ENTRY(Reset_Handler)
+_system_stack_size = 0x100;
+_ram_end = ORIGIN(DATA) + LENGTH(DATA);
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
+        _etext = .;
+    } > CODE = 0
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > CODE
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >DATA
+
+    .stack : 
+    {
+        . = . + _system_stack_size;
+        . = ALIGN(4);
+        _estack = .;
+    } >DATA
+
+    __bss_start__ = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+        
+        *(.bss.init)
+    } > DATA
+    __bss_end__ = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}

bsp/lpc1114/rtconfig.h

+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+/* RT_USING_ARCH_DATA_TYPE is not set */
+/* RT_USING_SMP is not set */
+#define RT_ALIGN_SIZE 4
+/* RT_THREAD_PRIORITY_8 is not set */
+#define RT_THREAD_PRIORITY_32
+/* RT_THREAD_PRIORITY_256 is not set */
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+/* RT_USING_OVERFLOW_CHECK is not set */
+/* RT_USING_HOOK is not set */
+/* RT_USING_IDLE_HOOK is not set */
+#define IDLE_THREAD_STACK_SIZE 256
+/* RT_USING_TIMER_SOFT is not set */
+/* RT_DEBUG is not set */
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+/* RT_USING_SIGNALS is not set */
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+/* RT_USING_MEMHEAP is not set */
+/* RT_USING_NOHEAP is not set */
+#define RT_USING_SMALL_MEM
+/* RT_USING_SLAB is not set */
+/* RT_USING_MEMTRACE is not set */
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+/* RT_USING_DEVICE_OPS is not set */
+/* RT_USING_INTERRUPT_INFO is not set */
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart"
+#define RT_VER_NUM 0x40001
+#define ARCH_ARM
+#define ARCH_ARM_CORTEX_M
+#define ARCH_ARM_CORTEX_M0
+/* ARCH_CPU_STACK_GROWS_UPWARD is not set */
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 512
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+/* RT_USING_CPLUSPLUS is not set */
+
+/* Command shell */
+
+/* RT_USING_FINSH is not set */
+
+/* Device virtual file system */
+
+/* RT_USING_DFS is not set */
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 128
+/* RT_USING_SYSTEM_WORKQUEUE is not set */
+#define RT_USING_SERIAL
+/* RT_SERIAL_USING_DMA is not set */
+#define RT_SERIAL_RB_BUFSZ 64
+/* RT_USING_CAN is not set */
+/* RT_USING_HWTIMER is not set */
+/* RT_USING_CPUTIME is not set */
+/* RT_USING_I2C is not set */
+#define RT_USING_PIN
+/* RT_USING_ADC is not set */
+/* RT_USING_PWM is not set */
+/* RT_USING_MTD_NOR is not set */
+/* RT_USING_MTD_NAND is not set */
+/* RT_USING_MTD is not set */
+/* RT_USING_PM is not set */
+/* RT_USING_RTC is not set */
+/* RT_USING_SDIO is not set */
+/* RT_USING_SPI is not set */
+/* RT_USING_WDT is not set */
+/* RT_USING_AUDIO is not set */
+/* RT_USING_SENSOR is not set */
+
+/* Using WiFi */
+
+/* RT_USING_WIFI is not set */
+
+/* Using USB */
+
+/* RT_USING_USB_HOST is not set */
+/* RT_USING_USB_DEVICE is not set */
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+/* RT_USING_PTHREADS is not set */
+
+/* Network */
+
+/* Socket abstraction layer */
+
+/* RT_USING_SAL is not set */
+
+/* Network interface device */
+
+/* RT_USING_NETDEV is not set */
+
+/* light weight TCP/IP stack */
+
+/* RT_USING_LWIP is not set */
+
+/* Modbus master and slave stack */
+
+/* RT_USING_MODBUS is not set */
+
+/* AT commands */
+
+/* RT_USING_AT is not set */
+
+/* VBUS(Virtual Software BUS) */
+
+/* RT_USING_VBUS is not set */
+
+/* Utilities */
+
+/* RT_USING_RYM is not set */
+/* RT_USING_ULOG is not set */
+/* RT_USING_UTEST is not set */
+/* RT_USING_LWP is not set */
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+/* PKG_USING_PAHOMQTT is not set */
+/* PKG_USING_WEBCLIENT is not set */
+/* PKG_USING_MONGOOSE is not set */
+/* PKG_USING_WEBTERMINAL is not set */
+/* PKG_USING_CJSON is not set */
+/* PKG_USING_JSMN is not set */
+/* PKG_USING_LJSON is not set */
+/* PKG_USING_EZXML is not set */
+/* PKG_USING_NANOPB is not set */
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+/* PKG_USING_WLANMARVELL is not set */
+
+/* Wiced WiFi */
+
+/* PKG_USING_WLAN_WICED is not set */
+/* PKG_USING_COAP is not set */
+/* PKG_USING_NOPOLL is not set */
+/* PKG_USING_NETUTILS is not set */
+/* PKG_USING_AT_DEVICE is not set */
+
+/* IoT Cloud */
+
+/* PKG_USING_ONENET is not set */
+/* PKG_USING_GAGENT_CLOUD is not set */
+/* PKG_USING_ALI_IOTKIT is not set */
+/* PKG_USING_AZURE is not set */
+
+/* security packages */
+
+/* PKG_USING_MBEDTLS is not set */
+/* PKG_USING_libsodium is not set */
+/* PKG_USING_TINYCRYPT is not set */
+
+/* language packages */
+
+/* PKG_USING_LUA is not set */
+/* PKG_USING_JERRYSCRIPT is not set */
+/* PKG_USING_MICROPYTHON is not set */
+
+/* multimedia packages */
+
+/* PKG_USING_OPENMV is not set */
+/* PKG_USING_MUPDF is not set */
+
+/* tools packages */
+
+/* PKG_USING_CMBACKTRACE is not set */
+/* PKG_USING_EASYFLASH is not set */
+/* PKG_USING_EASYLOGGER is not set */
+/* PKG_USING_SYSTEMVIEW is not set */
+
+/* system packages */
+
+/* PKG_USING_GUIENGINE is not set */
+/* PKG_USING_CAIRO is not set */
+/* PKG_USING_PIXMAN is not set */
+/* PKG_USING_LWEXT4 is not set */
+/* PKG_USING_PARTITION is not set */
+/* PKG_USING_FAL is not set */
+/* PKG_USING_SQLITE is not set */
+/* PKG_USING_RTI is not set */
+/* PKG_USING_LITTLEVGL2RTT is not set */
+/* PKG_USING_CMSIS is not set */
+/* PKG_USING_DFS_YAFFS is not set */
+
+/* peripheral libraries and drivers */
+
+/* PKG_USING_REALTEK_AMEBA is not set */
+/* PKG_USING_SHT2X is not set */
+/* PKG_USING_AHT10 is not set */
+/* PKG_USING_AP3216C is not set */
+/* PKG_USING_STM32_SDIO is not set */
+/* PKG_USING_ICM20608 is not set */
+
+/* miscellaneous packages */
+
+/* PKG_USING_LIBCSV is not set */
+/* PKG_USING_OPTPARSE is not set */
+/* PKG_USING_FASTLZ is not set */
+/* PKG_USING_MINILZO is not set */
+/* PKG_USING_QUICKLZ is not set */
+/* PKG_USING_MULTIBUTTON is not set */
+/* PKG_USING_CANFESTIVAL is not set */
+/* PKG_USING_ZLIB is not set */
+/* PKG_USING_DSTR is not set */
+
+/* sample package */
+
+/* samples: kernel and components samples */
+
+/* PKG_USING_KERNEL_SAMPLES is not set */
+/* PKG_USING_FILESYSTEM_SAMPLES is not set */
+/* PKG_USING_NETWORK_SAMPLES is not set */
+/* PKG_USING_PERIPHERAL_SAMPLES is not set */
+
+/* example package: hello */
+
+/* PKG_USING_HELLO is not set */
+#define SOC_LPC1114
+
+#endif

bsp/lpc1114/rtconfig.py

+import os
+
+# toolchains options
+ARCH        ='arm'
+CPU         ='cortex-m0'
+CROSS_TOOL  ='gcc'
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = '../..'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'/usr/bin'
+else:
+    print 'Please make sure your toolchains is GNU GCC!'
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'release'
+# BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX  = 'arm-none-eabi-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'g++'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    DEVICE  = ' -mcpu=cortex-m0 -mthumb -ffunction-sections -fdata-sections'
+    CFLAGS  = DEVICE + ' -Wall'
+    AFLAGS  = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T link.lds'
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -Os'
+
+    CXXFLAGS = CFLAGS
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'