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提交 d3648dbc 编写于 作者: G Grissiom
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rm48x50: cleanup sys_startup.c

上级 81ab083a
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Showing with 14 addition and 171 deletion
bsp/rm48x50/HALCoGen/source/sys_startup.c
浏览文件 @ d3648dbc
......@@ -59,9 +59,6 @@ extern uint32 * __binit__;
extern void main(void);
/* USER CODE BEGIN (3) */
/* USER CODE END */
/* Startup Routine */
/** @fn void memoryInit(uint32 ram)
......@@ -71,9 +68,6 @@ extern void main(void);
*/
void memoryInit(uint32 ram)
{
/* USER CODE BEGIN (11) */
/* USER CODE END */
/* Enable Memory Hardware Initialization */
systemREG1->MINITGCR = 0xAU;
......@@ -87,14 +81,8 @@ void memoryInit(uint32 ram)
/* Disable Memory Hardware Initialization */
systemREG1->MINITGCR = 0x5U;
/* USER CODE BEGIN (12) */
/* USER CODE END */
}
/* USER CODE BEGIN (4) */
/* USER CODE END */
void _c_int00(void)
{
/* Work Around for Errata DEVICE#140: ( Only on Rev A silicon)
......@@ -108,44 +96,21 @@ void _c_int00(void)
_esmCcmErrorsClear_();
}
/* USER CODE BEGIN (8) */
/* USER CODE END */
/* USER CODE BEGIN (11) */
/* USER CODE END */
_errata_CORTEXR4_66_();
_errata_CORTEXR4_57_();
/* Reset handler: the following instructions read from the system exception status register
* to identify the cause of the CPU reset. */
/* check for power-on reset condition */
if ((SYS_EXCEPTION & POWERON_RESET) != 0U)
{
/* USER CODE BEGIN (12) */
/* USER CODE END */
/* clear all reset status flags */
SYS_EXCEPTION = 0xFFFFU;
/* USER CODE BEGIN (13) */
/* USER CODE END */
_errata_CORTEXR4_66_();
/* USER CODE BEGIN (14) */
/* USER CODE END */
_errata_CORTEXR4_57_();
/* USER CODE BEGIN (15) */
/* USER CODE END */
/* continue with normal start-up sequence */
}
else if ((SYS_EXCEPTION & OSC_FAILURE_RESET) != 0U)
{
/* Reset caused due to oscillator failure.
Add user code here to handle oscillator failure */
/* USER CODE BEGIN (16) */
/* USER CODE END */
}
else if ((SYS_EXCEPTION & WATCHDOG_RESET) !=0U)
{
......@@ -157,21 +122,13 @@ void _c_int00(void)
if(WATCHDOG_STATUS != 0U)
{
/* Add user code here to handle watchdog violation. */
/* USER CODE BEGIN (17) */
/* USER CODE END */
/* Clear the Watchdog reset flag in Exception Status register */
SYS_EXCEPTION = WATCHDOG_RESET;
/* USER CODE BEGIN (18) */
/* USER CODE END */
}
else
{
/* Clear the ICEPICK reset flag in Exception Status register */
SYS_EXCEPTION = ICEPICK_RESET;
/* USER CODE BEGIN (19) */
/* USER CODE END */
}
}
else if ((SYS_EXCEPTION & CPU_RESET) !=0U)
......@@ -179,49 +136,23 @@ void _c_int00(void)
/* Reset caused due to CPU reset.
CPU reset can be caused by CPU self-test completion, or
by toggling the "CPU RESET" bit of the CPU Reset Control Register. */
/* USER CODE BEGIN (20) */
/* USER CODE END */
/* clear all reset status flags */
SYS_EXCEPTION = CPU_RESET;
/* USER CODE BEGIN (21) */
/* USER CODE END */
}
else if ((SYS_EXCEPTION & SW_RESET) != 0U)
{
/* Reset caused due to software reset.
Add user code to handle software reset. */
/* USER CODE BEGIN (22) */
/* USER CODE END */
}
else
{
/* Reset caused by nRST being driven low externally.
Add user code to handle external reset. */
/* USER CODE BEGIN (23) */
/* USER CODE END */
}
/* USER CODE BEGIN (26) */
/* USER CODE END */
/* Initialize System - Clock, Flash settings with Efuse self check */
systemInit();
/* USER CODE BEGIN (29) */
/* USER CODE END */
/* USER CODE BEGIN (31) */
/* USER CODE END */
/* USER CODE BEGIN (33) */
/* USER CODE END */
/* USER CODE BEGIN (36) */
/* USER CODE END */
/* USER CODE BEGIN (37) */
/* USER CODE END */
/* Initialize CPU RAM.
* This function uses the system module's hardware for auto-initialization of memories and their
* associated protection schemes. The CPU RAM is initialized by setting bit 0 of the MSIENA register.
......@@ -230,32 +161,7 @@ void _c_int00(void)
*/
memoryInit(0x1U);
/* USER CODE BEGIN (38) */
/* USER CODE END */
_coreEnableRamEcc_();
/* USER CODE BEGIN (39) */
/* USER CODE END */
/* USER CODE BEGIN (40) */
/* USER CODE END */
tcram1REG->RAMCTRL &= ~(0x00000100U); /* disable writes to ECC RAM */
tcram2REG->RAMCTRL &= ~(0x00000100U);
tcram1REG->RAMCTRL &= ~(0x00000100U); /* disable writes to ECC RAM */
tcram2REG->RAMCTRL &= ~(0x00000100U);
/* USER CODE BEGIN (41) */
/* USER CODE END */
/* USER CODE BEGIN (43) */
/* USER CODE END */
/* USER CODE BEGIN (44) */
/* USER CODE END */
/* USER CODE BEGIN (48) */
/* USER CODE END */
/* USER CODE BEGIN (56) */
/* USER CODE END */
/* Release the MibSPI1 modules from local reset.
* This will cause the MibSPI1 RAMs to get initialized along with the parity memory.
*/
......@@ -271,54 +177,17 @@ void _c_int00(void)
*/
mibspiREG5->GCR0 = 0x1U;
/* USER CODE BEGIN (57) */
/* USER CODE END */
/* Initialize all on-chip SRAMs except for MibSPIx RAMs
* The MibSPIx modules have their own auto-initialization mechanism which is triggered
* as soon as the modules are brought out of local reset.
*/
/* The system module auto-init will hang on the MibSPI RAM if the module is still in local reset.
*/
/* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories and their channel numbers.
Memory Initialization is perfomed only on the user selected memories in HALCoGen's GUI SAFETY INIT tab.
*/
memoryInit( (1U << 1U)
| (1U << 2U)
| (1U << 5U)
| (1U << 6U)
| (1U << 10U)
| (1U << 8U)
| (1U << 14U)
| (1U << 3U)
| (1U << 4U)
| (1U << 15U)
| (1U << 16U)
| (0U << 13U) );
/* USER CODE BEGIN (58) */
/* USER CODE END */
/* USER CODE BEGIN (59) */
/* USER CODE END */
/* USER CODE BEGIN (60) */
/* USER CODE END */
/* USER CODE BEGIN (61) */
/* USER CODE END */
/* USER CODE BEGIN (62) */
/* USER CODE END */
/* USER CODE BEGIN (63) */
/* USER CODE END */
/* USER CODE BEGIN (64) */
/* USER CODE END */
/* USER CODE BEGIN (65) */
/* USER CODE END */
/* USER CODE BEGIN (66) */
/* USER CODE END */
/* USER CODE BEGIN (67) */
/* USER CODE END */
/* USER CODE BEGIN (68) */
/* USER CODE END */
/* USER CODE BEGIN (69) */
/* USER CODE END */
/* Initialize all on-chip SRAMs except for MibSPIx RAMs The MibSPIx modules
* have their own auto-initialization mechanism which is triggered as soon
* as the modules are brought out of local reset. */
/* The system module auto-init will hang on the MibSPI RAM if the module is
* still in local reset. */
/* NOTE : Please Refer DEVICE DATASHEET for the list of Supported Memories
* and their channel numbers. Memory Initialization is perfomed only on
* the user selected memories in HALCoGen's GUI SAFETY INIT tab. */
memoryInit((1U << 1U) | (1U << 2U) | (1U << 5U) | (1U << 6U)
| (1U << 10U) | (1U << 8U) | (1U << 14U) | (1U << 3U)
| (1U << 4U) | (1U << 15U) | (1U << 16U) | (0U << 13U) );
while ((mibspiREG1->FLG & 0x01000000U) == 0x01000000U)
{
......@@ -333,24 +202,9 @@ void _c_int00(void)
}/* Wait */
/* wait for MibSPI5 RAM to complete initialization */
/* USER CODE BEGIN (70) */
/* USER CODE END */
/* USER CODE BEGIN (71) */
/* USER CODE END */
/* USER CODE BEGIN (72) */
/* USER CODE END */
/* USER CODE BEGIN (73) */
/* USER CODE END */
/* USER CODE BEGIN (74) */
/* USER CODE END */
/* Initialize VIM table */
vimInit();
/* USER CODE BEGIN (75) */
/* USER CODE END */
#ifdef __GNUC__
data_init();
#elif defined(__TI_COMPILER_VERSION__)
......@@ -390,17 +244,6 @@ void _c_int00(void)
}
}
#endif
/* USER CODE BEGIN (76) */
/* USER CODE END */
/* call the application */
main();
/* USER CODE BEGIN (77) */
/* USER CODE END */
/* USER CODE BEGIN (78) */
/* USER CODE END */
}
/* USER CODE BEGIN (79) */
/* USER CODE END */
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