[bsp] add ck802 bsp

bsp/ck802/.config

+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_DEBUG=y
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_DEBUG_INIT=0
+CONFIG_RT_DEBUG_THREAD=0
+CONFIG_RT_USING_HOOK=y
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=1
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=512
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+CONFIG_FINSH_USING_MSH_ONLY=y
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
+# CONFIG_RT_DFS_ELM_USE_LFN_3 is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_AUDIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+# CONFIG_RT_USING_LIBC is not set
+# CONFIG_RT_USING_PTHREADS is not set
+
+#
+# Network stack
+#
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# Modbus master and slave stack
+#
+# CONFIG_RT_USING_MODBUS is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_LOGTRACE is not set
+# CONFIG_RT_USING_RYM is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_ONENET is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+
+#
+# system packages
+#
+
+#
+# RT-Thread GUI Engine
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_STM32F4_HAL is not set
+# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+
+#
+# sample package
+#
+# CONFIG_PKG_USING_SAMPLES is not set
+
+#
+# example package: hello
+#
+# CONFIG_PKG_USING_HELLO is not set
+
+#
+# Privated Packages of RealThread
+#
+# CONFIG_PKG_USING_CODEC is not set
+# CONFIG_PKG_USING_PLAYER is not set
+# CONFIG_PKG_USING_PERSIMMON_SRC is not set
+
+#
+# Network Utilities
+#
+# CONFIG_PKG_USING_WLAN_WICED_SRC is not set
+# CONFIG_PKG_USING_CLOUDSDK is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_POWER_MANAGER is not set
+# CONFIG_PKG_USING_RT_OTA is not set
+# CONFIG_PKG_USING_RT_AT is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_RTINSIGHT is not set
+CONFIG_RT_USING_UART1=y

bsp/ck802/Kconfig

+mainmenu "RT-Thread Configuration"
+
+config $BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config $RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+# you can change the RTT_ROOT default "../.." to your rtthread_root,
+# example : default "F:/git_repositories/rt-thread"
+
+config $PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+if RT_USING_SERIAL
+
+    config RT_USING_UART1
+        bool "Using uart1"
+        default y 
+
+endif

bsp/ck802/README.md

+CK802
+
+## 简介
+
+CK802是杭州中天微系统有限公司自主开发的极低功耗、极低成本嵌入式CPU核产品，它以8位CPU的成本获得32位CPU的运行效率与性能。 BSP基于中天微提供的一块FPGA开发板完成。
+
+| 介绍 | 描述 |
+| ---- | ---- |
+| 主CPU平台 | CK802 |
+| 最高频率 | 600MHz |
+| SRAM | 128K |
+| FLASH | 256K |
+
+## 编译说明
+
+CK802板级包支持CDK集成开发环境和Scons编译。使用的编译器是csky-abiv2-elf-toolchain。
+
+| IDE/编译器 | 已测试版本 |
+| ---------- | --------- |
+| CDK | CDK 1.6.0 |
+| GCC | (C-SKY Tools V2.10.00(Minilibc), ABIV2, B20161206) 4.5.1 |
+
+使用scons编译，需要指定环境变量RTT_EXEC_PATH为正确的编译器路径，例如：
+
+Windows：
+
+```shell
+RTT_EXEC_PATH=r'D:\c-sky\CSKY\MinGW\csky-abiv2-elf-toolchain\bin'
+```
+
+Linux：
+
+```shell
+RTT_EXEC_PATH=r'/opt/csky-abiv2-elf-tools-x86_64-minilibc-20161211/bin'
+```
+
+
+
+## BSP使用
+
+### CDK
+#### 编译仿真
+打开project.cdkproj工程，点击菜单栏的`Project->Build Active Project`进行编译，编译完成后点击`Debug->Start/Stop Debugger`，就可以进入仿真。点击`Debug->Continue Debugger`全速运行。
+#### 更新工程
+在需要添加或者删除组件的时候，可以使用`menuconfig`进行配置。配置完成后输入`scons --target=cdk`更新工程
+### Scons
+
+#### 编译
+
+配置好环境变量`RTT_EXEC_PATH`后，使用[env工具][https://www.rt-thread.org/page/download.html]，可以在console下进入到bsp目录中，运行以下命令就可以编译该BSP：
+```
+scons
+```
+
+#### 仿真
+
+Windows平台打开CSkyDebugServer.exe，该软件会连接到仿真器并且提供一个gdb server。使用DebugServerConsole.exe在命令行下进行调试。
+
+Linux平台使用CSkyDebugServer.elf来连接仿真器，使用DebugServerConsole.exe在命令行下进行调试。
+
+### 运行结果
+
+如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息：
+
+```
+\ | /
+- RT -     Thread Operating System
+ / | \     3.0.4 build Jun  5 2018
+ 2006 - 2018 Copyright by rt-thread team
+msh >
+```
+
+## 4. 驱动支持情况及计划
+
+| 驱动 | 支持情况  | 备注 |
+| ------ | ----  | ------ |
+| UART | 支持 | UART 1 |
+
+
+## 5. 联系人信息
+
+维护人：
+
+- [tanek](https://github.com/TanekLiang)
\ No newline at end of file

bsp/ck802/SConscript

+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/ck802/SConstruct

+import os
+import sys
+import rtconfig
+
+# if os.getenv('RTT_ROOT'):
+    # RTT_ROOT = os.getenv('RTT_ROOT')
+# else:
+RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+print RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-ck802.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+# add --start-group and --end-group for GNU GCC
+env['LINKCOM'] = '$LINK -o $TARGET $LINKFLAGS $__RPATH $SOURCES $_LIBDIRFLAGS -Wl,--start-group $_LIBFLAGS -Wl,--end-group'
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/ck802/applications/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+CCFLAGS = ' -c -mistack -ffunction-sections'
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH, CCFLAGS=CCFLAGS)
+
+Return('group')

bsp/ck802/applications/main.c

+
+/*
+ * File      : clock.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-10-10     Tanek        first version
+ */
+
+#include <rtthread.h>
+
+int main(void)
+{
+    return 0;
+}
+
+/*@}*/

bsp/ck802/drivers/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'drivers')
+
+# add the general drivers.
+src = Glob("*.c") + Glob("*.cpp")
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/ck802/drivers/board.c

+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2018, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-08-10     Urey         first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "csi_core.h"
+#include "pinmux.h"
+
+extern int __bss_end__;
+#define SYS_HEAP_BEGIN    (&__bss_end__)
+
+#include "core_ck802.h"
+
+/**
+ * This function will initial CK802 board.
+ */
+void rt_hw_board_init(void)
+{
+    phobos_ioreuse_initial();
+
+    /* NVIC Configuration */
+    drv_nvic_init(2);
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *)SYS_HEAP_BEGIN, (void *)CK802_IRAM_END);
+#endif
+}
+
+/*@}*/

bsp/ck802/drivers/board.h

+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2018, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-08-10     Urey         first implementation
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#define APB_DEFAULT_FREQ        20000000   /* Hz */
+#define CK802_IRAM_SIZE         94
+#define CK802_IRAM_END          (0x20000000 + CK802_IRAM_SIZE * 1024)
+
+#endif /* __BOARD_H__ */

bsp/ck802/drivers/board_coretimer.c

+/*
+ * File      : board_coretimer.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-01-01     Urey      first version
+ */
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "board_coretimer.h"
+
+#include <stdint.h>
+
+static inline unsigned int readreg32(volatile unsigned int *addr)
+{
+    return *(volatile unsigned int *)addr;
+}
+
+static inline void writereg32(unsigned int b, volatile unsigned int *addr)
+{
+    *(volatile unsigned int *)addr = b;
+}
+
+void CKTimerInit(uint32_t timer_id, uint32_t freq)
+{
+    uint32_t reg;
+
+    writereg32(APB_DEFAULT_FREQ / freq, CORET_RVR);
+    writereg32(0, CORET_CVR);
+
+    reg = readreg32(CORET_CSR);
+    reg |= CORETIM_TXCONTROL_ENABLE;
+    reg |= CORETIM_TXCONTROL_INTMASK;
+    writereg32(reg, CORET_CSR);
+
+    return;
+}
+
+void CKTimerClear(uint32_t timer_id)
+{
+    uint32_t reg;
+
+    reg = readreg32(CORET_CSR);
+    reg |= ~CORETIM_TXCONTROL_MODE;
+    writereg32(reg, CORET_CSR);
+}
+
+uint32_t CKTimer_CurrentValue(void)
+{
+    return readreg32(CORET_CVR);
+}
+
+void __attribute__((isr)) SysTick_Handler(void)
+{
+    CKTimerClear(0x1);
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}

bsp/ck802/drivers/board_coretimer.h

+/*
+ * File      : board_coretimer.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-01-01     Urey      first version
+ */
+#ifndef _BOARD_CORETIMER_H_
+#define _BOARD_CORETIMER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#define CK_TIMER_BASE     (0xE000E000)
+
+#define CORET_CSR         (volatile unsigned int *)(CK_TIMER_BASE + 0x10)
+#define CORET_RVR         (volatile unsigned int *)(CK_TIMER_BASE + 0x14)
+#define CORET_CVR         (volatile unsigned int *)(CK_TIMER_BASE + 0x18)
+#define CORET_CALIB       (volatile unsigned int *)(CK_TIMER_BASE + 0x1c)
+
+/*
+ *  define the bits for TxControl
+ */
+#define CORETIM_TXCONTROL_ENABLE      (1UL << 0)
+#define CORETIM_TXCONTROL_INTMASK     (1UL << 1)
+#define CORETIM_TXCONTROL_MODE        (1UL << 16)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _BOARD_CORETIMER_H_ */

bsp/ck802/drivers/board_uart.c

+/*
+ * File      : board_uart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2018, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-09-23     Urey         first implementation
+ */
+
+#include <rtthread.h>
+
+#ifdef RT_USING_CONSOLE
+
+#include <rthw.h>
+#include <rtdevice.h>
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdbool.h>
+
+#include "board.h"
+#include "soc.h"
+#include "dw_usart.h"
+#include "drv_usart.h"
+#include "pin_name.h"
+#include "pinmux.h"
+
+#if CONFIG_USART
+struct
+{
+    uint32_t base;
+    uint32_t irq;
+} const sg_usart_config[CONFIG_USART_NUM] =
+{
+    { CSKY_UART0_BASE, UART0_IRQn },
+    { CSKY_UART1_BASE, UART1_IRQn },
+    { CSKY_UART2_BASE, UART2_IRQn },
+    { CSKY_UART3_BASE, UART3_IRQn }
+};
+
+typedef struct
+{
+    pin_t    tx;
+    pin_t    rx;
+    uint16_t cfg_idx;    //idx of sg_usart_config[]
+    uint16_t function;
+} usart_pin_map_t;
+const static usart_pin_map_t s_usart_pin_map[] =
+{
+    {
+        PA0_TXD0_PWM0_XX_SIROUT0,
+        PA1_RXD0_PWM1_XX_SIRIN0,
+        0,
+        0
+    },
+    {
+        PA10_TXD1_PWM1_XX_SIROUT1,
+        PA11_RXD1_PWM2_XX_SIRIN1,
+        1,
+        0
+    },
+    {
+        PA23_TXD2_PWM5_XX_SIROUT2,
+        PA22_RXD2_PWM4_XX_SIRIN2,
+        2,
+        0
+    },
+    {
+        PA26_TXD3_PWMFAULT_XX_SIROUT3,
+        PA27_RXD3_PWM0_XX_SIRIN3,
+        3,
+        0
+    }
+};
+
+int32_t target_usart_init(pin_t tx, pin_t rx, uint32_t *base, uint32_t *irq)
+{
+    uint32_t idx;
+
+    for (idx = 0; idx < sizeof(s_usart_pin_map) / sizeof(usart_pin_map_t); idx++)
+    {
+        if (s_usart_pin_map[idx].tx == tx && s_usart_pin_map[idx].rx == rx)
+        {
+            *base = sg_usart_config[s_usart_pin_map[idx].cfg_idx].base;
+            *irq = sg_usart_config[s_usart_pin_map[idx].cfg_idx].irq;
+
+            /*pinmux*/
+            pin_mux(s_usart_pin_map[idx].tx, s_usart_pin_map[idx].function);
+            pin_mux(s_usart_pin_map[idx].rx, s_usart_pin_map[idx].function);
+            return s_usart_pin_map[idx].cfg_idx;
+        }
+    }
+    return -1;
+}
+#endif
+
+#ifdef RT_USING_UART1
+#define UART_TXD1     PA10_TXD1_PWM1_XX_SIROUT1
+#define UART_RXD1     PA11_RXD1_PWM2_XX_SIRIN1
+
+static  usart_handle_t uart1_handle;
+static struct rt_serial_device  serial1;
+/*
+static void usart1_event_cb(uint32_t event, void *cb_arg)
+{
+    switch (event)
+    {
+    case USART_EVENT_SEND_COMPLETE:
+        rt_hw_serial_isr(&serial1,RT_SERIAL_EVENT_TX_DONE);
+        break;
+
+    case USART_EVENT_RECEIVED:
+        rt_hw_serial_isr(&serial1,RT_SERIAL_EVENT_RX_IND);
+        break;
+
+    default:
+        break;
+    }
+}
+*/
+
+__attribute__((isr)) void USART1_IRQHandler(void)
+{
+    rt_hw_serial_isr(&serial1,RT_SERIAL_EVENT_RX_IND);
+}
+#endif
+
+/*
+ * UART interface
+ */
+static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    int ret;
+    usart_handle_t uart;
+
+    uint32_t bauds;
+    usart_mode_e mode;
+    usart_parity_e parity;
+    usart_stop_bits_e stopbits;
+    usart_data_bits_e databits;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (usart_handle_t)serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+
+    /* set baudrate parity...*/
+    bauds = cfg->baud_rate;
+    mode = USART_MODE_ASYNCHRONOUS;
+
+    if (cfg->parity == PARITY_EVEN)
+        parity = USART_PARITY_EVEN;
+    else if (cfg->parity == PARITY_ODD)
+        parity = USART_PARITY_ODD;
+    else
+        parity = USART_PARITY_NONE;
+
+    stopbits = USART_STOP_BITS_1 ;
+    databits = USART_DATA_BITS_8;
+
+    ret = csi_usart_config(uart, SYSTEM_CLOCK, bauds, USART_MODE_ASYNCHRONOUS, parity, stopbits, databits);
+
+    if (ret < 0)
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    usart_handle_t uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (usart_handle_t)serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* Disable the UART Interrupt */
+        dw_usart_clr_int_flag(uart,IER_RDA_INT_ENABLE);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* Enable the UART Interrupt */
+        dw_usart_set_int_flag(uart,IER_RDA_INT_ENABLE);
+        break;
+    }
+
+    return (RT_EOK);
+}
+
+static int uart_putc(struct rt_serial_device *serial, char c)
+{
+    usart_handle_t uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (usart_handle_t)serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+
+    dw_usart_putchar(uart,c);
+
+    return (1);
+}
+
+static int uart_getc(struct rt_serial_device *serial)
+{
+    uint8_t ch;
+    usart_handle_t uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (usart_handle_t)serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+
+    if (!dw_usart_getchar_no_poll(uart, &ch))
+    {
+        return (int)(ch);
+    }
+    else
+    {
+        return -1;
+    }
+}
+
+const struct rt_uart_ops _uart_ops =
+{
+    uart_configure,
+    uart_control,
+    uart_putc,
+    uart_getc,
+};
+
+
+int rt_hw_usart_init(void)
+{
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+#ifdef RT_USING_UART1
+    serial1.ops                 = & _uart_ops;
+    serial1.config              = config;
+    serial1.config.bufsz        = 2048;
+    serial1.config.baud_rate    = 115200;
+
+    uart1_handle = csi_usart_initialize(UART_TXD1, UART_RXD1, NULL/*usart1_event_cb*/,
+                                        (void *) 0);
+
+    rt_hw_serial_register(&serial1,
+                          "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart1_handle);
+#endif
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_usart_init);
+#endif

bsp/ck802/drivers/config.h

+/* config.h -- Autogenerated! Do not edit. */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_KERNEL_NONE 1
+//#define CONFIG_AES 1
+//#define CONFIG_SPI 1
+//#define CONFIG_SPI_DMA 1
+//#define CONFIG_DMAC 1
+//#define CONFIG_GPIO 1
+//#define CONFIG_IIC 1
+//#define CONFIG_SHA 1
+//#define CONFIG_RSA 1
+//#define CONFIG_TIMER 1
+#define CONFIG_USART 1
+//#define CONFIG_TRNG 1
+//#define CONFIG_CRC 1
+//#define CONFIG_EFLASH 1
+//#define CONFIG_WDT 1
+//#define CONFIG_RTC 1
+//#define CONFIG_PWM 1
+//#define CONFIG_TEST 1
+//#define CONFIG_ETH 1
+//#define CONFIG_TEST_DRIVER 1
+//#define CONFIG_TEST_AES 1
+//#define CONFIG_TEST_ETH 1
+//#define CONFIG_TEST_DMAC 1
+//#define CONFIG_TEST_GPIO 1
+//#define CONFIG_TEST_IIC 1
+//#define CONFIG_TEST_SHA 1
+//#define CONFIG_TEST_RSA 1
+//#define CONFIG_TEST_TIMER 1
+//#define CONFIG_TEST_USART 1
+//#define CONFIG_TEST_TRNG 1
+//#define CONFIG_TEST_CRC 1
+//#define CONFIG_TEST_EFLASH 1
+//#define CONFIG_TEST_SPI 1
+//#define CONFIG_TEST_WDT 1
+//#define CONFIG_TEST_RTC 1
+//#define CONFIG_TEST_PWM 1
+
+#endif /* __CONFIG_H */
+

bsp/ck802/drivers/isr.c

+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     isr.c
+ * @brief    source file for the interrupt server route
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+#include <drv_common.h>
+#include "config.h"
+#include "soc.h"
+
+extern void dw_usart_irqhandler(int32_t idx);
+extern void dw_timer_irqhandler(int32_t idx);
+extern void dw_gpio_irqhandler(int32_t idx);
+extern void dw_iic_irqhandler(int32_t idx);
+extern void ck_rtc_irqhandler(int32_t idx);
+extern void dw_spi_irqhandler(int32_t idx);
+extern void dw_wdt_irqhandler(int32_t idx);
+extern void ck_dma_irqhandler(int32_t idx);
+extern void ck_aes_irqhandler(int32_t idx);
+extern void ck_sha_irqhandler(int32_t idx);
+#ifdef CONFIG_KERNEL_FREERTOS
+extern void CKTimer1Isr(void);
+extern void CKPendSVIsr(void);
+#endif
+
+#define readl(addr) \
+    ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
+
+__attribute__((isr)) void CORET_IRQHandler(void)
+{
+    readl(0xE000E010);
+}
+
+#if defined(CONFIG_USART)
+/*
+__attribute__((isr)) void USART0_IRQHandler(void)
+{
+    dw_usart_irqhandler(0);
+}
+
+
+__attribute__((isr)) void USART1_IRQHandler(void)
+{
+    dw_usart_irqhandler(1);
+}
+
+
+__attribute__((isr)) void USART2_IRQHandler(void)
+{
+    dw_usart_irqhandler(2);
+}
+
+__attribute__((isr)) void USART3_IRQHandler(void)
+{
+    dw_usart_irqhandler(3);
+}
+*/
+#endif
+
+#if defined(CONFIG_TIMER)
+__attribute__((isr)) void TIMA0_IRQHandler(void)
+{
+    dw_timer_irqhandler(0);
+}
+
+__attribute__((isr)) void TIMA1_IRQHandler(void)
+{
+    dw_timer_irqhandler(1);
+}
+__attribute__((isr)) void TIMB0_IRQHandler(void)
+{
+    dw_timer_irqhandler(2);
+}
+
+__attribute__((isr)) void TIMB1_IRQHandler(void)
+{
+    dw_timer_irqhandler(3);
+}
+
+#endif
+
+#if defined(CONFIG_GPIO)
+
+__attribute__((isr)) void GPIOA_IRQHandler(void)
+{
+    dw_gpio_irqhandler(0);
+}
+
+__attribute__((isr)) void GPIOB_IRQHandler(void)
+{
+    dw_gpio_irqhandler(1);
+}
+#endif
+
+#if defined(CONFIG_IIC)
+__attribute__((isr)) void I2C0_IRQHandler(void)
+{
+    dw_iic_irqhandler(0);
+}
+
+__attribute__((isr)) void I2C1_IRQHandler(void)
+{
+    dw_iic_irqhandler(1);
+}
+#endif
+
+#if defined(CONFIG_RTC)
+
+__attribute__((isr)) void RTC_IRQHandler(void)
+{
+    ck_rtc_irqhandler(0);
+}
+
+#endif
+
+#if defined(CONFIG_AES)
+
+__attribute__((isr)) void AES_IRQHandler(void)
+{
+    ck_aes_irqhandler(0);
+}
+
+#endif
+
+#if defined(CONFIG_SHA)
+
+__attribute__((isr)) void SHA_IRQHandler(void)
+{
+    ck_sha_irqhandler(0);
+}
+
+#endif
+
+#if defined(CONFIG_SPI) && defined(CONFIG_GPIO)
+__attribute__((isr)) void SPI0_IRQHandler(void)
+{
+    dw_spi_irqhandler(0);
+}
+
+__attribute__((isr)) void SPI1_IRQHandler(void)
+{
+    dw_spi_irqhandler(1);
+}
+#endif
+
+#if defined(CONFIG_WDT)
+__attribute__((isr)) void WDT_IRQHandler(void)
+{
+    dw_wdt_irqhandler(0);
+}
+#endif
+
+#if defined(CONFIG_DMAC)
+__attribute__((isr)) void DMAC_IRQHandler(void)
+{
+    ck_dma_irqhandler(0);
+}
+#endif

bsp/ck802/drivers/pin_name.h

+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     pn_name.h
+ * @brief    header file for the pin_name
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+#ifndef _PINNAMES_H
+#define _PINNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum
+{
+    PA0_TXD0_PWM0_XX_SIROUT0 = 0,
+    PA1_RXD0_PWM1_XX_SIRIN0,
+    PA2_CTS0_PWM2_SPI0CLK_XX,
+    PA3_RTS0_PWM3_SPI0TX_XX,
+    PA4_SCL0_PWM4_SPI0RX_XX,
+    PA5_SDA0_PWM5_SPI0CS_XX,
+    PA6_SPI0CLK_PWMTRIG0_SCL0_XX,
+    PA7_SPI0TX_PWMTRIG1_SDA0_XX,
+    PA8_SPI0RX_TRIGFAULT_SCL1_XX,
+    PA9_SPI0CS_PWM0_SDA1_XX,
+    PA10_TXD1_PWM1_XX_SIROUT1,
+    PA11_RXD1_PWM2_XX_SIRIN1,
+    PA12_CTS1_PWM3_SPI1CLK_XX,
+    PA13_RTS1_PWM4_SPI1TX_XX,
+    PA14_SCL1_PWM5_SPI1RX_XX,
+    PA15_SDA1_PWMTRIG0_SPI1CS0_XX,
+    PA16_SPI1CLK_PWMTRIG1_XX_XX,
+    PA17_SPI1TX_PWMFAULT_XX_XX,
+    PA18_SPI1RX_PWM0_XX_XX,
+    PA19_SPI1CS0_PWM1_XX_XX,
+    PA20_SPI1CS1_PWM2_XX_XX,
+    PA21_SPI1CS2_PWM3_XX_XX,
+    PA22_RXD2_PWM4_XX_SIRIN2,
+    PA23_TXD2_PWM5_XX_SIROUT2,
+    PA24_CTS2_PWMTRIG0_SPI1CS1_XX,
+    PA25_XX_PWMTRIG1_SPI1CS2_XX,
+    PA26_TXD3_PWMFAULT_XX_SIROUT3,
+    PA27_RXD3_PWM0_XX_SIRIN3,
+    PA28_I2SMCLK_PWM1_XX_XX,
+    PA29_I2SSCLK_PWM2_XX_XX,
+    PA30_I2SWSCLK_PWM3_XX_XX,
+    PA31_I2SSDA__SCL0_PWM4_XX,
+    PB0_ADC0_SDA0_PWM5_XX,
+    PB1_ADC1_SCL1_USISCLK_XX,
+    PB2_ADC2_SDA1_USISD0_XX,
+    PB3_ADC3_SPI1CLK_USISD1_XX,
+    PB4_ADC4_SPI1TX_USINSS_XX,
+    PB5_ADC5_SPI1RX_USISCLK_XX,
+    PB6_ADC6_SPI1CS0_USISD0_XX,
+    PB7_ADC7_SPI1CS1_USISD1_XX,
+    PB8_PWMTRIG0_SPI1CS2_USINSS_XX,
+    PB9_PWMTRIG1_CTS3_XX_XX,
+    PB10_PWMFAULT_RTS3_XX_XX
+}
+pin_name_t;
+
+typedef enum
+{
+    PORTA = 0,
+    PORTB = 1
+} port_name_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/ck802/drivers/pinmux.c

+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     pinmux.c
+ * @brief    source file for the pinmux
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+#include <stdint.h>
+#include "pinmux.h"
+#include "pin_name.h"
+
+#define readl(addr) \
+    ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; })
+
+#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
+
+/*******************************************************************************
+ * function: phobos_ioreuse_inital
+ *
+ * description:
+ *   initial phobos_pinmux
+ *******************************************************************************/
+
+void phobos_ioreuse_initial(void)
+{
+    unsigned int value;
+
+    /* gpio data source select */
+    value = readl(PHOBOS_GIPO0_PORTCTL_REG);
+    value |= GPIO0_REUSE_EN;
+    writel(value, PHOBOS_GIPO0_PORTCTL_REG);
+
+    value = readl(PHOBOS_GIPO1_PORTCTL_REG);
+    value |= GPIO1_REUSE_EN;
+    writel(value, PHOBOS_GIPO1_PORTCTL_REG);
+
+    /* reuse function select */
+    value = readl(PHOBOS_IOMUX0L_REG);
+    value |= IOMUX0L_FUNCTION_SEL;
+    writel(value, PHOBOS_IOMUX0L_REG);
+
+    value = readl(PHOBOS_IOMUX0H_REG);
+    value |= IOMUX1L_FUNCTION_SEL;
+    writel(value, PHOBOS_IOMUX0H_REG);
+
+    value = readl(PHOBOS_IOMUX1L_REG);
+    value |= IOMUX1L_FUNCTION_SEL;
+    writel(value, PHOBOS_IOMUX1L_REG);
+}
+
+void phobos_pwm_ioreuse(void)
+{
+    unsigned int value;
+
+    /* gpio data source select */
+    value = readl(PHOBOS_GIPO0_PORTCTL_REG);
+    value |= PWM_GPIO0_REUSE_EN;
+    writel(value, PHOBOS_GIPO0_PORTCTL_REG);
+
+    /* reuse function select */
+    value = readl(PHOBOS_IOMUX0L_REG);
+    value |= PWM_IOMUX0L_FUNCTION_SEL;
+    writel(value, PHOBOS_IOMUX0L_REG);
+}
+
+
+int32_t pin_mux(pin_name_t pin, uint16_t function)
+{
+    unsigned int val = 0;
+    unsigned int reg_val = 0;
+
+    uint8_t offset;
+
+    if (function > 3)
+    {
+        if (pin < PB0_ADC0_SDA0_PWM5_XX)
+        {
+            offset = pin;
+            /* gpio data source select */
+            val = readl(PHOBOS_GIPO0_PORTCTL_REG);
+            val &= ~(1 << offset);
+            writel(val, PHOBOS_GIPO0_PORTCTL_REG);
+            return 0;
+        }
+        else if (pin >= PB0_ADC0_SDA0_PWM5_XX)
+        {
+            offset = pin - 32;
+            /* gpio data source select */
+            val = readl(PHOBOS_GIPO1_PORTCTL_REG);
+            val &= ~(1 << offset);
+            writel(val, PHOBOS_GIPO1_PORTCTL_REG);
+            return 0;
+        }
+        else
+        {
+            return -1;
+        }
+    }
+
+    if (pin >= PB0_ADC0_SDA0_PWM5_XX)
+    {
+        offset = pin - 32;
+
+        /* gpio data source select */
+        val = readl(PHOBOS_GIPO1_PORTCTL_REG);
+        val |= (1 << offset);
+        writel(val, PHOBOS_GIPO1_PORTCTL_REG);
+
+        reg_val = (0x3 << (offset * 2));
+        /* reuse function select */
+        val = readl(PHOBOS_IOMUX1L_REG);
+        val &= ~(reg_val);
+        val |= (function << (2 * offset));
+        writel(val, PHOBOS_IOMUX1L_REG);
+        return 0;
+    }
+
+    offset = pin;
+    /* gpio data source select */
+    val = readl(PHOBOS_GIPO0_PORTCTL_REG);
+    val |= (1 << offset);
+    writel(val, PHOBOS_GIPO0_PORTCTL_REG);
+
+    if (pin >= PA16_SPI1CLK_PWMTRIG1_XX_XX)
+    {
+        offset = pin - 16;
+        reg_val = (0x3 << (offset * 2));
+        /* reuse function select */
+        val = readl(PHOBOS_IOMUX0H_REG);
+        val &= ~(reg_val);
+        val |= (function << (2 * offset));
+        writel(val, PHOBOS_IOMUX0H_REG);
+        return 0;
+    }
+
+    reg_val = (0x3 << (offset * 2));
+    /* reuse function select */
+    val = readl(PHOBOS_IOMUX0L_REG);
+    val &= ~(reg_val);
+    val |= (function << (2 * offset));
+    writel(val, PHOBOS_IOMUX0L_REG);
+    return 0;
+}

bsp/ck802/drivers/pinmux.h

+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     pinmux.h
+ * @brief    Header file for the pinmux
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+#ifndef PHOBOS_PINMUX_H
+#define PHOBOS_PINMUX_H
+
+#include <stdint.h>
+#include "pin_name.h"
+
+void phobos_ioreuse_initial(void);
+int32_t pin_mux(pin_name_t pin, uint16_t function);
+
+/* IOMUX0L function definition */
+#define PA0_UART0_TX      0x00000000
+#define PA0_PWM_CH0       0x00000001
+#define PA0_UART0_SIROUT  0x00000003
+#define PA1_UART0_RX      0x00000000
+#define PA1_PWM_CH1       0x00000004
+#define PA1_UART0_SIRIN   0x0000000C
+#define PA2_UART0_CTS     0x00000000
+#define PA2_PWM_CH2       0x00000010
+#define PA2_SPI0_CLK      0x00000020
+#define PA3_UART0_TRS     0x00000000
+#define PA3_PWM_CH3       0x00000040
+#define PA3_SPI0_TX       0x00000080
+#define PA4_I2C0_SCL      0x00000000
+#define PA4_PWM_CH4       0x00000100
+#define PA4_SPI0_RX       0x00000200
+#define PA5_I2C0_SDA      0x00000000
+#define PA5_PWM_CH5       0x00000400
+#define PA5_SPI0_CS       0x00000800
+#define PA6_SPI0_CLK      0x00000000
+#define PA6_ETB_TRIG0     0x00001000
+#define PA6_I2C0_SCL      0x00002000
+#define PA7_SPI_TX        0x00000000
+#define PA7_ETB_TRIG1     0x00004000
+#define PA7_I2C0_SDA      0x00008000
+#define PA8_SPI0_TX       0x00000000
+#define PA8_PWM_FAULT     0x00010000
+#define PA8_I2C1_SCL      0x00020000
+#define PA9_SPI0_CS       0x00000000
+#define PA9_PWM_CH0       0x00040000
+#define PA9_I2C1_SDA      0x00080000
+#define PA10_UART1_TX     0x00000000
+#define PA10_PWM_CH1      0x00100000
+#define PA10_UART1_SIROUT 0x00300000
+#define PA11_UART1_RX     0x00000000
+#define PA11_PWM_CH2      0x00400000
+#define PA11_UART1_SIRIN  0x00C00000
+#define PA12_UART1_CTS    0x00000000
+#define PA12_PWM_CH3      0x01000000
+#define PA12_SPI1_CLK     0x02000000
+#define PA13_UART1_RTS    0x00000000
+#define PA13_PWM_CH4      0x04000000
+#define PA13_SPI1_TX      0x08000000
+#define PA14_I2C1_SCL     0x00000000
+#define PA14_PWM_CH5      0x10000000
+#define PA14_SPI1_RX      0x20000000
+#define PA15_I2C1_SDA     0x00000000
+#define PA15_ETB_TRIG0    0x40000000
+#define PA15_SPI1_CS0     0x80000000
+
+/* IOMUX0H function definition */
+#define PA16_SPI1_CLK     0x00000000
+#define PA16_ETB_TRIG1    0x00000001
+#define PA17_SPI1_TX      0x00000000
+#define PA17_PWM_FAULT    0x00000004
+#define PA18_SPI1_RX      0x00000000
+#define PA18_PWM_CH0      0x00000010
+#define PA19_SPI1_CS0     0x00000000
+#define PA19_PWM_CH1      0x00000040
+#define PA20_UART2_RX     0x00000000
+#define PA20_PWM_CH2      0x00000100
+#define PA21_SPI1_CS2     0x00000000
+#define PA21_PWM_CH3      0x00000400
+#define PA22_UART2_RX     0x00000000
+#define PA22_PWM_CH4      0x00001000
+#define PA22_UART2_SIRI   0x00003000
+#define PA23_UART2_TX     0x00000000
+#define PA23_PWM_CH5      0x00004000
+#define PA23_UART2_SIROUT 0x0000C000
+#define PA24_UART2_CTS    0x00000000
+#define PA24_ETB_TRIG0    0x00010000
+#define PA24_SPI1_CS1     0x00020000
+#define PA25_UART2_RTS    0x00000000
+#define PA25_ETB_TRIG1    0x00040000
+#define PA25_SPI1_CS2     0x00080000
+#define PA26_UART3_TX     0x00000000
+#define PA26_PWM_FAULT    0x00100000
+#define PA26_UART3_SIROUT 0x00300000
+#define PA27_UART3_RX     0x00000000
+#define PA27_PWM_CH0      0x00400000
+#define PA27_UART3_SIRIN  0x00C00000
+#define PA28_I2S_MCLK     0x00000000
+#define PA28_PWM_CH1      0x01000000
+#define PA29_I2S_SCLK     0x00000000
+#define PA29_PWM_CH2      0x04000000
+#define PA30_I2S_WSCLK    0x00000000
+#define PA30_PWM_CH3      0x10000000
+#define PA31_I2S_SDA      0x00000000
+#define PA31_I2C0_SCL     0x40000000
+#define PA31_PWM_CH4      0x80000000
+
+/* IOMUX1L function definition */
+#define PB0_ADC0       0x00000000
+#define PB0_I2C0_SDA   0x00000001
+#define PB0_PWM_CH5    0x00000002
+#define PB1_ADC1       0x00000000
+#define PB1_I2C1_SCL   0x00000004
+#define PB1_USI_SCLK   0x00000008
+#define PB2_ADC2       0x00000000
+#define PB2_I2C1_SDA   0x00000010
+#define PB2_USI_SD0    0x00000020
+#define PB3_ADC3       0x00000000
+#define PB3_SPI1_CLK   0x00000040
+#define PB3_USI_SD1    0x00000080
+#define PB4_ADC4       0x00000000
+#define PB4_SPI1_TX    0x00000100
+#define PB4_USI_NSS    0x00000200
+#define PB5_ADC5       0x00000000
+#define PB5_SPI1_RX    0x00000400
+#define PB5_USI_SCLK   0x00000800
+#define PB6_ADC6       0x00000000
+#define PB6_SPI1_CS0   0x00001000
+#define PB6_USI_SD0    0x00002000
+#define PB7_ADC7       0x00000000
+#define PB7_SPI1_CS1   0x00004000
+#define PB7_USI_SD1    0x00008000
+#define PB8_ETB_TRIG0  0x00000000
+#define PB8_SPI1_CS2   0x00010000
+#define PB8_USI_NSS    0x00020000
+#define PB9_ETB_TRIG1  0x00000000
+#define PB9_UART3_CTS  0x00040000
+#define PB10_PWM_FAULT 0x00000000
+#define PB10_UART3_RTS 0x00100000
+
+
+/* flag as identification */
+#define GPIO_SET_BIT0  0x00000001
+#define GPIO_SET_BIT1  0x00000002
+#define GPIO_SET_BIT2  0x00000004
+#define GPIO_SET_BIT3  0x00000008
+#define GPIO_SET_BIT4  0x00000010
+#define GPIO_SET_BIT5  0x00000020
+#define GPIO_SET_BIT6  0x00000040
+#define GPIO_SET_BIT7  0x00000080
+#define GPIO_SET_BIT8  0x00000100
+#define GPIO_SET_BIT9  0x00000200
+#define GPIO_SET_BIT10 0x00000400
+#define GPIO_SET_BIT11 0x00000800
+#define GPIO_SET_BIT12 0x00001000
+#define GPIO_SET_BIT13 0x00002000
+#define GPIO_SET_BIT14 0x00004000
+#define GPIO_SET_BIT15 0x00008000
+#define GPIO_SET_BIT16 0x00010000
+#define GPIO_SET_BIT17 0x00020000
+#define GPIO_SET_BIT18 0x00040000
+#define GPIO_SET_BIT19 0x00080000
+#define GPIO_SET_BIT20 0x00100000
+#define GPIO_SET_BIT21 0x00200000
+#define GPIO_SET_BIT22 0x00400000
+#define GPIO_SET_BIT23 0x00800000
+#define GPIO_SET_BIT24 0x01000000
+#define GPIO_SET_BIT25 0x02000000
+#define GPIO_SET_BIT26 0x04000000
+#define GPIO_SET_BIT27 0x08000000
+#define GPIO_SET_BIT28 0x10000000
+#define GPIO_SET_BIT29 0x20000000
+#define GPIO_SET_BIT30 0x40000000
+#define GPIO_SET_BIT31 0x80000000
+
+/******************************************************************************
+ * phobos gpio control and gpio reuse function
+ * selecting regester adddress
+ ******************************************************************************/
+
+#define PHOBOS_GIPO0_PORTCTL_REG 0x50018008
+#define PHOBOS_GIPO1_PORTCTL_REG 0x60018008
+#define PHOBOS_IOMUX0L_REG       0x50018100
+#define PHOBOS_IOMUX0H_REG       0x50018104
+#define PHOBOS_IOMUX1L_REG       0x50018108
+
+/*************basic gpio reuse v1.0********************************************
+ * UART0(PA0,PA1)
+ * UART1(PA10,PA11)
+ * UART2(PA22,PA23)
+ * UART3(PA26,PA27)
+ * IIS(PA24,PA25,PA26,PA27)
+ * SPI1(PA16,PA17,PA18)
+ * IIC0(PA4,PA5)
+ ******************************************************************************/
+#define GPIO0_REUSE_EN                (GPIO_SET_BIT0|GPIO_SET_BIT1|GPIO_SET_BIT4|GPIO_SET_BIT5|GPIO_SET_BIT6|GPIO_SET_BIT9|GPIO_SET_BIT10|GPIO_SET_BIT11|GPIO_SET_BIT16|GPIO_SET_BIT17|GPIO_SET_BIT18|GPIO_SET_BIT22|GPIO_SET_BIT23|GPIO_SET_BIT26|GPIO_SET_BIT27)
+#define GPIO1_REUSE_EN                (GPIO_SET_BIT0)
+#define IOMUX0L_FUNCTION_SEL          (PA0_UART0_TX|PA1_UART0_RX|PA4_I2C0_SCL|PA5_I2C0_SDA|PA6_ETB_TRIG0|PA9_PWM_CH0|PA10_UART1_TX|PA11_UART1_RX)
+#define IOMUX0H_FUNCTION_SEL          (PA16_SPI1_CLK|PA17_SPI1_TX|PA18_SPI1_RX|PA22_UART2_RX|PA23_UART2_TX|PA26_UART3_TX|PA27_UART3_RX)
+#define IOMUX1L_FUNCTION_SEL          (PB0_ADC0)
+
+#define PWM_GPIO0_REUSE_EN          (GPIO0_REUSE_EN|GPIO_SET_BIT0|GPIO_SET_BIT1|GPIO_SET_BIT2|GPIO_SET_BIT12|GPIO_SET_BIT13|GPIO_SET_BIT14)
+#define PWM_IOMUX0L_FUNCTION_SEL    (IOMUX0L_FUNCTION_SEL|PA0_PWM_CH0|PA1_PWM_CH1|PA2_PWM_CH2|PA12_PWM_CH3|PA13_PWM_CH4|PA14_PWM_CH5)
+
+#endif /* PHOBOS_PINMUX_H */

bsp/ck802/drivers/soc.h

+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/**************************************************************************//**
+ * @file     soc.h
+ * @brief    CSI Core Peripheral Access Layer Header File for
+ *           CSKYSOC Device Series
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+
+#ifndef SOC_H
+#define SOC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define  SYSTEM_CLOCK    (20000000)
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+typedef enum IRQn
+{
+    /* ----------------------  CSKYCK801 Specific Interrupt Numbers  --------------------- */
+    GPIOA_IRQn                      =   0,
+    CORET_IRQn                      =   1,      /* core Timer Interrupt */
+    TIMA0_IRQn                      =   2,      /* timerA0 Interrupt */
+    TIMA1_IRQn                      =   3,      /* timerA1 Interrupt */
+    WDT_IRQn                        =   5,      /* wdt Interrupt */
+    UART0_IRQn                      =   6,      /* uart0 Interrupt */
+    UART1_IRQn                      =   7,      /* uart1 Interrupt */
+    UART2_IRQn                      =   8,      /* uart2 Interrupt */
+    I2C0_IRQn                       =   9,      /* i2c0 Interrupt */
+    I2C1_IRQn                       =   10,     /* i2c1 Interrupt */
+    SPI1_IRQn                       =   11,     /* spi0 Interrupt */
+    SPI0_IRQn                       =   12,     /* spi1 Interrupt */
+    RTC_IRQn                        =   13,     /* rtc Interrupt */
+    EXTWAK_IRQn                     =   14,     /* extwakeup Interrupt */
+    DMAC_IRQn                       =   17,     /* dmac Interrupt */
+    PMU_IRQn                        =   18,     /* pmu Interrupt */
+    PWM_IRQn                        =   19,     /* pwm Interrupt */
+    UART3_IRQn                      =   21,     /* uart3 Interrupt */
+    TIMB0_IRQn                      =   23,     /* timerB0 Interrupt */
+    TIMB1_IRQn                      =   24,     /* timerB1 Interrupt */
+    GPIOB_IRQn                      =   27,     /* GPIOB Interrupt */
+    AES_IRQn                        =   26,     /* aes Interrupt */
+    RSA_IRQn                        =   28,     /* rsa Interrupt */
+    SHA_IRQn                        =   29,     /* sha Interrupt */
+
+}
+IRQn_Type;
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+/* --------  Configuration of the CK801 Processor and Core Peripherals  ------- */
+#define __CK802_REV               0x0000U   /* Core revision r0p0 */
+#define __MGU_PRESENT             0         /* MGU present or not */
+#define __NVIC_PRIO_BITS          2         /* Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig    0         /* Set to 1 if different SysTick Config is used */
+
+#include "core_ck802.h"                     /* Processor and core peripherals */
+#include "stdint.h"
+
+typedef enum
+{
+    CKENUM_DMA_UART0_RX,
+    CKENUM_DMA_UART0_TX,
+    CKENUM_DMA_UART1_RX,
+    CKENUM_DMA_UART1_TX,
+    CKENUM_DMA_ADC_RX,
+    CKENUM_DMA_ADC_TX,
+    CKENUM_DMA_SPI1_RX,
+    CKENUM_DMA_SPI1_TX,
+    CKENUM_DMA_SPI0_RX,
+    CKENUM_DMA_SPI0_TX,
+    CKENUM_DMA_IIC_RX,
+    CKENUM_DMA_IIC_TX,
+    CKENUM_DMA_IIC1_RX,
+    CKENUM_DMA_IIC1_TX,
+    CKENUM_DMA_IIS_RX,
+    CKENUM_DMA_IIS_TX,
+    CKENUM_DMA_MEMORY
+} ckenum_dma_device_e;
+
+/* ================================================================================ */
+/* ================       Device Specific Peripheral Section       ================ */
+/* ================================================================================ */
+#if 0
+
+/* ================================================================================ */
+/* ============== Universal Asyncronous Receiver / Transmitter (UART) ============= */
+/* ================================================================================ */
+typedef struct
+{
+    union
+    {
+        __IM uint32_t RBR;           /* Offset: 0x000 (R/ )  Receive buffer register */
+        __OM uint32_t THR;           /* Offset: 0x000 ( /W)  Transmission hold register */
+        __IOM uint32_t DLL;          /* Offset: 0x000 (R/W)  Clock frequency division low section register */
+    };
+    union
+    {
+        __IOM uint32_t DLH;          /* Offset: 0x004 (R/W)  Clock frequency division high section register */
+        __IOM uint32_t IER;          /* Offset: 0x004 (R/W)  Interrupt enable register */
+    };
+    __IM uint32_t IIR;             /* Offset: 0x008 (R/ )  Interrupt indicia register */
+    __IOM uint32_t LCR;            /* Offset: 0x00C (R/W)  Transmission control register */
+    __IOM uint32_t MCR;            /* Offset: 0x010 (R/W)  Modem control register */
+    __IM uint32_t LSR;             /* Offset: 0x014 (R/ )  Transmission state register */
+    __IM uint32_t MSR;             /* Offset: 0x018 (R/ )  Modem state register */
+    uint32_t RESERVED1[24];
+    __IM uint32_t USR;             /* Offset: 0x07c (R/ )  UART state register */
+} CSKY_UART_TypeDef;
+
+/* ================================================================================ */
+/* ==============            Inter-Integrated Circuit (IIC)           ============= */
+/* ================================================================================ */
+typedef struct
+{
+    __IOM uint32_t IC_CON;                    /* Offset: 0x000 (R/W)  Receive buffer register */
+    __IOM uint32_t IC_TAR;                    /* Offset: 0x004 (R/W)  Transmission hold register */
+    __IOM uint32_t IC_SAR;                    /* Offset: 0x008 (R/W)  Clock frequency division low section register */
+    __IOM uint32_t IC_HS_MADDR;               /* Offset: 0x00c (R/W)  Clock frequency division high section register */
+    __IOM uint32_t IC_DATA_CMD;               /* Offset: 0x010 (R/W)  Interrupt enable register */
+    __IOM uint32_t IC_SS_SCL_HCNT;            /* Offset: 0x014 (R/W)  Interrupt indicia register */
+    __IOM uint32_t IC_SS_SCL_LCNT;            /* Offset: 0x018 (R/W)  Transmission control register */
+    __IOM uint32_t IC_FS_SCL_HCNT;            /* Offset: 0x01c (R/W)  Modem control register */
+    __IOM uint32_t IC_FS_SCL_LCNT;            /* Offset: 0x020 (R/W)  Transmission state register */
+    __IOM uint32_t IC_HS_SCL_HCNT;            /* Offset: 0x024 (R/W)  Transmission state register */
+    __IOM uint32_t IC_HS_SCL_LCNT;            /* Offset: 0x028 (R/W)  Transmission state register */
+    __IOM uint32_t IC_INTR_STAT;              /* Offset: 0x02c (R)  Transmission state register */
+    __IOM uint32_t IC_INTR_MASK;              /* Offset: 0x030 (R/W)  Transmission state register */
+    __IOM uint32_t IC_RAW_INTR_STAT;          /* Offset: 0x034 (R)  Transmission state register */
+    __IOM uint32_t IC_RX_TL;                  /* Offset: 0x038 (R/W)  Transmission state register */
+    __IOM uint32_t IC_TX_TL;                  /* Offset: 0x03c (R/W)  Transmission state register */
+    __IOM uint32_t IC_CLR_INTR;               /* Offset: 0x040 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_RX_UNDER;           /* Offset: 0x044 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_RX_OVER;            /* Offset: 0x048 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_TX_OVER;            /* Offset: 0x04c (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_RD_REQ;             /* Offset: 0x050 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_TX_ABRT;            /* Offset: 0x054 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_RX_DONE;            /* Offset: 0x058 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_ACTIVITY;           /* Offset: 0x05c (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_STOP_DET;           /* Offset: 0x060 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_START_DET;          /* Offset: 0x064 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_GEN_CALL;           /* Offset: 0x068 (R)  Transmission state register */
+    __IOM uint32_t IC_ENABLE;                 /* Offset: 0x06c (R/W)  Transmission state register */
+    __IOM uint32_t IC_STATUS;                 /* Offset: 0x070 (R)  Transmission state register */
+    __IOM uint32_t IC_TXFLR;                  /* Offset: 0x074 (R)  Transmission state register */
+    __IOM uint32_t IC_RXFLR;                  /* Offset: 0x078 (R)  Transmission state register */
+    uint32_t RESERVED;                        /* Offset: 0x014 (R/ )  Transmission state register */
+    __IOM uint32_t IC_TX_ABRT_SOURCE;         /* Offset: 0x080 (R/W)  Transmission state register */
+    __IOM uint32_t IC_SAR1;                   /* Offset: 0x084 (R/W)  Transmission state register */
+    __IOM uint32_t IC_DMA_CR;                 /* Offset: 0x088 (R/W)  Transmission state register */
+    __IOM uint32_t IC_DMA_TDLR;               /* Offset: 0x08c (R/W)  Transmission state register */
+    __IOM uint32_t IC_DMA_RDLR;               /* Offset: 0x090 (R/W)  Transmission state register */
+    __IOM uint32_t IC_SAR2;                   /* Offset: 0x094 (R/W)  Transmission state register */
+    __IOM uint32_t IC_SAR3;                   /* Offset: 0x098 (R/W)  Transmission state register */
+    __IOM uint32_t IC_MULTI_SLAVE;            /* Offset: 0x09c (R/W)  Transmission state register */
+    __IOM uint32_t IC_GEN_CALL_EN;            /* Offset: 0x0a0 (R/W)  Transmission state register */
+
+} CSKY_IIC_TypeDef;
+
+/* ================================================================================ */
+/* ==============                          TIMER                      ============= */
+/* ================================================================================ */
+typedef struct
+{
+    __IOM uint32_t TxLoadCount;               /* Offset: 0x000 (R/W)  Receive buffer register */
+    __IOM uint32_t TxCurrentValue;            /* Offset: 0x004 (R)  Transmission hold register */
+    __IOM uint32_t TxControl;                 /* Offset: 0x008 (R/W)  Clock frequency division low section register */
+    __IOM uint32_t TxEOI;                     /* Offset: 0x00c (R)  Clock frequency division high section register */
+    __IOM uint32_t TxIntStatus;               /* Offset: 0x010 (R)  Interrupt enable register */
+
+} CSKY_TIMER_TypeDef;
+
+/* ================================================================================ */
+/* ==============                    TIMER  Control                   ============= */
+/* ================================================================================ */
+typedef struct
+{
+    __IOM uint32_t TimersIntStatus;            /* Offset: 0x000 (R)  Interrupt indicia register */
+    __IOM uint32_t TimerEOI;                   /* Offset: 0x004 (R)  Transmission control register */
+    __IOM uint32_t TimerRawIntStatus;          /* Offset: 0x008 (R)  Modem control register */
+
+} CSKY_TIMER_Control_TypeDef;
+
+/* ================================================================================ */
+/* ==============                        GPIO                         ============= */
+/* ================================================================================ */
+typedef struct
+{
+    __IOM uint32_t SWPORT_DR;                 /* Offset: 0x000 (R/W)  Interrupt indicia register */
+    __IOM uint32_t SWPORT_DDR;                /* Offset: 0x004 (R/W)  Interrupt indicia register */
+    __IOM uint32_t PORT_CTL;                  /* Offset: 0x008 (R/W)  Interrupt indicia register */
+} CKStruct_GPIO, *PCKStruct_GPIO;
+
+typedef struct
+{
+    __IOM uint32_t SHA_CON;                     /* Offset: 0x000 (R/W)  Control register */
+    __IOM uint32_t SHA_INTSTATE;                /* Offset: 0x004 (R/W)  Instatus register */
+    __IOM uint32_t SHA_H0L;                     /* Offset: 0x008 (R/W)  H0L register */
+    __IOM uint32_t SHA_H1L;                     /* Offset: 0x00c (R/W)  H1L register */
+    __IOM uint32_t SHA_H2L;                     /* Offset: 0x010 (R/W)  H2L register */
+    __IOM uint32_t SHA_H3L;                     /* Offset: 0x014 (R/W)  H3L register */
+    __IOM uint32_t SHA_H4L;                     /* Offset: 0x018 (R/W)  H4L register */
+    __IOM uint32_t SHA_H5L;                     /* Offset: 0x01c (R/W)  H5L register */
+    __IOM uint32_t SHA_H6L;                     /* Offset: 0x020 (R/W)  H6L register */
+    __IOM uint32_t SHA_H7L;                     /* Offset: 0x024 (R/W)  H7L register */
+    __IOM uint32_t SHA_H0H;                     /* Offset: 0x028 (R/W)  H0H register */
+    __IOM uint32_t SHA_H1H;                     /* Offset: 0x02c (R/W)  H1H register */
+    __IOM uint32_t SHA_H2H;                     /* Offset: 0x030 (R/W)  H2H register */
+    __IOM uint32_t SHA_H3H;                     /* Offset: 0x034 (R/W)  H3H register */
+    __IOM uint32_t SHA_H4H;                     /* Offset: 0x038 (R/W)  H4H register */
+    __IOM uint32_t SHA_H5H;                     /* Offset: 0x03c (R/W)  H5H register */
+    __IOM uint32_t SHA_H6H;                     /* Offset: 0x040 (R/W)  H6H register */
+    __IOM uint32_t SHA_H7H;                     /* Offset: 0x044 (R/W)  H7H register */
+    __IOM uint32_t SHA_DATA1;                   /* Offset: 0x048 (R/W)  DATA1 register */
+    uint32_t REV[15];
+    __IOM uint32_t SHA_DATA2;                   /* Offset: 0x088 (R/W)  DATA2 register */
+} CSKY_SHA_TypeDef;
+
+#endif
+
+#define CONFIG_CRC_NUM  1
+#define CONFIG_IIC_NUM  2
+#define CONFIG_TRNG_NUM 1
+#define CONFIG_EFLASH_NUM 1
+#define CONFIG_AES_NUM  1
+#define CONFIG_RSA_NUM  1
+#define CONFIG_SHA_NUM  1
+#define CONFIG_SPI_NUM  2
+#define CONFIG_PWM_NUM  1
+#define CONFIG_TIMER_NUM 4
+#define CONFIG_RTC_NUM 1
+#define CONFIG_WDT_NUM 1
+#define CONFIG_DMAC_NUM 1
+#define CONFIG_ETH_NUM 2
+
+#define CSKY_I2C0_BASE             (0x50014000UL)
+#define CSKY_I2C1_BASE             (0x60014000UL)
+
+#define CONFIG_USART_NUM 4
+#define CSKY_UART0_BASE            (0x50010000UL)
+#define CSKY_UART1_BASE            (0x50010400UL)
+#define CSKY_UART2_BASE            (0x60010000UL)
+#define CSKY_UART3_BASE            (0x60010400UL)
+
+/* ================================================================================ */
+/* ================              Peripheral memory map             ================ */
+/* ================================================================================ */
+/* --------------------------  CPU FPGA memory map  ------------------------------- */
+#define CSKY_EFLASH_BASE           (0x10000000UL)
+#define CSKY_SRAM_BASE             (0x20000000UL)
+
+#define CSKY_PMU_BASE              (0x40000000UL)
+#define CSKY_DMA_BASE              (0x40001000UL)
+#define CSKY_EFLASH_CONTROL_BASE   (0x40005000UL)
+#define CSKY_OTP_BASE              (0x40006000UL)
+#define CSKY_SRAM_CONTROL_BASE     (0x40009000UL)
+#define CSKY_AES_BASE              (0x4000d000UL)
+#define CSKY_SHA_BASE              (0x4000e000UL)
+#define CSKY_RSA_BASE              (0x4000f000UL)
+#define CSKY_CRC_BASE              (0x40010000UL)
+#define CSKY_TRNG_BASE             (0x40015000UL)
+#define CSKY_TIMERA0_BASE          (0x50000000UL)
+#define CSKY_TIMERA1_BASE          (0x50000014UL)
+#define CSKY_TIMERA_CONTROL_BASE   (0x500000a0UL)
+#define CSKY_RTC_BASE              (0x50004000UL)
+#define CSKY_WDT_BASE              (0x50008000UL)
+#define CSKY_SPI0_BASE             (0x5000c000UL)
+
+#define CONFIG_GPIO_NUM            2
+#define CONFIG_GPIO_PIN_NUM        43
+#define CSKY_GPIOA_BASE            (0x50018000UL)
+#define CSKY_GPIOA_CONTROL_BASE    (0x50018030UL)
+#define CSKY_PWM_BASE              (0x5001c000UL)
+#define CSKY_ADC_BASE              (0x50020000UL)
+#define CSKY_I2S0_BASE             (0x50030000UL)
+#define CSKY_TIMERB0_BASE          (0x60000000UL)
+#define CSKY_TIMERB1_BASE          (0x60000014UL)
+#define CSKY_SPI1_BASE             (0x6000c000UL)
+
+#define CSKY_GPIOB_BASE            (0x60018000UL)
+#define CSKY_GPIOB_CONTROL_BASE    (0x60018030UL)
+#define CSKY_TIMERB_CONTROL_BASE   (0x600000a0UL)
+#define CSKY_SIPC_BASE             (0x6001c000UL)
+#define CSKY_I2S1_BASE             (0x60020000UL)
+#define CSKY_ETB_BASE              (0x60024000UL)
+#define CSKY_USI_BASE              (0x60028000UL)
+
+/* ================================================================================ */
+/* ================             Peripheral declaration             ================ */
+/* ================================================================================ */
+#define CSKY_UART1                 ((   CSKY_UART_TypeDef *)    CSKY_UART1_BASE)
+#define CSKY_SHA                   ((   CSKY_SHA_TypeDef *)     CSKY_SHA_BASE)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* SOC_H */

bsp/ck802/drivers/system.c

+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     system_PHOBOS.c
+ * @brief    CSI Device System Source File for PHOBOS
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+
+#include "soc.h"
+#include "csi_core.h"
+#include "config.h"
+
+/*----------------------------------------------------------------------------
+  Define clocks
+ *----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------
+  System Core Clock Variable
+ *----------------------------------------------------------------------------*/
+int SystemCoreClock = SYSTEM_CLOCK;  /* System Core Clock Frequency      */
+
+extern int __Vectors;
+
+void SystemCoreClockUpdate(void)
+{
+    SystemCoreClock = SYSTEM_CLOCK;
+}
+
+/**
+  * @brief  initialize the system
+  *         Initialize the psr and vbr.
+  * @param  None
+  * @return None
+  */
+void SystemInit(void)
+{
+    /* Here we may setting exception vector, MGU, cache, and so on. */
+#ifdef CONFIG_SYSTEM_SECURE
+    __set_PSR(0xc0000140);
+#else
+    __set_PSR(0x80000140);
+#endif
+    __set_VBR((uint32_t) & (__Vectors));
+
+    drv_coret_config(200 * 1000, CORET_IRQn);    //10ms
+    drv_nvic_enable_irq(CORET_IRQn);
+
+    SystemCoreClock = SYSTEM_CLOCK;
+}

bsp/ck802/gcc_csky.ld

+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     gcc_csky.h
+ * @brief    csky linker file for PHOBOS
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+MEMORY
+{
+	ROM    : ORIGIN = 0x0        , LENGTH = 0x1FFF    /* ROM  8KB*/
+	EFLASH : ORIGIN = 0x10000000 , LENGTH = 0x3FFFF   /* E-FLASH 256KB*/
+	SRAM   : ORIGIN = 0x20000000 , LENGTH = 0x18000   /* on-chip SRAM 128KB*/
+}
+
+PROVIDE (__StackTop = 0x20020000 - 0x8);
+PROVIDE (Stack_Size = 0x1000);
+/*
+PROVIDE (__heap_start = 0x20018000);
+PROVIDE (__heap_end = 0x2001a000);
+PROVIDE (Heap_Size = 0x2000);
+*/
+
+REGION_ALIAS("REGION_TEXT",    SRAM);
+REGION_ALIAS("REGION_RODATA",  SRAM);
+REGION_ALIAS("REGION_CUSTOM1", SRAM);
+REGION_ALIAS("REGION_CUSTOM2", SRAM);
+REGION_ALIAS("REGION_DATA",    SRAM);
+REGION_ALIAS("REGION_BSS",     SRAM);
+
+ENTRY(Reset_Handler)
+SECTIONS
+{
+ .text : AT(ADDR(.text)){
+  . = ALIGN(0x4) ;
+  *(.vectors)
+  __stext = . ;
+  *(.text)
+  *(.text*)
+  *(.text.*)
+  *(.gnu.warning)
+  *(.stub)
+  *(.gnu.linkonce.t*)
+  *(.glue_7t)
+  *(.glue_7)
+  *(.jcr)
+  *(.init)
+  *(.fini)
+
+  . = ALIGN (4) ;
+  PROVIDE(__ctbp = .);
+  *(.call_table_data)
+  *(.call_table_text)
+
+	/* section information for finsh shell */
+	. = ALIGN(4);
+	__fsymtab_start = .;
+	KEEP(*(FSymTab))
+	__fsymtab_end = .;
+	. = ALIGN(4);
+	__vsymtab_start = .;
+	KEEP(*(VSymTab))
+	__vsymtab_end = .;
+	. = ALIGN(4);
+
+	/* section information for initial. */
+	. = ALIGN(4);
+	__rt_init_start = .;
+	KEEP(*(SORT(.rti_fn*)))
+	__rt_init_end = .;
+	. = ALIGN(4);
+  . = ALIGN(0x10) ;
+  __etext = . ;
+ } > REGION_TEXT
+ .rodata : AT(LOADADDR(.text) + SIZEOF(.text)){
+  . = ALIGN(0x4) ;
+  __srodata = .;
+  *(.rdata)
+  *(.rdata*)
+  *(.rdata1)
+  *(.rdata.*)
+  *(.rodata)
+  *(.rodata1)
+  *(.rodata*)
+  *(.rodata.*)
+  *(.rodata.str1.4)
+  . = ALIGN(0x4) ;
+  __erodata = .;
+ } > REGION_RODATA
+ .data : AT(LOADADDR(.rodata) + SIZEOF(.rodata)){
+  . = ALIGN(0x4) ;
+  __sdata = . ;
+  __data_start__ = . ;
+  data_start = . ;
+  *(.got.plt)
+  *(.got)
+  *(.gnu.linkonce.r*)
+  *(.data)
+  *(.data*)
+  *(.data1)
+  *(.data.*)
+  *(.gnu.linkonce.d*)
+  *(.data1)
+  *(.gcc_except_table)
+  *(.gcc_except_table*)
+  __start_init_call = .;
+  *(.initcall.init)
+  __stop_init_call = .;
+  __start_cmd = .;
+  *(.bootloaddata.cmd)
+  . = ALIGN(4) ;
+  __stop_cmd = .;
+  *(.sdata)
+  *(.sdata.*)
+  *(.gnu.linkonce.s.*)
+  *(__libc_atexit)
+  *(__libc_subinit)
+  *(__libc_subfreeres)
+  *(.note.ABI-tag)
+  . = ALIGN(0x4) ;
+  __edata = .;
+  __data_end__ = .;
+ } > REGION_DATA
+ .bss : {
+  . = ALIGN(0x4) ;
+  __sbss = ALIGN(0x4) ;
+  __bss_start__ = . ;
+  *(.dynsbss)
+  *(.sbss)
+  *(.sbss.*)
+  *(.scommon)
+  *(.dynbss)
+  *(.bss)
+  *(.bss.*)
+  *(COMMON)
+  . = ALIGN(0x4) ;
+  __ebss = . ;
+  __end = . ;
+  end = . ;
+  __bss_end__ = .;
+ } > REGION_BSS
+ .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } > REGION_BSS
+ .gcc_except_table : ONLY_IF_RO { *(.gcc_except_table .gcc_except_table.*) } > REGION_BSS
+ .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) }
+ .gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) }
+ .eh_frame_hdr : { *(.eh_frame_hdr) }
+ .preinit_array :
+ {
+  PROVIDE_HIDDEN (__preinit_array_start = .);
+  KEEP (*(.preinit_array))
+  PROVIDE_HIDDEN (__preinit_array_end = .);
+ }
+ .init_array :
+ {
+  PROVIDE_HIDDEN (__init_array_start = .);
+  KEEP (*(SORT(.init_array.*)))
+  KEEP (*(.init_array))
+  PROVIDE_HIDDEN (__init_array_end = .);
+ }
+ .fini_array :
+ {
+  PROVIDE_HIDDEN (__fini_array_start = .);
+  KEEP (*(.fini_array))
+  KEEP (*(SORT(.fini_array.*)))
+  PROVIDE_HIDDEN (__fini_array_end = .);
+ }
+ .ctors :
+ {
+  KEEP (*crtbegin.o(.ctors))
+  KEEP (*crtbegin?.o(.ctors))
+  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+  KEEP (*(SORT(.ctors.*)))
+  KEEP (*(.ctors))
+ } > REGION_BSS
+ .dtors :
+ {
+  KEEP (*crtbegin.o(.dtors))
+  KEEP (*crtbegin?.o(.dtors))
+  KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+  KEEP (*(SORT(.dtors.*)))
+  KEEP (*(.dtors))
+ } > REGION_BSS
+ .junk 0 : { *(.rel*) *(.rela*) }
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ .debug_pubtypes 0 : { *(.debug_pubtypes) }
+ .debug_ranges 0 : { *(.debug_ranges) }
+ .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
+ /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
+}

bsp/ck802/libraries/SConscript

+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+src = Split("""
+startup_gcc.S
+common/aes/ck_aes.c
+common/crc/ck_crc.c
+common/dmac/ck_dmac.c
+common/eflash/ck_eflash.c
+common/pwm/ck_pwm.c
+common/rsa/ck_rsa.c
+common/sha/ck_sha.c
+common/trng/ck_trng.c
+common/timer/dw_timer.c
+common/gpio/dw_gpio.c
+common/spi/dw_spi.c
+common/iic/dw_iic.c
+common/usart/dw_usart.c
+common/wdt/dw_wdt.c
+""")
+
+path = [cwd + '/include',
+    cwd + '/common/aes', 
+    cwd + '/common/aes',
+    cwd + '/common/crc',
+    cwd + '/common/dmac',
+    cwd + '/common/eflash',
+    cwd + '/common/gpio',
+    cwd + '/common/iic',
+    cwd + '/common/pwm',
+    cwd + '/common/rsa',
+    cwd + '/common/rtc',
+    cwd + '/common/sha',
+    cwd + '/common/spi',
+    cwd + '/common/timer',
+    cwd + '/common/trng',
+    cwd + '/common/usart',
+    cwd + '/common/wdt'
+]
+
+group = DefineGroup('libraries', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/ck802/libraries/common/aes/ck_aes.c

+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     ck_aes.c
+ * @brief    CSI Source File for aes driver
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+#include "csi_core.h"
+#include "drv_aes.h"
+#include "ck_aes.h"
+
+#define ERR_AES(errno) (CSI_DRV_ERRNO_AES_BASE | errno)
+#define AES_NULL_PARA_CHK(para)                         \
+        do {                                        \
+            if (para == NULL) {                     \
+                return ERR_AES(EDRV_PARAMETER);   \
+            }                                       \
+        } while (0)
+static ck_aes_reg_t *aes_reg = NULL;
+
+typedef struct {
+    uint32_t base;
+    uint32_t irq;
+    void *iv;
+    uint8_t *result_out;
+    uint32_t len;
+    aes_event_cb_t cb;
+    aes_mode_e mode;
+    aes_key_len_bits_e keylen;
+    aes_endian_mode_e endian;
+    aes_status_t status;
+} ck_aes_priv_t;
+
+static ck_aes_priv_t aes_handle[CONFIG_AES_NUM];
+
+/* Driver Capabilities */
+static const aes_capabilities_t driver_capabilities = {
+    .ecb_mode = 1, /* ECB mode */
+    .cbc_mode = 1, /* CBC mode */
+    .cfb_mode = 0, /* CFB mode */
+    .ofb_mode = 0, /* OFB mode */
+    .ctr_mode = 0, /* CTR mode */
+    .bits_128 = 1, /* 128bits key length mode */
+    .bits_192 = 1, /* 192bits key lenght mode */
+    .bits_256 = 1  /* 256bits key length mode */
+};
+
+//
+// Functions
+//
+
+static inline void aes_set_opcode(aes_crypto_mode_e opcode)
+{
+    aes_reg->ctrl &= ~(3 << AES_OPCODE_OFFSET);          //clear bit[7:6]
+    aes_reg->ctrl |= (opcode << AES_OPCODE_OFFSET);    //set opcode
+}
+
+static inline void aes_set_endian(aes_endian_mode_e endian)
+{
+    if (endian == AES_ENDIAN_LITTLE) {
+        aes_reg->ctrl &= ~AES_LITTLE_ENDIAN;
+    } else {
+        aes_reg->ctrl |= AES_LITTLE_ENDIAN;
+    }
+}
+
+static inline uint32_t aes_set_keylen(aes_key_len_bits_e keylength)
+{
+    aes_reg->ctrl &= ~(3 << AES_KEY_LEN_OFFSET);        //clear bit[5:4]
+    aes_reg->ctrl |= (keylength << AES_KEY_LEN_OFFSET);// Set key length
+
+    return 0;
+}
+
+static inline void aes_set_mode(aes_mode_e mode)
+{
+    aes_reg->ctrl &= ~(1 << AES_MODE_OFFSET);      //clear bit 3
+    aes_reg->ctrl |= (mode << AES_MODE_OFFSET);  //set mode
+}
+
+static inline void aes_enable(void)
+{
+    aes_reg->ctrl |= (1 << AES_WORK_ENABLE_OFFSET);
+}
+
+static inline void aes_disable(void)
+{
+    aes_reg->ctrl &= ~(1 << AES_WORK_ENABLE_OFFSET);
+}
+
+static inline void aes_enable_interrupt(void)
+{
+    aes_reg->ctrl |= (1 << AES_INT_ENABLE_OFFSET);
+}
+
+static inline void aes_disable_interrupt(void)
+{
+    aes_reg->ctrl &= ~(1 << AES_INT_ENABLE_OFFSET);
+}
+
+static inline void aes_clear_interrupt(void)
+{
+    aes_reg->state = 0x0;
+}
+
+static inline uint32_t aes_get_intstatus(uint32_t AES_IT)
+{
+    return (aes_reg->state & AES_IT) ? 1 : 0;
+}
+
+static void aes_set_key(void *context, uint8_t *key, uint32_t keylen, uint32_t enc, uint32_t endian)
+{
+    uint8_t keynum = 0;
+
+    if (keylen == AES_KEY_LEN_BITS_128) {
+        keynum = 4;
+    } else if (keylen == AES_KEY_LEN_BITS_192) {
+        keynum = 6;
+    } else if (keylen == AES_KEY_LEN_BITS_256) {
+        keynum = 8;
+    }
+
+    uint32_t i;
+    /* set key according to the endian mode */
+    if (endian == AES_ENDIAN_LITTLE) {
+        for (i = 0; i < keynum; i++) {
+            aes_reg->key[keynum - 1 - i] = *(uint32_t *)key;
+            key += 4;
+        }
+    } else if (endian == AES_ENDIAN_BIG) {
+        for (i = 0; i < keynum; i++) {
+            aes_reg->key[i] = *(uint32_t *)key;
+            key += 4;
+        }
+    }
+
+    if (enc == AES_CRYPTO_MODE_DECRYPT) {
+        aes_set_opcode(AES_CRYPTO_KEYEXP);      /* if the mode is decrypt before decrypt you have to keyexpand */
+        aes_enable();
+
+        while (aes_get_intstatus(AES_IT_KEYINT));
+
+        aes_set_opcode(AES_CRYPTO_MODE_DECRYPT);
+    } else if (enc == AES_CRYPTO_MODE_ENCRYPT) {
+        aes_set_opcode(AES_CRYPTO_MODE_ENCRYPT);
+    }
+
+    aes_disable();
+}
+
+static int aes_crypto(void *context, uint8_t *in, uint8_t *out,
+               uint32_t len, uint8_t *iv, uint32_t mode, uint32_t endian)
+{
+    uint32_t i = 0;
+
+    /* set iv if the mode is CBC */
+    if (mode == AES_MODE_CBC) {
+        if (endian == AES_ENDIAN_BIG) {
+            for (i = 0; i < 4; i++) {
+                aes_reg->iv[i] = *(uint32_t *)iv;
+                iv += 4;
+            }
+        } else if (endian == AES_ENDIAN_LITTLE) {
+            for (i = 0; i < 4; i++) {
+                aes_reg->iv[3 - i] = *(uint32_t *)iv;
+                iv += 4;
+            }
+        }
+    }
+
+    uint32_t j = 0;
+    /* set the text before aes calculating */
+    for (i = 0; i < len; i = i + 16) {
+        for (j = 0; j < 4; j++) {
+            if (endian == AES_ENDIAN_BIG) {
+                aes_reg->datain[j] = *(uint32_t *)in;
+            } else if (endian == AES_ENDIAN_LITTLE) {
+                aes_reg->datain[3 - j] = *(uint32_t *)in;
+            }
+
+            in += 4;
+        }
+
+        aes_enable();
+    }
+
+    return 0;
+}
+
+void ck_aes_irqhandler(int32_t idx)
+{
+    ck_aes_priv_t *aes_priv = &aes_handle[idx];
+
+    volatile uint32_t j;
+    uint32_t tmp = 0;
+    /* get the result after aes calculating*/
+    if (aes_priv->result_out != NULL) {
+        for (j = 0; j < 4; j++) {
+            if (aes_priv->endian == AES_ENDIAN_BIG) {
+                tmp = aes_reg->dataout[j];
+            } else if (aes_priv->endian == AES_ENDIAN_LITTLE) {
+                tmp = aes_reg->dataout[3 - j];
+            }
+
+            *(uint32_t *)aes_priv->result_out = tmp;
+            aes_priv->result_out += 4;
+            aes_priv->len -= 4;
+        }
+    }
+
+    /* disable aes and clear the aes interrupt */
+    aes_disable();
+    aes_clear_interrupt();
+
+    /* execute the callback function */
+    if (aes_priv->len == 0) {
+        if (aes_priv->cb) {
+            aes_priv->cb(AES_EVENT_CRYPTO_COMPLETE);
+        }
+    }
+}
+
+
+int32_t __attribute__((weak)) target_get_aes_count(void)
+{
+    return 0;
+}
+
+int32_t __attribute__((weak)) target_get_aes(int32_t idx, uint32_t *base, uint32_t *irq)
+{
+    return NULL;
+}
+
+/**
+  \brief       get aes instance count.
+  \return      aes handle count
+*/
+int32_t csi_aes_get_instance_count(void)
+{
+    return target_get_aes_count();
+}
+
+/**
+  \brief       Initialize AES Interface. 1. Initializes the resources needed for the AES interface 2.registers event callback function
+  \param[in]   idx must not exceed return value of csi_aes_get_instance_count().
+  \param[in]   cb_event  Pointer to \ref aes_event_cb_t
+  \return      return aes handle if success
+*/
+aes_handle_t csi_aes_initialize(int32_t idx, aes_event_cb_t cb_event)
+{
+
+    if (idx < 0 || idx >= CONFIG_AES_NUM) {
+        return NULL;
+    }
+
+    uint32_t irq = 0u;
+    uint32_t base = 0u;
+    /* obtain the aes information */
+    int32_t real_idx = target_get_aes(idx, &base, &irq);
+
+    if (real_idx != idx) {
+        return NULL;
+    }
+
+    ck_aes_priv_t *aes_priv = &aes_handle[idx];
+
+    aes_priv->base = base;
+    aes_priv->irq  = irq;
+
+    /* initialize the aes context */
+    aes_reg = (ck_aes_reg_t *)(aes_priv->base);
+    aes_priv->cb = cb_event;
+    aes_priv->iv = NULL;
+    aes_priv->len = 16;
+    aes_priv->result_out = NULL;
+    aes_priv->mode = AES_MODE_CBC;
+    aes_priv->keylen = AES_KEY_LEN_BITS_128;
+    aes_priv->endian = AES_ENDIAN_LITTLE;
+    aes_priv->status.busy = 0;
+
+    aes_enable_interrupt();             /* enable the aes interrupt */
+
+    drv_nvic_enable_irq(aes_priv->irq); /* enable the aes bit in nvic */
+
+    return (aes_handle_t)aes_priv;
+}
+
+/**
+  \brief       De-initialize AES Interface. stops operation and releases the software resources used by the interface
+  \param[in]   handle  aes handle to operate.
+  \return      error code
+*/
+int32_t csi_aes_uninitialize(aes_handle_t handle)
+{
+    AES_NULL_PARA_CHK(handle);
+
+    ck_aes_priv_t *aes_priv = handle;
+    aes_priv->cb = NULL;
+
+    aes_disable_interrupt();            /* disable the aes interrupt */
+
+    drv_nvic_disable_irq(aes_priv->irq);
+
+    return 0;
+}
+
+/**
+  \brief       Get driver capabilities.
+  \param[in]   handle  aes handle to operate.
+  \return      \ref aes_capabilities_t
+*/
+aes_capabilities_t csi_aes_get_capabilities(aes_handle_t handle)
+{
+    return driver_capabilities;
+}
+
+/**
+  \brief       config aes mode.
+  \param[in]   handle  aes handle to operate.
+  \param[in]   mode      \ref aes_mode_e
+  \param[in]   keylen_bits \ref aes_key_len_bits_e
+  \param[in]   endian    \ref aes_endian_mode_e
+  \param[in]   arg       Pointer to the iv address when mode is cbc_mode
+  \return      error code
+*/
+int32_t csi_aes_config(aes_handle_t handle, aes_mode_e mode, aes_key_len_bits_e keylen_bits, aes_endian_mode_e endian, uint32_t arg)
+{
+    AES_NULL_PARA_CHK(handle);
+
+    ck_aes_priv_t *aes_priv = handle;
+    aes_reg = (ck_aes_reg_t *)(aes_priv->base);
+
+    /* config the aes mode */
+    switch (mode) {
+        case AES_MODE_CBC:
+            aes_priv->iv = (void *)arg;
+            aes_priv->mode = mode;
+            aes_set_mode(mode);
+            break;
+
+        case AES_MODE_ECB:
+            aes_priv->mode = mode;
+            aes_set_mode(mode);
+            break;
+
+        case AES_MODE_CFB:
+        case AES_MODE_OFB:
+        case AES_MODE_CTR:
+            return ERR_AES(EDRV_UNSUPPORTED);
+
+        default:
+            return ERR_AES(EDRV_PARAMETER);
+    }
+
+    /* config the key length */
+    switch (keylen_bits) {
+        case AES_KEY_LEN_BITS_128:
+        case AES_KEY_LEN_BITS_192:
+        case AES_KEY_LEN_BITS_256:
+            aes_priv->keylen = keylen_bits;
+            aes_set_keylen(keylen_bits);
+            break;
+
+        default:
+            return ERR_AES(EDRV_PARAMETER);
+    }
+
+    /* config the endian mode */
+    switch (endian) {
+        case AES_ENDIAN_LITTLE:
+            aes_priv->endian = endian;
+            aes_set_endian(endian);
+            break;
+
+        case AES_ENDIAN_BIG:
+            aes_priv->endian = endian;
+            aes_set_endian(endian);
+            break;
+
+        default:
+            return ERR_AES(EDRV_PARAMETER);
+    }
+
+    return 0;
+}
+
+/**
+  \brief       set crypto key.
+  \param[in]   handle    aes handle to operate.
+  \param[in]   context   aes information context(NULL when hardware implementation)
+  \param[in]   key       Pointer to the key buf
+  \param[in]   key_len    the key len
+  \param[in]   enc       \ref aes_crypto_mode_e
+  \return      error code
+*/
+int32_t csi_aes_set_key(aes_handle_t handle, void *context, void *key, uint32_t key_len, aes_crypto_mode_e enc)
+{
+    AES_NULL_PARA_CHK(handle);
+    AES_NULL_PARA_CHK(key);
+    if ((key_len != AES_KEY_LEN_BITS_128 &&
+        key_len != AES_KEY_LEN_BITS_192 &&
+        key_len != AES_KEY_LEN_BITS_256) ||
+        (enc != AES_CRYPTO_MODE_ENCRYPT &&
+        enc != AES_CRYPTO_MODE_DECRYPT)) {
+        return ERR_AES(EDRV_PARAMETER);
+    }
+
+    ck_aes_priv_t *aes_priv = handle;
+    aes_set_key(context, key, key_len, enc, aes_priv->endian);
+
+    return 0;
+}
+
+/**
+  \brief       encrypt or decrypt
+  \param[in]   handle  aes handle to operate.
+  \param[in]   context aes information context(NULL when hardware implementation)
+  \param[in]   in   Pointer to the Source data
+  \param[out]  out  Pointer to the Result data.
+  \param[in]   len  the Source data len.
+  \param[in]   padding \ref aes_padding_mode_e.
+  \return      error code
+*/
+int32_t csi_aes_crypto(aes_handle_t handle, void *context, void *in, void *out, uint32_t len, aes_padding_mode_e padding)
+{
+    AES_NULL_PARA_CHK(handle);
+    AES_NULL_PARA_CHK(in);
+    AES_NULL_PARA_CHK(out);
+    AES_NULL_PARA_CHK(len);
+
+    ck_aes_priv_t *aes_priv = handle;
+
+    aes_priv->status.busy = 1;
+
+    uint8_t left_len = len & 0xf;
+    switch (padding) {
+        case AES_PADDING_MODE_NO:
+            if (left_len) {
+                return ERR_AES(EDRV_PARAMETER);
+            }
+
+            /* crypto in padding no mode */
+            aes_priv->result_out = out;
+            aes_priv->len = len;
+            aes_crypto(context, in, out, len, aes_priv->iv, aes_priv->mode, aes_priv->endian);
+            break;
+
+        case AES_PADDING_MODE_ZERO:
+            if (left_len == 0) {
+                return ERR_AES(EDRV_PARAMETER);
+            }
+
+            uint8_t i = 0;
+            for (i = 0; i < (16 - left_len); i++) {
+                *((uint8_t *)in + len + i) = 0x0;
+            }
+
+            /* crypto in padding zero mode */
+            aes_priv->result_out = out;
+            aes_priv->len = len + 16 -left_len;
+            aes_crypto(context, in, out, len + 16 - left_len, aes_priv->iv, aes_priv->mode, aes_priv->endian);
+            break;
+
+        case AES_PADDING_MODE_PKCS5:
+            return ERR_AES(EDRV_UNSUPPORTED);
+
+        default:
+            return ERR_AES(EDRV_PARAMETER);
+    }
+
+    aes_priv->status.busy = 0;
+    return 0;
+}
+
+/**
+  \brief       Get AES status.
+  \param[in]   handle  aes handle to operate.
+  \return      AES status \ref aes_status_t
+*/
+aes_status_t csi_aes_get_status(aes_handle_t handle)
+{
+    ck_aes_priv_t *aes_priv = handle;
+    return aes_priv->status;
+}

bsp/ck802/libraries/common/aes/ck_aes.h

+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     ck_aes.h
+ * @brief    header file for aes driver
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+#ifndef _CK_AES_H_
+#define _CK_AES_H_
+
+#include <stdio.h>
+#include "drv_aes.h"
+#include "soc.h"
+
+#define AES_LITTLE_ENDIAN   0x00000100
+
+#define AES_MAX_KEY_LENGTH  32
+#define AES_IT_DATAINT      0x4
+#define AES_IT_KEYINT       0x2
+#define AES_IT_BUSY         0x1
+#define AES_IT_ALL          0x7
+#define AES_CRYPTO_KEYEXP   0x2
+
+#define AES_WORK_ENABLE_OFFSET  0
+#define AES_INT_ENABLE_OFFSET   2
+#define AES_MODE_OFFSET         3
+#define AES_KEY_LEN_OFFSET      4
+#define AES_OPCODE_OFFSET       6
+
+typedef struct {
+    __IOM uint32_t datain[4];                 /* Offset: 0x000 (R/W) Data input 0~127 */
+    __IOM uint32_t key[8];                    /* Offset: 0x010 (R/W) Key 0~255 */
+    __IOM uint32_t iv[4];                     /* Offset: 0x030 (R/W) Initial Vector: 0~127 */
+    __IOM uint32_t ctrl;                      /* Offset: 0x040 (R/W) AES Control Register */
+    __IOM uint32_t state;                     /* Offset: 0x044 (R/W) AES State Register */
+    __IOM uint32_t dataout[4];                /* Offset: 0x048 (R/W) Data Output 0~31 */
+} ck_aes_reg_t;
+
+#endif

bsp/ck802/libraries/common/crc/ck_crc.c

+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     ck_crc.c
+ * @brief    CSI Source File for CRC Driver
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+#include <stdio.h>
+#include "drv_crc.h"
+#include "ck_crc.h"
+
+#define ERR_CRC(errno) (CSI_DRV_ERRNO_CRC_BASE | errno)
+#define CRC_NULL_PARAM_CHK(para)                         \
+        do {                                        \
+            if (para == NULL) {                     \
+                return ERR_CRC(EDRV_PARAMETER);   \
+            }                                       \
+        } while (0)
+
+typedef struct {
+    uint32_t base;
+    crc_event_cb_t cb;
+    crc_status_t status;
+} ck_crc_priv_t;
+
+
+static ck_crc_priv_t crc_handle[CONFIG_CRC_NUM];
+/* Driver Capabilities */
+static const crc_capabilities_t driver_capabilities = {
+    .ROHC = 1, /* ROHC mode */
+    .MAXIM = 1, /* MAXIM mode */
+    .X25 = 1, /* X25 mode */
+    .CCITT = 1, /* CCITT mode */
+    .USB = 1, /* USB mode */
+    .IBM = 1, /* IBM mode */
+    .MODBUS = 1  /* MODBUS mode */
+};
+
+//
+// Functions
+//
+
+static ck_crc_reg_t *crc_reg = NULL;
+
+static int32_t crc_set_mode(crc_mode_e mode, crc_standard_crc_e standard)
+{
+    if (mode == CRC_MODE_CRC16) {
+        switch (standard) {
+            case CRC_STANDARD_CRC_MODBUS:
+                crc_reg->CRC_SEL = 0x0;
+                crc_reg->CRC_INIT = 0xffff;
+                break;
+
+            case CRC_STANDARD_CRC_IBM:
+                crc_reg->CRC_SEL = 0x0;
+                crc_reg->CRC_INIT = 0x0;
+                break;
+
+            case CRC_STANDARD_CRC_MAXIM:
+                crc_reg->CRC_SEL = 0x4;
+                crc_reg->CRC_INIT = 0x0;
+                break;
+
+            case CRC_STANDARD_CRC_USB:
+                crc_reg->CRC_SEL = 0x4;
+                crc_reg->CRC_INIT = 0xffff;
+                break;
+
+            case CRC_STANDARD_CRC_CCITT:
+                crc_reg->CRC_SEL = 0x1;
+                crc_reg->CRC_INIT = 0x0;
+                break;
+
+            case CRC_STANDARD_CRC_X25:
+                crc_reg->CRC_SEL = 0x5;
+                crc_reg->CRC_INIT = 0xffff;
+                break;
+
+            default:
+                return ERR_CRC(EDRV_PARAMETER);
+        }
+    } else if (mode == CRC_MODE_CRC8) {
+        switch (standard) {
+            case CRC_STANDARD_CRC_MAXIM:
+                crc_reg->CRC_SEL = 0x2;
+                crc_reg->CRC_INIT = 0x0;
+                break;
+
+            case CRC_STANDARD_CRC_ROHC:
+                crc_reg->CRC_SEL = 0x3;
+                crc_reg->CRC_INIT = 0xff;
+                break;
+
+            default:
+                return ERR_CRC(EDRV_PARAMETER);
+        }
+    } else {
+        return ERR_CRC(EDRV_PARAMETER);
+    }
+
+    return 0;
+}
+
+static int32_t crc_set_data(uint32_t data)
+{
+    crc_reg->CRC_DATA = data;
+    return 0;
+}
+
+static int32_t crc_get_data(uint32_t *data)
+{
+    *data = crc_reg->CRC_DATA;
+    return 0;
+}
+
+int32_t __attribute__((weak)) target_get_crc_count(void)
+{
+    return 0;
+}
+
+int32_t __attribute__((weak)) target_get_crc(int32_t idx, uint32_t *base)
+{
+    return NULL;
+}
+
+/**
+  \brief       get crc handle count.
+  \return      crc handle count
+*/
+int32_t csi_crc_get_instance_count(void)
+{
+    return target_get_crc_count();
+}
+
+/**
+  \brief       Initialize CRC Interface. 1. Initializes the resources needed for the CRC interface 2.registers event callback function
+  \param[in]   idx must not exceed return value of csi_crc_get_handle_count()
+  \param[in]   cb_event  Pointer to \ref crc_event_cb_t
+  \return      return crc handle if success
+*/
+crc_handle_t csi_crc_initialize(int32_t idx, crc_event_cb_t cb_event)
+{
+    if (idx < 0 || idx >= CONFIG_CRC_NUM) {
+        return NULL;
+    }
+
+    /* obtain the crc information */
+    uint32_t base = 0u;
+    int32_t real_idx = target_get_crc(idx, &base);
+
+    if (real_idx != idx) {
+        return NULL;
+    }
+
+    ck_crc_priv_t *crc_priv = &crc_handle[idx];
+    crc_reg = (ck_crc_reg_t *)(crc_priv->base);
+
+    crc_priv->base = base;
+    crc_priv->cb = cb_event;
+    crc_priv->status.busy = 0;
+
+    return (crc_handle_t)crc_priv;
+}
+
+/**
+  \brief       De-initialize CRC Interface. stops operation and releases the software resources used by the interface
+  \param[in]   handle  crc handle to operate.
+  \return      error code
+*/
+int32_t csi_crc_uninitialize(crc_handle_t handle)
+{
+    CRC_NULL_PARAM_CHK(handle);
+
+    ck_crc_priv_t *crc_priv = handle;
+    crc_priv->cb = NULL;
+
+    return 0;
+}
+
+/**
+  \brief       Get driver capabilities.
+  \param[in]   handle crc handle to operate.
+  \return      \ref crc_capabilities_t
+*/
+crc_capabilities_t csi_crc_get_capabilities(crc_handle_t handle)
+{
+    return driver_capabilities;
+}
+
+/**
+  \brief       config crc mode.
+  \param[in]   handle  crc handle to operate.
+  \param[in]   mode      \ref crc_mode_e
+  \param[in]   standard  \ref crc_standard_crc_e
+  \return      error code
+*/
+int32_t csi_crc_config(crc_handle_t handle, crc_mode_e mode, crc_standard_crc_e standard)
+{
+    CRC_NULL_PARAM_CHK(handle);
+
+    /* set the crc mode */
+    uint32_t ret = crc_set_mode(mode, standard);
+
+    return ret;
+}
+
+/**
+  \brief       calculate crc.
+  \param[in]   handle  crc handle to operate.
+  \param[in]   in      Pointer to the input data
+  \param[out]  out     Pointer to the result.
+  \param[in]   len     intpu data len.
+  \return      error code
+*/
+int32_t csi_crc_calculate(crc_handle_t handle, const void *in, void *out, uint32_t len)
+{
+    CRC_NULL_PARAM_CHK(handle);
+    CRC_NULL_PARAM_CHK(in);
+    CRC_NULL_PARAM_CHK(out);
+    if (len <= 0) {
+        return ERR_CRC(EDRV_PARAMETER);
+    }
+
+    ck_crc_priv_t *crc_priv = handle;
+    crc_reg = (ck_crc_reg_t *)(crc_priv->base);
+
+    crc_priv->status.busy = 1;
+
+    /* put the data int the register */
+    uint8_t cur;
+    uint8_t *p = (uint8_t *)in;
+    for (cur=0; cur<len - 3; cur += 4, p+=4) {
+        crc_set_data(p[0]
+                    | (p[1] << 8)
+                    | (p[2] << 16)
+                    | (p[3] << 24));
+    }
+    uint32_t data = 0;
+    uint8_t i;
+    if (cur < len) {
+        for (i=0; i<len-cur; i++) {
+            data |= (p[cur + i] << (i*8));
+        }
+        crc_set_data(data);
+    }
+
+    crc_get_data((uint32_t *)out);
+    crc_priv->status.busy = 0;
+
+    return 0;
+}
+
+/**
+  \brief       Get CRC status.
+  \param[in]   handle  crc handle to operate.
+  \return      CRC status \ref crc_status_t
+*/
+crc_status_t csi_crc_get_status(crc_handle_t handle)
+{
+    ck_crc_priv_t *crc_priv = handle;
+    return crc_priv->status;
+}

bsp/ck802/libraries/common/crc/ck_crc.h

+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/******************************************************************************
+ * @file     ck_crc.h
+ * @brief    header file for crc driver
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+#ifndef _CK_CRC_H_
+#define _CK_CRC_H_
+
+#include "stdint.h"
+#include "soc.h"
+
+typedef struct {
+    __IOM uint32_t CRC_DATA;                     /* Offset: 0x000 (W/R)  data register */
+    __IOM uint32_t CRC_SEL;                      /* Offset: 0x004 (W/R)  mode select register for CRC */
+    __OM  uint32_t CRC_INIT;                     /* Offset: 0x008 (W)    initial value register */
+
+} ck_crc_reg_t;
+#endif

bsp/ck802/libraries/common/dmac/ck_dmac.c

+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/******************************************************************************
+* @file     ck_dmac.c
+* @brief    CSI Source File for DMAC Driver
+* @version  V1.0
+* @date     02. June 2017
+******************************************************************************/
+#include <stdbool.h>
+#include "ck_dmac.h"
+#include "csi_core.h"
+#include "drv_dmac.h"
+#include "soc.h"
+
+#define ERR_DMA(errno) (CSI_DRV_ERRNO_DMA_BASE | errno)
+
+typedef struct {
+    uint32_t base;
+    uint32_t irq;
+    dma_event_cb_t cb_event;
+    uint8_t ch_num;
+} ck_dma_priv_t;
+
+static ck_dma_priv_t dma_instance[CONFIG_DMAC_NUM];
+
+static const dma_capabilities_t dma_capabilities = {
+    .unalign_addr = 1,          ///< support for unalign address transfer when memory is source
+};
+
+static volatile dma_status_e status[CK_DMA_MAXCHANNEL] = {DMA_STATE_FREE, DMA_STATE_FREE};
+static volatile uint8_t ch_opened[CK_DMA_MAXCHANNEL] = {0, 0};
+
+static int32_t ck_dma_set_channel(ck_dma_reg_t *addr, uint32_t source, uint32_t dest, uint32_t size)
+{
+    uint32_t temp = addr->CHCTRLA;
+    temp &= 0xff000fff;
+    temp |= (size << 12);
+    addr->SAR = source;
+    addr->DAR = dest ;
+    addr->CHCTRLA = temp;
+
+    return 0;
+}
+
+static int32_t ck_dma_set_transfertype(ck_dma_reg_t *addr, dma_trans_type_e transtype)
+{
+    uint32_t temp = addr->CHCTRLB;
+    temp &= 0xffffff7f;
+
+    if (transtype >= DMA_PERH2PERH) {
+        return ERR_DMA(EDRV_PARAMETER);
+    }
+
+    if (transtype == DMA_MEM2MEM) {
+        temp |= (transtype << 7);
+    } else {
+        temp |= (1 << 7);
+    }
+
+    addr->CHCTRLB = temp;
+
+    return 0;
+}
+
+static int32_t ck_dma_set_addrinc(ck_dma_reg_t *addr, enum_addr_state_e src_addrinc, enum_addr_state_e dst_addrinc)
+{
+    if ((src_addrinc != DMA_ADDR_INCREMENT && src_addrinc != DMA_ADDR_DECREMENT && src_addrinc != DMA_ADDR_NOCHANGE) ||
+        (dst_addrinc != DMA_ADDR_INCREMENT && dst_addrinc != DMA_ADDR_DECREMENT && dst_addrinc != DMA_ADDR_NOCHANGE)) {
+        return ERR_DMA(EDRV_PARAMETER);
+    }
+
+    uint32_t  temp = addr->CHCTRLA;
+    temp &= 0xffffff0f;
+    temp |= (src_addrinc << 6);
+    temp |= (dst_addrinc << 4);
+    addr->CHCTRLA = temp;
+
+    return 0;
+}
+
+static int32_t ck_dma_set_transferwidth(ck_dma_reg_t *addr, dma_datawidth_e src_width, dma_datawidth_e dst_width)
+{
+    if ((src_width != DMA_DATAWIDTH_SIZE8 && src_width != DMA_DATAWIDTH_SIZE16 && src_width != DMA_DATAWIDTH_SIZE32) ||
+        (dst_width != DMA_DATAWIDTH_SIZE8 && dst_width != DMA_DATAWIDTH_SIZE16 && dst_width != DMA_DATAWIDTH_SIZE32)) {
+        return ERR_DMA(EDRV_PARAMETER);
+    }
+
+    uint32_t temp = addr->CHCTRLA;
+    temp &= 0xfffffff0;
+    temp |= (src_width - 1) << 2;
+    temp |= dst_width - 1;
+    addr->CHCTRLA = temp;
+
+    return 0;
+}
+
+static int32_t ck_dma_set_burstlength(ck_dma_reg_t *addr, uint8_t burstlength)
+{
+    uint32_t temp = addr->CHCTRLA;
+    temp &= 0xfffff0ff;
+    temp |= (burstlength << 8);
+    addr->CHCTRLA = temp;
+
+    return 0;
+
+}
+
+/**
+  \brief       Set software or hardware handshaking.
+  \param[in]   addr pointer to dma register.
+  \return      error code
+*/
+static int32_t ck_dma_set_handshaking(ck_dma_reg_t *addr, dma_handshaking_select_e handshaking)
+{
+    uint32_t  temp = addr->CHCTRLB;
+    temp &= 0xfffffeff;
+    temp |= (handshaking << 8);
+    addr->CHCTRLB = temp;
+
+    return 0;
+}
+
+static int ck_dma_assign_hdhs_interface(ck_dma_reg_t *addr, ckenum_dma_device_e device)
+{
+    if (device < 0 || device >= CKENUM_DMA_MEMORY) {
+        return ERR_DMA(EDRV_PARAMETER);
+    }
+
+    addr->CHCTRLB &= 0xffffe1ff;
+    addr->CHCTRLB |= (device << 9);
+
+    return 0;
+}
+
+
+void ck_dma_irqhandler(int32_t idx)
+{
+    ck_dma_priv_t *dma_priv = &dma_instance[idx];
+    ck_dma_reg_t *addr = (ck_dma_reg_t *)(dma_priv->base);
+
+    /*
+     * StatusInt_temp contain the information that which types of interrupr are
+     * requested.
+     */
+    int32_t count = 0;
+    uint32_t temp = 0;
+
+    for (count = 0; count < dma_priv->ch_num; count++) {
+        addr = (ck_dma_reg_t *)(dma_priv->base + count * 0x30);
+
+        temp = addr->CHINTS;
+
+        if (temp != 0) {
+            break;
+        }
+    }
+
+    /* If Tfr interrupt is requested */
+    if (temp == CK_DMA_TFR) {
+        status[count] = DMA_STATE_DONE;
+        addr->CHINTC = temp;
+
+        if (dma_priv->cb_event) {
+            dma_priv->cb_event(DMA_EVENT_TRANSFER_DONE, count);
+        }
+    }
+
+    /* If Err interrput is requested */
+    if (temp == CK_DMA_ERR) {
+        status[count] =  DMA_STATE_ERROR;
+        addr->CHINTC = temp;
+
+        if (dma_priv->cb_event) {
+            dma_priv->cb_event(DMA_EVENT_TRANSFER_ERROR, count);
+        }
+    }
+}
+
+int32_t __attribute__((weak)) target_get_dmac_count(void)
+{
+    return 0;
+}
+
+int32_t __attribute__((weak)) target_get_dmac(uint32_t idx, uint32_t *base, uint32_t *irq)
+{
+    return NULL;
+}
+
+/**
+  \brief       get dma instance count.
+  \return      dma instance count
+*/
+int32_t csi_dma_get_instance_count(void)
+{
+    return target_get_dmac_count();
+}
+
+/**
+  \brief       Initialize DMA Interface. 1. Initializes the resources needed for the DMA interface 2.registers event callback function
+  \param[in]   idx must not exceed return value of csi_dma_get_instance_count()
+  \return      pointer to dma instances
+*/
+dmac_handle_t csi_dma_initialize(int32_t idx)
+{
+
+    if (idx < 0 || idx >= CONFIG_DMAC_NUM) {
+        return NULL;
+    }
+
+    uint32_t base = 0u;
+    uint32_t irq = 0u;
+
+    int32_t real_idx = target_get_dmac(idx, &base, &irq);
+
+    if (real_idx != idx) {
+        return NULL;
+    }
+
+    ck_dma_priv_t *dma_priv = &dma_instance[idx];
+
+    dma_priv->base = base;
+    dma_priv->irq  = irq;
+    dma_priv->ch_num = CK_DMA_MAXCHANNEL;
+    drv_nvic_enable_irq(dma_priv->irq);
+    uint8_t count = 0u;
+
+    for (count = 0; count < dma_priv->ch_num; count++) {
+        ck_dma_reg_t *addr = (ck_dma_reg_t *)(dma_priv->base + count * 0x30);
+        addr->CHINTM = CK_DMA_MASK;
+        addr->CHINTC = CK_DMA_INTC;
+    }
+
+    return (dmac_handle_t)dma_priv;
+}
+
+/**
+  \brief       De-initialize DMA Interface. stops operation and releases the software resources used by the interface
+  \param[in]   handle damc handle to operate.
+  \return      error code
+*/
+int32_t csi_dma_uninitialize(dmac_handle_t handle)
+{
+    if (handle == NULL) {
+        return ERR_DMA(EDRV_PARAMETER);
+    }
+
+    ck_dma_priv_t *dma_priv = handle;
+    ck_dma_reg_t *addr = (ck_dma_reg_t *)(dma_priv->base);
+
+    uint8_t count;
+
+    for (count = 0; count < dma_priv->ch_num; count++) {
+        addr = (ck_dma_reg_t *)(dma_priv->base + count * 0x30);
+        addr->CHINTM = CK_DMA_MASK;
+        addr->CHINTC = CK_DMA_INTC;
+    }
+
+    drv_nvic_disable_irq(dma_priv->irq);
+
+    return 0;
+}
+
+/**
+  \brief       Get driver capabilities.
+  \param[in]   handle damc handle to operate.
+  \return      \ref dma_capabilities_t
+*/
+dma_capabilities_t csi_dma_get_capabilities(dmac_handle_t handle)
+{
+    return dma_capabilities;
+}
+
+/**
+  \brief     get one free dma channel
+  \param[in] handle damc handle to operate.
+  \param[in] ch channel num. if -1 then allocate a free channal in this dma
+  \return    -1 - no channel can be used, other - channel index
+ */
+int32_t csi_dma_alloc_channel(dmac_handle_t handle, int32_t ch)
+{
+    ck_dma_priv_t *dma_priv = handle;
+
+    if (handle == NULL || ch > dma_priv->ch_num) {
+        return ERR_DMA(EDRV_PARAMETER);
+    }
+
+    uint8_t ch_num = 0;
+    ck_dma_reg_t *addr = NULL;
+
+    if (ch == -1) {     // alloc a free channal
+        for (ch_num = 0; ch_num < dma_priv->ch_num; ch_num++) {
+            addr = (ck_dma_reg_t *)(dma_priv->base + ch_num * 0x30);
+
+            if (ch_opened[ch_num] != 0x1) {
+                ch_opened[ch_num] = 1;
+                break;
+            }
+        }
+
+        if (ch_num >= dma_priv->ch_num) {
+            return -1;
+        }
+    } else {    //alloc a fixed channel
+        addr = (ck_dma_reg_t *)(dma_priv->base + ch * 0x30);
+
+        if (ch_opened[ch] == 0x1) {
+            return ERR_DMA(EDRV_BUSY);
+        }
+
+        ch_opened[ch] = 1;
+        ch_num = ch;
+    }
+
+    addr->CHINTC = CK_DMA_INTC;
+    addr->CHINTM &= ~CK_DMA_MASK;
+    status[ch_num] = DMA_STATE_READY;
+
+    return ch_num;
+}
+
+/**
+  \brief        release dma channel and related resources
+  \param[in]    handle damc handle to operate.
+  \param[in]    ch  channel num.
+  \return       error code
+ */
+int32_t csi_dma_release_channel(dmac_handle_t handle, int32_t ch)
+{
+    ck_dma_priv_t *dma_priv = handle;
+
+    if (handle == NULL || ch >= dma_priv->ch_num || ch < 0) {
+        return ERR_DMA(EDRV_PARAMETER);
+    }
+
+    ck_dma_reg_t *addr = (ck_dma_reg_t *)(dma_priv->base + ch * 0x30);
+    status[ch] = DMA_STATE_FREE;
+    ch_opened[ch] = 0;
+
+    addr->CHINTC = CK_DMA_INTC;
+    addr->CHINTM = CK_DMA_MASK;
+    return 0;
+}
+
+/**
+  \brief
+  \param[in]    handle damc handle to operate.
+  \param[in]    ch          channel num. if -1 then allocate a free channal in this dma
+  \param[in]    psrcaddr    dma transfer source address
+  \param[in]    pstdaddr    dma transfer source address
+  \param[in]    length      dma transfer length
+  \param[in]    config      dma transfer configure
+  \param[in]    cb_event    Pointer to \ref dma_event_cb_t
+  \return       error code
+ */
+int32_t csi_dma_config(dmac_handle_t handle, int32_t ch,
+                       void *psrcaddr, void *pstdaddr,
+                       uint32_t length, dma_config_t *config, dma_event_cb_t cb_event)
+{
+    ck_dma_priv_t *dma_priv = handle;
+
+    if (handle == NULL || ch >= dma_priv->ch_num || config == NULL) {
+        return ERR_DMA(EDRV_PARAMETER);
+    }
+
+    if (ch == -1) { //alloc a free channel
+        ch = csi_dma_alloc_channel(handle, -1);
+
+        if (ch < 0) {
+            return ERR_DMA(EDRV_BUSY);
+        }
+    }
+
+    dma_priv->cb_event = cb_event;
+
+    ck_dma_reg_t *addr = (ck_dma_reg_t *)(dma_priv->base + ch * 0x30);
+
+    /* Initializes corresponding channel registers */
+
+    if ((length * config->src_tw) % config->dst_tw != 0) {
+        return ERR_DMA(EDRV_PARAMETER);
+    }
+
+    int32_t ret = ck_dma_set_transferwidth(addr, config->src_tw, config->dst_tw);
+
+    if (ret) {
+        return ret;
+    }
+
+    int32_t grouplen = ((length * config->src_tw / config->dst_tw) - 1) % 16;
+    ck_dma_set_burstlength(addr, grouplen);
+
+    ret = ck_dma_set_transfertype(addr, config->type);
+
+    if (ret < 0) {
+        return ret;
+    }
+
+    if (config->type == DMA_MEM2MEM) {
+        ck_dma_set_handshaking(addr, DMA_HANDSHAKING_SOFTWARE);
+        ret = ck_dma_set_addrinc(addr , config->src_inc, config->dst_inc);
+    } else if (config->type == DMA_MEM2PERH) {
+        ck_dma_set_handshaking(addr, DMA_HANDSHAKING_HARDWARE);
+        ret = ck_dma_set_addrinc(addr , config->src_inc, config->dst_inc);
+
+        if (ret) {
+            return ret;
+        }
+
+        ret = ck_dma_assign_hdhs_interface(addr, config->hs_if);
+
+        if (ret) {
+            return ret;
+        }
+
+    } else if (config->type == DMA_PERH2MEM) {
+        ck_dma_set_handshaking(addr, DMA_HANDSHAKING_HARDWARE);
+        ret = ck_dma_set_addrinc(addr , config->src_inc, config->dst_inc);
+
+        if (ret) {
+            return ret;
+        }
+
+        ret = ck_dma_assign_hdhs_interface(addr, config->hs_if);
+
+        if (ret) {
+            return ret;
+        }
+    }
+
+    ck_dma_set_channel(addr, (uint32_t)psrcaddr, (uint32_t)pstdaddr, length);
+    status[ch] = DMA_STATE_READY;
+
+    return 0;
+}
+
+/**
+  \brief       start generate dma signal.
+  \param[in]   handle damc handle to operate.
+  \param[in]   ch  channel num.
+  \return      error code
+*/
+int32_t csi_dma_start(dmac_handle_t handle, int32_t ch)
+{
+    ck_dma_priv_t *dma_priv = handle;
+
+    if (handle == NULL || ch >= dma_priv->ch_num || ch < 0) {
+        return ERR_DMA(EDRV_PARAMETER);
+    }
+
+    status[ch] = DMA_STATE_BUSY;
+    ck_dma_reg_t *addr = (ck_dma_reg_t *)(dma_priv->base + ch * 0x30);
+    addr->CHCTRLB |= CK_DMA_INT_EN;      // interrupt enable
+    addr->CHEN    |= CK_DMA_CH_EN;
+
+    return 0;
+}
+
+/**
+  \brief       Stop generate dma signal.
+  \param[in]   handle damc handle to operate.
+  \param[in]   ch  channel num.
+  \return      error code
+*/
+int32_t csi_dma_stop(dmac_handle_t handle, int32_t ch)
+{
+    if (handle == NULL) {
+        return ERR_DMA(EDRV_PARAMETER);
+    }
+
+    ck_dma_priv_t *dma_priv = handle;
+
+    if (ch >= dma_priv->ch_num || ch < 0) {
+        return ERR_DMA(EDRV_PARAMETER);
+    }
+
+    status[ch] = DMA_STATE_DONE;
+
+    ck_dma_reg_t *addr = (ck_dma_reg_t *)(dma_priv->base + ch * 0x30);
+    addr->CHCTRLB &= ~CK_DMA_INT_EN;      // interrupt disable
+    addr->CHEN    &= ~CK_DMA_CH_EN;
+    return 0;
+}
+
+/**
+  \brief       Get DMA status.
+  \param[in]   handle damc handle to operate.
+  \param[in]   ch  channel num.
+  \return      DMA status \ref dma_status_t
+*/
+dma_status_e csi_dma_get_status(dmac_handle_t handle, int32_t ch)
+{
+    if (handle == NULL) {
+        return ERR_DMA(EDRV_PARAMETER);
+    }
+
+    ck_dma_priv_t *dma_priv = handle;
+
+    if (ch >= dma_priv->ch_num || ch < 0) {
+        return ERR_DMA(EDRV_PARAMETER);
+    }
+
+    return status[ch];
+}
+

bsp/ck802/libraries/common/dmac/ck_dmac.h

+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/******************************************************************************
+* @file     ck_dmac.h
+* @brief    header file for DMAC Driver
+* @version  V1.0
+* @date     02. June 2017
+******************************************************************************/
+#ifndef __CK_DMA_H
+#define __CK_DMA_H
+#include <stdio.h>
+#include "soc.h"
+
+#define CK_DMA_MAXCHANNEL  2
+#define CK_DMA_INT_EN      1
+#define CK_DMA_CH_EN       1
+#define CK_DMA_TFR   0x0002
+#define CK_DMA_ERR   0x0001
+#define CK_DMA_INTC     0x03
+#define CK_DMA_MASK     0x03
+
+typedef enum {
+    DMA_ADDR_INCREMENT = 0,
+    DMA_ADDR_DECREMENT = 1,
+    DMA_ADDR_NOCHANGE  = 2
+} enum_addr_state_e;
+
+typedef enum {
+    DMA_DATAWIDTH_SIZE8  = 1,
+    DMA_DATAWIDTH_SIZE16 = 2,
+    DMA_DATAWIDTH_SIZE32 = 4
+} dma_datawidth_e;
+
+typedef enum {
+    DMA_HANDSHAKING_HARDWARE = 0,
+    DMA_HANDSHAKING_SOFTWARE = 1,
+} dma_handshaking_select_e;
+
+typedef enum {
+    DMA_PRIORITY0 = 0,
+    DMA_PRIORITY1 = 1,
+    DMA_PRIOTITY2 = 2,
+    DMA_PRIOTITY3 = 3
+} dma_priority_t;
+
+typedef struct {
+    __IOM uint32_t   SAR;       /* offset: 0x00 (R/W) Channel Source Address Register        */
+    __IOM uint32_t   DAR;       /* offset: 0x04 (R/W) Channel Destination Address Register   */
+    __IOM uint32_t   CHCTRLA;   /* offset: 0x08 (R/W) Channel Control Register A             */
+    __IOM uint32_t   CHCTRLB;   /* offset: 0x0C (R/W) Channel Control Register B             */
+    __IOM uint8_t   CHINTM:2;    /* offset: 0x10 (R/W) Channel Interrupt Mask Register        */
+    uint8_t  RESERVED0[3];
+    __IM  uint8_t   CHINTS:2;    /* offset: 0x14 (R/ ) Channel Interrupt Status Register      */
+    uint8_t  RESERVED1[3];
+    __IOM uint8_t   CHINTC:2;    /* offset: 0x18 (R/W) Channel Interrupt Clear Register       */
+    uint8_t  RESERVED2[3];
+    __IOM uint8_t   CHSREQ:1;    /* offset: 0x1C (R/W) Channel Software Request Register      */
+    uint8_t  RESERVED3[3];
+    __IOM uint8_t   CHEN:1;      /* offset: 0x20 (R/W) Channel Enable Register                */
+    uint8_t  RESERVED4[3];
+} ck_dma_reg_t;
+#endif /* __CK_DMA_H */

bsp/ck802/libraries/common/eflash/ck_eflash.c

+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/******************************************************************************
+ * @file     ck_eflash.c
+ * @brief    CSI Source File for Embedded Flash Driver
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+#include <stdio.h>
+#include "drv_eflash.h"
+#include "ck_eflash.h"
+
+
+#define ERR_EFLASH(errno) (CSI_DRV_ERRNO_EFLASH_BASE | errno)
+#define EFLASH_NULL_PARAM_CHK(para)                         \
+        do {                                        \
+            if (para == NULL) {                     \
+                return ERR_EFLASH(EDRV_PARAMETER);   \
+            }                                       \
+        } while (0)
+
+typedef struct {
+    uint32_t base;
+    eflash_info eflashinfo;
+    eflash_event_cb_t cb;
+    eflash_status_t status;
+} ck_eflash_priv_t;
+
+static ck_eflash_priv_t eflash_handle[CONFIG_EFLASH_NUM];
+/* Driver Capabilities */
+static const eflash_capabilities_t driver_capabilities = {
+    .event_ready = 1, /* event_ready */
+    .data_width = 2, /* data_width = 0:8-bit, 1:16-bit, 2:32-bit */
+    .erase_chip = 0  /* erase_chip */
+};
+
+//
+// Functions
+//
+
+static int32_t eflash_program_word(eflash_handle_t handle, uint32_t dstaddr, uint32_t *srcbuf, uint32_t len)
+{
+    ck_eflash_priv_t *eflash_priv = handle;
+    uint32_t fbase = eflash_priv->base;
+    uint32_t i;
+
+    for (i = 0; i < len; i++) {
+        *(volatile uint32_t *)(fbase + 0x04) = dstaddr;
+        *(volatile uint32_t *)(fbase + 0x1c) = *srcbuf;
+        *(volatile uint32_t *)(fbase + 0x18) = 1;
+        srcbuf++;
+        dstaddr += 4;
+    }
+
+    return (i << 2);
+}
+
+int32_t __attribute__((weak)) target_get_eflash_count(void)
+{
+    return 0;
+}
+
+int32_t __attribute__((weak)) target_get_eflash(int32_t idx, uint32_t *base, eflash_info *info)
+{
+    return NULL;
+}
+/**
+  \brief       get eflash handle count.
+  \return      eflash handle count
+*/
+int32_t csi_eflash_get_instance_count(void)
+{
+    return target_get_eflash_count();
+}
+
+/**
+  \brief       Initialize EFLASH Interface. 1. Initializes the resources needed for the EFLASH interface 2.registers event callback function
+  \param[in]   idx  must not exceed return value of csi_eflash_get_instance_count()
+  \param[in]   cb_event  Pointer to \ref eflash_event_cb_t
+  \return      pointer to eflash handle
+*/
+eflash_handle_t csi_eflash_initialize(int32_t idx, eflash_event_cb_t cb_event)
+{
+    if (idx < 0 || idx >= CONFIG_EFLASH_NUM) {
+        return NULL;
+    }
+
+    /* obtain the eflash information */
+    uint32_t base = 0u;
+    eflash_info info;
+    int32_t real_idx = target_get_eflash(idx, &base, &info);
+
+    if (real_idx != idx) {
+        return NULL;
+    }
+
+    ck_eflash_priv_t *eflash_priv = &eflash_handle[idx];
+
+    eflash_priv->base = base;
+    eflash_priv->eflashinfo.start = info.start;
+    eflash_priv->eflashinfo.end = info.end;
+    eflash_priv->eflashinfo.sector_count = info.sector_count;
+
+    /* initialize the eflash context */
+    eflash_priv->cb = cb_event;
+    eflash_priv->status.busy = 0;
+    eflash_priv->status.error = 0U;
+    eflash_priv->eflashinfo.sector_size = EFLASH_SECTOR_SIZE;
+    eflash_priv->eflashinfo.page_size = EFLASH_PAGE_SIZE;
+    eflash_priv->eflashinfo.program_unit = EFLASH_PROGRAM_UINT;
+    eflash_priv->eflashinfo.erased_value = EFLASH_ERASED_VALUE;
+
+    return (eflash_handle_t)eflash_priv;
+}
+
+/**
+  \brief       De-initialize EFLASH Interface. stops operation and releases the software resources used by the interface
+  \param[in]   handle  eflash handle to operate.
+  \return      error code
+*/
+int32_t csi_eflash_uninitialize(eflash_handle_t handle)
+{
+    EFLASH_NULL_PARAM_CHK(handle);
+
+    ck_eflash_priv_t *eflash_priv = handle;
+    eflash_priv->cb = NULL;
+
+    return 0;
+}
+
+/**
+  \brief       Get driver capabilities.
+  \param[in]   eflash handle to operate.
+  \return      \ref eflash_capabilities_t
+*/
+eflash_capabilities_t csi_eflash_get_capabilities(eflash_handle_t handle)
+{
+    return driver_capabilities;
+}
+
+/**
+  \brief       Read data from Flash.
+  \param[in]   handle  eflash handle to operate.
+  \param[in]   addr  Data address.
+  \param[out]  data  Pointer to a buffer storing the data read from Flash.
+  \param[in]   cnt   Number of data items to read.
+  \return      number of data items read or error code
+*/
+int32_t csi_eflash_read(eflash_handle_t handle, uint32_t addr, void *data, uint32_t cnt)
+{
+    EFLASH_NULL_PARAM_CHK(handle);
+    EFLASH_NULL_PARAM_CHK(data);
+    EFLASH_NULL_PARAM_CHK(cnt);
+    if (!IS_EFLASH_ADDR(addr) || !(IS_EFLASH_ADDR(addr + cnt -1))) {
+        return ERR_EFLASH(EDRV_PARAMETER);
+    }
+
+    volatile uint8_t *src_addr = (uint8_t *)addr;
+    ck_eflash_priv_t *eflash_priv = handle;
+
+    if (eflash_priv->status.busy) {
+        return ERR_EFLASH(EDRV_BUSY);
+    }
+
+    eflash_priv->status.error = 0U;
+
+    int i;
+    for (i = 0; i < cnt; i++) {
+        *((uint8_t *)data + i) = *(src_addr + i);
+    }
+
+    return i;
+}
+
+/**
+  \brief       Program data to Flash.
+  \param[in]   handle  eflash handle to operate.
+  \param[in]   addr  Data address.
+  \param[in]   data  Pointer to a buffer containing the data to be programmed to Flash..
+  \param[in]   cnt   Number of data items to program.
+  \return      number of data items programmed or error code
+*/
+int32_t csi_eflash_program(eflash_handle_t handle, uint32_t addr, const void *data, uint32_t cnt)
+{
+    EFLASH_NULL_PARAM_CHK(handle);
+    EFLASH_NULL_PARAM_CHK(data);
+    EFLASH_NULL_PARAM_CHK(cnt);
+    if (!IS_EFLASH_ADDR(addr) || !(IS_EFLASH_ADDR(addr + cnt -1))) {
+        return ERR_EFLASH(EDRV_PARAMETER);
+    }
+
+    ck_eflash_priv_t *eflash_priv = handle;
+
+    if ((addr & 0x3) || ((uint32_t)data & 0x3) || (cnt & 0x3)) {
+        return ERR_EFLASH(EDRV_PARAMETER);
+    }
+
+    if (eflash_priv->status.busy) {
+        return ERR_EFLASH(EDRV_BUSY);
+    }
+
+    eflash_priv->status.busy = 1U;
+    eflash_priv->status.error = 0U;
+    uint32_t ret = eflash_program_word(handle, addr, (uint32_t *)data, cnt >> 2);
+    eflash_priv->status.busy = 0U;
+
+    return ret;
+}
+
+/**
+  \brief       Erase Flash Sector.
+  \param[in]   handle  eflash handle to operate.
+  \param[in]   addr  Sector address
+  \return      error code
+*/
+int32_t csi_eflash_erase_sector(eflash_handle_t handle, uint32_t addr)
+{
+    EFLASH_NULL_PARAM_CHK(handle);
+    if (!IS_EFLASH_ADDR(addr)) {
+        return ERR_EFLASH(EDRV_PARAMETER);
+    }
+
+    addr = addr & ~(EFLASH_SECTOR_SIZE - 1);
+    ck_eflash_priv_t *eflash_priv = handle;
+    uint32_t fbase = eflash_priv->base;
+
+    if (eflash_priv->status.busy) {
+        return ERR_EFLASH(EDRV_BUSY);
+    }
+
+    eflash_priv->status.busy = 1U;
+    eflash_priv->status.error = 0U;
+    *(volatile uint32_t *)(fbase + 0x4) = addr;
+    *(volatile uint32_t *)(fbase + 0x10) = 0x1;
+    eflash_priv->status.busy = 0U;
+
+    return 0;
+}
+
+/**
+  \brief       Erase complete Flash.
+  \param[in]   handle  eflash handle to operate.
+  \return      error code
+*/
+int32_t csi_eflash_erase_chip(eflash_handle_t handle)
+{
+    EFLASH_NULL_PARAM_CHK(handle);
+
+    return ERR_EFLASH(EDRV_UNSUPPORTED);
+}
+
+/**
+  \brief       Get Flash information.
+  \param[in]   handle  eflash handle to operate.
+  \return      Pointer to Flash information \ref eflash_info
+*/
+eflash_info *csi_eflash_get_info(eflash_handle_t handle)
+{
+    ck_eflash_priv_t *eflash_priv = handle;
+    eflash_info *eflash_info = &(eflash_priv->eflashinfo);
+
+    return eflash_info;
+}
+
+/**
+  \brief       Get EFLASH status.
+  \param[in]   handle  eflash handle to operate.
+  \return      EFLASH status \ref eflash_status_t
+*/
+eflash_status_t csi_eflash_get_status(eflash_handle_t handle)
+{
+    ck_eflash_priv_t *eflash_priv = handle;
+
+    return eflash_priv->status;
+}

bsp/ck802/libraries/common/eflash/ck_eflash.h

+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/******************************************************************************
+ * @file     ck_eflash.h
+ * @brief    head file for ck eflash
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+#ifndef _CK_EFLASH_H_
+#define _CK_EFLASH_H_
+
+#include "drv_eflash.h"
+#include "soc.h"
+
+#define EFLASH_ADDR_START   0x10000000
+#define EFLASH_ADDR_END     0x1003f7ff
+#define EFLASH_SECTOR_SIZE  0x200
+#define EFLASH_ERASED_VALUE 0xff
+#define EFLASH_PROGRAM_UINT 0x4
+#define EFLASH_PAGE_SIZE    0
+#define BLOCK_SIZE          0x200
+#define IS_EFLASH_ADDR(addr) \
+    ((addr >= EFLASH_ADDR_START) && (addr <= EFLASH_ADDR_END))
+
+#endif

bsp/ck802/libraries/common/eth/ethernet_enc28j60.h

+/****************************************************************************
+ * csky/hardware/bsp/common/ethernet_enc28j60/ethernet_enc28j60.h
+ *
+ * Copyright (C) 2016 The YunOS Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ****************************************************************************/
+
+#ifndef _ETHERNET_ENC28J60_H__
+#define _ETHERNET_ENC28J60_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/* ****** ETH ****** */
+#define ETH_HEADER_LEN  14
+/* values of certain bytes: */
+#define ETHTYPE_ARP_H_V 0x08
+#define ETHTYPE_ARP_L_V 0x06
+#define ETHTYPE_IP_H_V  0x08
+#define ETHTYPE_IP_L_V  0x00
+/* byte positions in the ethernet frame:
+ Ethernet type field (2bytes): */
+#define ETH_TYPE_H_P    12
+#define ETH_TYPE_L_P    13
+
+#define ETH_DST_MAC     0
+#define ETH_SRC_MAC     6
+
+
+/* ******* ARP ******* */
+#define ETH_ARP_OPCODE_REPLY_H_V 0x0
+#define ETH_ARP_OPCODE_REPLY_L_V 0x02
+
+#define ETHTYPE_ARP_L_V          0x06
+/* arp.dst.ip */
+#define ETH_ARP_DST_IP_P         0x26
+/* arp.opcode */
+#define ETH_ARP_OPCODE_H_P       0x14
+#define ETH_ARP_OPCODE_L_P       0x15
+/* arp.src.mac */
+#define ETH_ARP_SRC_MAC_P        0x16
+#define ETH_ARP_SRC_IP_P         0x1c
+#define ETH_ARP_DST_MAC_P        0x20
+#define ETH_ARP_DST_IP_P         0x26
+
+/* ******* IP ******* */
+#define IP_HEADER_LEN       20
+/* ip.src */
+#define IP_SRC_P            0x1a
+#define IP_DST_P            0x1e
+#define IP_HEADER_LEN_VER_P 0xe
+#define IP_CHECKSUM_P       0x18
+#define IP_TTL_P            0x16
+#define IP_FLAGS_P          0x14
+#define IP_P                0xe
+#define IP_TOTLEN_H_P       0x10
+#define IP_TOTLEN_L_P       0x11
+
+#define IP_PROTO_P          0x17
+
+#define IP_PROTO_ICMP_V     1
+#define IP_PROTO_TCP_V      6
+/* 17=0x11 */
+#define IP_PROTO_UDP_V      17
+/* ******* ICMP ******* */
+#define ICMP_TYPE_ECHOREPLY_V   0
+#define ICMP_TYPE_ECHOREQUEST_V 8
+
+#define ICMP_TYPE_P             0x22
+#define ICMP_CHECKSUM_P         0x24
+
+/* ******* UDP ******* */
+#define UDP_HEADER_LEN   8
+
+#define UDP_SRC_PORT_H_P 0x22
+#define UDP_SRC_PORT_L_P 0x23
+#define UDP_DST_PORT_H_P 0x24
+#define UDP_DST_PORT_L_P 0x25
+
+#define UDP_LEN_H_P      0x26
+#define UDP_LEN_L_P      0x27
+#define UDP_CHECKSUM_H_P 0x28
+#define UDP_CHECKSUM_L_P 0x29
+#define UDP_DATA_P       0x2a
+
+/* ******* TCP ******* */
+#define TCP_SRC_PORT_H_P     0x22
+#define TCP_SRC_PORT_L_P     0x23
+#define TCP_DST_PORT_H_P     0x24
+#define TCP_DST_PORT_L_P     0x25
+/* the tcp seq number is 4 bytes 0x26-0x29 */
+#define TCP_SEQ_H_P          0x26
+#define TCP_SEQACK_H_P       0x2a
+/* flags: SYN=2 */
+#define TCP_FLAGS_P          0x2f
+#define TCP_FLAGS_SYN_V      2
+#define TCP_FLAGS_FIN_V      1
+#define TCP_FLAGS_PUSH_V     8
+#define TCP_FLAGS_SYNACK_V   0x12
+#define TCP_FLAGS_ACK_V      0x10
+#define TCP_FLAGS_PSHACK_V   0x18
+/* plain len without the options: */
+#define TCP_HEADER_LEN_PLAIN 20
+#define TCP_HEADER_LEN_P     0x2e
+#define TCP_CHECKSUM_H_P     0x32
+#define TCP_CHECKSUM_L_P     0x33
+#define TCP_OPTIONS_P        0x36
+
+
+/* ENC28J60 Control Registers
+ Control register definitions are a combination of address,
+ bank number, and Ethernet/MAC/PHY indicator bits.
+ - Register address        (bits 0-4)
+ - Bank number        (bits 5-6)
+ - MAC/PHY indicator        (bit 7) */
+#define ADDR_MASK        0x1F
+#define BANK_MASK        0x60
+#define SPRD_MASK        0x80
+/* All-bank registers */
+#define EIE              0x1B
+#define EIR              0x1C
+#define ESTAT            0x1D
+#define ECON2            0x1E
+#define ECON1            0x1F
+/* Bank 0 registers */
+#define ERDPTL           (0x00|0x00)
+#define ERDPTH           (0x01|0x00)
+#define EWRPTL           (0x02|0x00)
+#define EWRPTH           (0x03|0x00)
+#define ETXSTL           (0x04|0x00)
+#define ETXSTH           (0x05|0x00)
+#define ETXNDL           (0x06|0x00)
+#define ETXNDH           (0x07|0x00)
+#define ERXSTL           (0x08|0x00)
+#define ERXSTH           (0x09|0x00)
+#define ERXNDL           (0x0A|0x00)
+#define ERXNDH           (0x0B|0x00)
+#define ERXRDPTL         (0x0C|0x00)
+#define ERXRDPTH         (0x0D|0x00)
+#define ERXWRPTL         (0x0E|0x00)
+#define ERXWRPTH         (0x0F|0x00)
+#define EDMASTL          (0x10|0x00)
+#define EDMASTH          (0x11|0x00)
+#define EDMANDL          (0x12|0x00)
+#define EDMANDH          (0x13|0x00)
+#define EDMADSTL         (0x14|0x00)
+#define EDMADSTH         (0x15|0x00)
+#define EDMACSL          (0x16|0x00)
+#define EDMACSH          (0x17|0x00)
+/* Bank 1 registers */
+#define EHT0             (0x00|0x20)
+#define EHT1             (0x01|0x20)
+#define EHT2             (0x02|0x20)
+#define EHT3             (0x03|0x20)
+#define EHT4             (0x04|0x20)
+#define EHT5             (0x05|0x20)
+#define EHT6             (0x06|0x20)
+#define EHT7             (0x07|0x20)
+#define EPMM0            (0x08|0x20)
+#define EPMM1            (0x09|0x20)
+#define EPMM2            (0x0A|0x20)
+#define EPMM3            (0x0B|0x20)
+#define EPMM4            (0x0C|0x20)
+#define EPMM5            (0x0D|0x20)
+#define EPMM6            (0x0E|0x20)
+#define EPMM7            (0x0F|0x20)
+#define EPMCSL           (0x10|0x20)
+#define EPMCSH           (0x11|0x20)
+#define EPMOL            (0x14|0x20)
+#define EPMOH            (0x15|0x20)
+#define EWOLIE           (0x16|0x20)
+#define EWOLIR           (0x17|0x20)
+#define ERXFCON          (0x18|0x20)
+#define EPKTCNT          (0x19|0x20)
+/* Bank 2 registers */
+#define MACON1           (0x00|0x40|0x80)
+#define MACON2           (0x01|0x40|0x80)
+#define MACON3           (0x02|0x40|0x80)
+#define MACON4           (0x03|0x40|0x80)
+#define MABBIPG          (0x04|0x40|0x80)
+#define MAIPGL           (0x06|0x40|0x80)
+#define MAIPGH           (0x07|0x40|0x80)
+#define MACLCON1         (0x08|0x40|0x80)
+#define MACLCON2         (0x09|0x40|0x80)
+#define MAMXFLL          (0x0A|0x40|0x80)
+#define MAMXFLH          (0x0B|0x40|0x80)
+#define MAPHSUP          (0x0D|0x40|0x80)
+#define MICON            (0x11|0x40|0x80)
+#define MICMD            (0x12|0x40|0x80)
+#define MIREGADR         (0x14|0x40|0x80)
+#define MIWRL            (0x16|0x40|0x80)
+#define MIWRH            (0x17|0x40|0x80)
+#define MIRDL            (0x18|0x40|0x80)
+#define MIRDH            (0x19|0x40|0x80)
+/* Bank 3 registers */
+#define MAADR1           (0x00|0x60|0x80)
+#define MAADR0           (0x01|0x60|0x80)
+#define MAADR3           (0x02|0x60|0x80)
+#define MAADR2           (0x03|0x60|0x80)
+#define MAADR5           (0x04|0x60|0x80)
+#define MAADR4           (0x05|0x60|0x80)
+#define EBSTSD           (0x06|0x60)
+#define EBSTCON          (0x07|0x60)
+#define EBSTCSL          (0x08|0x60)
+#define EBSTCSH          (0x09|0x60)
+#define MISTAT           (0x0A|0x60|0x80)
+#define EREVID           (0x12|0x60)
+#define ECOCON           (0x15|0x60)
+#define EFLOCON          (0x17|0x60)
+#define EPAUSL           (0x18|0x60)
+#define EPAUSH           (0x19|0x60)
+/* PHY registers */
+#define PHCON1           0x00
+#define PHSTAT1          0x01
+#define PHHID1           0x02
+#define PHHID2           0x03
+#define PHCON2           0x10
+#define PHSTAT2          0x11
+#define PHIE             0x12
+#define PHIR             0x13
+#define PHLCON           0x14
+
+/* ENC28J60 ERXFCON Register Bit Definitions */
+#define ERXFCON_UCEN     0x80
+#define ERXFCON_ANDOR    0x40
+#define ERXFCON_CRCEN    0x20
+#define ERXFCON_PMEN     0x10
+#define ERXFCON_MPEN     0x08
+#define ERXFCON_HTEN     0x04
+#define ERXFCON_MCEN     0x02
+#define ERXFCON_BCEN     0x01
+/* ENC28J60 EIE Register Bit Definitions */
+#define EIE_INTIE        0x80
+#define EIE_PKTIE        0x40
+#define EIE_DMAIE        0x20
+#define EIE_LINKIE       0x10
+#define EIE_TXIE         0x08
+#define EIE_WOLIE        0x04
+#define EIE_TXERIE       0x02
+#define EIE_RXERIE       0x01
+#define EIE_ALLCLOSE     0xff
+
+/* ENC28J60 EIR Register Bit Definitions */
+#define EIR_PKTIF        0x40
+#define EIR_DMAIF        0x20
+#define EIR_LINKIF       0x10
+#define EIR_TXIF         0x08
+#define EIR_WOLIF        0x04
+#define EIR_TXERIF       0x02
+#define EIR_RXERIF       0x01
+#define EIR_ALLINTS      0x7b  /* All interrupts */
+
+/* ENC28J60 ESTAT Register Bit Definitions */
+#define ESTAT_INT        0x80
+#define ESTAT_LATECOL    0x10
+#define ESTAT_RXBUSY     0x04
+#define ESTAT_TXABRT     0x02
+#define ESTAT_CLKRDY     0x01
+/*  ENC28J60 ECON2 Register Bit Definitions */
+#define ECON2_AUTOINC    0x80
+#define ECON2_PKTDEC     0x40
+#define ECON2_PWRSV      0x20
+#define ECON2_VRPS       0x08
+/*  ENC28J60 ECON1 Register Bit Definitions */
+#define ECON1_TXRST      0x80
+#define ECON1_RXRST      0x40
+#define ECON1_DMAST      0x20
+#define ECON1_CSUMEN     0x10
+#define ECON1_TXRTS      0x08
+#define ECON1_RXEN       0x04
+#define ECON1_BSEL1      0x02
+#define ECON1_BSEL0      0x01
+/*  ENC28J60 MACON1 Register Bit Definitions */
+#define MACON1_LOOPBK    0x10
+#define MACON1_TXPAUS    0x08
+#define MACON1_RXPAUS    0x04
+#define MACON1_PASSALL   0x02
+#define MACON1_MARXEN    0x01
+/*  ENC28J60 MACON2 Register Bit Definitions */
+#define MACON2_MARST     0x80
+#define MACON2_RNDRST    0x40
+#define MACON2_MARXRST   0x08
+#define MACON2_RFUNRST   0x04
+#define MACON2_MATXRST   0x02
+#define MACON2_TFUNRST   0x01
+/*  ENC28J60 MACON3 Register Bit Definitions */
+#define MACON3_PADCFG2   0x80
+#define MACON3_PADCFG1   0x40
+#define MACON3_PADCFG0   0x20
+#define MACON3_TXCRCEN   0x10
+#define MACON3_PHDRLEN   0x08
+#define MACON3_HFRMLEN   0x04
+#define MACON3_FRMLNEN   0x02
+#define MACON3_FULDPX    0x01
+/*  ENC28J60 MICMD Register Bit Definitions */
+#define MICMD_MIISCAN    0x02
+#define MICMD_MIIRD      0x01
+/*  ENC28J60 MISTAT Register Bit Definitions */
+#define MISTAT_NVALID    0x04
+#define MISTAT_SCAN      0x02
+#define MISTAT_BUSY      0x01
+/*  ENC28J60 PHY PHCON1 Register Bit Definitions */
+#define PHCON1_PRST      0x8000
+#define PHCON1_PLOOPBK   0x4000
+#define PHCON1_PPWRSV    0x0800
+#define PHCON1_PDPXMD    0x0100
+/*  ENC28J60 PHY PHSTAT1 Register Bit Definitions */
+#define PHSTAT1_PFDPX    0x1000
+#define PHSTAT1_PHDPX    0x0800
+#define PHSTAT1_LLSTAT   0x0004
+#define PHSTAT1_JBSTAT   0x0002
+/*  ENC28J60 PHY PHCON2 Register Bit Definitions */
+#define PHCON2_FRCLINK   0x4000
+#define PHCON2_TXDIS     0x2000
+#define PHCON2_JABBER    0x0400
+#define PHCON2_HDLDIS    0x0100
+/*  ENC28J60 PHY PHIE Register Bit Definitions */
+#define PHIE_PLNKIE      0x0010
+#define PHIE_PGEIE       0x0002
+
+/*  ENC28J60 Packet Control Byte Bit Definitions */
+#define PKTCTRL_PHUGEEN  0x08
+#define PKTCTRL_PPADEN   0x04
+#define PKTCTRL_PCRCEN   0x02
+#define PKTCTRL_POVERRIDE 0x01
+
+/*  SPI operation codes */
+#define ENC28J60_READ_CTRL_REG  0x00
+#define ENC28J60_READ_BUF_MEM   0x3A
+#define ENC28J60_WRITE_CTRL_REG 0x40
+#define ENC28J60_WRITE_BUF_MEM  0x7A
+#define ENC28J60_BIT_FIELD_SET  0x80
+#define ENC28J60_BIT_FIELD_CLR  0xA0
+#define ENC28J60_SOFT_RESET     0xFF
+
+/*  The RXSTART_INIT should be zero. See Rev. B4 Silicon Errata
+ buffer boundaries applied to internal 8K ram
+ the entire available packet buffer space is allocated
+
+ start with recbuf at 0/ */
+#define RXSTART_INIT   0x0
+/*  receive buffer end */
+#define RXSTOP_INIT    (0x1FFF-0x0600-1)
+/*  start TX buffer at 0x1FFF-0x0600, pace for one full ethernet frame (~1500 bytes) */
+#define TXSTART_INIT   (0x1FFF-0x0600)
+/*  stp TX buffer at end of mem */
+#define TXSTOP_INIT    0x1FFF
+
+/*  max frame length which the conroller will accept: */
+#define MAX_FRAMELEN   1518        /*  (note: maximum ethernet frame length would be 1518) */
+
+void enc28j60_spi_cs_status_change(int status);
+
+#if 1//defined CONFIG_PHOBOS_GENERAL
+#define PA5_A8         15
+#define PA1            12
+
+#define ENC28J60_CSL()  enc28j60_spi_cs_status_change(0);  //yunos_bsp_gpio_set_value(20, GPIO_VALUE_LOW);  /* SPI_CS_LOW */
+
+#define ENC28J60_CSH()  enc28j60_spi_cs_status_change(1);  //yunos_bsp_gpio_set_value(20, GPIO_VALUE_HIGH);   /* SPI_CS_HIGH */
+
+#else
+#define PA5_A8         47
+#define ENC28J60_CSL() enc28j60_spi_cs_status_change(0);  //yunos_bsp_gpio_set_value(44, GPIO_VALUE_LOW);    /* SPI_CS_LOW */
+
+#define ENC28J60_CSH() enc28j60_spi_cs_status_change(1); //yunos_bsp_gpio_set_value(44, GPIO_VALUE_HIGH);   /* SPI_CS_HIGH */
+#endif
+
+typedef struct _spi_net_ops_t {
+    int (*init)(const uint8_t *macaddr);
+    int (*recv)(uint8_t *, uint16_t);
+    int (*send)(uint8_t *, uint16_t);
+    int (*reset)(void);
+    int (*irq_enable)(int);
+    int (*set_macaddr)(const uint8_t *macaddr);
+    int (*get_link_status)(void);
+} net_ops_t;
+
+enum enc28j60_reset {
+    RST_ENC28J60_ALL,
+    RST_ENC28J60_TX,
+    RST_ENC28J60_RX
+};
+
+int yunos_bsp_enc28j60_init(const uint8_t *macaddr);
+int yunos_bsp_enc28j60_reset(void);
+int yunos_bsp_enc28j60_get_link_status(void);
+int yunos_bsp_enc28j60_set_irq_enable(int enable);
+int yunos_bsp_enc28j60_get_interrupt_status(void);
+int yunos_bsp_enc28j60_set_interrupt_status(int status);
+//int yunos_bsp_enc28j60_set_interrupt(gpio_interrupt_t interrupt_cb);
+int yunos_bsp_enc28j60_get_pkt_cnt(void);
+int yunos_bsp_enc28j60_net_init(void);
+int yunos_bsp_enc28j60_set_macaddr(const uint8_t *macaddr);
+net_ops_t *yunos_bsp_spi_net_get_ctrl_ops(void);
+int yunos_bsp_enc28j60_handle_int_error(int status);
+
+int yunos_bsp_enc28j60_send_start(uint16_t len);
+void yunos_bsp_enc28j60_send_data(uint8_t *packet, uint16_t len);
+void yunos_bsp_enc28j60_send_end(void);
+
+int yunos_bsp_enc28j60_recv_start(uint16_t maxlen);
+int yunos_bsp_enc28j60_recv_data(uint8_t *packet, uint16_t len);
+void yunos_bsp_enc28j60_recv_end(void);
+
+void yunos_bsp_enc28j60_hard_reset(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ETHERNET_ENC28J60_H__ */

bsp/ck802/libraries/common/gpio/dw_gpio.h

+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     dw_gpio.h
+ * @brief    header file for GPIO Driver
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+#ifndef _DW_GPIO_H_
+#define _DW_GPIO_H_
+
+#include "drv_gpio.h"
+#include "soc.h"
+
+
+typedef struct {
+    __IOM uint32_t SWPORT_DR;                     /* Offset: 0x000 (W/R)  PortA data register */
+    __IOM uint32_t SWPORT_DDR;                    /* Offset: 0x004 (W/R)  PortA data direction register */
+    __IOM uint32_t PORT_CTL;                      /* Offset: 0x008 (W/R)  PortA source register */
+
+} dw_gpio_reg_t;
+
+typedef struct {
+    __IOM uint32_t INTEN;                         /* Offset: 0x000 (W/R)  Interrupt enable register */
+    __IOM uint32_t INTMASK;                       /* Offset: 0x004 (W/R)  Interrupt mask register */
+    __IOM uint32_t INTTYPE_LEVEL;                 /* Offset: 0x008 (W/R)  Interrupt level register */
+    __IOM uint32_t INT_POLARITY;                  /* Offset: 0x00c (W/R)  Interrupt polarity register */
+    __IM  uint32_t INTSTATUS;                     /* Offset: 0x010 (R)    Interrupt status of Port */
+    __IM  uint32_t RAWINTSTATUS;                  /* Offset: 0x014 (W/R)  Raw interrupt status of Port */
+    __IOM uint32_t revreg1;                       /* Offset: 0x018 (W/R)  Reserve register */
+    __OM  uint32_t PORTA_EOI;                     /* Offset: 0x01c (W/R)  Port clear interrupt register */
+    __IM  uint32_t EXT_PORTA;                     /* Offset: 0x020 (W/R)  PortA external port register */
+    __IM  uint32_t EXT_PORTB;                     /* Offset: 0x024 (W/R)  PortB external port register */
+    __IOM uint32_t revreg2[2];                    /* Offset: 0x028 (W/R)  Reserve register */
+    __IOM uint32_t LS_SYNC;                       /* Offset: 0x030 (W/R)  Level-sensitive synchronization enable register */
+
+} dw_gpio_control_reg_t;
+
+#endif
+

bsp/ck802/libraries/common/iic/dw_iic.h

+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/******************************************************************************
+ * @file     dw_iic.h
+ * @brief    header File for IIC Driver
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+#ifndef __DW_IIC_H
+#define __DW_IIC_H
+#include "soc.h"
+
+/*
+ * Define the speed of I2C
+ */
+typedef enum {
+    DW_IIC_STANDARDSPEED = 1,
+    DW_IIC_FASTSPEED     = 2,
+    DW_IIC_HIGHSPEED     = 3
+} DWENUM_IIC_SPEED;
+
+enum i2c_state_e {
+    IIC_STATE_NONE = 0,          /* Send start + (first part of) address. */
+    IIC_STATE_DATASEND,          /* Send data. */
+    IIC_STATE_WFDATA,            /* Wait for data. */
+    IIC_STATE_WFSTOPSENT,        /* Wait for STOP to have been transmitted. */
+    IIC_STATE_DONE,              /* Transfer completed successfully. */
+    IIC_STATE_ERROR              /* Transfer error. */
+};
+/*
+ * Define the interrupt type of I2C
+ */
+typedef enum {
+    DW_IIC_RX_UNDER  = 0,
+    DW_IIC_RX_OVER   = 1,
+    DW_IIC_RX_FULL   = 2,
+    DW_IIC_TX_OVER   = 3,
+    DW_IIC_TX_EMPTY  = 4,
+    DW_IIC_RD_REQ    = 5,
+    DW_IIC_TX_ABRT   = 6,
+    DW_IIC_RX_DONE   = 7,
+    DW_IIC_ACTIVITY  = 8,
+    DW_IIC_STOP_DET  = 9,
+    DW_IIC_START_DET = 10,
+    DW_IIC_GEN_CALL  = 11
+} DWENUM_IIC_INTERRUPT_TYPE;
+
+/*
+ * I2C register bit definitions
+ */
+#define DW_IIC_DISABLE      0
+#define DW_IIC_ENABLE       1
+#define DW_IIC_FIFO_MAX_LV  0x8
+#define DW_IIC_TXFIFO_LV    0x2
+#define DW_IIC_RXFIFO_LV    0x0
+
+#define DW_IIC_RXFIFO_FULL       (0x1 << 4)
+#define DW_IIC_RXFIFO_NOT_EMPTY  (0x1 << 3)
+#define DW_IIC_TXFIFO_EMPTY      (0x1 << 2)
+#define DW_IIC_TXFIFO_NOT_FULL   (0x1 << 1)
+#define DW_IIC_STATUS_ACTIVITY      0x1
+
+#define DW_IIC_CON_DEFAUL   0x23
+
+typedef struct {
+    __IOM uint32_t IC_CON;                    /* Offset: 0x000 (R/W)  Receive buffer register */
+    __IOM uint32_t IC_TAR;                    /* Offset: 0x004 (R/W)  Transmission hold register */
+    __IOM uint32_t IC_SAR;                    /* Offset: 0x008 (R/W)  Clock frequency division low section register */
+    __IOM uint32_t IC_HS_MADDR;               /* Offset: 0x00c (R/W)  Clock frequency division high section register */
+    __IOM uint32_t IC_DATA_CMD;               /* Offset: 0x010 (R/W)  Interrupt enable register */
+    __IOM uint32_t IC_SS_SCL_HCNT;            /* Offset: 0x014 (R/W)  Interrupt indicia register */
+    __IOM uint32_t IC_SS_SCL_LCNT;            /* Offset: 0x018 (R/W)  Transmission control register */
+    __IOM uint32_t IC_FS_SCL_HCNT;            /* Offset: 0x01c (R/W)  Modem control register */
+    __IOM uint32_t IC_FS_SCL_LCNT;            /* Offset: 0x020 (R/W)  Transmission state register */
+    __IOM uint32_t IC_HS_SCL_HCNT;            /* Offset: 0x024 (R/W)  Transmission state register */
+    __IOM uint32_t IC_HS_SCL_LCNT;            /* Offset: 0x028 (R/W)  Transmission state register */
+    __IOM uint32_t IC_INTR_STAT;              /* Offset: 0x02c (R)  Transmission state register */
+    __IOM uint32_t IC_INTR_MASK;              /* Offset: 0x030 (R/W)  Transmission state register */
+    __IOM uint32_t IC_RAW_INTR_STAT;          /* Offset: 0x034 (R)  Transmission state register */
+    __IOM uint32_t IC_RX_TL;                  /* Offset: 0x038 (R/W)  Transmission state register */
+    __IOM uint32_t IC_TX_TL;                  /* Offset: 0x03c (R/W)  Transmission state register */
+    __IOM uint32_t IC_CLR_INTR;               /* Offset: 0x040 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_RX_UNDER;           /* Offset: 0x044 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_RX_OVER;            /* Offset: 0x048 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_TX_OVER;            /* Offset: 0x04c (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_RD_REQ;             /* Offset: 0x050 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_TX_ABRT;            /* Offset: 0x054 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_RX_DONE;            /* Offset: 0x058 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_ACTIVITY;           /* Offset: 0x05c (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_STOP_DET;           /* Offset: 0x060 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_START_DET;          /* Offset: 0x064 (R)  Transmission state register */
+    __IOM uint32_t IC_CLR_GEN_CALL;           /* Offset: 0x068 (R)  Transmission state register */
+    __IOM uint32_t IC_ENABLE;                 /* Offset: 0x06c (R/W)  Transmission state register */
+    __IOM uint32_t IC_STATUS;                 /* Offset: 0x070 (R)  Transmission state register */
+    __IOM uint32_t IC_TXFLR;                  /* Offset: 0x074 (R)  Transmission state register */
+    __IOM uint32_t IC_RXFLR;                  /* Offset: 0x078 (R)  Transmission state register */
+    uint32_t RESERVED;                        /* Offset: 0x014 (R/ )  Transmission state register */
+    __IOM uint32_t IC_TX_ABRT_SOURCE;         /* Offset: 0x080 (R/W)  Transmission state register */
+    __IOM uint32_t IC_SAR1;                   /* Offset: 0x084 (R/W)  Transmission state register */
+    __IOM uint32_t IC_DMA_CR;                 /* Offset: 0x088 (R/W)  Transmission state register */
+    __IOM uint32_t IC_DMA_TDLR;               /* Offset: 0x08c (R/W)  Transmission state register */
+    __IOM uint32_t IC_DMA_RDLR;               /* Offset: 0x090 (R/W)  Transmission state register */
+    __IOM uint32_t IC_SAR2;                   /* Offset: 0x094 (R/W)  Transmission state register */
+    __IOM uint32_t IC_SAR3;                   /* Offset: 0x098 (R/W)  Transmission state register */
+    __IOM uint32_t IC_MULTI_SLAVE;            /* Offset: 0x09c (R/W)  Transmission state register */
+    __IOM uint32_t IC_GEN_CALL_EN;            /* Offset: 0x0a0 (R/W)  Transmission state register */
+} dw_iic_reg_t;
+
+#endif /* __DW_IIC_H */

bsp/ck802/libraries/common/pwm/ck_pwm.h

+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/******************************************************************************
+ * @file     ck_pwm.h
+ * @brief    header file for pwm driver
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+#ifndef __CK_PWM_H
+#define __CK_PWM_H
+#include <stdio.h>
+#include "soc.h"
+
+typedef enum {
+    CKENUM_PWM_CH0    = 0,
+    CKENUM_PWM_CH1    = 1,
+    CKENUM_PWM_CH2    = 2,
+    CKENUM_PWM_CH3    = 3,
+    CKENUM_PWM_CH4    = 4,
+    CKENUM_PWM_CH5    = 5,
+    CKENUM_PWM_CH6    = 6,
+    CKENUM_PWM_CH7    = 7,
+    CKENUM_PWM_CH8    = 8,
+    CKENUM_PWM_CH9    = 9,
+    CKENUM_PWM_CH10   = 10,
+    CKENUM_PWM_CH11   = 11
+} CKENUM_PWM_CHANNEL;
+
+typedef enum {
+    CKENUM_PWM_COUNT_UP          = 0,
+    CKENUM_PWM_COUNT_UP_DOWN     = 1
+} CKENUM_PWM_COUNTER_MODE;
+
+typedef struct {
+    __IOM uint32_t     PWMCFG;              /* Offset: 0x000 (R/W)  PWM configure register */
+    __IOM uint32_t     PWMINVERTTRIG;       /* Offset: 0x004 (R/W)  PWM signal is inverted register */
+    __IOM uint32_t     PWM01TRIG;           /* Offset: 0x008 (R/W)  contain the trigger generate compare value */
+    __IOM uint32_t     PWM23TRIG;           /* Offset: 0x00C (R/W)  contain the trigger generate compare value */
+    __IOM uint32_t     PWM45TRIG;           /* Offset: 0x010 (N/A)  contain the trigger generate compare value */
+    __IOM uint32_t     PWMINTEN1;           /* Offset: 0x014 (R/W)  interrupt enable */
+    __IM  uint32_t     PWMINTEN2;           /* Offset: 0x018 (N/A)  interrupt enable */
+    __IOM uint32_t     PWMRIS1;             /* Offset: 0x01C (R/ )  raw interrupt status */
+    __IOM uint32_t     PWMRIS2;             /* Offset: 0x020 (N/A)  raw interrupt status */
+    __IOM uint32_t     PWMIC1;              /* Offset: 0x024 (R/W)  interrupt clear */
+    __IOM uint32_t     PWMIC2;              /* Offset: 0x028 (R/W)  interrupt clear */
+    __IOM uint32_t     PWMIS1;              /* Offset: 0x02C (R/W)  interrupt status */
+    __IOM uint32_t     PWMIS2;              /* Offset: 0x030 (R/W)  interrupt status */
+    __IOM uint32_t     PWMCTL;              /* Offset: 0x034 (R/W)  configure the pwm generation blocks */
+    __IOM uint32_t     PWM01LOAD;           /* Offset: 0x038 (R/W)  contain the load value of the PWM count */
+    __IOM uint32_t     PWM23LOAD;           /* Offset: 0x03C (R/W)  contain the load value of the PWM count */
+    __IOM uint32_t     PWM45LOAD;           /* Offset: 0x040 (N/A)  contain the load value of the PWM count */
+    __IM  uint32_t     PWM01COUNT;          /* Offset: 0x044 (R/ )  contain the current value of the PWM count */
+    __IM  uint32_t     PWM23COUNT;          /* Offset: 0x048 (R/ )  contain the current value of the PWM count */
+    __IOM uint32_t     PWM45COUNT;          /* Offset: 0x04C (N/A)  contain the current value of the PWM count */
+    __IOM uint32_t     PWM0CMP;             /* Offset: 0x050 (R/W)  contain a value to be compared against the counter */
+    __IOM uint32_t     PWM1CMP;             /* Offset: 0x054 (R/W)  contain a value to be compared against the counter */
+    __IOM uint32_t     PWM2CMP;             /* Offset: 0x058 (R/W)  contain a value to be compared against the counter */
+    __IOM uint32_t     PWM3CMP;             /* Offset: 0x05C (N/A)  contain a value to be compared against the counter */
+    __IOM uint32_t     PWM4CMP;             /* Offset: 0x060 (N/A)  contain a value to be compared against the counter */
+    __IOM uint32_t     PWM5CMP;             /* Offset: 0x064 (N/A)  contain a value to be compared against the counter */
+    __IOM uint32_t     PWM01DB;             /* Offset: 0x068 (R/W)  contain the number of clock ticks to delay */
+    __IOM uint32_t     PWM23DB;             /* Offset: 0x06C (R/W)  contain the number of clock ticks to delayr */
+    __IOM uint32_t     PWM45DB;             /* Offset: 0x070 (N/A)  contain the number of clock ticks to delay */
+    __IOM uint32_t     CAPCTL;              /* Offset: 0x074 (R/W)  input capture control */
+    __IOM uint32_t     CAPINTEN;            /* Offset: 0x078 (R/W)  input capture interrupt enable */
+    __IM  uint32_t     CAPRIS;              /* Offset: 0x07C (R/ )  input capture raw interrupt status */
+    __IOM uint32_t     CAPIC;               /* Offset: 0x080 (R/W)  input capture interrupt clear */
+    __IM  uint32_t     CAPIS;               /* Offset: 0x084 (R/ )  input capture interrupt status */
+    __IM  uint32_t     CAP01T;              /* Offset: 0x088 (R/ )  input capture count value  */
+    __IM  uint32_t     CAP23T;              /* Offset: 0x08C (R/ )  input capture count value  */
+    __IOM uint32_t     CAP45T;              /* Offset: 0x090 (N/A)  input capture count value  */
+    __IOM uint32_t     CAP01MATCH;          /* Offset: 0x094 (R/W)  input capture match value  */
+    __IOM uint32_t     CAP23MATCH;          /* Offset: 0x098 (R/W)  input capture match value  */
+    __IOM uint32_t     CAP45MATCH;          /* Offset: 0x09C (N/A)  input capture match value  */
+    __IOM uint32_t     TIMINTEN;            /* Offset: 0x0A0 (R/W)  time interrupt enable */
+    __IM  uint32_t     TIMRIS;              /* Offset: 0x0A4 (R/ )  time raw interrupt stats */
+    __IOM uint32_t     TIMIC;               /* Offset: 0x0A8 (R/W)  time interrupt clear */
+    __IM  uint32_t     TIMIS;               /* Offset: 0x0AC (R/ )  time interrupt status */
+    __IOM uint32_t     TIM01LOAD;           /* Offset: 0x0B0 (R/W)  time load value */
+    __IOM uint32_t     TIM23LOAD;           /* Offset: 0x0B4 (R/W)  time load value */
+    __IOM uint32_t     TIM45LOAD;           /* Offset: 0x0B8 (N/A)  time load value */
+    __IOM uint32_t     TIM01COUNT;          /* Offset: 0x0BC (R/W)  time current count time */
+    __IOM uint32_t     TIM23COUNT;          /* Offset: 0x0C0 (R/W)  time current count time */
+    __IOM uint32_t     TIM45COUNT;          /* Offset: 0x0C4 (R/W)  time current count time */
+} ck_pwm_reg_t;
+
+#endif /* __CK_PWM_H */
+

bsp/ck802/libraries/common/rsa/ck_rsa.h

+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/******************************************************************************
+ * @file     ck_rsa.h
+ * @brief    header file for rsa driver
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+#ifndef _CK_RSA_H_
+#define _CK_RSA_H_
+
+#include <stdio.h>
+#include "drv_rsa.h"
+#include "soc.h"
+
+#define RSA_KEY_LEN     1024
+#define RSA_KEY_BYTE    (RSA_KEY_LEN >> 3)
+#define RSA_KEY_WORD    (RSA_KEY_LEN >> 5)
+
+#define BN_MAX_BITS     ((RSA_KEY_LEN << 1) + 32)
+#define BN_MAX_BYTES    ((BN_MAX_BITS + 7) >> 3)
+#define BN_MAX_WORDS    ((BN_MAX_BYTES + 3) >> 2)
+
+#define MAX_RSA_LP_CNT  10000
+
+#define UINT32_TO_UINT64(data)     ((uint64_t)(((uint64_t)(data)) & 0x00000000ffffffffU))
+#define UINT64L_TO_UINT32(data)    ((uint32_t)(((uint64_t)(data)) & 0x00000000ffffffffU))
+#define UINT64H_TO_UINT32(data)    ((uint32_t)((((uint64_t)(data)) >> 32) & 0x00000000ffffffffU))
+
+#define PKCS1_PADDING   0x01
+#define NO_PADDING      0x02
+
+#define MD5_PADDING     0x00
+#define SHA1_PADDING    0x01
+
+#define MD5_HASH_SZ   16
+#define SHA1_HASH_SZ  20
+
+#define RAS_CALCULATE_Q     0x6
+#define RSA_ENABLE_MODULE   0x3
+#define RSA_ENDIAN_MODE     0x8
+#define RSA_RESET           0x1
+#define RSA_CAL_Q_DONE_OFFSET   0x5
+
+typedef struct bignum {
+    uint32_t pdata[BN_MAX_WORDS];
+    uint32_t words;
+} bignum_t;
+
+typedef struct {
+    __IOM uint32_t rsa_mwid;          /* Offset: 0x000 (R/W)  Width of M register */
+    __IOM uint32_t rsa_ckid;          /* Offset: 0x004 (R/W)  Width of D register */
+    __IOM uint32_t rsa_bwid;          /* Offset: 0x008 (R/W)  Width of B register */
+    __IOM uint32_t rsa_ctrl;          /* Offset: 0x00c (R/W)  RSA control register */
+    __OM  uint32_t rsa_rst;           /* Offset: 0x010 (W)    RSA reset register */
+    __IM  uint32_t rsa_lp_cnt;        /* Offset: 0x014 (R)    Loop counter for inquiry register*/
+    __IM  uint32_t rsa_q0;            /* Offset: 0x018 (R)    High-radix MM algorithm assistant register,part 1*/
+    __IM  uint32_t rsa_q1;            /* Offset: 0x01c (R)    High-radix MM algorithm assistant register,part 2*/
+    __IOM uint32_t rsa_isr;           /* Offset: 0x020 (W/R)  Interrupt raw status register */
+    __IOM uint32_t rsa_imr;           /* Offset: 0x024 (W/R)  Interrupt mask register */
+    __IOM uint32_t rev1[54];          /* Reserve regiser */
+    __IOM uint32_t rsa_rfm;           /* Offset: 0x100 (W/R)  Register file for modulus M */
+    __IOM uint32_t rev2[63];          /* Reserve regiser */
+    __IOM uint32_t rsa_rfd;           /* Offset: 0x200 (W/R)  Register file for exponent D */
+    __IOM uint32_t rev3[63];          /* Reserve regiser */
+    __IOM uint32_t rsa_rfc;           /* Offset: 0x300 (W/R)  Register file for hard C */
+    __IOM uint32_t rev4[63];          /* Reserve regiser */
+    __IOM uint32_t rsa_rfb;           /* Offset: 0x400 (W/R)  Register file for data B */
+    __IOM uint32_t rev5[63];          /* Reserve regiser */
+    __IM  uint32_t rsa_rfr;           /* Offset: 0x500 (R)    Register file for storing the result */
+} ck_rsa_reg_t;
+
+#endif

bsp/ck802/libraries/common/rtc/ck_rtc.h

+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/******************************************************************************
+ * @file     ck_rtc.h
+ * @brief    header file for rtc driver
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+#ifndef __CK_RTC_H
+#define __CK_RTC_H
+
+#include <stdio.h>
+#include "soc.h"
+
+#define SEC_PER_MIN  ((time_t)60)
+#define SEC_PER_HOUR ((time_t)60 * SEC_PER_MIN)
+#define SEC_PER_DAY  ((time_t)24 * SEC_PER_HOUR)
+
+typedef struct {
+    __IM  uint32_t    RTC_CCVR;         /* Offset: 0x000 (R/ )  current count value register */
+    __IOM uint32_t    RTC_CMR;          /* Offset: 0x004 (R/W)  count match register */
+    __IOM uint32_t    RTC_CLR;          /* Offset: 0x008 (R/W)  count load register */
+    __IOM uint32_t    RTC_CCR;          /* Offset: 0x00c (R/W)  count control register */
+    __IM  uint32_t    RTC_STAT;         /* Offset: 0x010 (R/ )  interrupt status register */
+    __IM  uint32_t    RTC_RSTAT;        /* Offset: 0x014 (R/ )  interrupt raw status register */
+    __IM  uint32_t    RTC_EOI;          /* Offset: 0x018 (R/ )  end of interrupt register */
+    __IM  uint32_t    RTC_COMP_VERSION; /* Offset: 0x01c (R/ )  component version register */
+} ck_rtc_reg_t;
+
+#endif /* __CK_RTC_H */
+

bsp/ck802/libraries/common/trng/ck_trng.h

+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/******************************************************************************
+ * @file     ck_trng.h
+ * @brief    header file for trng driver
+ * @version  V1.0
+ * @date     02. June 2017
+ ******************************************************************************/
+#ifndef _CK_TRNG_H_
+#define _CK_TRNG_H_
+
+#include "drv_trng.h"
+#include "soc.h"
+
+/*
+ *  define the bits for TCR
+ */
+#define TRNG_EN              (1UL << 1)
+#define TRNG_LOWPER_MODE     (1UL << 2)
+#define TRNG_DATA_READY      1
+
+typedef struct {
+    __IOM uint32_t TCR;                     /* Offset: 0x000 (W/R)  TRNG control register */
+    __IM  uint32_t TDR;                     /* Offset: 0x004 (R)    TRNG Data register */
+
+} ck_trng_reg_t;
+#endif