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958d9405
编写于
3月 17, 2021
作者:
mysterywolf
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电子邮件补丁
差异文件
[lpcxxx] auto formatted
上级
c3ffe186
变更
171
展开全部
隐藏空白更改
内联
并排
Showing
171 changed file
with
5733 addition
and
5670 deletion
+5733
-5670
bsp/lpc1114/driver/board.c
bsp/lpc1114/driver/board.c
+2
-2
bsp/lpc1114/driver/drv_uart.c
bsp/lpc1114/driver/drv_uart.c
+1
-1
bsp/lpc176x/applications/application.c
bsp/lpc176x/applications/application.c
+18
-18
bsp/lpc176x/applications/platform.c
bsp/lpc176x/applications/platform.c
+4
-4
bsp/lpc176x/applications/platform.h
bsp/lpc176x/applications/platform.h
+1
-1
bsp/lpc176x/applications/startup.c
bsp/lpc176x/applications/startup.c
+28
-28
bsp/lpc176x/drivers/board.c
bsp/lpc176x/drivers/board.c
+17
-17
bsp/lpc176x/drivers/board.h
bsp/lpc176x/drivers/board.h
+1
-1
bsp/lpc176x/drivers/emac.c
bsp/lpc176x/drivers/emac.c
+420
-420
bsp/lpc176x/drivers/emac.h
bsp/lpc176x/drivers/emac.h
+10
-1
bsp/lpc176x/drivers/led.h
bsp/lpc176x/drivers/led.h
+1
-1
bsp/lpc176x/drivers/sd.c
bsp/lpc176x/drivers/sd.c
+4
-4
bsp/lpc176x/drivers/spi.c
bsp/lpc176x/drivers/spi.c
+129
-120
bsp/lpc176x/drivers/spi.h
bsp/lpc176x/drivers/spi.h
+17
-8
bsp/lpc176x/drivers/uart.c
bsp/lpc176x/drivers/uart.c
+5
-5
bsp/lpc176x/rtconfig.h
bsp/lpc176x/rtconfig.h
+26
-26
bsp/lpc178x/applications/application.c
bsp/lpc178x/applications/application.c
+45
-45
bsp/lpc178x/applications/startup.c
bsp/lpc178x/applications/startup.c
+32
-32
bsp/lpc178x/drivers/board.c
bsp/lpc178x/drivers/board.c
+1
-1
bsp/lpc178x/drivers/board.h
bsp/lpc178x/drivers/board.h
+2
-2
bsp/lpc178x/drivers/drv_glcd.c
bsp/lpc178x/drivers/drv_glcd.c
+185
-185
bsp/lpc178x/drivers/drv_glcd.h
bsp/lpc178x/drivers/drv_glcd.h
+6
-6
bsp/lpc178x/drivers/emac.c
bsp/lpc178x/drivers/emac.c
+418
-418
bsp/lpc178x/drivers/emac.h
bsp/lpc178x/drivers/emac.h
+10
-1
bsp/lpc178x/drivers/lpc177x_8x_clkpwr.c
bsp/lpc178x/drivers/lpc177x_8x_clkpwr.c
+188
-188
bsp/lpc178x/drivers/lpc177x_8x_clkpwr.h
bsp/lpc178x/drivers/lpc177x_8x_clkpwr.h
+87
-87
bsp/lpc178x/drivers/lpc177x_8x_emc.c
bsp/lpc178x/drivers/lpc177x_8x_emc.c
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-250
bsp/lpc178x/drivers/lpc177x_8x_emc.h
bsp/lpc178x/drivers/lpc177x_8x_emc.h
+71
-71
bsp/lpc178x/drivers/lpc177x_8x_pinsel.c
bsp/lpc178x/drivers/lpc177x_8x_pinsel.c
+209
-209
bsp/lpc178x/drivers/lpc177x_8x_pinsel.h
bsp/lpc178x/drivers/lpc177x_8x_pinsel.h
+174
-174
bsp/lpc178x/drivers/lpc177x_8x_uart.c
bsp/lpc178x/drivers/lpc177x_8x_uart.c
+1072
-1072
bsp/lpc178x/drivers/lpc177x_8x_uart.h
bsp/lpc178x/drivers/lpc177x_8x_uart.h
+257
-257
bsp/lpc178x/drivers/lpc17xx_lcd.c
bsp/lpc178x/drivers/lpc17xx_lcd.c
+48
-48
bsp/lpc178x/drivers/lpc_types.h
bsp/lpc178x/drivers/lpc_types.h
+18
-18
bsp/lpc178x/drivers/sdram.c
bsp/lpc178x/drivers/sdram.c
+56
-56
bsp/lpc178x/drivers/sdram.h
bsp/lpc178x/drivers/sdram.h
+9
-0
bsp/lpc178x/drivers/uart.c
bsp/lpc178x/drivers/uart.c
+171
-171
bsp/lpc178x/rtconfig.h
bsp/lpc178x/rtconfig.h
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-28
bsp/lpc2148/applications/application.c
bsp/lpc2148/applications/application.c
+1
-1
bsp/lpc2148/applications/startup.c
bsp/lpc2148/applications/startup.c
+1
-1
bsp/lpc2148/drivers/board.c
bsp/lpc2148/drivers/board.c
+43
-43
bsp/lpc2148/drivers/board.h
bsp/lpc2148/drivers/board.h
+4
-4
bsp/lpc2148/drivers/dm9000.c
bsp/lpc2148/drivers/dm9000.c
+48
-48
bsp/lpc2148/drivers/sd.c
bsp/lpc2148/drivers/sd.c
+45
-45
bsp/lpc2148/drivers/serial.c
bsp/lpc2148/drivers/serial.c
+253
-253
bsp/lpc2148/rtconfig.h
bsp/lpc2148/rtconfig.h
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-23
bsp/lpc2478/applications/application.c
bsp/lpc2478/applications/application.c
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-1
bsp/lpc2478/applications/startup.c
bsp/lpc2478/applications/startup.c
+1
-1
bsp/lpc2478/drivers/board.c
bsp/lpc2478/drivers/board.c
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-14
bsp/lpc2478/drivers/board.h
bsp/lpc2478/drivers/board.h
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-70
bsp/lpc2478/drivers/serial.c
bsp/lpc2478/drivers/serial.c
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-264
bsp/lpc2478/rtconfig.h
bsp/lpc2478/rtconfig.h
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-19
bsp/lpc408x/applications/main.c
bsp/lpc408x/applications/main.c
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-4
bsp/lpc408x/drivers/board.c
bsp/lpc408x/drivers/board.c
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-1
bsp/lpc408x/drivers/board.h
bsp/lpc408x/drivers/board.h
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-1
bsp/lpc408x/drivers/drv_emac.c
bsp/lpc408x/drivers/drv_emac.c
+1
-1
bsp/lpc408x/drivers/drv_emac.h
bsp/lpc408x/drivers/drv_emac.h
+1
-1
bsp/lpc408x/drivers/drv_hwtimer.c
bsp/lpc408x/drivers/drv_hwtimer.c
+1
-1
bsp/lpc408x/drivers/drv_hwtimer.h
bsp/lpc408x/drivers/drv_hwtimer.h
+1
-1
bsp/lpc408x/drivers/drv_led.c
bsp/lpc408x/drivers/drv_led.c
+1
-1
bsp/lpc408x/drivers/drv_led.h
bsp/lpc408x/drivers/drv_led.h
+1
-1
bsp/lpc408x/drivers/drv_sdram.c
bsp/lpc408x/drivers/drv_sdram.c
+1
-1
bsp/lpc408x/drivers/drv_sdram.h
bsp/lpc408x/drivers/drv_sdram.h
+1
-1
bsp/lpc408x/drivers/drv_uart.c
bsp/lpc408x/drivers/drv_uart.c
+1
-1
bsp/lpc408x/drivers/drv_uart.h
bsp/lpc408x/drivers/drv_uart.h
+1
-1
bsp/lpc43xx/M0/applications/application.c
bsp/lpc43xx/M0/applications/application.c
+1
-1
bsp/lpc43xx/M0/applications/board.c
bsp/lpc43xx/M0/applications/board.c
+1
-1
bsp/lpc43xx/M0/applications/board.h
bsp/lpc43xx/M0/applications/board.h
+1
-1
bsp/lpc43xx/M0/applications/startup.c
bsp/lpc43xx/M0/applications/startup.c
+1
-1
bsp/lpc43xx/M0/applications/vbus_drv.c
bsp/lpc43xx/M0/applications/vbus_drv.c
+2
-2
bsp/lpc43xx/M0/applications/vbus_hw.h
bsp/lpc43xx/M0/applications/vbus_hw.h
+2
-2
bsp/lpc43xx/M4/applications/application.c
bsp/lpc43xx/M4/applications/application.c
+3
-3
bsp/lpc43xx/M4/applications/board.c
bsp/lpc43xx/M4/applications/board.c
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-1
bsp/lpc43xx/M4/applications/board.h
bsp/lpc43xx/M4/applications/board.h
+1
-1
bsp/lpc43xx/M4/applications/startup.c
bsp/lpc43xx/M4/applications/startup.c
+1
-1
bsp/lpc43xx/M4/applications/vbus_drv.c
bsp/lpc43xx/M4/applications/vbus_drv.c
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-2
bsp/lpc43xx/M4/applications/vbus_hw.h
bsp/lpc43xx/M4/applications/vbus_hw.h
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-2
bsp/lpc43xx/drivers/drv_emac.c
bsp/lpc43xx/drivers/drv_emac.c
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-1
bsp/lpc43xx/drivers/drv_emac.h
bsp/lpc43xx/drivers/drv_emac.h
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-1
bsp/lpc43xx/drivers/drv_led.c
bsp/lpc43xx/drivers/drv_led.c
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-1
bsp/lpc43xx/drivers/drv_uart.c
bsp/lpc43xx/drivers/drv_uart.c
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-4
bsp/lpc5410x/applications/application.c
bsp/lpc5410x/applications/application.c
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-1
bsp/lpc5410x/applications/board.c
bsp/lpc5410x/applications/board.c
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-2
bsp/lpc5410x/applications/board.h
bsp/lpc5410x/applications/board.h
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-1
bsp/lpc5410x/applications/demo_thread.c
bsp/lpc5410x/applications/demo_thread.c
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-30
bsp/lpc5410x/applications/startup.c
bsp/lpc5410x/applications/startup.c
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-1
bsp/lpc5410x/drivers/drv_led.c
bsp/lpc5410x/drivers/drv_led.c
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-1
bsp/lpc5410x/drivers/drv_led.h
bsp/lpc5410x/drivers/drv_led.h
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-0
bsp/lpc5410x/drivers/drv_uart.c
bsp/lpc5410x/drivers/drv_uart.c
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-1
bsp/lpc5410x/drivers/drv_uart.h
bsp/lpc5410x/drivers/drv_uart.h
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-0
bsp/lpc5410x/rtconfig.h
bsp/lpc5410x/rtconfig.h
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-26
bsp/lpc54114-lite/applications/main.c
bsp/lpc54114-lite/applications/main.c
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-3
bsp/lpc54114-lite/applications/mnt.c
bsp/lpc54114-lite/applications/mnt.c
+5
-5
bsp/lpc54114-lite/drivers/audio/drv_mic.c
bsp/lpc54114-lite/drivers/audio/drv_mic.c
+2
-2
bsp/lpc54114-lite/drivers/audio/drv_mic.h
bsp/lpc54114-lite/drivers/audio/drv_mic.h
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-1
bsp/lpc54114-lite/drivers/audio/drv_sound.c
bsp/lpc54114-lite/drivers/audio/drv_sound.c
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-2
bsp/lpc54114-lite/drivers/audio/drv_sound.h
bsp/lpc54114-lite/drivers/audio/drv_sound.h
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-1
bsp/lpc54114-lite/drivers/board.c
bsp/lpc54114-lite/drivers/board.c
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bsp/lpc54114-lite/drivers/board.h
bsp/lpc54114-lite/drivers/board.h
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bsp/lpc54114-lite/drivers/drv_gpio.c
bsp/lpc54114-lite/drivers/drv_gpio.c
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bsp/lpc54114-lite/drivers/drv_gpio.h
bsp/lpc54114-lite/drivers/drv_gpio.h
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bsp/lpc54114-lite/drivers/drv_i2c.c
bsp/lpc54114-lite/drivers/drv_i2c.c
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bsp/lpc54114-lite/drivers/drv_i2c.h
bsp/lpc54114-lite/drivers/drv_i2c.h
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bsp/lpc54114-lite/drivers/drv_romfs.c
bsp/lpc54114-lite/drivers/drv_romfs.c
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-9
bsp/lpc54114-lite/drivers/drv_sdcard.c
bsp/lpc54114-lite/drivers/drv_sdcard.c
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bsp/lpc54114-lite/drivers/drv_sdcard.h
bsp/lpc54114-lite/drivers/drv_sdcard.h
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bsp/lpc54114-lite/drivers/drv_spi.c
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bsp/lpc54114-lite/drivers/drv_spi.h
bsp/lpc54114-lite/drivers/drv_spi.h
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bsp/lpc54114-lite/drivers/drv_spi_flash.c
bsp/lpc54114-lite/drivers/drv_spi_flash.c
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bsp/lpc54114-lite/drivers/drv_spi_flash.h
bsp/lpc54114-lite/drivers/drv_spi_flash.h
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bsp/lpc54114-lite/drivers/drv_uart.c
bsp/lpc54114-lite/drivers/drv_uart.c
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-23
bsp/lpc54114-lite/drivers/drv_uart.h
bsp/lpc54114-lite/drivers/drv_uart.h
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bsp/lpc54608-LPCXpresso/applications/application.c
bsp/lpc54608-LPCXpresso/applications/application.c
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bsp/lpc54608-LPCXpresso/applications/mnt.c
bsp/lpc54608-LPCXpresso/applications/mnt.c
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bsp/lpc54608-LPCXpresso/applications/startup.c
bsp/lpc54608-LPCXpresso/applications/startup.c
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bsp/lpc54608-LPCXpresso/drivers/board.c
bsp/lpc54608-LPCXpresso/drivers/board.c
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bsp/lpc54608-LPCXpresso/drivers/board.h
bsp/lpc54608-LPCXpresso/drivers/board.h
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bsp/lpc54608-LPCXpresso/drivers/drt_mpu.c
bsp/lpc54608-LPCXpresso/drivers/drt_mpu.c
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bsp/lpc54608-LPCXpresso/drivers/drt_mpu.h
bsp/lpc54608-LPCXpresso/drivers/drt_mpu.h
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bsp/lpc54608-LPCXpresso/drivers/drv_emac.c
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bsp/lpc54608-LPCXpresso/drivers/drv_emac.h
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bsp/lpc54608-LPCXpresso/drivers/drv_ft5406.c
bsp/lpc54608-LPCXpresso/drivers/drv_ft5406.c
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bsp/lpc54608-LPCXpresso/drivers/drv_i2c.c
bsp/lpc54608-LPCXpresso/drivers/drv_i2c.c
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bsp/lpc54608-LPCXpresso/drivers/drv_lcd.c
bsp/lpc54608-LPCXpresso/drivers/drv_lcd.c
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bsp/lpc54608-LPCXpresso/drivers/drv_sd.c
bsp/lpc54608-LPCXpresso/drivers/drv_sd.c
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bsp/lpc54608-LPCXpresso/drivers/drv_sd.h
bsp/lpc54608-LPCXpresso/drivers/drv_sd.h
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bsp/lpc54608-LPCXpresso/drivers/drv_sdram.c
bsp/lpc54608-LPCXpresso/drivers/drv_sdram.c
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bsp/lpc54608-LPCXpresso/drivers/drv_sdram.h
bsp/lpc54608-LPCXpresso/drivers/drv_sdram.h
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bsp/lpc54608-LPCXpresso/drivers/drv_sram.c
bsp/lpc54608-LPCXpresso/drivers/drv_sram.c
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bsp/lpc54608-LPCXpresso/drivers/drv_sram.h
bsp/lpc54608-LPCXpresso/drivers/drv_sram.h
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bsp/lpc54608-LPCXpresso/drivers/drv_uart.c
bsp/lpc54608-LPCXpresso/drivers/drv_uart.c
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bsp/lpc54608-LPCXpresso/drivers/fsl_phy.c
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bsp/lpc55sxx/Libraries/drivers/drv_adc.c
bsp/lpc55sxx/Libraries/drivers/drv_adc.c
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bsp/lpc55sxx/Libraries/drivers/drv_adc.h
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bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.c
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bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.h
bsp/lpc55sxx/Libraries/drivers/drv_hwtimer.h
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bsp/lpc55sxx/Libraries/drivers/drv_i2c.c
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bsp/lpc55sxx/Libraries/drivers/drv_i2c.h
bsp/lpc55sxx/Libraries/drivers/drv_i2c.h
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bsp/lpc55sxx/Libraries/drivers/drv_key.c
bsp/lpc55sxx/Libraries/drivers/drv_key.c
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bsp/lpc55sxx/Libraries/drivers/drv_key.h
bsp/lpc55sxx/Libraries/drivers/drv_key.h
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bsp/lpc55sxx/Libraries/drivers/drv_led.c
bsp/lpc55sxx/Libraries/drivers/drv_led.c
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bsp/lpc55sxx/Libraries/drivers/drv_log.h
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bsp/lpc55sxx/Libraries/drivers/drv_pin.h
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bsp/lpc55sxx/Libraries/drivers/drv_pwm.h
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bsp/lpc55sxx/Libraries/drivers/drv_rtc.h
bsp/lpc55sxx/Libraries/drivers/drv_rtc.h
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bsp/lpc55sxx/Libraries/drivers/drv_sd.c
bsp/lpc55sxx/Libraries/drivers/drv_sd.c
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bsp/lpc55sxx/Libraries/drivers/drv_sd.h
bsp/lpc55sxx/Libraries/drivers/drv_sd.h
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bsp/lpc55sxx/Libraries/drivers/drv_spi.c
bsp/lpc55sxx/Libraries/drivers/drv_spi.c
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bsp/lpc55sxx/Libraries/drivers/drv_spi.h
bsp/lpc55sxx/Libraries/drivers/drv_spi.h
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bsp/lpc55sxx/Libraries/drivers/drv_uart.c
bsp/lpc55sxx/Libraries/drivers/drv_uart.c
+18
-18
bsp/lpc55sxx/Libraries/drivers/drv_uart.h
bsp/lpc55sxx/Libraries/drivers/drv_uart.h
+1
-1
bsp/lpc55sxx/Libraries/drivers/drv_wdt.c
bsp/lpc55sxx/Libraries/drivers/drv_wdt.c
+7
-7
bsp/lpc55sxx/Libraries/drivers/drv_wdt.h
bsp/lpc55sxx/Libraries/drivers/drv_wdt.h
+1
-1
bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/applications/main.c
...c55sxx/Libraries/template/lpc55s6xxxx/applications/main.c
+2
-2
bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.c
bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.c
+9
-9
bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.h
bsp/lpc55sxx/Libraries/template/lpc55s6xxxx/board/board.h
+1
-1
bsp/lpc55sxx/lpc55s69_nxp_evk/applications/main.c
bsp/lpc55sxx/lpc55s69_nxp_evk/applications/main.c
+1
-1
bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.c
bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.c
+9
-9
bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.h
bsp/lpc55sxx/lpc55s69_nxp_evk/board/board.h
+1
-1
bsp/lpc824/applications/application.c
bsp/lpc824/applications/application.c
+10
-10
bsp/lpc824/applications/startup.c
bsp/lpc824/applications/startup.c
+2
-2
bsp/lpc824/drivers/board.c
bsp/lpc824/drivers/board.c
+2
-2
bsp/lpc824/drivers/board.h
bsp/lpc824/drivers/board.h
+1
-1
bsp/lpc824/drivers/usart.c
bsp/lpc824/drivers/usart.c
+43
-43
bsp/lpc824/drivers/usart.h
bsp/lpc824/drivers/usart.h
+1
-1
bsp/lpc824/rtconfig.h
bsp/lpc824/rtconfig.h
+10
-10
未找到文件。
bsp/lpc1114/driver/board.c
浏览文件 @
958d9405
/*
/*
* Copyright (c) 20
19
, RT-Thread Development Team
* Copyright (c) 20
06-2021
, RT-Thread Development Team
*
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-License-Identifier: Apache-2.0
*
*
...
@@ -33,7 +33,7 @@
...
@@ -33,7 +33,7 @@
#define NVIC_ISPR HWREG32(SCB_BASE + 0x200)
#define NVIC_ISPR HWREG32(SCB_BASE + 0x200)
#define NVIC_ICPR HWREG32(SCB_BASE + 0x280)
#define NVIC_ICPR HWREG32(SCB_BASE + 0x280)
#define NVIC_IPR(irqno) HWREG32(SCB_BASE + 0x400 + (((irqno) / 4) << 2))
#define NVIC_IPR(irqno) HWREG32(SCB_BASE + 0x400 + (((irqno) / 4) << 2))
#define SCB_SHPR3 HWREG32(SCB_BASE + 0xd20)
#define SCB_SHPR3 HWREG32(SCB_BASE + 0xd20)
extern
unsigned
char
__bss_end__
[];
extern
unsigned
char
__bss_end__
[];
extern
unsigned
char
_ram_end
[];
extern
unsigned
char
_ram_end
[];
...
...
bsp/lpc1114/driver/drv_uart.c
浏览文件 @
958d9405
/*
/*
* Copyright (c) 2006-20
19
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-License-Identifier: Apache-2.0
*
*
...
...
bsp/lpc176x/applications/application.c
浏览文件 @
958d9405
/*
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-License-Identifier: Apache-2.0
*
*
...
@@ -38,44 +38,44 @@ extern int lwip_system_init(void);
...
@@ -38,44 +38,44 @@ extern int lwip_system_init(void);
/* thread phase init */
/* thread phase init */
void
rt_init_thread_entry
(
void
*
parameter
)
void
rt_init_thread_entry
(
void
*
parameter
)
{
{
/* initialize platform */
/* initialize platform */
platform_init
();
platform_init
();
#ifdef RT_USING_LWIP
#ifdef RT_USING_LWIP
/* register Ethernet interface device */
/* register Ethernet interface device */
lpc17xx_emac_hw_init
();
lpc17xx_emac_hw_init
();
/* initialize lwip stack */
/* initialize lwip stack */
/* register ethernetif device */
/* register ethernetif device */
eth_system_device_init
();
eth_system_device_init
();
/* initialize lwip system */
/* initialize lwip system */
lwip_system_init
();
lwip_system_init
();
rt_kprintf
(
"TCP/IP initialized!
\n
"
);
rt_kprintf
(
"TCP/IP initialized!
\n
"
);
#endif
#endif
/* Filesystem Initialization */
/* Filesystem Initialization */
#ifdef RT_USING_DFS
#ifdef RT_USING_DFS
rt_hw_sdcard_init
();
rt_hw_sdcard_init
();
/* initialize the device file system */
/* initialize the device file system */
dfs_init
();
dfs_init
();
#ifdef RT_USING_DFS_ELMFAT
#ifdef RT_USING_DFS_ELMFAT
/* initialize the elm chan FatFS file system*/
/* initialize the elm chan FatFS file system*/
elm_init
();
elm_init
();
#endif
#endif
/* mount sd card fat partition 1 as root directory */
/* mount sd card fat partition 1 as root directory */
if
(
dfs_mount
(
"sd0"
,
"/"
,
"elm"
,
0
,
0
)
==
0
)
if
(
dfs_mount
(
"sd0"
,
"/"
,
"elm"
,
0
,
0
)
==
0
)
rt_kprintf
(
"File System initialized!
\n
"
);
rt_kprintf
(
"File System initialized!
\n
"
);
else
else
rt_kprintf
(
"File System init failed!
\n
"
);
rt_kprintf
(
"File System init failed!
\n
"
);
#endif
#endif
#ifdef RT_USING_FINSH
#ifdef RT_USING_FINSH
/* initialize finsh */
/* initialize finsh */
finsh_system_init
();
finsh_system_init
();
#endif
#endif
}
}
...
@@ -84,8 +84,8 @@ int rt_application_init()
...
@@ -84,8 +84,8 @@ int rt_application_init()
rt_thread_t
tid
;
rt_thread_t
tid
;
tid
=
rt_thread_create
(
"init"
,
tid
=
rt_thread_create
(
"init"
,
rt_init_thread_entry
,
RT_NULL
,
rt_init_thread_entry
,
RT_NULL
,
2048
,
RT_THREAD_PRIORITY_MAX
/
3
,
20
);
2048
,
RT_THREAD_PRIORITY_MAX
/
3
,
20
);
if
(
tid
!=
RT_NULL
)
rt_thread_startup
(
tid
);
if
(
tid
!=
RT_NULL
)
rt_thread_startup
(
tid
);
return
0
;
return
0
;
...
...
bsp/lpc176x/applications/platform.c
浏览文件 @
958d9405
/*
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-License-Identifier: Apache-2.0
*
*
...
@@ -16,11 +16,11 @@ static struct rt_memheap _memheap;
...
@@ -16,11 +16,11 @@ static struct rt_memheap _memheap;
void
platform_init
(
void
)
void
platform_init
(
void
)
{
{
#ifdef RT_USING_MEMHEAP
#ifdef RT_USING_MEMHEAP
/* create memory heap object on 0x2007 C000 - 0x2008 4000*/
/* create memory heap object on 0x2007 C000 - 0x2008 4000*/
#ifdef RT_USING_LWIP
#ifdef RT_USING_LWIP
rt_memheap_init
(
&
_memheap
,
"system"
,
(
void
*
)
0x2007C000
,
16
*
1024
);
rt_memheap_init
(
&
_memheap
,
"system"
,
(
void
*
)
0x2007C000
,
16
*
1024
);
#else
#else
rt_memheap_init
(
&
_memheap
,
"system"
,
(
void
*
)
0x2007C000
,
32
*
1024
);
rt_memheap_init
(
&
_memheap
,
"system"
,
(
void
*
)
0x2007C000
,
32
*
1024
);
#endif
#endif
#endif
#endif
}
}
bsp/lpc176x/applications/platform.h
浏览文件 @
958d9405
/*
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-License-Identifier: Apache-2.0
*
*
...
...
bsp/lpc176x/applications/startup.c
浏览文件 @
958d9405
/*
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-License-Identifier: Apache-2.0
*
*
...
@@ -33,28 +33,28 @@ extern int __bss_end;
...
@@ -33,28 +33,28 @@ extern int __bss_end;
*/
*/
void
rtthread_startup
(
void
)
void
rtthread_startup
(
void
)
{
{
/* initialize board */
/* initialize board */
rt_hw_board_init
();
rt_hw_board_init
();
/* show version */
/* show version */
rt_show_version
();
rt_show_version
();
#ifdef RT_USING_HEAP
#ifdef RT_USING_HEAP
/* initialize memory system */
/* initialize memory system */
#ifdef __CC_ARM
#ifdef __CC_ARM
rt_system_heap_init
((
void
*
)
&
Image
$$
RW_IRAM1
$$
ZI
$$
Limit
,
(
void
*
)
0x10008000
);
rt_system_heap_init
((
void
*
)
&
Image
$$
RW_IRAM1
$$
ZI
$$
Limit
,
(
void
*
)
0x10008000
);
#elif __ICCARM__
#elif __ICCARM__
rt_system_heap_init
(
__segment_end
(
"HEAP"
),
(
void
*
)
0x10008000
);
rt_system_heap_init
(
__segment_end
(
"HEAP"
),
(
void
*
)
0x10008000
);
#else
#else
rt_system_heap_init
((
void
*
)
&
__bss_end
,
(
void
*
)
0x10008000
);
rt_system_heap_init
((
void
*
)
&
__bss_end
,
(
void
*
)
0x10008000
);
#endif
#endif
#endif
#endif
/* initialize scheduler system */
/* initialize scheduler system */
rt_system_scheduler_init
();
rt_system_scheduler_init
();
/* initialize application */
/* initialize application */
rt_application_init
();
rt_application_init
();
/* initialize timer */
/* initialize timer */
rt_system_timer_init
();
rt_system_timer_init
();
...
@@ -62,25 +62,25 @@ void rtthread_startup(void)
...
@@ -62,25 +62,25 @@ void rtthread_startup(void)
/* initialize timer thread */
/* initialize timer thread */
rt_system_timer_thread_init
();
rt_system_timer_thread_init
();
/* initialize idle thread */
/* initialize idle thread */
rt_thread_idle_init
();
rt_thread_idle_init
();
/* start scheduler */
/* start scheduler */
rt_system_scheduler_start
();
rt_system_scheduler_start
();
/* never reach here */
/* never reach here */
return
;
return
;
}
}
int
main
(
void
)
int
main
(
void
)
{
{
/* disable interrupt first */
/* disable interrupt first */
rt_hw_interrupt_disable
();
rt_hw_interrupt_disable
();
/* startup RT-Thread RTOS */
/* startup RT-Thread RTOS */
rtthread_startup
();
rtthread_startup
();
return
0
;
return
0
;
}
}
/*@}*/
/*@}*/
bsp/lpc176x/drivers/board.c
浏览文件 @
958d9405
/*
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-License-Identifier: Apache-2.0
*
*
...
@@ -29,13 +29,13 @@
...
@@ -29,13 +29,13 @@
*/
*/
void
rt_hw_timer_handler
(
void
)
void
rt_hw_timer_handler
(
void
)
{
{
/* enter interrupt */
/* enter interrupt */
rt_interrupt_enter
();
rt_interrupt_enter
();
rt_tick_increase
();
rt_tick_increase
();
/* leave interrupt */
/* leave interrupt */
rt_interrupt_leave
();
rt_interrupt_leave
();
}
}
void
SysTick_Handler
(
void
)
void
SysTick_Handler
(
void
)
...
@@ -48,24 +48,24 @@ void SysTick_Handler(void)
...
@@ -48,24 +48,24 @@ void SysTick_Handler(void)
*/
*/
void
rt_hw_board_init
()
void
rt_hw_board_init
()
{
{
/* NVIC Configuration */
/* NVIC Configuration */
#define NVIC_VTOR_MASK 0x3FFFFF80
#define NVIC_VTOR_MASK 0x3FFFFF80
#ifdef VECT_TAB_RAM
#ifdef VECT_TAB_RAM
/* Set the Vector Table base location at 0x10000000 */
/* Set the Vector Table base location at 0x10000000 */
SCB
->
VTOR
=
(
0x10000000
&
NVIC_VTOR_MASK
);
SCB
->
VTOR
=
(
0x10000000
&
NVIC_VTOR_MASK
);
#else
/* VECT_TAB_FLASH */
#else
/* VECT_TAB_FLASH */
/* Set the Vector Table base location at 0x00000000 */
/* Set the Vector Table base location at 0x00000000 */
SCB
->
VTOR
=
(
0x00000000
&
NVIC_VTOR_MASK
);
SCB
->
VTOR
=
(
0x00000000
&
NVIC_VTOR_MASK
);
#endif
#endif
/* initialize systick */
/* initialize systick */
SysTick_Config
(
SystemCoreClock
/
RT_TICK_PER_SECOND
);
SysTick_Config
(
SystemCoreClock
/
RT_TICK_PER_SECOND
);
/* set pend exception priority */
/* set pend exception priority */
NVIC_SetPriority
(
PendSV_IRQn
,
(
1
<<
__NVIC_PRIO_BITS
)
-
1
);
NVIC_SetPriority
(
PendSV_IRQn
,
(
1
<<
__NVIC_PRIO_BITS
)
-
1
);
#ifdef RT_USING_UART0
#ifdef RT_USING_UART0
rt_hw_uart_init
();
rt_hw_uart_init
();
rt_console_set_device
(
RT_CONSOLE_DEVICE_NAME
);
rt_console_set_device
(
RT_CONSOLE_DEVICE_NAME
);
#endif
#endif
}
}
...
...
bsp/lpc176x/drivers/board.h
浏览文件 @
958d9405
/*
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-License-Identifier: Apache-2.0
*
*
...
...
bsp/lpc176x/drivers/emac.c
浏览文件 @
958d9405
此差异已折叠。
点击以展开。
bsp/lpc176x/drivers/emac.h
浏览文件 @
958d9405
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef __LPC17XX_EMAC_H
#ifndef __LPC17XX_EMAC_H
#define __LPC17XX_EMAC_H
#define __LPC17XX_EMAC_H
...
@@ -11,7 +20,7 @@
...
@@ -11,7 +20,7 @@
#define ETH_MAX_FLEN 1536
/* Max. Ethernet Frame Size */
#define ETH_MAX_FLEN 1536
/* Max. Ethernet Frame Size */
/* EMAC variables located in 16K Ethernet SRAM */
/* EMAC variables located in 16K Ethernet SRAM */
#define RX_DESC_BASE
0x20080000
#define RX_DESC_BASE
0x20080000
#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)
#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)
#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)
#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)
#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)
#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)
...
...
bsp/lpc176x/drivers/led.h
浏览文件 @
958d9405
/*
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-License-Identifier: Apache-2.0
*
*
...
...
bsp/lpc176x/drivers/sd.c
浏览文件 @
958d9405
/*
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-License-Identifier: Apache-2.0
*
*
...
@@ -467,12 +467,12 @@ static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args)
...
@@ -467,12 +467,12 @@ static rt_err_t rt_sdcard_control(rt_device_t dev, int cmd, void *args)
if
(
cmd
==
RT_DEVICE_CTRL_BLK_GETGEOME
)
if
(
cmd
==
RT_DEVICE_CTRL_BLK_GETGEOME
)
{
{
struct
rt_device_blk_geometry
*
geometry
;
struct
rt_device_blk_geometry
*
geometry
;
geometry
=
(
struct
rt_device_blk_geometry
*
)
args
;
geometry
=
(
struct
rt_device_blk_geometry
*
)
args
;
if
(
geometry
==
RT_NULL
)
return
-
RT_ERROR
;
if
(
geometry
==
RT_NULL
)
return
-
RT_ERROR
;
if
(
dev
->
user_data
==
RT_NULL
)
return
-
RT_ERROR
;
if
(
dev
->
user_data
==
RT_NULL
)
return
-
RT_ERROR
;
geometry
->
bytes_per_sector
=
((
SDCFG
*
)
dev
->
user_data
)
->
sectorsize
;
geometry
->
bytes_per_sector
=
((
SDCFG
*
)
dev
->
user_data
)
->
sectorsize
;
geometry
->
block_size
=
((
SDCFG
*
)
dev
->
user_data
)
->
blocksize
;
geometry
->
block_size
=
((
SDCFG
*
)
dev
->
user_data
)
->
blocksize
;
geometry
->
sector_count
=
((
SDCFG
*
)
dev
->
user_data
)
->
sectorcnt
;
geometry
->
sector_count
=
((
SDCFG
*
)
dev
->
user_data
)
->
sectorcnt
;
...
...
bsp/lpc176x/drivers/spi.c
浏览文件 @
958d9405
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include "LPC17xx.h"
/* LPC17xx definitions */
#include "LPC17xx.h"
/* LPC17xx definitions */
#include "spi.h"
#include "spi.h"
...
@@ -21,98 +30,98 @@ static uint8_t LPC17xx_SPI_SendRecvByte (uint8_t byte_s);
...
@@ -21,98 +30,98 @@ static uint8_t LPC17xx_SPI_SendRecvByte (uint8_t byte_s);
/* Initialize the SSP0, SSP0_PCLK=CCLK=72MHz */
/* Initialize the SSP0, SSP0_PCLK=CCLK=72MHz */
void
LPC17xx_SPI_Init
(
void
)
void
LPC17xx_SPI_Init
(
void
)
{
{
uint32_t
dummy
;
uint32_t
dummy
;
dummy
=
dummy
;
// avoid warning
dummy
=
dummy
;
// avoid warning
#if 0
#if 0
/* Initialize and enable the SSP0 Interface module. */
/* Initialize and enable the SSP0 Interface module. */
LPC_SC->PCONP |= (1 << 21); /* Enable power to SSPI0 block */
LPC_SC->PCONP |= (1 << 21); /* Enable power to SSPI0 block */
/* SSEL is GPIO, output set to high. */
/* SSEL is GPIO, output set to high. */
LPC_GPIO0->FIODIR |= (1<<16); /* P0.16 is output */
LPC_GPIO0->FIODIR |= (1<<16); /* P0.16 is output */
LPC_PINCON->PINSEL1 &= ~(3<<0); /* P0.16 SSEL (used as GPIO) */
LPC_PINCON->PINSEL1 &= ~(3<<0); /* P0.16 SSEL (used as GPIO) */
LPC17xx_SPI_DeSelect ();
/* set P0.16 high (SSEL inactiv) */
LPC17xx_SPI_DeSelect ();
/* set P0.16 high (SSEL inactiv) */
/* SCK, MISO, MOSI are SSP pins. */
/* SCK, MISO, MOSI are SSP pins. */
LPC_PINCON->PINSEL0 &= ~(3UL<<30); /* P0.15 cleared */
LPC_PINCON->PINSEL0 &= ~(3UL<<30); /* P0.15 cleared */
LPC_PINCON->PINSEL0 |= (2UL<<30); /* P0.15 SCK0 */
LPC_PINCON->PINSEL0 |= (2UL<<30); /* P0.15 SCK0 */
LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4)); /* P0.17, P0.18 cleared */
LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4)); /* P0.17, P0.18 cleared */
LPC_PINCON->PINSEL1 |= ((2<<2) | (2<<4)); /* P0.17 MISO0, P0.18 MOSI0 */
LPC_PINCON->PINSEL1 |= ((2<<2) | (2<<4)); /* P0.17 MISO0, P0.18 MOSI0 */
#else
#else
LPC_SC
->
PCONP
|=
(
1
<<
21
);
/* Enable power to SSPI0 block */
LPC_SC
->
PCONP
|=
(
1
<<
21
);
/* Enable power to SSPI0 block */
/* SSEL is GPIO, output set to high. */
/* SSEL is GPIO, output set to high. */
LPC_GPIO1
->
FIODIR
|=
(
1
<<
21
);
/* P1.21 is output */
LPC_GPIO1
->
FIODIR
|=
(
1
<<
21
);
/* P1.21 is output */
LPC_GPIO1
->
FIOPIN
|=
(
1
<<
21
);
/* set P1.21 high (SSEL inact.)*/
LPC_GPIO1
->
FIOPIN
|=
(
1
<<
21
);
/* set P1.21 high (SSEL inact.)*/
LPC_PINCON
->
PINSEL3
&=
~
(
0
<<
10
);
/* P1.21 SSEL (used as GPIO) */
LPC_PINCON
->
PINSEL3
&=
~
(
0
<<
10
);
/* P1.21 SSEL (used as GPIO) */
/* P3.26 is SD Card Power Supply Enable Pin */
/* P3.26 is SD Card Power Supply Enable Pin */
LPC_GPIO3
->
FIODIR
|=
(
1
<<
26
);
/* P3.26 is output */
LPC_GPIO3
->
FIODIR
|=
(
1
<<
26
);
/* P3.26 is output */
LPC_GPIO3
->
FIOPIN
&=
~
(
1
<<
26
);
/* set P3.26 low(enable power) */
LPC_GPIO3
->
FIOPIN
&=
~
(
1
<<
26
);
/* set P3.26 low(enable power) */
/* SCK, MISO, MOSI are SSP pins. */
/* SCK, MISO, MOSI are SSP pins. */
LPC_PINCON
->
PINSEL3
&=
~
(
3UL
<<
8
);
/* P1.20 cleared */
LPC_PINCON
->
PINSEL3
&=
~
(
3UL
<<
8
);
/* P1.20 cleared */
LPC_PINCON
->
PINSEL3
|=
(
3UL
<<
8
);
/* P1.20 SCK0 */
LPC_PINCON
->
PINSEL3
|=
(
3UL
<<
8
);
/* P1.20 SCK0 */
LPC_PINCON
->
PINSEL3
&=
~
((
3
<<
14
)
|
(
3
<<
16
));
/* P1.23, P1.24 cleared */
LPC_PINCON
->
PINSEL3
&=
~
((
3
<<
14
)
|
(
3
<<
16
));
/* P1.23, P1.24 cleared */
LPC_PINCON
->
PINSEL3
|=
((
3
<<
14
)
|
(
3
<<
16
));
/* P1.23 MISO0, P1.24 MOSI0 */
LPC_PINCON
->
PINSEL3
|=
((
3
<<
14
)
|
(
3
<<
16
));
/* P1.23 MISO0, P1.24 MOSI0 */
#endif
#endif
/* PCLK_SSP0=CCLK */
/* PCLK_SSP0=CCLK */
LPC_SC
->
PCLKSEL1
&=
~
(
3
<<
10
);
/* PCLKSP0 = CCLK/4 (18MHz) */
LPC_SC
->
PCLKSEL1
&=
~
(
3
<<
10
);
/* PCLKSP0 = CCLK/4 (18MHz) */
LPC_SC
->
PCLKSEL1
|=
(
1
<<
10
);
/* PCLKSP0 = CCLK (72MHz) */
LPC_SC
->
PCLKSEL1
|=
(
1
<<
10
);
/* PCLKSP0 = CCLK (72MHz) */
LPC_SSP0
->
CR0
=
0x0007
;
/* 8Bit, CPOL=0, CPHA=0 */
LPC_SSP0
->
CR0
=
0x0007
;
/* 8Bit, CPOL=0, CPHA=0 */
LPC_SSP0
->
CR1
=
0x0002
;
/* SSP0 enable, master */
LPC_SSP0
->
CR1
=
0x0002
;
/* SSP0 enable, master */
LPC17xx_SPI_SetSpeed
(
SPI_SPEED_400kHz
);
LPC17xx_SPI_SetSpeed
(
SPI_SPEED_400kHz
);
/* wait for busy gone */
/* wait for busy gone */
while
(
LPC_SSP0
->
SR
&
(
1
<<
SSPSR_BSY
)
);
while
(
LPC_SSP0
->
SR
&
(
1
<<
SSPSR_BSY
)
);
/* drain SPI RX FIFO */
/* drain SPI RX FIFO */
while
(
LPC_SSP0
->
SR
&
(
1
<<
SSPSR_RNE
)
)
while
(
LPC_SSP0
->
SR
&
(
1
<<
SSPSR_RNE
)
)
{
{
dummy
=
LPC_SSP0
->
DR
;
dummy
=
LPC_SSP0
->
DR
;
}
}
}
}
/* Close SSP0 */
/* Close SSP0 */
void
LPC17xx_SPI_DeInit
(
void
)
void
LPC17xx_SPI_DeInit
(
void
)
{
{
// disable SPI
// disable SPI
LPC_SSP0
->
CR1
=
0
;
LPC_SSP0
->
CR1
=
0
;
#if 0
#if 0
// Pins to GPIO
// Pins to GPIO
LPC_PINCON->PINSEL0 &= ~(3UL<<30);
LPC_PINCON->PINSEL0 &= ~(3UL<<30);
LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4));
LPC_PINCON->PINSEL1 &= ~((3<<2) | (3<<4));
#else
#else
LPC_PINCON
->
PINSEL3
&=
~
(
3UL
<<
8
);
/* P1.20 cleared */
LPC_PINCON
->
PINSEL3
&=
~
(
3UL
<<
8
);
/* P1.20 cleared */
LPC_PINCON
->
PINSEL3
&=
~
((
3
<<
14
)
|
(
3
<<
16
));
/* P1.23, P1.24 cleared */
LPC_PINCON
->
PINSEL3
&=
~
((
3
<<
14
)
|
(
3
<<
16
));
/* P1.23, P1.24 cleared */
#endif
#endif
// disable SSP power
// disable SSP power
LPC_SC
->
PCONP
&=
~
(
1
<<
21
);
LPC_SC
->
PCONP
&=
~
(
1
<<
21
);
}
}
/* Set a SSP0 clock speed to desired value. */
/* Set a SSP0 clock speed to desired value. */
void
LPC17xx_SPI_SetSpeed
(
uint8_t
speed
)
void
LPC17xx_SPI_SetSpeed
(
uint8_t
speed
)
{
{
speed
&=
0xFE
;
speed
&=
0xFE
;
if
(
speed
<
2
)
{
if
(
speed
<
2
)
{
speed
=
2
;
speed
=
2
;
}
}
LPC_SSP0
->
CPSR
=
speed
;
LPC_SSP0
->
CPSR
=
speed
;
}
}
/* SSEL: low */
/* SSEL: low */
void
LPC17xx_SPI_Select
()
void
LPC17xx_SPI_Select
()
{
{
#if 0
#if 0
LPC_GPIO0->FIOPIN &= ~(1<<16);
LPC_GPIO0->FIOPIN &= ~(1<<16);
#else
#else
LPC_GPIO1
->
FIOPIN
&=
~
(
1
<<
21
);
/* SSEL is GPIO, set to high. */
LPC_GPIO1
->
FIOPIN
&=
~
(
1
<<
21
);
/* SSEL is GPIO, set to high. */
#endif
#endif
}
}
...
@@ -120,41 +129,41 @@ void LPC17xx_SPI_Select ()
...
@@ -120,41 +129,41 @@ void LPC17xx_SPI_Select ()
void
LPC17xx_SPI_DeSelect
()
void
LPC17xx_SPI_DeSelect
()
{
{
#if 0
#if 0
LPC_GPIO0->FIOPIN |= (1<<16);
LPC_GPIO0->FIOPIN |= (1<<16);
#else
#else
LPC_GPIO1
->
FIOPIN
|=
(
1
<<
21
);
/* SSEL is GPIO, set to high. */
LPC_GPIO1
->
FIOPIN
|=
(
1
<<
21
);
/* SSEL is GPIO, set to high. */
#endif
#endif
}
}
/* Send one byte then recv one byte of response. */
/* Send one byte then recv one byte of response. */
static
uint8_t
LPC17xx_SPI_SendRecvByte
(
uint8_t
byte_s
)
static
uint8_t
LPC17xx_SPI_SendRecvByte
(
uint8_t
byte_s
)
{
{
uint8_t
byte_r
;
uint8_t
byte_r
;
LPC_SSP0
->
DR
=
byte_s
;
LPC_SSP0
->
DR
=
byte_s
;
while
(
LPC_SSP0
->
SR
&
(
1
<<
SSPSR_BSY
)
/*BSY*/
);
/* Wait for transfer to finish */
while
(
LPC_SSP0
->
SR
&
(
1
<<
SSPSR_BSY
)
/*BSY*/
);
/* Wait for transfer to finish */
byte_r
=
LPC_SSP0
->
DR
;
byte_r
=
LPC_SSP0
->
DR
;
return
byte_r
;
/* Return received value */
return
byte_r
;
/* Return received value */
}
}
/* Send one byte */
/* Send one byte */
void
LPC17xx_SPI_SendByte
(
uint8_t
data
)
void
LPC17xx_SPI_SendByte
(
uint8_t
data
)
{
{
LPC17xx_SPI_SendRecvByte
(
data
);
LPC17xx_SPI_SendRecvByte
(
data
);
}
}
/* Recv one byte */
/* Recv one byte */
uint8_t
LPC17xx_SPI_RecvByte
()
uint8_t
LPC17xx_SPI_RecvByte
()
{
{
return
LPC17xx_SPI_SendRecvByte
(
0xFF
);
return
LPC17xx_SPI_SendRecvByte
(
0xFF
);
}
}
/* Release SSP0 */
/* Release SSP0 */
void
LPC17xx_SPI_Release
(
void
)
void
LPC17xx_SPI_Release
(
void
)
{
{
LPC17xx_SPI_DeSelect
();
LPC17xx_SPI_DeSelect
();
LPC17xx_SPI_RecvByte
();
LPC17xx_SPI_RecvByte
();
}
}
...
@@ -163,66 +172,66 @@ void LPC17xx_SPI_Release (void)
...
@@ -163,66 +172,66 @@ void LPC17xx_SPI_Release (void)
#define FIFO_ELEM 8
#define FIFO_ELEM 8
/* Receive btr (must be multiple of 4) bytes of data and store in buff. */
/* Receive btr (must be multiple of 4) bytes of data and store in buff. */
void
LPC17xx_SPI_RecvBlock_FIFO
(
uint8_t
*
buff
,
uint32_t
btr
)
void
LPC17xx_SPI_RecvBlock_FIFO
(
uint8_t
*
buff
,
uint32_t
btr
)
{
{
uint32_t
hwtr
,
startcnt
,
i
,
rec
;
uint32_t
hwtr
,
startcnt
,
i
,
rec
;
hwtr
=
btr
/
2
;
/* byte number in unit of short */
hwtr
=
btr
/
2
;
/* byte number in unit of short */
if
(
btr
<
FIFO_ELEM
)
{
if
(
btr
<
FIFO_ELEM
)
{
startcnt
=
hwtr
;
startcnt
=
hwtr
;
}
else
{
}
else
{
startcnt
=
FIFO_ELEM
;
startcnt
=
FIFO_ELEM
;
}
}
LPC_SSP0
->
CR0
|=
0x0f
;
/* DSS to 16 bit */
LPC_SSP0
->
CR0
|=
0x0f
;
/* DSS to 16 bit */
for
(
i
=
startcnt
;
i
;
i
--
)
{
for
(
i
=
startcnt
;
i
;
i
--
)
{
LPC_SSP0
->
DR
=
0xffff
;
/* fill TX FIFO, prepare clk for receive */
LPC_SSP0
->
DR
=
0xffff
;
/* fill TX FIFO, prepare clk for receive */
}
}
do
{
do
{
while
(
!
(
LPC_SSP0
->
SR
&
(
1
<<
SSPSR_RNE
)
)
)
{
while
(
!
(
LPC_SSP0
->
SR
&
(
1
<<
SSPSR_RNE
)
)
)
{
// wait for data in RX FIFO (RNE set)
// wait for data in RX FIFO (RNE set)
}
}
rec
=
LPC_SSP0
->
DR
;
rec
=
LPC_SSP0
->
DR
;
if
(
i
<
(
hwtr
-
startcnt
)
)
{
if
(
i
<
(
hwtr
-
startcnt
)
)
{
LPC_SSP0
->
DR
=
0xffff
;
/* fill TX FIFO, prepare clk for receive */
LPC_SSP0
->
DR
=
0xffff
;
/* fill TX FIFO, prepare clk for receive */
}
}
*
buff
++
=
(
uint8_t
)(
rec
>>
8
);
*
buff
++
=
(
uint8_t
)(
rec
>>
8
);
*
buff
++
=
(
uint8_t
)(
rec
);
*
buff
++
=
(
uint8_t
)(
rec
);
i
++
;
i
++
;
}
while
(
i
<
hwtr
);
}
while
(
i
<
hwtr
);
LPC_SSP0
->
CR0
&=
~
0x08
;
/* DSS to 8 bit */
LPC_SSP0
->
CR0
&=
~
0x08
;
/* DSS to 8 bit */
}
}
/* Send 512 bytes of data block (stored in buff). */
/* Send 512 bytes of data block (stored in buff). */
void
LPC17xx_SPI_SendBlock_FIFO
(
const
uint8_t
*
buff
)
void
LPC17xx_SPI_SendBlock_FIFO
(
const
uint8_t
*
buff
)
{
{
uint32_t
cnt
;
uint32_t
cnt
;
uint16_t
data
;
uint16_t
data
;
LPC_SSP0
->
CR0
|=
0x0f
;
/* DSS to 16 bit */
LPC_SSP0
->
CR0
|=
0x0f
;
/* DSS to 16 bit */
/* fill the FIFO unless it is full */
/* fill the FIFO unless it is full */
for
(
cnt
=
0
;
cnt
<
(
512
/
2
);
cnt
++
)
for
(
cnt
=
0
;
cnt
<
(
512
/
2
);
cnt
++
)
{
{
/* wait for TX FIFO not full (TNF) */
/* wait for TX FIFO not full (TNF) */
while
(
!
(
LPC_SSP0
->
SR
&
(
1
<<
SSPSR_TNF
)
)
);
while
(
!
(
LPC_SSP0
->
SR
&
(
1
<<
SSPSR_TNF
)
)
);
data
=
(
*
buff
++
)
<<
8
;
data
=
(
*
buff
++
)
<<
8
;
data
|=
*
buff
++
;
data
|=
*
buff
++
;
LPC_SSP0
->
DR
=
data
;
LPC_SSP0
->
DR
=
data
;
}
}
/* wait for BSY gone */
/* wait for BSY gone */
while
(
LPC_SSP0
->
SR
&
(
1
<<
SSPSR_BSY
)
);
while
(
LPC_SSP0
->
SR
&
(
1
<<
SSPSR_BSY
)
);
/* drain receive FIFO */
/* drain receive FIFO */
while
(
LPC_SSP0
->
SR
&
(
1
<<
SSPSR_RNE
)
)
{
while
(
LPC_SSP0
->
SR
&
(
1
<<
SSPSR_RNE
)
)
{
data
=
LPC_SSP0
->
DR
;
data
=
LPC_SSP0
->
DR
;
}
}
LPC_SSP0
->
CR0
&=
~
0x08
;
/* DSS to 8 bit */
LPC_SSP0
->
CR0
&=
~
0x08
;
/* DSS to 8 bit */
}
}
#endif
/* USE_FIFO */
#endif
/* USE_FIFO */
bsp/lpc176x/drivers/spi.h
浏览文件 @
958d9405
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef __LPC17XX_SPI_H__
#ifndef __LPC17XX_SPI_H__
#define __LPC17XX_SPI_H__
#define __LPC17XX_SPI_H__
#include <stdint.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdbool.h>
// if not use FIFO,
R: 600kB/s, W: 500kB/s
// if not use FIFO,
R: 600kB/s, W: 500kB/s
// if use FIFO,
R: 1.2MB/s, W: 800kB/s
// if use FIFO,
R: 1.2MB/s, W: 800kB/s
#define USE_FIFO 1
#define USE_FIFO 1
/* bit-frequency = PCLK / (CPSDVSR * [SCR+1]), here SCR=0, PCLK=72MHz, must be even
*/
/* bit-frequency = PCLK / (CPSDVSR * [SCR+1]), here SCR=0, PCLK=72MHz, must be even
*/
#define SPI_SPEED_20MHz
4
/* => 18MHz */
#define SPI_SPEED_20MHz
4
/* => 18MHz */
#define SPI_SPEED_25MHz
4
/* => 18MHz */
#define SPI_SPEED_25MHz
4
/* => 18MHz */
#define SPI_SPEED_400kHz 180
/* => 400kHz */
#define SPI_SPEED_400kHz 180
/* => 400kHz */
/* external functions */
/* external functions */
void
LPC17xx_SPI_Init
(
void
);
void
LPC17xx_SPI_Init
(
void
);
...
@@ -24,8 +33,8 @@ void LPC17xx_SPI_SendByte (uint8_t data);
...
@@ -24,8 +33,8 @@ void LPC17xx_SPI_SendByte (uint8_t data);
uint8_t
LPC17xx_SPI_RecvByte
(
void
);
uint8_t
LPC17xx_SPI_RecvByte
(
void
);
#if USE_FIFO
#if USE_FIFO
void
LPC17xx_SPI_RecvBlock_FIFO
(
uint8_t
*
buff
,
uint32_t
btr
);
void
LPC17xx_SPI_RecvBlock_FIFO
(
uint8_t
*
buff
,
uint32_t
btr
);
void
LPC17xx_SPI_SendBlock_FIFO
(
const
uint8_t
*
buff
);
void
LPC17xx_SPI_SendBlock_FIFO
(
const
uint8_t
*
buff
);
#endif
#endif
#endif
// __LPC17XX_SPI_H__
#endif
// __LPC17XX_SPI_H__
bsp/lpc176x/drivers/uart.c
浏览文件 @
958d9405
/*
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-License-Identifier: Apache-2.0
*
*
...
@@ -56,8 +56,8 @@ void UART0_IRQHandler(void)
...
@@ -56,8 +56,8 @@ void UART0_IRQHandler(void)
{
{
rt_ubase_t
level
,
iir
;
rt_ubase_t
level
,
iir
;
struct
rt_uart_lpc
*
uart
=
&
uart_device
;
struct
rt_uart_lpc
*
uart
=
&
uart_device
;
/* enter interrupt */
/* enter interrupt */
rt_interrupt_enter
();
rt_interrupt_enter
();
/* read IIR and clear it */
/* read IIR and clear it */
iir
=
LPC_UART
->
IIR
;
iir
=
LPC_UART
->
IIR
;
...
@@ -91,8 +91,8 @@ void UART0_IRQHandler(void)
...
@@ -91,8 +91,8 @@ void UART0_IRQHandler(void)
{
{
iir
=
LPC_UART
->
LSR
;
//oe pe fe oe read for clear interrupt
iir
=
LPC_UART
->
LSR
;
//oe pe fe oe read for clear interrupt
}
}
/* leave interrupt */
/* leave interrupt */
rt_interrupt_leave
();
rt_interrupt_leave
();
return
;
return
;
}
}
...
...
bsp/lpc176x/rtconfig.h
浏览文件 @
958d9405
...
@@ -4,17 +4,17 @@
...
@@ -4,17 +4,17 @@
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
// <integer name="RT_NAME_MAX" description="Maximal size of kernel object name length" default="6" />
#define RT_NAME_MAX
6
#define RT_NAME_MAX
6
// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
// <integer name="RT_ALIGN_SIZE" description="Alignment size for CPU architecture data access" default="4" />
#define RT_ALIGN_SIZE
4
#define RT_ALIGN_SIZE
4
// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
// <integer name="RT_THREAD_PRIORITY_MAX" description="Maximal level of thread priority" default="32">
// <item description="8">8</item>
// <item description="8">8</item>
// <item description="32">32</item>
// <item description="32">32</item>
// <item description="256">256</item>
// <item description="256">256</item>
// </integer>
// </integer>
#define RT_THREAD_PRIORITY_MAX
32
#define RT_THREAD_PRIORITY_MAX
32
// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" />
// <integer name="RT_TICK_PER_SECOND" description="OS tick per second" default="100" />
#define RT_TICK_PER_SECOND
100
#define RT_TICK_PER_SECOND
100
// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
// <section name="RT_DEBUG" description="Kernel Debug Configuration" default="true" >
#define RT_DEBUG
#define RT_DEBUG
#define RT_DEBUG_COLOR
#define RT_DEBUG_COLOR
...
@@ -29,11 +29,11 @@
...
@@ -29,11 +29,11 @@
// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
// <section name="RT_USING_TIMER_SOFT" description="Using software timer which will start a thread to handle soft-timer" default="true" >
// #define RT_USING_TIMER_SOFT
// #define RT_USING_TIMER_SOFT
// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
// <integer name="RT_TIMER_THREAD_PRIO" description="The priority level of timer thread" default="4" />
#define RT_TIMER_THREAD_PRIO
4
#define RT_TIMER_THREAD_PRIO
4
// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
// <integer name="RT_TIMER_THREAD_STACK_SIZE" description="The stack size of timer thread" default="512" />
#define RT_TIMER_THREAD_STACK_SIZE
512
#define RT_TIMER_THREAD_STACK_SIZE
512
// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
// <integer name="RT_TIMER_TICK_PER_SECOND" description="The soft-timer tick per second" default="10" />
#define RT_TIMER_TICK_PER_SECOND
10
#define RT_TIMER_TICK_PER_SECOND
10
// </section>
// </section>
// <section name="IPC" description="Inter-Thread communication" default="always" >
// <section name="IPC" description="Inter-Thread communication" default="always" >
...
@@ -67,15 +67,15 @@
...
@@ -67,15 +67,15 @@
// <bool name="RT_USING_UART0" description="Using UART0" default="true" />
// <bool name="RT_USING_UART0" description="Using UART0" default="true" />
#define RT_USING_UART0
#define RT_USING_UART0
// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
// <integer name="RT_UART_RX_BUFFER_SIZE" description="The buffer size for UART reception" default="64" />
#define RT_UART_RX_BUFFER_SIZE
64
#define RT_UART_RX_BUFFER_SIZE
64
// </section>
// </section>
// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
// <section name="RT_USING_CONSOLE" description="Using console" default="true" >
#define RT_USING_CONSOLE
#define RT_USING_CONSOLE
// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
// <integer name="RT_CONSOLEBUF_SIZE" description="The buffer size for console output" default="128" />
#define RT_CONSOLEBUF_SIZE
128
#define RT_CONSOLEBUF_SIZE
128
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
#define RT_CONSOLE_DEVICE_NAME
"uart0"
#define RT_CONSOLE_DEVICE_NAME
"uart0"
// </section>
// </section>
// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
// <bool name="RT_USING_COMPONENTS_INIT" description="Using RT-Thread components initialization" default="true" />
...
@@ -87,7 +87,7 @@
...
@@ -87,7 +87,7 @@
// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
// <bool name="FINSH_USING_DESCRIPTION" description="Keeping description in symbol table" default="true" />
#define FINSH_USING_DESCRIPTION
#define FINSH_USING_DESCRIPTION
// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
// <integer name="FINSH_THREAD_STACK_SIZE" description="The stack size for finsh thread" default="4096" />
#define FINSH_THREAD_STACK_SIZE
4096
#define FINSH_THREAD_STACK_SIZE
4096
// </section>
// </section>
// <section name="LIBC" description="C Runtime library setting" default="always" >
// <section name="LIBC" description="C Runtime library setting" default="always" >
...
@@ -102,16 +102,16 @@
...
@@ -102,16 +102,16 @@
// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
// <bool name="DFS_USING_WORKDIR" description="Using working directory" default="true" />
#define DFS_USING_WORKDIR
#define DFS_USING_WORKDIR
// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
// <integer name="DFS_FILESYSTEMS_MAX" description="The maximal number of mounted file system" default="4" />
#define DFS_FILESYSTEMS_MAX
2
#define DFS_FILESYSTEMS_MAX
2
// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
// <integer name="DFS_FD_MAX" description="The maximal number of opened files" default="4" />
#define DFS_FD_MAX
4
#define DFS_FD_MAX
4
// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
// <bool name="RT_USING_DFS_ELMFAT" description="Using ELM FatFs" default="true" />
#define RT_USING_DFS_ELMFAT
#define RT_USING_DFS_ELMFAT
// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
// <integer name="RT_DFS_ELM_USE_LFN" description="Support long file name" default="0">
// <item description="LFN1">1</item>
// <item description="LFN1">1</item>
// <item description="LFN1">2</item>
// <item description="LFN1">2</item>
// </integer>
// </integer>
#define RT_DFS_ELM_USE_LFN
1
#define RT_DFS_ELM_USE_LFN
1
// <integer name="RT_DFS_ELM_CODE_PAGE" description="specifies the OEM code page to be used on the target system" default="936">
// <integer name="RT_DFS_ELM_CODE_PAGE" description="specifies the OEM code page to be used on the target system" default="936">
// <item description="Japanese Shift-JIS (DBCS, OEM, Windows)">932</item>
// <item description="Japanese Shift-JIS (DBCS, OEM, Windows)">932</item>
// <item description="Simplified Chinese GBK (DBCS, OEM, Windows)">936</item>
// <item description="Simplified Chinese GBK (DBCS, OEM, Windows)">936</item>
...
@@ -142,7 +142,7 @@
...
@@ -142,7 +142,7 @@
// </integer>
// </integer>
#define RT_DFS_ELM_CODE_PAGE 437
#define RT_DFS_ELM_CODE_PAGE 437
// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="255" />
// <integer name="RT_DFS_ELM_MAX_LFN" description="Maximal size of file name length" default="255" />
#define RT_DFS_ELM_MAX_LFN
64
#define RT_DFS_ELM_MAX_LFN
64
// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
// <bool name="RT_USING_DFS_YAFFS2" description="Using YAFFS2" default="false" />
// #define RT_USING_DFS_YAFFS2
// #define RT_USING_DFS_YAFFS2
// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
// <bool name="RT_USING_DFS_UFFS" description="Using UFFS" default="false" />
...
@@ -152,7 +152,7 @@
...
@@ -152,7 +152,7 @@
// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
// <bool name="RT_USING_DFS_NFS" description="Using NFS v3 client file system" default="false" />
// #define RT_USING_DFS_NFS
// #define RT_USING_DFS_NFS
// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
// <string name="RT_NFS_HOST_EXPORT" description="NFSv3 host export" default="192.168.1.5:/" />
#define RT_NFS_HOST_EXPORT
"192.168.1.5:/"
#define RT_NFS_HOST_EXPORT
"192.168.1.5:/"
// </section>
// </section>
// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
// <section name="RT_USING_LWIP" description="lwip, a lightweight TCP/IP protocol stack" default="true" >
...
@@ -168,29 +168,29 @@
...
@@ -168,29 +168,29 @@
// <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
// <bool name="RT_LWIP_DNS" description="Enable DNS protocol" default="true" />
#define RT_LWIP_DNS
#define RT_LWIP_DNS
// <integer name="RT_LWIP_PBUF_NUM" description="Maximal number of buffers in the pbuf pool" default="4" />
// <integer name="RT_LWIP_PBUF_NUM" description="Maximal number of buffers in the pbuf pool" default="4" />
#define RT_LWIP_PBUF_NUM
4
#define RT_LWIP_PBUF_NUM
4
// <integer name="RT_LWIP_TCP_PCB_NUM" description="Maximal number of simultaneously active TCP connections" default="5" />
// <integer name="RT_LWIP_TCP_PCB_NUM" description="Maximal number of simultaneously active TCP connections" default="5" />
#define RT_LWIP_TCP_PCB_NUM
3
#define RT_LWIP_TCP_PCB_NUM
3
// <integer name="RT_LWIP_TCP_SND_BUF" description="TCP sender buffer size" default="8192" />
// <integer name="RT_LWIP_TCP_SND_BUF" description="TCP sender buffer size" default="8192" />
#define RT_LWIP_TCP_SND_BUF
(2 * TCP_MSS)
#define RT_LWIP_TCP_SND_BUF
(2 * TCP_MSS)
// <integer name="RT_LWIP_TCP_WND" description="TCP receive window" default="8192" />
// <integer name="RT_LWIP_TCP_WND" description="TCP receive window" default="8192" />
#define RT_LWIP_TCP_WND
2048
#define RT_LWIP_TCP_WND
2048
// <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
// <bool name="RT_LWIP_SNMP" description="Enable SNMP protocol" default="false" />
// #define RT_LWIP_SNMP
// #define RT_LWIP_SNMP
// <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
// <bool name="RT_LWIP_DHCP" description="Enable DHCP client to get IP address" default="false" />
// #define RT_LWIP_DHCP
// #define RT_LWIP_DHCP
// <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
// <integer name="RT_LWIP_TCPTHREAD_PRIORITY" description="the thread priority of TCP thread" default="128" />
#define RT_LWIP_TCPTHREAD_PRIORITY
12
#define RT_LWIP_TCPTHREAD_PRIORITY
12
// <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
// <integer name="RT_LWIP_TCPTHREAD_MBOX_SIZE" description="the mail box size of TCP thread to wait for" default="32" />
#define RT_LWIP_TCPTHREAD_MBOX_SIZE
8
#define RT_LWIP_TCPTHREAD_MBOX_SIZE
8
// <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
// <integer name="RT_LWIP_TCPTHREAD_STACKSIZE" description="the thread stack size of TCP thread" default="4096" />
#define RT_LWIP_TCPTHREAD_STACKSIZE
4096
#define RT_LWIP_TCPTHREAD_STACKSIZE
4096
// <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
// <integer name="RT_LWIP_ETHTHREAD_PRIORITY" description="the thread priority of ethnetif thread" default="144" />
#define RT_LWIP_ETHTHREAD_PRIORITY
14
#define RT_LWIP_ETHTHREAD_PRIORITY
14
// <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
// <integer name="RT_LWIP_ETHTHREAD_MBOX_SIZE" description="the mail box size of ethnetif thread to wait for" default="8" />
#define RT_LWIP_ETHTHREAD_MBOX_SIZE
8
#define RT_LWIP_ETHTHREAD_MBOX_SIZE
8
// <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
// <integer name="RT_LWIP_ETHTHREAD_STACKSIZE" description="the stack size of ethnetif thread" default="512" />
#define RT_LWIP_ETHTHREAD_STACKSIZE
512
#define RT_LWIP_ETHTHREAD_STACKSIZE
512
// <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
// <ipaddr name="RT_LWIP_IPADDR" description="IP address of device" default="192.168.1.30" />
#define RT_LWIP_IPADDR "192.168.1.30"
#define RT_LWIP_IPADDR "192.168.1.30"
// <ipaddr name="RT_LWIP_GWADDR" description="Gateway address of device" default="192.168.1.1" />
// <ipaddr name="RT_LWIP_GWADDR" description="Gateway address of device" default="192.168.1.1" />
...
...
bsp/lpc178x/applications/application.c
浏览文件 @
958d9405
/*
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-License-Identifier: Apache-2.0
*
*
...
@@ -75,33 +75,33 @@ void rt_init_thread_entry(void *parameter)
...
@@ -75,33 +75,33 @@ void rt_init_thread_entry(void *parameter)
#ifdef RT_USING_RTGUI
#ifdef RT_USING_RTGUI
{
{
extern
void
rtgui_system_server_init
(
void
);
extern
void
rtgui_system_server_init
(
void
);
extern
void
application_init
(
void
);
extern
void
application_init
(
void
);
rt_device_t
lcd
;
rt_device_t
lcd
;
/* init lcd */
/* init lcd */
rt_hw_lcd_init
();
rt_hw_lcd_init
();
/* find lcd device */
/* find lcd device */
lcd
=
rt_device_find
(
"lcd"
);
lcd
=
rt_device_find
(
"lcd"
);
if
(
lcd
!=
RT_NULL
)
if
(
lcd
!=
RT_NULL
)
{
{
/* set lcd device as rtgui graphic driver */
/* set lcd device as rtgui graphic driver */
rtgui_graphic_set_device
(
lcd
);
rtgui_graphic_set_device
(
lcd
);
/* init rtgui system server */
/* init rtgui system server */
rtgui_system_server_init
();
rtgui_system_server_init
();
/* startup rtgui in demo of RT-Thread/GUI examples */
/* startup rtgui in demo of RT-Thread/GUI examples */
application_init
();
application_init
();
}
}
}
}
#endif
#endif
#ifdef RT_USING_FINSH
#ifdef RT_USING_FINSH
/* initialize finsh */
/* initialize finsh */
finsh_system_init
();
finsh_system_init
();
#endif
#endif
}
}
...
@@ -143,22 +143,22 @@ static void rt_thread_entry_led(void* parameter)
...
@@ -143,22 +143,22 @@ static void rt_thread_entry_led(void* parameter)
int
rt_application_init
(
void
)
int
rt_application_init
(
void
)
{
{
rt_thread_t
tid
;
rt_thread_t
tid
;
rt_thread_init
(
&
thread_led
,
rt_thread_init
(
&
thread_led
,
"led"
,
"led"
,
rt_thread_entry_led
,
rt_thread_entry_led
,
RT_NULL
,
RT_NULL
,
&
thread_led_stack
[
0
],
&
thread_led_stack
[
0
],
sizeof
(
thread_led_stack
),
11
,
5
);
sizeof
(
thread_led_stack
),
11
,
5
);
rt_thread_startup
(
&
thread_led
);
rt_thread_startup
(
&
thread_led
);
tid
=
rt_thread_create
(
"init"
,
tid
=
rt_thread_create
(
"init"
,
rt_init_thread_entry
,
RT_NULL
,
rt_init_thread_entry
,
RT_NULL
,
2048
,
RT_THREAD_PRIORITY_MAX
/
3
,
20
);
2048
,
RT_THREAD_PRIORITY_MAX
/
3
,
20
);
if
(
tid
!=
RT_NULL
)
rt_thread_startup
(
tid
);
if
(
tid
!=
RT_NULL
)
rt_thread_startup
(
tid
);
return
0
;
return
0
;
}
}
#if defined(RT_USING_RTGUI) && defined(RT_USING_FINSH)
#if defined(RT_USING_RTGUI) && defined(RT_USING_FINSH)
...
@@ -170,20 +170,20 @@ int rt_application_init(void)
...
@@ -170,20 +170,20 @@ int rt_application_init(void)
void
key
(
rt_uint32_t
key
)
void
key
(
rt_uint32_t
key
)
{
{
struct
rtgui_event_kbd
ekbd
;
struct
rtgui_event_kbd
ekbd
;
RTGUI_EVENT_KBD_INIT
(
&
ekbd
);
RTGUI_EVENT_KBD_INIT
(
&
ekbd
);
ekbd
.
mod
=
RTGUI_KMOD_NONE
;
ekbd
.
mod
=
RTGUI_KMOD_NONE
;
ekbd
.
unicode
=
0
;
ekbd
.
unicode
=
0
;
ekbd
.
key
=
key
;
ekbd
.
key
=
key
;
ekbd
.
type
=
RTGUI_KEYDOWN
;
ekbd
.
type
=
RTGUI_KEYDOWN
;
rtgui_server_post_event
((
struct
rtgui_event
*
)
&
ekbd
,
sizeof
(
ekbd
));
rtgui_server_post_event
((
struct
rtgui_event
*
)
&
ekbd
,
sizeof
(
ekbd
));
rt_thread_delay
(
2
);
rt_thread_delay
(
2
);
ekbd
.
type
=
RTGUI_KEYUP
;
ekbd
.
type
=
RTGUI_KEYUP
;
rtgui_server_post_event
((
struct
rtgui_event
*
)
&
ekbd
,
sizeof
(
ekbd
));
rtgui_server_post_event
((
struct
rtgui_event
*
)
&
ekbd
,
sizeof
(
ekbd
));
}
}
FINSH_FUNCTION_EXPORT
(
key
,
send
a
key
to
gui
server
);
FINSH_FUNCTION_EXPORT
(
key
,
send
a
key
to
gui
server
);
#endif
#endif
bsp/lpc178x/applications/startup.c
浏览文件 @
958d9405
/*
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-License-Identifier: Apache-2.0
*
*
...
@@ -37,11 +37,11 @@ extern int __bss_end;
...
@@ -37,11 +37,11 @@ extern int __bss_end;
*******************************************************************************/
*******************************************************************************/
void
assert_failed
(
u8
*
file
,
u32
line
)
void
assert_failed
(
u8
*
file
,
u32
line
)
{
{
rt_kprintf
(
"
\n\r
Wrong parameter value detected on
\r\n
"
);
rt_kprintf
(
"
\n\r
Wrong parameter value detected on
\r\n
"
);
rt_kprintf
(
" file %s
\r\n
"
,
file
);
rt_kprintf
(
" file %s
\r\n
"
,
file
);
rt_kprintf
(
" line %d
\r\n
"
,
line
);
rt_kprintf
(
" line %d
\r\n
"
,
line
);
while
(
1
)
;
while
(
1
)
;
}
}
#endif
#endif
...
@@ -50,28 +50,28 @@ void assert_failed(u8* file, u32 line)
...
@@ -50,28 +50,28 @@ void assert_failed(u8* file, u32 line)
*/
*/
void
rtthread_startup
(
void
)
void
rtthread_startup
(
void
)
{
{
/* initialize board */
/* initialize board */
rt_hw_board_init
();
rt_hw_board_init
();
/* show version */
/* show version */
rt_show_version
();
rt_show_version
();
#ifdef RT_USING_HEAP
#ifdef RT_USING_HEAP
/* initialize memory system */
/* initialize memory system */
#ifdef __CC_ARM
#ifdef __CC_ARM
rt_system_heap_init
((
void
*
)
&
Image
$$
RW_IRAM1
$$
ZI
$$
Limit
,
(
void
*
)(
0x10000000
+
1024
*
64
));
rt_system_heap_init
((
void
*
)
&
Image
$$
RW_IRAM1
$$
ZI
$$
Limit
,
(
void
*
)(
0x10000000
+
1024
*
64
));
#elif __ICCARM__
#elif __ICCARM__
rt_system_heap_init
(
__segment_end
(
"HEAP"
),
(
void
*
)(
0x10000000
+
1024
*
64
));
rt_system_heap_init
(
__segment_end
(
"HEAP"
),
(
void
*
)(
0x10000000
+
1024
*
64
));
#else
#else
rt_system_heap_init
((
void
*
)
&
__bss_end
,
(
void
*
)(
0x10000000
+
1024
*
64
));
rt_system_heap_init
((
void
*
)
&
__bss_end
,
(
void
*
)(
0x10000000
+
1024
*
64
));
#endif
#endif
#endif
#endif
/* initialize scheduler system */
/* initialize scheduler system */
rt_system_scheduler_init
();
rt_system_scheduler_init
();
/* initialize application */
/* initialize application */
rt_application_init
();
rt_application_init
();
/* initialize timer */
/* initialize timer */
rt_system_timer_init
();
rt_system_timer_init
();
...
@@ -79,23 +79,23 @@ void rtthread_startup(void)
...
@@ -79,23 +79,23 @@ void rtthread_startup(void)
/* initialize timer thread */
/* initialize timer thread */
rt_system_timer_thread_init
();
rt_system_timer_thread_init
();
/* initialize idle thread */
/* initialize idle thread */
rt_thread_idle_init
();
rt_thread_idle_init
();
/* start scheduler */
/* start scheduler */
rt_system_scheduler_start
();
rt_system_scheduler_start
();
/* never reach here */
/* never reach here */
return
;
return
;
}
}
int
main
(
void
)
int
main
(
void
)
{
{
/* disable interrupt first */
/* disable interrupt first */
rt_hw_interrupt_disable
();
rt_hw_interrupt_disable
();
/* startup RT-Thread RTOS */
/* startup RT-Thread RTOS */
rtthread_startup
();
rtthread_startup
();
return
0
;
return
0
;
}
}
bsp/lpc178x/drivers/board.c
浏览文件 @
958d9405
/*
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-License-Identifier: Apache-2.0
*
*
...
...
bsp/lpc178x/drivers/board.h
浏览文件 @
958d9405
/*
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-License-Identifier: Apache-2.0
*
*
...
@@ -31,7 +31,7 @@
...
@@ -31,7 +31,7 @@
//#define RT_USING_UART2
//#define RT_USING_UART2
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
// <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
#define RT_CONSOLE_DEVICE_NAME
"uart0"
#define RT_CONSOLE_DEVICE_NAME
"uart0"
// </RDTConfigurator>
// </RDTConfigurator>
...
...
bsp/lpc178x/drivers/drv_glcd.c
浏览文件 @
958d9405
...
@@ -37,14 +37,14 @@
...
@@ -37,14 +37,14 @@
#define C_GLCD_LINES_PER_FRAME (C_GLCD_V_SIZE + C_GLCD_V_PULSE + C_GLCD_V_FRONT_PORCH + C_GLCD_V_BACK_PORCH)
#define C_GLCD_LINES_PER_FRAME (C_GLCD_V_SIZE + C_GLCD_V_PULSE + C_GLCD_V_FRONT_PORCH + C_GLCD_V_BACK_PORCH)
#define C_GLCD_PIX_CLK (C_GLCD_CLK_PER_LINE * C_GLCD_LINES_PER_FRAME)
#define C_GLCD_PIX_CLK (C_GLCD_CLK_PER_LINE * C_GLCD_LINES_PER_FRAME)
//LPC_LCD_TypeDef
* const g_pLCD = ((LPC_LCD_TypeDef*) LPC_LCD_BASE);
//LPC_LCD_TypeDef
* const g_pLCD = ((LPC_LCD_TypeDef*) LPC_LCD_BASE);
//LPC_SC_TypeDef * const g_pSC = ((LPC_SC_TypeDef*) LPC_SC_BASE);
//LPC_SC_TypeDef * const g_pSC = ((LPC_SC_TypeDef*) LPC_SC_BASE);
#define SDRAM_BASE
0xA0000000
/* CS0 */
#define SDRAM_BASE
0xA0000000
/* CS0 */
#define SDRAM_BASE_ADDR
SDRAM_BASE
#define SDRAM_BASE_ADDR
SDRAM_BASE
#define LCD_VRAM_BASE_ADDR
((unsigned long)SDRAM_BASE_ADDR + 0x00000000)
#define LCD_VRAM_BASE_ADDR
((unsigned long)SDRAM_BASE_ADDR + 0x00000000)
#define LCD_CURSOR_BASE_ADDR
((unsigned long)0x20088800)
#define LCD_CURSOR_BASE_ADDR
((unsigned long)0x20088800)
static
pFontType_t
pCurrFont
=
NULL
;
static
pFontType_t
pCurrFont
=
NULL
;
...
@@ -155,18 +155,18 @@ void GLCD_Move_Cursor(int x, int y)
...
@@ -155,18 +155,18 @@ void GLCD_Move_Cursor(int x, int y)
*************************************************************************/
*************************************************************************/
void
GLCD_Copy_Cursor
(
const
unsigned
long
*
pCursor
,
int
cursor
,
int
size
)
void
GLCD_Copy_Cursor
(
const
unsigned
long
*
pCursor
,
int
cursor
,
int
size
)
{
{
unsigned
long
i
;
unsigned
long
i
;
unsigned
long
*
pDst
=
(
unsigned
long
*
)
LCD_CURSOR_BASE_ADDR
;
unsigned
long
*
pDst
=
(
unsigned
long
*
)
LCD_CURSOR_BASE_ADDR
;
pDst
+=
cursor
*
64
;
pDst
+=
cursor
*
64
;
for
(
i
=
0
;
i
<
size
;
i
++
)
for
(
i
=
0
;
i
<
size
;
i
++
)
//
*pDst++ = *pCursor++;
//
*pDst++ = *pCursor++;
{
{
*
pDst
=
*
pCursor
;
*
pDst
=
*
pCursor
;
pDst
++
;
pDst
++
;
pCursor
++
;
pCursor
++
;
}
}
}
}
/*************************************************************************
/*************************************************************************
* Function Name: GLCD_Init
* Function Name: GLCD_Init
...
@@ -179,101 +179,101 @@ void GLCD_Copy_Cursor (const unsigned long *pCursor, int cursor, int size)
...
@@ -179,101 +179,101 @@ void GLCD_Copy_Cursor (const unsigned long *pCursor, int cursor, int size)
*************************************************************************/
*************************************************************************/
void
GLCD_Init
(
void
*
VRAMBase
)
void
GLCD_Init
(
void
*
VRAMBase
)
{
{
// unsigned long i;
// unsigned long i;
// Assign pins
// Assign pins
LPC_IOCON
->
P2_9
=
0x06
;
// VD3,
R0
LPC_IOCON
->
P2_9
=
0x06
;
// VD3,
R0
LPC_IOCON
->
P2_6
=
0x07
;
// VD4,
R1
LPC_IOCON
->
P2_6
=
0x07
;
// VD4,
R1
LPC_IOCON
->
P2_7
=
0x07
;
// VD5,
R2
LPC_IOCON
->
P2_7
=
0x07
;
// VD5,
R2
LPC_IOCON
->
P4_28
=
0x05
;
// VD6,
R3
LPC_IOCON
->
P4_28
=
0x05
;
// VD6,
R3
LPC_IOCON
->
P4_29
=
0x05
;
// VD7,
R4
LPC_IOCON
->
P4_29
=
0x05
;
// VD7,
R4
LPC_IOCON
->
P1_20
=
0x07
;
// VD10,
G0
LPC_IOCON
->
P1_20
=
0x07
;
// VD10,
G0
LPC_IOCON
->
P1_21
=
0x07
;
// VD11,
G1
LPC_IOCON
->
P1_21
=
0x07
;
// VD11,
G1
LPC_IOCON
->
P1_22
=
0x07
;
// VD12,
G2
LPC_IOCON
->
P1_22
=
0x07
;
// VD12,
G2
LPC_IOCON
->
P1_23
=
0x07
;
// VD13,
G3
LPC_IOCON
->
P1_23
=
0x07
;
// VD13,
G3
LPC_IOCON
->
P1_24
=
0x07
;
// VD14,
G4
LPC_IOCON
->
P1_24
=
0x07
;
// VD14,
G4
LPC_IOCON
->
P1_25
=
0x07
;
// VD15,
G5
LPC_IOCON
->
P1_25
=
0x07
;
// VD15,
G5
LPC_IOCON
->
P2_13
=
0x07
;
// VD19,
B0
LPC_IOCON
->
P2_13
=
0x07
;
// VD19,
B0
LPC_IOCON
->
P1_26
=
0x07
;
// VD20,
B1
LPC_IOCON
->
P1_26
=
0x07
;
// VD20,
B1
LPC_IOCON
->
P1_27
=
0x07
;
// VD21,
B2
LPC_IOCON
->
P1_27
=
0x07
;
// VD21,
B2
LPC_IOCON
->
P1_28
=
0x07
;
// VD22,
B3
LPC_IOCON
->
P1_28
=
0x07
;
// VD22,
B3
LPC_IOCON
->
P1_29
=
0x07
;
// VD23,
B4
LPC_IOCON
->
P1_29
=
0x07
;
// VD23,
B4
LPC_IOCON
->
P2_2
=
0x07
;
// DCLK
LPC_IOCON
->
P2_2
=
0x07
;
// DCLK
LPC_IOCON
->
P2_0
=
0x07
;
// DSIP(power)
LPC_IOCON
->
P2_0
=
0x07
;
// DSIP(power)
LPC_IOCON
->
P2_5
=
0x07
;
// HSYNC
LPC_IOCON
->
P2_5
=
0x07
;
// HSYNC
LPC_IOCON
->
P2_3
=
0x07
;
// VSYNC
LPC_IOCON
->
P2_3
=
0x07
;
// VSYNC
LPC_IOCON
->
P2_4
=
0x07
;
// DataEn
LPC_IOCON
->
P2_4
=
0x07
;
// DataEn
//
LPC_IOCON->P5_4 = 0x00;
// Backlight
//
LPC_IOCON->P5_4 = 0x00;
// Backlight
// >>> debug >>>
// >>> debug >>>
// <<< debug <<<
// <<< debug <<<
/*Back light enable*/
/*Back light enable*/
//
LPC_GPIO5->DIR = (1<<4);
//
LPC_GPIO5->DIR = (1<<4);
//
LPC_GPIO5->SET= (5<<4);
//
LPC_GPIO5->SET= (5<<4);
//Turn on LCD clock
//Turn on LCD clock
CLKPWR_ConfigPPWR
(
CLKPWR_PCONP_PCLCD
,
ENABLE
);
CLKPWR_ConfigPPWR
(
CLKPWR_PCONP_PCLCD
,
ENABLE
);
// Disable cursor
// Disable cursor
LPC_LCD
->
CRSR_CTRL
&=~
(
1
<<
0
);
LPC_LCD
->
CRSR_CTRL
&=~
(
1
<<
0
);
// disable GLCD controller
// disable GLCD controller
LPC_LCD
->
CTRL
=
0
;
LPC_LCD
->
CTRL
=
0
;
// RGB888
// RGB888
LPC_LCD
->
CTRL
&=
~
(
0x07
<<
1
);
LPC_LCD
->
CTRL
&=
~
(
0x07
<<
1
);
LPC_LCD
->
CTRL
|=
(
6
<<
1
);
LPC_LCD
->
CTRL
|=
(
6
<<
1
);
// TFT panel
// TFT panel
LPC_LCD
->
CTRL
|=
(
1
<<
5
);
LPC_LCD
->
CTRL
|=
(
1
<<
5
);
// single panel
// single panel
LPC_LCD
->
CTRL
&=
~
(
1
<<
7
);
LPC_LCD
->
CTRL
&=
~
(
1
<<
7
);
// notmal output
// notmal output
LPC_LCD
->
CTRL
&=
~
(
1
<<
8
);
LPC_LCD
->
CTRL
&=
~
(
1
<<
8
);
// little endian byte order
// little endian byte order
LPC_LCD
->
CTRL
&=
~
(
1
<<
9
);
LPC_LCD
->
CTRL
&=
~
(
1
<<
9
);
// little endian pix order
// little endian pix order
LPC_LCD
->
CTRL
&=
~
(
1
<<
10
);
LPC_LCD
->
CTRL
&=
~
(
1
<<
10
);
// disable power
// disable power
LPC_LCD
->
CTRL
&=
~
(
1
<<
11
);
LPC_LCD
->
CTRL
&=
~
(
1
<<
11
);
// init pixel clock
// init pixel clock
//
g_pSC->LCD_CFG = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER) / ((unsigned long)C_GLCD_PIX_CLK);
//
g_pSC->LCD_CFG = CLKPWR_GetCLK(CLKPWR_CLKTYPE_PER) / ((unsigned long)C_GLCD_PIX_CLK);
LPC_SC
->
LCD_CFG
=
CLKPWR_GetCLK
(
CLKPWR_CLKTYPE_PER
)
/
((
unsigned
long
)
C_GLCD_PIX_CLK
);
LPC_SC
->
LCD_CFG
=
CLKPWR_GetCLK
(
CLKPWR_CLKTYPE_PER
)
/
((
unsigned
long
)
C_GLCD_PIX_CLK
);
// bypass inrenal clk divider
// bypass inrenal clk divider
LPC_LCD
->
POL
|=
(
1
<<
26
);
LPC_LCD
->
POL
|=
(
1
<<
26
);
// clock source for the LCD block is HCLK
// clock source for the LCD block is HCLK
LPC_LCD
->
POL
&=
~
(
1
<<
5
);
LPC_LCD
->
POL
&=
~
(
1
<<
5
);
// LCDFP pin is active LOW and inactive HIGH
// LCDFP pin is active LOW and inactive HIGH
LPC_LCD
->
POL
|=
(
1
<<
11
);
LPC_LCD
->
POL
|=
(
1
<<
11
);
// LCDLP pin is active LOW and inactive HIGH
// LCDLP pin is active LOW and inactive HIGH
LPC_LCD
->
POL
|=
(
1
<<
12
);
LPC_LCD
->
POL
|=
(
1
<<
12
);
// data is driven out into the LCD on the falling edge
// data is driven out into the LCD on the falling edge
LPC_LCD
->
POL
&=
~
(
1
<<
13
);
LPC_LCD
->
POL
&=
~
(
1
<<
13
);
// active high
// active high
LPC_LCD
->
POL
&=
~
(
1
<<
14
);
LPC_LCD
->
POL
&=
~
(
1
<<
14
);
LPC_LCD
->
POL
&=
~
(
0x3FF
<<
16
);
LPC_LCD
->
POL
&=
~
(
0x3FF
<<
16
);
LPC_LCD
->
POL
|=
(
C_GLCD_H_SIZE
-
1
)
<<
16
;
LPC_LCD
->
POL
|=
(
C_GLCD_H_SIZE
-
1
)
<<
16
;
// init Horizontal Timing
// init Horizontal Timing
LPC_LCD
->
TIMH
=
0
;
//reset TIMH before set value
LPC_LCD
->
TIMH
=
0
;
//reset TIMH before set value
LPC_LCD
->
TIMH
|=
(
C_GLCD_H_BACK_PORCH
-
1
)
<<
24
;
LPC_LCD
->
TIMH
|=
(
C_GLCD_H_BACK_PORCH
-
1
)
<<
24
;
LPC_LCD
->
TIMH
|=
(
C_GLCD_H_FRONT_PORCH
-
1
)
<<
16
;
LPC_LCD
->
TIMH
|=
(
C_GLCD_H_FRONT_PORCH
-
1
)
<<
16
;
LPC_LCD
->
TIMH
|=
(
C_GLCD_H_PULSE
-
1
)
<<
8
;
LPC_LCD
->
TIMH
|=
(
C_GLCD_H_PULSE
-
1
)
<<
8
;
LPC_LCD
->
TIMH
|=
((
C_GLCD_H_SIZE
/
16
)
-
1
)
<<
2
;
LPC_LCD
->
TIMH
|=
((
C_GLCD_H_SIZE
/
16
)
-
1
)
<<
2
;
// init Vertical Timing
// init Vertical Timing
LPC_LCD
->
TIMV
=
0
;
//reset TIMV value before setting
LPC_LCD
->
TIMV
=
0
;
//reset TIMV value before setting
LPC_LCD
->
TIMV
|=
(
C_GLCD_V_BACK_PORCH
)
<<
24
;
LPC_LCD
->
TIMV
|=
(
C_GLCD_V_BACK_PORCH
)
<<
24
;
LPC_LCD
->
TIMV
|=
(
C_GLCD_V_FRONT_PORCH
)
<<
16
;
LPC_LCD
->
TIMV
|=
(
C_GLCD_V_FRONT_PORCH
)
<<
16
;
LPC_LCD
->
TIMV
|=
(
C_GLCD_V_PULSE
-
1
)
<<
10
;
LPC_LCD
->
TIMV
|=
(
C_GLCD_V_PULSE
-
1
)
<<
10
;
LPC_LCD
->
TIMV
|=
C_GLCD_V_SIZE
-
1
;
LPC_LCD
->
TIMV
|=
C_GLCD_V_SIZE
-
1
;
// Frame Base Address doubleword aligned
// Frame Base Address doubleword aligned
LPC_LCD
->
UPBASE
=
(
unsigned
long
)
VRAMBase
&
~
7UL
;
LPC_LCD
->
UPBASE
=
(
unsigned
long
)
VRAMBase
&
~
7UL
;
LPC_LCD
->
LPBASE
=
(
unsigned
long
)
VRAMBase
&
~
7UL
;
LPC_LCD
->
LPBASE
=
(
unsigned
long
)
VRAMBase
&
~
7UL
;
}
}
/*************************************************************************
/*************************************************************************
...
@@ -287,13 +287,13 @@ void GLCD_Init (void* VRAMBase)
...
@@ -287,13 +287,13 @@ void GLCD_Init (void* VRAMBase)
*************************************************************************/
*************************************************************************/
void
GLCD_SetPallet
(
const
unsigned
long
*
pPallete
)
void
GLCD_SetPallet
(
const
unsigned
long
*
pPallete
)
{
{
unsigned
long
i
;
unsigned
long
i
;
unsigned
long
*
pDst
=
(
unsigned
long
*
)
LPC_LCD
->
PAL
;
unsigned
long
*
pDst
=
(
unsigned
long
*
)
LPC_LCD
->
PAL
;
// //assert(pPallete);
// //assert(pPallete);
for
(
i
=
0
;
i
<
128
;
i
++
)
for
(
i
=
0
;
i
<
128
;
i
++
)
{
{
*
pDst
++
=
*
pPallete
++
;
*
pDst
++
=
*
pPallete
++
;
}
}
}
}
/*************************************************************************
/*************************************************************************
...
@@ -307,7 +307,7 @@ void GLCD_SetPallet (const unsigned long * pPallete)
...
@@ -307,7 +307,7 @@ void GLCD_SetPallet (const unsigned long * pPallete)
*************************************************************************/
*************************************************************************/
void
GLCD_Ctrl
(
Bool
bEna
)
void
GLCD_Ctrl
(
Bool
bEna
)
{
{
volatile
unsigned
long
i
;
volatile
unsigned
long
i
;
if
(
bEna
)
if
(
bEna
)
{
{
// LCD_CTRL_bit.LcdEn = 1;
// LCD_CTRL_bit.LcdEn = 1;
...
@@ -473,7 +473,7 @@ Bool GLCD_TextCalcWindow (unsigned long * pXL, unsigned long * pXR,
...
@@ -473,7 +473,7 @@ Bool GLCD_TextCalcWindow (unsigned long * pXL, unsigned long * pXR,
*
pXR
=
XL_Win
+
((
TextX_Pos
+
1
)
*
pCurrFont
->
H_Size
)
-
1
;
*
pXR
=
XL_Win
+
((
TextX_Pos
+
1
)
*
pCurrFont
->
H_Size
)
-
1
;
if
(
*
pXR
>
XR_Win
)
if
(
*
pXR
>
XR_Win
)
{
{
*
pH_Size
-=
*
pXR
-
XR_Win
;
*
pH_Size
-=
*
pXR
-
XR_Win
;
*
pXR
=
XR_Win
;
*
pXR
=
XR_Win
;
}
}
...
@@ -514,19 +514,19 @@ unsigned long i, j, k;
...
@@ -514,19 +514,19 @@ unsigned long i, j, k;
++
TextY_Pos
;
++
TextY_Pos
;
break
;
break
;
case
'\r'
:
// go to begin of this line (Carriage Return)
case
'\r'
:
// go to begin of this line (Carriage Return)
// clear from current position to end of line
// clear from current position to end of line
while
(
GLCD_TextCalcWindow
(
&
xl
,
&
xr
,
&
yu
,
&
yd
,
&
H_Size
,
&
V_Size
))
while
(
GLCD_TextCalcWindow
(
&
xl
,
&
xr
,
&
yu
,
&
yd
,
&
H_Size
,
&
V_Size
))
{
{
LCD_SET_WINDOW
(
xl
,
xr
,
yu
,
yd
);
LCD_SET_WINDOW
(
xl
,
xr
,
yu
,
yd
);
for
(
i
=
0
;
i
<
V_Size
;
++
i
)
for
(
i
=
0
;
i
<
V_Size
;
++
i
)
{
{
for
(
j
=
0
;
j
<
H_Size
;
++
j
)
for
(
j
=
0
;
j
<
H_Size
;
++
j
)
{
{
LCD_WRITE_PIXEL
(
TextBackgndColour
);
LCD_WRITE_PIXEL
(
TextBackgndColour
);
}
}
}
}
++
TextX_Pos
;
++
TextX_Pos
;
}
}
TextX_Pos
=
0
;
TextX_Pos
=
0
;
break
;
break
;
case
'\b'
:
// go back one position (BackSpace)
case
'\b'
:
// go back one position (BackSpace)
...
@@ -534,45 +534,45 @@ unsigned long i, j, k;
...
@@ -534,45 +534,45 @@ unsigned long i, j, k;
{
{
--
TextX_Pos
;
--
TextX_Pos
;
// del current position
// del current position
if
(
GLCD_TextCalcWindow
(
&
xl
,
&
xr
,
&
yu
,
&
yd
,
&
H_Size
,
&
V_Size
))
if
(
GLCD_TextCalcWindow
(
&
xl
,
&
xr
,
&
yu
,
&
yd
,
&
H_Size
,
&
V_Size
))
{
{
LCD_SET_WINDOW
(
xl
,
xr
,
yu
,
yd
);
LCD_SET_WINDOW
(
xl
,
xr
,
yu
,
yd
);
for
(
i
=
0
;
i
<
V_Size
;
++
i
)
for
(
i
=
0
;
i
<
V_Size
;
++
i
)
{
{
for
(
j
=
0
;
j
<
H_Size
;
++
j
)
for
(
j
=
0
;
j
<
H_Size
;
++
j
)
{
{
LCD_WRITE_PIXEL
(
TextBackgndColour
);
LCD_WRITE_PIXEL
(
TextBackgndColour
);
}
}
}
}
}
}
}
}
break
;
break
;
case
'\t'
:
// go to next Horizontal Tab stop
case
'\t'
:
// go to next Horizontal Tab stop
WhiteSpaceNumb
=
TabSize
-
(
TextX_Pos
%
TabSize
);
WhiteSpaceNumb
=
TabSize
-
(
TextX_Pos
%
TabSize
);
for
(
k
=
0
;
k
<
WhiteSpaceNumb
;
++
k
)
for
(
k
=
0
;
k
<
WhiteSpaceNumb
;
++
k
)
{
{
LCD_SET_WINDOW
(
xl
,
xr
,
yu
,
yd
);
LCD_SET_WINDOW
(
xl
,
xr
,
yu
,
yd
);
if
(
GLCD_TextCalcWindow
(
&
xl
,
&
xr
,
&
yu
,
&
yd
,
&
H_Size
,
&
V_Size
))
if
(
GLCD_TextCalcWindow
(
&
xl
,
&
xr
,
&
yu
,
&
yd
,
&
H_Size
,
&
V_Size
))
{
{
for
(
i
=
0
;
i
<
V_Size
;
++
i
)
for
(
i
=
0
;
i
<
V_Size
;
++
i
)
{
{
for
(
j
=
0
;
j
<
H_Size
;
++
j
)
for
(
j
=
0
;
j
<
H_Size
;
++
j
)
{
{
LCD_WRITE_PIXEL
(
TextBackgndColour
);
LCD_WRITE_PIXEL
(
TextBackgndColour
);
}
}
}
}
++
TextX_Pos
;
++
TextX_Pos
;
}
}
else
else
{
{
break
;
break
;
}
}
}
}
break
;
break
;
case
'\f'
:
// go to top of page (Form Feed)
case
'\f'
:
// go to top of page (Form Feed)
// clear entire window
// clear entire window
H_Size
=
XR_Win
-
XL_Win
;
H_Size
=
XR_Win
-
XL_Win
;
V_Size
=
YD_Win
-
YU_Win
;
V_Size
=
YD_Win
-
YU_Win
;
// set character window X left, Y right
// set character window X left, Y right
LCD_SET_WINDOW
(
XL_Win
,
XR_Win
,
YU_Win
,
YD_Win
);
LCD_SET_WINDOW
(
XL_Win
,
XR_Win
,
YU_Win
,
YD_Win
);
// Fill window with background font color
// Fill window with background font color
...
@@ -584,7 +584,7 @@ unsigned long i, j, k;
...
@@ -584,7 +584,7 @@ unsigned long i, j, k;
}
}
}
}
TextX_Pos
=
TextY_Pos
=
0
;
TextX_Pos
=
TextY_Pos
=
0
;
break
;
break
;
case
'\a'
:
// signal an alert (BELl)
case
'\a'
:
// signal an alert (BELl)
TEXT_BEL1_FUNC
();
TEXT_BEL1_FUNC
();
...
@@ -593,37 +593,37 @@ unsigned long i, j, k;
...
@@ -593,37 +593,37 @@ unsigned long i, j, k;
// Calculate the current character base address from stream
// Calculate the current character base address from stream
// and the character position
// and the character position
if
((
c
<
pCurrFont
->
CharacterOffset
)
&&
if
((
c
<
pCurrFont
->
CharacterOffset
)
&&
(
c
>=
pCurrFont
->
CharactersNuber
))
(
c
>=
pCurrFont
->
CharactersNuber
))
{
{
c
=
0
;
c
=
0
;
}
}
else
else
{
{
c
-=
pCurrFont
->
CharacterOffset
;
c
-=
pCurrFont
->
CharacterOffset
;
}
}
pSrc
=
pCurrFont
->
pFontStream
+
(
H_Line
*
pCurrFont
->
V_Size
*
c
);
pSrc
=
pCurrFont
->
pFontStream
+
(
H_Line
*
pCurrFont
->
V_Size
*
c
);
// Calculate character window and fit it in the text window
// Calculate character window and fit it in the text window
if
(
GLCD_TextCalcWindow
(
&
xl
,
&
xr
,
&
yu
,
&
yd
,
&
H_Size
,
&
V_Size
))
if
(
GLCD_TextCalcWindow
(
&
xl
,
&
xr
,
&
yu
,
&
yd
,
&
H_Size
,
&
V_Size
))
{
{
// set character window X left, Y right
// set character window X left, Y right
LCD_SET_WINDOW
(
xl
,
xr
,
yu
,
yd
);
LCD_SET_WINDOW
(
xl
,
xr
,
yu
,
yd
);
// Send char data
// Send char data
for
(
i
=
0
;
i
<
V_Size
;
++
i
)
for
(
i
=
0
;
i
<
V_Size
;
++
i
)
{
{
SrcInc
=
H_Line
;
SrcInc
=
H_Line
;
for
(
j
=
0
;
j
<
H_Size
;
++
j
)
for
(
j
=
0
;
j
<
H_Size
;
++
j
)
{
{
Temp
=
(
*
pSrc
&
(
1UL
<<
(
j
&
0x7
)))
?
TextColour
:
TextBackgndColour
;
Temp
=
(
*
pSrc
&
(
1UL
<<
(
j
&
0x7
)))
?
TextColour
:
TextBackgndColour
;
LCD_WRITE_PIXEL
(
Temp
);
LCD_WRITE_PIXEL
(
Temp
);
if
((
j
&
0x7
)
==
7
)
if
((
j
&
0x7
)
==
7
)
{
{
++
pSrc
;
++
pSrc
;
--
SrcInc
;
--
SrcInc
;
}
}
}
}
// next line of character
// next line of character
pSrc
+=
SrcInc
;
pSrc
+=
SrcInc
;
}
}
}
}
++
TextX_Pos
;
++
TextX_Pos
;
}
}
...
...
bsp/lpc178x/drivers/drv_glcd.h
浏览文件 @
958d9405
...
@@ -33,7 +33,7 @@ typedef unsigned long Boolean;
...
@@ -33,7 +33,7 @@ typedef unsigned long Boolean;
/**
/**
* @brief A struct for Bitmap on LCD screen
* @brief A struct for Bitmap on LCD screen
*/
*/
typedef
struct
_Bmp_t
typedef
struct
_Bmp_t
{
{
U32
H_Size
;
U32
H_Size
;
U32
V_Size
;
U32
V_Size
;
...
@@ -47,8 +47,8 @@ typedef struct _Bmp_t
...
@@ -47,8 +47,8 @@ typedef struct _Bmp_t
/**
/**
* @brief A struct for Font Type on LCD screen
* @brief A struct for Font Type on LCD screen
*/
*/
typedef
struct
_FontType_t
typedef
struct
_FontType_t
{
{
U32
H_Size
;
U32
H_Size
;
U32
V_Size
;
U32
V_Size
;
...
@@ -62,9 +62,9 @@ typedef U32 LdcPixel_t, *pLdcPixel_t;
...
@@ -62,9 +62,9 @@ typedef U32 LdcPixel_t, *pLdcPixel_t;
#define C_GLCD_REFRESH_FREQ (60HZ)
#define C_GLCD_REFRESH_FREQ (60HZ)
#define C_GLCD_H_SIZE 480
#define C_GLCD_H_SIZE 480
#define C_GLCD_H_PULSE 2
//
#define C_GLCD_H_PULSE 2
//
#define C_GLCD_H_FRONT_PORCH 5
//
#define C_GLCD_H_FRONT_PORCH 5
//
#define C_GLCD_H_BACK_PORCH 40
//
#define C_GLCD_H_BACK_PORCH 40
//
#define C_GLCD_V_SIZE 272
#define C_GLCD_V_SIZE 272
#define C_GLCD_V_PULSE 2
#define C_GLCD_V_PULSE 2
#define C_GLCD_V_FRONT_PORCH 8
#define C_GLCD_V_FRONT_PORCH 8
...
...
bsp/lpc178x/drivers/emac.c
浏览文件 @
958d9405
此差异已折叠。
点击以展开。
bsp/lpc178x/drivers/emac.h
浏览文件 @
958d9405
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef __LPC17XX_EMAC_H
#ifndef __LPC17XX_EMAC_H
#define __LPC17XX_EMAC_H
#define __LPC17XX_EMAC_H
...
@@ -11,7 +20,7 @@
...
@@ -11,7 +20,7 @@
#define ETH_MAX_FLEN 1536
/* Max. Ethernet Frame Size */
#define ETH_MAX_FLEN 1536
/* Max. Ethernet Frame Size */
/* EMAC variables located in 16K Ethernet SRAM */
/* EMAC variables located in 16K Ethernet SRAM */
#define RX_DESC_BASE
0x20000000
#define RX_DESC_BASE
0x20000000
#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)
#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)
#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)
#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)
#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)
#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)
...
...
bsp/lpc178x/drivers/lpc177x_8x_clkpwr.c
浏览文件 @
958d9405
/**********************************************************************
/**********************************************************************
* $Id$
lpc177x_8x_clkpwr.c
2011-06-02
* $Id$
lpc177x_8x_clkpwr.c
2011-06-02
*//**
*//**
* @file
lpc177x_8x_clkpwr.c
* @file
lpc177x_8x_clkpwr.c
* @brief
Contains all functions support for Clock and Power Control
* @brief
Contains all functions support for Clock and Power Control
*
firmware library on LPC177x_8x
*
firmware library on LPC177x_8x
* @version
1.0
* @version
1.0
* @date
02. June. 2011
* @date
02. June. 2011
* @author
NXP MCU SW Application Team
* @author
NXP MCU SW Application Team
*
*
* Copyright(C) 2011, NXP Semiconductor
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
* All rights reserved.
*
*
...
@@ -41,253 +41,253 @@ uint32_t SPIFIFrequency = 0;
...
@@ -41,253 +41,253 @@ uint32_t SPIFIFrequency = 0;
*/
*/
/*********************************************************************//**
/*********************************************************************//**
* @brief
Set value of each Peripheral Clock Selection
* @brief
Set value of each Peripheral Clock Selection
* @param[in]
ClkType clock type that will be divided, should be:
* @param[in]
ClkType clock type that will be divided, should be:
*
- CLKPWR_CLKTYPE_CPU
: CPU clock
*
- CLKPWR_CLKTYPE_CPU
: CPU clock
*
- CLKPWR_CLKTYPE_PER
: Peripheral clock
*
- CLKPWR_CLKTYPE_PER
: Peripheral clock
*
- CLKPWR_CLKTYPE_EMC
: EMC clock
*
- CLKPWR_CLKTYPE_EMC
: EMC clock
*
- CLKPWR_CLKTYPE_USB
: USB clock
*
- CLKPWR_CLKTYPE_USB
: USB clock
* @param[in]
DivVal
Value of divider. This value should be set as follows:
* @param[in]
DivVal
Value of divider. This value should be set as follows:
*
- CPU clock: DivVal must be in range: 0..31
*
- CPU clock: DivVal must be in range: 0..31
*
- Peripheral clock: DivVal must be in range: 0..31
*
- Peripheral clock: DivVal must be in range: 0..31
*
- EMC clock: DivVal must be:
*
- EMC clock: DivVal must be:
*
+ 0: The EMC uses the same clock as the CPU
*
+ 0: The EMC uses the same clock as the CPU
*
+ 1: The EMC uses a clock at half the rate of the CPU
*
+ 1: The EMC uses a clock at half the rate of the CPU
*
- USB clock: DivVal must be:
*
- USB clock: DivVal must be:
*
+ 0: the divider is turned off, no clock will
*
+ 0: the divider is turned off, no clock will
*
be provided to the USB subsystem
*
be provided to the USB subsystem
*
+ 4: PLL0 output is divided by 4. PLL0 output must be 192MHz
*
+ 4: PLL0 output is divided by 4. PLL0 output must be 192MHz
*
+ 6: PLL0 output is divided by 6. PLL0 output must be 288MHz
*
+ 6: PLL0 output is divided by 6. PLL0 output must be 288MHz
* @return none
* @return none
* Note: Pls assign right DivVal, this function will not check if it is illegal.
* Note: Pls assign right DivVal, this function will not check if it is illegal.
**********************************************************************/
**********************************************************************/
void
CLKPWR_SetCLKDiv
(
uint8_t
ClkType
,
uint8_t
DivVal
)
void
CLKPWR_SetCLKDiv
(
uint8_t
ClkType
,
uint8_t
DivVal
)
{
{
switch
(
ClkType
)
switch
(
ClkType
)
{
{
case
CLKPWR_CLKTYPE_CPU
:
case
CLKPWR_CLKTYPE_CPU
:
LPC_SC
->
CCLKSEL
=
DivVal
;
LPC_SC
->
CCLKSEL
=
DivVal
;
SystemCoreClockUpdate
();
//Update clock
SystemCoreClockUpdate
();
//Update clock
break
;
break
;
case
CLKPWR_CLKTYPE_PER
:
case
CLKPWR_CLKTYPE_PER
:
LPC_SC
->
PCLKSEL
=
DivVal
;
LPC_SC
->
PCLKSEL
=
DivVal
;
SystemCoreClockUpdate
();
//Update clock
SystemCoreClockUpdate
();
//Update clock
break
;
break
;
case
CLKPWR_CLKTYPE_EMC
:
case
CLKPWR_CLKTYPE_EMC
:
LPC_SC
->
EMCCLKSEL
=
DivVal
;
LPC_SC
->
EMCCLKSEL
=
DivVal
;
SystemCoreClockUpdate
();
//Update clock
SystemCoreClockUpdate
();
//Update clock
break
;
break
;
case
CLKPWR_CLKTYPE_USB
:
case
CLKPWR_CLKTYPE_USB
:
LPC_SC
->
USBCLKSEL
&=
~
(
0x0000001F
);
LPC_SC
->
USBCLKSEL
&=
~
(
0x0000001F
);
LPC_SC
->
USBCLKSEL
|=
DivVal
;
LPC_SC
->
USBCLKSEL
|=
DivVal
;
break
;
break
;
default:
default:
while
(
1
);
//Error Loop;
while
(
1
);
//Error Loop;
}
}
}
}
/*********************************************************************//**
/*********************************************************************//**
* @brief
Get current clock value
* @brief
Get current clock value
* @param[in]
ClkType clock type that will be divided, should be:
* @param[in]
ClkType clock type that will be divided, should be:
*
- CLKPWR_CLKTYPE_CPU
: CPU clock
*
- CLKPWR_CLKTYPE_CPU
: CPU clock
*
- CLKPWR_CLKTYPE_PER
: Peripheral clock
*
- CLKPWR_CLKTYPE_PER
: Peripheral clock
*
- CLKPWR_CLKTYPE_EMC
: EMC clock
*
- CLKPWR_CLKTYPE_EMC
: EMC clock
*
- CLKPWR_CLKTYPE_USB
: USB clock
*
- CLKPWR_CLKTYPE_USB
: USB clock
**********************************************************************/
**********************************************************************/
uint32_t
CLKPWR_GetCLK
(
uint8_t
ClkType
)
uint32_t
CLKPWR_GetCLK
(
uint8_t
ClkType
)
{
{
switch
(
ClkType
)
switch
(
ClkType
)
{
{
case
CLKPWR_CLKTYPE_CPU
:
case
CLKPWR_CLKTYPE_CPU
:
return
SystemCoreClock
;
return
SystemCoreClock
;
case
CLKPWR_CLKTYPE_PER
:
case
CLKPWR_CLKTYPE_PER
:
return
PeripheralClock
;
return
PeripheralClock
;
case
CLKPWR_CLKTYPE_EMC
:
case
CLKPWR_CLKTYPE_EMC
:
return
EMCClock
;
return
EMCClock
;
case
CLKPWR_CLKTYPE_USB
:
case
CLKPWR_CLKTYPE_USB
:
return
USBClock
;
return
USBClock
;
default:
default:
while
(
1
);
//error loop
while
(
1
);
//error loop
}
}
}
}
/*********************************************************************//**
/*********************************************************************//**
* @brief
Configure power supply for each peripheral according to NewState
* @brief
Configure power supply for each peripheral according to NewState
* @param[in]
PPType
Type of peripheral used to enable power,
* @param[in]
PPType
Type of peripheral used to enable power,
*
should be one of the following:
*
should be one of the following:
*
- CLKPWR_PCONP_PCLCD
: LCD
*
- CLKPWR_PCONP_PCLCD
: LCD
*
- CLKPWR_PCONP_PCTIM0
: Timer 0
*
- CLKPWR_PCONP_PCTIM0
: Timer 0
- CLKPWR_PCONP_PCTIM1
: Timer 1
- CLKPWR_PCONP_PCTIM1
: Timer 1
- CLKPWR_PCONP_PCUART0
: UART 0
- CLKPWR_PCONP_PCUART0
: UART 0
- CLKPWR_PCONP_PCUART1
: UART 1
- CLKPWR_PCONP_PCUART1
: UART 1
- CLKPWR_PCONP_PCPWM0
: PWM 0
- CLKPWR_PCONP_PCPWM0
: PWM 0
- CLKPWR_PCONP_PCPWM1
: PWM 1
- CLKPWR_PCONP_PCPWM1
: PWM 1
- CLKPWR_PCONP_PCI2C0
: I2C 0
- CLKPWR_PCONP_PCI2C0
: I2C 0
- CLKPWR_PCONP_PCUART4
: UART4
- CLKPWR_PCONP_PCUART4
: UART4
- CLKPWR_PCONP_PCRTC
: RTC
- CLKPWR_PCONP_PCRTC
: RTC
- CLKPWR_PCONP_PCSSP1
: SSP 1
- CLKPWR_PCONP_PCSSP1
: SSP 1
- CLKPWR_PCONP_PCEMC
: EMC
- CLKPWR_PCONP_PCEMC
: EMC
- CLKPWR_PCONP_PCADC
: ADC
- CLKPWR_PCONP_PCADC
: ADC
- CLKPWR_PCONP_PCAN1
: CAN 1
- CLKPWR_PCONP_PCAN1
: CAN 1
- CLKPWR_PCONP_PCAN2
: CAN 2
- CLKPWR_PCONP_PCAN2
: CAN 2
- CLKPWR_PCONP_PCGPIO
: GPIO
- CLKPWR_PCONP_PCGPIO
: GPIO
- CLKPWR_PCONP_PCMC
: MCPWM
- CLKPWR_PCONP_PCMC
: MCPWM
- CLKPWR_PCONP_PCQEI
: QEI
- CLKPWR_PCONP_PCQEI
: QEI
- CLKPWR_PCONP_PCI2C1
: I2C 1
- CLKPWR_PCONP_PCI2C1
: I2C 1
- CLKPWR_PCONP_PCSSP2
: SSP 2
- CLKPWR_PCONP_PCSSP2
: SSP 2
- CLKPWR_PCONP_PCSSP0
: SSP 0
- CLKPWR_PCONP_PCSSP0
: SSP 0
- CLKPWR_PCONP_PCTIM2
: Timer 2
- CLKPWR_PCONP_PCTIM2
: Timer 2
- CLKPWR_PCONP_PCTIM3
: Timer 3
- CLKPWR_PCONP_PCTIM3
: Timer 3
- CLKPWR_PCONP_PCUART2
: UART 2
- CLKPWR_PCONP_PCUART2
: UART 2
- CLKPWR_PCONP_PCUART3
: UART 3
- CLKPWR_PCONP_PCUART3
: UART 3
- CLKPWR_PCONP_PCI2C2
: I2C 2
- CLKPWR_PCONP_PCI2C2
: I2C 2
- CLKPWR_PCONP_PCI2S
: I2S
- CLKPWR_PCONP_PCI2S
: I2S
- CLKPWR_PCONP_PCSDC
: SDC
- CLKPWR_PCONP_PCSDC
: SDC
- CLKPWR_PCONP_PCGPDMA
: GPDMA
- CLKPWR_PCONP_PCGPDMA
: GPDMA
- CLKPWR_PCONP_PCENET
: Ethernet
- CLKPWR_PCONP_PCENET
: Ethernet
- CLKPWR_PCONP_PCUSB
: USB
- CLKPWR_PCONP_PCUSB
: USB
*
*
* @param[in]
NewState
New state of Peripheral Power, should be:
* @param[in]
NewState
New state of Peripheral Power, should be:
*
- ENABLE
: Enable power for this peripheral
*
- ENABLE
: Enable power for this peripheral
*
- DISABLE
: Disable power for this peripheral
*
- DISABLE
: Disable power for this peripheral
*
*
* @return none
* @return none
**********************************************************************/
**********************************************************************/
void
CLKPWR_ConfigPPWR
(
uint32_t
PPType
,
FunctionalState
NewState
)
void
CLKPWR_ConfigPPWR
(
uint32_t
PPType
,
FunctionalState
NewState
)
{
{
if
(
NewState
==
ENABLE
)
if
(
NewState
==
ENABLE
)
{
{
LPC_SC
->
PCONP
|=
PPType
;
LPC_SC
->
PCONP
|=
PPType
;
}
}
else
if
(
NewState
==
DISABLE
)
else
if
(
NewState
==
DISABLE
)
{
{
LPC_SC
->
PCONP
&=
~
PPType
;
LPC_SC
->
PCONP
&=
~
PPType
;
}
}
}
}
#if 0
#if 0
// nxp21346
// nxp21346
/*********************************************************************//**
/*********************************************************************//**
* @brief
Configure hardware reset for each peripheral according to NewState
* @brief
Configure hardware reset for each peripheral according to NewState
* @param[in]
PPType
Type of peripheral used to enable power,
* @param[in]
PPType
Type of peripheral used to enable power,
*
should be one of the following:
*
should be one of the following:
*
- CLKPWR_RSTCON0_LCD
: LCD
*
- CLKPWR_RSTCON0_LCD
: LCD
*
- CLKPWR_RSTCON0_TIM0
: Timer 0
*
- CLKPWR_RSTCON0_TIM0
: Timer 0
- CLKPWR_RSTCON0_TIM1
: Timer 1
- CLKPWR_RSTCON0_TIM1
: Timer 1
- CLKPWR_RSTCON0_UART0
: UART 0
- CLKPWR_RSTCON0_UART0
: UART 0
- CLKPWR_RSTCON0_UART1
: UART 1
- CLKPWR_RSTCON0_UART1
: UART 1
- CLKPWR_RSTCON0_PWM0
: PWM 0
- CLKPWR_RSTCON0_PWM0
: PWM 0
- CLKPWR_RSTCON0_PWM1
: PWM 1
- CLKPWR_RSTCON0_PWM1
: PWM 1
- CLKPWR_RSTCON0_I2C0
: I2C 0
- CLKPWR_RSTCON0_I2C0
: I2C 0
- CLKPWR_RSTCON0_UART4
: UART 4
- CLKPWR_RSTCON0_UART4
: UART 4
- CLKPWR_RSTCON0_RTC
: RTC
- CLKPWR_RSTCON0_RTC
: RTC
- CLKPWR_RSTCON0_SSP1
: SSP 1
- CLKPWR_RSTCON0_SSP1
: SSP 1
- CLKPWR_RSTCON0_EMC
: EMC
- CLKPWR_RSTCON0_EMC
: EMC
- CLKPWR_RSTCON0_ADC
: ADC
- CLKPWR_RSTCON0_ADC
: ADC
- CLKPWR_RSTCON0_CAN1
: CAN 1
- CLKPWR_RSTCON0_CAN1
: CAN 1
- CLKPWR_RSTCON0_CAN2
: CAN 2
- CLKPWR_RSTCON0_CAN2
: CAN 2
- CLKPWR_RSTCON0_GPIO
: GPIO
- CLKPWR_RSTCON0_GPIO
: GPIO
- CLKPWR_RSTCON0_MCPWM
: MCPWM
- CLKPWR_RSTCON0_MCPWM
: MCPWM
- CLKPWR_RSTCON0_QEI
: QEI
- CLKPWR_RSTCON0_QEI
: QEI
- CLKPWR_RSTCON0_I2C1
: I2C 1
- CLKPWR_RSTCON0_I2C1
: I2C 1
- CLKPWR_RSTCON0_SSP2
: SSP 2
- CLKPWR_RSTCON0_SSP2
: SSP 2
- CLKPWR_RSTCON0_SSP0
: SSP 0
- CLKPWR_RSTCON0_SSP0
: SSP 0
- CLKPWR_RSTCON0_TIM2
: Timer 2
- CLKPWR_RSTCON0_TIM2
: Timer 2
- CLKPWR_RSTCON0_TIM3
: Timer 3
- CLKPWR_RSTCON0_TIM3
: Timer 3
- CLKPWR_RSTCON0_UART2
: UART 2
- CLKPWR_RSTCON0_UART2
: UART 2
- CLKPWR_RSTCON0_UART3
: UART 3
- CLKPWR_RSTCON0_UART3
: UART 3
- CLKPWR_RSTCON0_I2C2
: I2C 2
- CLKPWR_RSTCON0_I2C2
: I2C 2
- CLKPWR_RSTCON0_I2S
: I2S
- CLKPWR_RSTCON0_I2S
: I2S
- CLKPWR_RSTCON0_SDC
: SDC
- CLKPWR_RSTCON0_SDC
: SDC
- CLKPWR_RSTCON0_GPDMA
: GPDMA
- CLKPWR_RSTCON0_GPDMA
: GPDMA
- CLKPWR_RSTCON0_ENET
: Ethernet
- CLKPWR_RSTCON0_ENET
: Ethernet
- CLKPWR_RSTCON0_USB
: USB
- CLKPWR_RSTCON0_USB
: USB
*
*
* @param[in]
NewState
New state of Peripheral Power, should be:
* @param[in]
NewState
New state of Peripheral Power, should be:
*
- ENABLE
: Enable power for this peripheral
*
- ENABLE
: Enable power for this peripheral
*
- DISABLE
: Disable power for this peripheral
*
- DISABLE
: Disable power for this peripheral
*
*
* @return none
* @return none
**********************************************************************/
**********************************************************************/
void CLKPWR_ConfigReset(uint8_t PType, FunctionalState NewState)
void CLKPWR_ConfigReset(uint8_t PType, FunctionalState NewState)
{
{
if(PType < 32)
if(PType < 32)
{
{
if(NewState == ENABLE)
if(NewState == ENABLE)
LPC_SC->RSTCON0 |=(1<<PType);
LPC_SC->RSTCON0 |=(1<<PType);
else
else
LPC_SC->RSTCON0 &=~(1<<PType);
LPC_SC->RSTCON0 &=~(1<<PType);
}
}
else
else
{
{
if(NewState == ENABLE)
if(NewState == ENABLE)
LPC_SC->RSTCON1 |= (1<<(PType - 31));
LPC_SC->RSTCON1 |= (1<<(PType - 31));
else
else
LPC_SC->RSTCON1 &= ~(1<<(PType - 31));
LPC_SC->RSTCON1 &= ~(1<<(PType - 31));
}
}
}
}
// nxp21346
// nxp21346
#endif
#endif
/*********************************************************************//**
/*********************************************************************//**
* @brief
Enter Sleep mode with co-operated instruction by the Cortex-M3.
* @brief
Enter Sleep mode with co-operated instruction by the Cortex-M3.
* @param[in]
None
* @param[in]
None
* @return
None
* @return
None
**********************************************************************/
**********************************************************************/
void
CLKPWR_Sleep
(
void
)
void
CLKPWR_Sleep
(
void
)
{
{
LPC_SC
->
PCON
=
0x00
;
LPC_SC
->
PCON
=
0x00
;
/* Sleep Mode*/
/* Sleep Mode*/
__WFI
();
__WFI
();
}
}
/*********************************************************************//**
/*********************************************************************//**
* @brief
Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
* @brief
Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
* @param[in]
None
* @param[in]
None
* @return
None
* @return
None
**********************************************************************/
**********************************************************************/
void
CLKPWR_DeepSleep
(
void
)
void
CLKPWR_DeepSleep
(
void
)
{
{
/* Deep-Sleep Mode, set SLEEPDEEP bit */
/* Deep-Sleep Mode, set SLEEPDEEP bit */
SCB
->
SCR
=
0x4
;
SCB
->
SCR
=
0x4
;
LPC_SC
->
PCON
=
0x8
;
LPC_SC
->
PCON
=
0x8
;
/* Deep Sleep Mode*/
/* Deep Sleep Mode*/
__WFI
();
__WFI
();
}
}
/*********************************************************************//**
/*********************************************************************//**
* @brief
Enter Power Down mode with co-operated instruction by the Cortex-M3.
* @brief
Enter Power Down mode with co-operated instruction by the Cortex-M3.
* @param[in]
None
* @param[in]
None
* @return
None
* @return
None
**********************************************************************/
**********************************************************************/
void
CLKPWR_PowerDown
(
void
)
void
CLKPWR_PowerDown
(
void
)
{
{
/* Deep-Sleep Mode, set SLEEPDEEP bit */
/* Deep-Sleep Mode, set SLEEPDEEP bit */
SCB
->
SCR
=
0x4
;
SCB
->
SCR
=
0x4
;
LPC_SC
->
PCON
=
0x09
;
LPC_SC
->
PCON
=
0x09
;
/* Power Down Mode*/
/* Power Down Mode*/
__WFI
();
__WFI
();
}
}
/*********************************************************************//**
/*********************************************************************//**
* @brief
Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
* @brief
Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
* @param[in]
None
* @param[in]
None
* @return
None
* @return
None
**********************************************************************/
**********************************************************************/
void
CLKPWR_DeepPowerDown
(
void
)
void
CLKPWR_DeepPowerDown
(
void
)
{
{
/* Deep-Sleep Mode, set SLEEPDEEP bit */
/* Deep-Sleep Mode, set SLEEPDEEP bit */
SCB
->
SCR
=
0x4
;
SCB
->
SCR
=
0x4
;
LPC_SC
->
PCON
=
0x03
;
LPC_SC
->
PCON
=
0x03
;
/* Deep Power Down Mode*/
/* Deep Power Down Mode*/
__WFI
();
__WFI
();
}
}
/**
/**
...
...
bsp/lpc178x/drivers/lpc177x_8x_clkpwr.h
浏览文件 @
958d9405
/**********************************************************************
/**********************************************************************
* $Id$
lpc177x_8x_clkpwr.h
2011-06-02
* $Id$
lpc177x_8x_clkpwr.h
2011-06-02
*//**
*//**
* @file
lpc177x_8x_clkpwr.h
* @file
lpc177x_8x_clkpwr.h
* @brief
Contains all macro definitions and function prototypes
* @brief
Contains all macro definitions and function prototypes
*
support for Clock and Power Control firmware library on
*
support for Clock and Power Control firmware library on
*
LPC177x_8x
*
LPC177x_8x
* @version
1.0
* @version
1.0
* @date
02. June. 2011
* @date
02. June. 2011
* @author
NXP MCU SW Application Team
* @author
NXP MCU SW Application Team
*
*
* Copyright(C) 2011, NXP Semiconductor
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
* All rights reserved.
*
*
...
@@ -26,7 +26,7 @@
...
@@ -26,7 +26,7 @@
**********************************************************************/
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup CLKPWR
Clock Power
/** @defgroup CLKPWR
Clock Power
* @ingroup LPC177x_8xCMSIS_FwLib_Drivers
* @ingroup LPC177x_8xCMSIS_FwLib_Drivers
* @{
* @{
*/
*/
...
@@ -52,163 +52,163 @@ extern "C"
...
@@ -52,163 +52,163 @@ extern "C"
/********************************************************************
/********************************************************************
* Clock Source Selection Definitions
* Clock Source Selection Definitions
**********************************************************************/
**********************************************************************/
#define CLKPWR_CLKSRCSEL_IRCOSC
((uint32_t)(0))
#define CLKPWR_CLKSRCSEL_IRCOSC
((uint32_t)(0))
#define CLKPWR_CLKSRCSEL_MAINOSC
((uint32_t)(1))
#define CLKPWR_CLKSRCSEL_MAINOSC
((uint32_t)(1))
/********************************************************************
/********************************************************************
* Clock type/domain Definitions (calculated from input and pre-configuration
* Clock type/domain Definitions (calculated from input and pre-configuration
* parameter(s)
* parameter(s)
**********************************************************************/
**********************************************************************/
#define CLKPWR_CLKTYPE_CPU
((uint32_t)(0))
#define CLKPWR_CLKTYPE_CPU
((uint32_t)(0))
#define CLKPWR_CLKTYPE_PER
((uint32_t)(1))
#define CLKPWR_CLKTYPE_PER
((uint32_t)(1))
#define CLKPWR_CLKTYPE_EMC
((uint32_t)(2))
#define CLKPWR_CLKTYPE_EMC
((uint32_t)(2))
#define CLKPWR_CLKTYPE_USB
((uint32_t)(3))
#define CLKPWR_CLKTYPE_USB
((uint32_t)(3))
/********************************************************************
/********************************************************************
* Power Control for Peripherals Definitions
* Power Control for Peripherals Definitions
**********************************************************************/
**********************************************************************/
/** LCD controller power/clock control bit */
/** LCD controller power/clock control bit */
#define CLKPWR_PCONP_PCLCD
((uint32_t)(1<<0))
#define CLKPWR_PCONP_PCLCD
((uint32_t)(1<<0))
/** Timer/Counter 0 power/clock control bit */
/** Timer/Counter 0 power/clock control bit */
#define
CLKPWR_PCONP_PCTIM0
((uint32_t)(1<<1))
#define
CLKPWR_PCONP_PCTIM0
((uint32_t)(1<<1))
/* Timer/Counter 1 power/clock control bit */
/* Timer/Counter 1 power/clock control bit */
#define
CLKPWR_PCONP_PCTIM1
((uint32_t)(1<<2))
#define
CLKPWR_PCONP_PCTIM1
((uint32_t)(1<<2))
/** UART0 power/clock control bit */
/** UART0 power/clock control bit */
#define
CLKPWR_PCONP_PCUART0
((uint32_t)(1<<3))
#define
CLKPWR_PCONP_PCUART0
((uint32_t)(1<<3))
/** UART1 power/clock control bit */
/** UART1 power/clock control bit */
#define
CLKPWR_PCONP_PCUART1
((uint32_t)(1<<4))
#define
CLKPWR_PCONP_PCUART1
((uint32_t)(1<<4))
/** PWM0 power/clock control bit */
/** PWM0 power/clock control bit */
#define CLKPWR_PCONP_PCPWM0
((uint32_t)(1<<5))
#define CLKPWR_PCONP_PCPWM0
((uint32_t)(1<<5))
/** PWM1 power/clock control bit */
/** PWM1 power/clock control bit */
#define
CLKPWR_PCONP_PCPWM1
((uint32_t)(1<<6))
#define
CLKPWR_PCONP_PCPWM1
((uint32_t)(1<<6))
/** The I2C0 interface power/clock control bit */
/** The I2C0 interface power/clock control bit */
#define
CLKPWR_PCONP_PCI2C0
((uint32_t)(1<<7))
#define
CLKPWR_PCONP_PCI2C0
((uint32_t)(1<<7))
/** UART4 power/clock control bit */
/** UART4 power/clock control bit */
#define CLKPWR_PCONP_PCUART4
((uint32_t)(1<<8))
#define CLKPWR_PCONP_PCUART4
((uint32_t)(1<<8))
/** The RTC power/clock control bit */
/** The RTC power/clock control bit */
#define
CLKPWR_PCONP_PCRTC
((uint32_t)(1<<9))
#define
CLKPWR_PCONP_PCRTC
((uint32_t)(1<<9))
/** The SSP1 interface power/clock control bit */
/** The SSP1 interface power/clock control bit */
#define
CLKPWR_PCONP_PCSSP1
((uint32_t)(1<<10))
#define
CLKPWR_PCONP_PCSSP1
((uint32_t)(1<<10))
/** External Memory controller power/clock control bit */
/** External Memory controller power/clock control bit */
#define CLKPWR_PCONP_PCEMC
((uint32_t)(1<<11))
#define CLKPWR_PCONP_PCEMC
((uint32_t)(1<<11))
/** A/D converter 0 (ADC0) power/clock control bit */
/** A/D converter 0 (ADC0) power/clock control bit */
#define
CLKPWR_PCONP_PCADC
((uint32_t)(1<<12))
#define
CLKPWR_PCONP_PCADC
((uint32_t)(1<<12))
/** CAN Controller 1 power/clock control bit */
/** CAN Controller 1 power/clock control bit */
#define
CLKPWR_PCONP_PCAN1
((uint32_t)(1<<13))
#define
CLKPWR_PCONP_PCAN1
((uint32_t)(1<<13))
/** CAN Controller 2 power/clock control bit */
/** CAN Controller 2 power/clock control bit */
#define
CLKPWR_PCONP_PCAN2
((uint32_t)(1<<14))
#define
CLKPWR_PCONP_PCAN2
((uint32_t)(1<<14))
/** GPIO power/clock control bit */
/** GPIO power/clock control bit */
#define
CLKPWR_PCONP_PCGPIO
((uint32_t)(1<<15))
#define
CLKPWR_PCONP_PCGPIO
((uint32_t)(1<<15))
/** Motor Control PWM */
/** Motor Control PWM */
#define CLKPWR_PCONP_PCMCPWM
((uint32_t)(1<<17))
#define CLKPWR_PCONP_PCMCPWM
((uint32_t)(1<<17))
/** Quadrature Encoder Interface power/clock control bit */
/** Quadrature Encoder Interface power/clock control bit */
#define CLKPWR_PCONP_PCQEI
((uint32_t)(1<<18))
#define CLKPWR_PCONP_PCQEI
((uint32_t)(1<<18))
/** The I2C1 interface power/clock control bit */
/** The I2C1 interface power/clock control bit */
#define
CLKPWR_PCONP_PCI2C1
((uint32_t)(1<<19))
#define
CLKPWR_PCONP_PCI2C1
((uint32_t)(1<<19))
/** The SSP2 interface power/clock control bit */
/** The SSP2 interface power/clock control bit */
#define CLKPWR_PCONP_PCSSP2
((uint32_t)(1<<20))
#define CLKPWR_PCONP_PCSSP2
((uint32_t)(1<<20))
/** The SSP0 interface power/clock control bit */
/** The SSP0 interface power/clock control bit */
#define
CLKPWR_PCONP_PCSSP0
((uint32_t)(1<<21))
#define
CLKPWR_PCONP_PCSSP0
((uint32_t)(1<<21))
/** Timer 2 power/clock control bit */
/** Timer 2 power/clock control bit */
#define
CLKPWR_PCONP_PCTIM2
((uint32_t)(1<<22))
#define
CLKPWR_PCONP_PCTIM2
((uint32_t)(1<<22))
/** Timer 3 power/clock control bit */
/** Timer 3 power/clock control bit */
#define
CLKPWR_PCONP_PCTIM3
((uint32_t)(1<<23))
#define
CLKPWR_PCONP_PCTIM3
((uint32_t)(1<<23))
/** UART 2 power/clock control bit */
/** UART 2 power/clock control bit */
#define
CLKPWR_PCONP_PCUART2
((uint32_t)(1<<24))
#define
CLKPWR_PCONP_PCUART2
((uint32_t)(1<<24))
/** UART 3 power/clock control bit */
/** UART 3 power/clock control bit */
#define
CLKPWR_PCONP_PCUART3
((uint32_t)(1<<25))
#define
CLKPWR_PCONP_PCUART3
((uint32_t)(1<<25))
/** I2C interface 2 power/clock control bit */
/** I2C interface 2 power/clock control bit */
#define
CLKPWR_PCONP_PCI2C2
((uint32_t)(1<<26))
#define
CLKPWR_PCONP_PCI2C2
((uint32_t)(1<<26))
/** I2S interface power/clock control bit*/
/** I2S interface power/clock control bit*/
#define
CLKPWR_PCONP_PCI2S
((uint32_t)(1<<27))
#define
CLKPWR_PCONP_PCI2S
((uint32_t)(1<<27))
/** SD card interface power/clock control bit */
/** SD card interface power/clock control bit */
#define CLKPWR_PCONP_PCSDC
((uint32_t)(1<<28))
#define CLKPWR_PCONP_PCSDC
((uint32_t)(1<<28))
/** GP DMA function power/clock control bit*/
/** GP DMA function power/clock control bit*/
#define
CLKPWR_PCONP_PCGPDMA
((uint32_t)(1<<29))
#define
CLKPWR_PCONP_PCGPDMA
((uint32_t)(1<<29))
/** Ethernet block power/clock control bit*/
/** Ethernet block power/clock control bit*/
#define
CLKPWR_PCONP_PCENET
((uint32_t)(1<<30))
#define
CLKPWR_PCONP_PCENET
((uint32_t)(1<<30))
/** USB interface power/clock control bit*/
/** USB interface power/clock control bit*/
#define
CLKPWR_PCONP_PCUSB
((uint32_t)(1<<31))
#define
CLKPWR_PCONP_PCUSB
((uint32_t)(1<<31))
/********************************************************************
/********************************************************************
* Power Control for Peripherals Definitions
* Power Control for Peripherals Definitions
**********************************************************************/
**********************************************************************/
#define CLKPWR_RSTCON0_LCD
((uint32_t)(0))
#define CLKPWR_RSTCON0_LCD
((uint32_t)(0))
#define CLKPWR_RSTCON0_TIM0
((uint32_t)(1))
#define CLKPWR_RSTCON0_TIM0
((uint32_t)(1))
#define CLKPWR_RSTCON0_TIM1
((uint32_t)(2))
#define CLKPWR_RSTCON0_TIM1
((uint32_t)(2))
#define CLKPWR_RSTCON0_UART0
((uint32_t)(3))
#define CLKPWR_RSTCON0_UART0
((uint32_t)(3))
#define CLKPWR_RSTCON0_UART1
((uint32_t)(4))
#define CLKPWR_RSTCON0_UART1
((uint32_t)(4))
#define CLKPWR_RSTCON0_PWM0
((uint32_t)(5))
#define CLKPWR_RSTCON0_PWM0
((uint32_t)(5))
#define CLKPWR_RSTCON0_PWM1
((uint32_t)(6))
#define CLKPWR_RSTCON0_PWM1
((uint32_t)(6))
#define CLKPWR_RSTCON0_I2C0
((uint32_t)(7))
#define CLKPWR_RSTCON0_I2C0
((uint32_t)(7))
#define CLKPWR_RSTCON0_UART4
((uint32_t)(8))
#define CLKPWR_RSTCON0_UART4
((uint32_t)(8))
#define CLKPWR_RSTCON0_RTC
((uint32_t)(9))
#define CLKPWR_RSTCON0_RTC
((uint32_t)(9))
#define CLKPWR_RSTCON0_SSP1
((uint32_t)(10))
#define CLKPWR_RSTCON0_SSP1
((uint32_t)(10))
#define CLKPWR_RSTCON0_EMC
((uint32_t)(11))
#define CLKPWR_RSTCON0_EMC
((uint32_t)(11))
#define CLKPWR_RSTCON0_ADC
((uint32_t)(12))
#define CLKPWR_RSTCON0_ADC
((uint32_t)(12))
#define CLKPWR_RSTCON0_CAN1
((uint32_t)(13))
#define CLKPWR_RSTCON0_CAN1
((uint32_t)(13))
#define CLKPWR_RSTCON0_CAN2
((uint32_t)(14))
#define CLKPWR_RSTCON0_CAN2
((uint32_t)(14))
#define CLKPWR_RSTCON0_GPIO
((uint32_t)(15))
#define CLKPWR_RSTCON0_GPIO
((uint32_t)(15))
#define CLKPWR_RSTCON0_MCPWM
((uint32_t)(17))
#define CLKPWR_RSTCON0_MCPWM
((uint32_t)(17))
#define CLKPWR_RSTCON0_QEI
((uint32_t)(18))
#define CLKPWR_RSTCON0_QEI
((uint32_t)(18))
#define CLKPWR_RSTCON0_I2C1
((uint32_t)(19))
#define CLKPWR_RSTCON0_I2C1
((uint32_t)(19))
#define CLKPWR_RSTCON0_SSP2
((uint32_t)(20))
#define CLKPWR_RSTCON0_SSP2
((uint32_t)(20))
#define CLKPWR_RSTCON0_SSP0
((uint32_t)(21))
#define CLKPWR_RSTCON0_SSP0
((uint32_t)(21))
#define CLKPWR_RSTCON0_TIM2
((uint32_t)(22))
#define CLKPWR_RSTCON0_TIM2
((uint32_t)(22))
#define CLKPWR_RSTCON0_TIM3
((uint32_t)(23))
#define CLKPWR_RSTCON0_TIM3
((uint32_t)(23))
#define CLKPWR_RSTCON0_UART2
((uint32_t)(24))
#define CLKPWR_RSTCON0_UART2
((uint32_t)(24))
#define CLKPWR_RSTCON0_UART3
((uint32_t)(25))
#define CLKPWR_RSTCON0_UART3
((uint32_t)(25))
#define CLKPWR_RSTCON0_I2C2
((uint32_t)(26))
#define CLKPWR_RSTCON0_I2C2
((uint32_t)(26))
#define CLKPWR_RSTCON0_I2S
((uint32_t)(27))
#define CLKPWR_RSTCON0_I2S
((uint32_t)(27))
#define CLKPWR_RSTCON0_SDC
((uint32_t)(28))
#define CLKPWR_RSTCON0_SDC
((uint32_t)(28))
#define CLKPWR_RSTCON0_GPDMA
((uint32_t)(29))
#define CLKPWR_RSTCON0_GPDMA
((uint32_t)(29))
#define CLKPWR_RSTCON0_ENET
((uint32_t)(30))
#define CLKPWR_RSTCON0_ENET
((uint32_t)(30))
#define CLKPWR_RSTCON0_USB
((uint32_t)(31))
#define CLKPWR_RSTCON0_USB
((uint32_t)(31))
#define CLKPWR_RSTCON1_IOCON
((uint32_t)(32))
#define CLKPWR_RSTCON1_IOCON
((uint32_t)(32))
#define CLKPWR_RSTCON1_DAC
((uint32_t)(33))
#define CLKPWR_RSTCON1_DAC
((uint32_t)(33))
#define CLKPWR_RSTCON1_CANACC
((uint32_t)(34))
#define CLKPWR_RSTCON1_CANACC
((uint32_t)(34))
/**
/**
* @}
* @}
*/
*/
/* External clock variable from system_LPC177x_8x.h */
/* External clock variable from system_LPC177x_8x.h */
extern
uint32_t
SystemCoreClock
;
/*!< System Clock Frequency (Core Clock)
*/
extern
uint32_t
SystemCoreClock
;
/*!< System Clock Frequency (Core Clock)
*/
extern
uint32_t
PeripheralClock
;
/*!< Peripheral Clock Frequency (Pclk)
*/
extern
uint32_t
PeripheralClock
;
/*!< Peripheral Clock Frequency (Pclk)
*/
extern
uint32_t
EMCClock
;
/*!< EMC Clock Frequency
*/
extern
uint32_t
EMCClock
;
/*!< EMC Clock Frequency
*/
/* External clock variable from lpc177x_8x_clkpwr.h */
/* External clock variable from lpc177x_8x_clkpwr.h */
extern
uint32_t
USBClock
;
/*!< USB Frequency
*/
extern
uint32_t
USBClock
;
/*!< USB Frequency
*/
/* Public Functions ----------------------------------------------------------- */
/* Public Functions ----------------------------------------------------------- */
/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions
/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions
...
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bsp/lpc178x/drivers/lpc177x_8x_emc.c
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bsp/lpc178x/drivers/lpc177x_8x_emc.h
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/**********************************************************************
/**********************************************************************
* $Id$
lpc177x_8x_emc.h
2011-06-02
* $Id$
lpc177x_8x_emc.h
2011-06-02
*//**
*//**
* @file
lpc177x_8x_emc.h
* @file
lpc177x_8x_emc.h
* @brief
Contains all macro definitions and function prototypes
* @brief
Contains all macro definitions and function prototypes
*
support for EMC firmware library on LPC177x_8x
*
support for EMC firmware library on LPC177x_8x
* @version
1.0
* @version
1.0
* @date
02. June. 2011
* @date
02. June. 2011
* @author
NXP MCU SW Application Team
* @author
NXP MCU SW Application Team
*
*
* Copyright(C) 2011, NXP Semiconductor
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
* All rights reserved.
*
*
...
@@ -25,7 +25,7 @@
...
@@ -25,7 +25,7 @@
**********************************************************************/
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup EMC
EMC (External Memory Controller)
/** @defgroup EMC
EMC (External Memory Controller)
* @ingroup LPC177x_8xCMSIS_FwLib_Drivers
* @ingroup LPC177x_8xCMSIS_FwLib_Drivers
* @{
* @{
*/
*/
...
@@ -45,233 +45,233 @@
...
@@ -45,233 +45,233 @@
* EMC Control Register (EMCControl)
* EMC Control Register (EMCControl)
**********************************************************************/
**********************************************************************/
/* Control register mask */
/* Control register mask */
#define EMC_Control_MASK
((uint32_t )0x07)
#define EMC_Control_MASK
((uint32_t )0x07)
/* Control register EMC: Enable control. */
/* Control register EMC: Enable control. */
#define EMC_Control_E
((uint32_t )(1<<0))
#define EMC_Control_E
((uint32_t )(1<<0))
/* Control register EMC: Address mirror control. */
/* Control register EMC: Address mirror control. */
#define EMC_Control_M
((uint32_t )(1<<1))
#define EMC_Control_M
((uint32_t )(1<<1))
/* Control register EMC: Low-power mode control. */
/* Control register EMC: Low-power mode control. */
#define EMC_Control_L
((uint32_t )(1<<2))
#define EMC_Control_L
((uint32_t )(1<<2))
/***********************************************************************
/***********************************************************************
* EMC Status Register (EMCStatus)
* EMC Status Register (EMCStatus)
**********************************************************************/
**********************************************************************/
/* Status register mask */
/* Status register mask */
#define EMC_Status_MASK
((uint32_t )0x07)
#define EMC_Status_MASK
((uint32_t )0x07)
/* Status register EMC: Busy. */
/* Status register EMC: Busy. */
#define EMC_Status_B
((uint32_t )(1<<0))
#define EMC_Status_B
((uint32_t )(1<<0))
/* Status register EMC: Write buffer status. */
/* Status register EMC: Write buffer status. */
#define EMC_Status_S
((uint32_t )(1<<1))
#define EMC_Status_S
((uint32_t )(1<<1))
/* Status register EMC: Self-refresh acknowledge.. */
/* Status register EMC: Self-refresh acknowledge.. */
#define EMC_Status_SA
((uint32_t )(1<<2))
#define EMC_Status_SA
((uint32_t )(1<<2))
/***********************************************************************
/***********************************************************************
* EMC Configuration register (EMCConfig)
* EMC Configuration register (EMCConfig)
**********************************************************************/
**********************************************************************/
/* EMC Configuration register : Enable control. */
/* EMC Configuration register : Enable control. */
#define EMC_Config_Endian_Mode
((uint32_t )(1<<0))
#define EMC_Config_Endian_Mode
((uint32_t )(1<<0))
/* EMC Configuration register: CCLK. */
/* EMC Configuration register: CCLK. */
#define EMC_Config_CCLK
((uinr32_t)(1<<8))
#define EMC_Config_CCLK
((uinr32_t)(1<<8))
/* EMC Configuration register mask */
/* EMC Configuration register mask */
#define EMC_Config_MASK
((uint32_t)(0x101))
#define EMC_Config_MASK
((uint32_t)(0x101))
/***********************************************************************
/***********************************************************************
* Dynamic Memory Control register (EMCDynamicControl)
* Dynamic Memory Control register (EMCDynamicControl)
**********************************************************************/
**********************************************************************/
/* Dynamic Memory Control register EMC: Dynamic memory clock enable. */
/* Dynamic Memory Control register EMC: Dynamic memory clock enable. */
#define EMC_DynamicControl_CE
((uint32_t )(1<<0))
#define EMC_DynamicControl_CE
((uint32_t )(1<<0))
/* Dynamic Memory Control register EMC: Dynamic memory clock control */
/* Dynamic Memory Control register EMC: Dynamic memory clock control */
#define EMC_DynamicControl_CS
((uint32_t )(1<<1))
#define EMC_DynamicControl_CS
((uint32_t )(1<<1))
/* Dynamic Memory Control register EMC: Self-refresh request, EMCSREFREQ*/
/* Dynamic Memory Control register EMC: Self-refresh request, EMCSREFREQ*/
#define EMC_DynamicControl_SR
((uint32_t )(1<<2))
#define EMC_DynamicControl_SR
((uint32_t )(1<<2))
/* Dynamic Memory Control register EMC: Memory clock control (MMC)*/
/* Dynamic Memory Control register EMC: Memory clock control (MMC)*/
#define EMC_DynamicControl_MMC
((uint32_t )(1<<5))
#define EMC_DynamicControl_MMC
((uint32_t )(1<<5))
/* Dynamic Memory Control register EMC: SDRAM initialization*/
/* Dynamic Memory Control register EMC: SDRAM initialization*/
#define EMC_DynamicControl_I(n)
((uint32_t )(n<<7))
#define EMC_DynamicControl_I(n)
((uint32_t )(n<<7))
/* Dynamic Memory Control register EMC: Low-power SDRAM deep-sleep mode (DP)*/
/* Dynamic Memory Control register EMC: Low-power SDRAM deep-sleep mode (DP)*/
#define EMC_DynamicControl_DP
((uint32_t ) (1<<13))
#define EMC_DynamicControl_DP
((uint32_t ) (1<<13))
/***********************************************************************
/***********************************************************************
* Dynamic Memory Refresh Timer register (EMCDynamicRefresh)
* Dynamic Memory Refresh Timer register (EMCDynamicRefresh)
**********************************************************************/
**********************************************************************/
/* Dynamic Memory Refresh Timer register EMC: Refresh timer (REFRESH) */
/* Dynamic Memory Refresh Timer register EMC: Refresh timer (REFRESH) */
#define EMC_DynamicRefresh_REFRESH(n)
((uint32_t ) (n & 0x3ff))
#define EMC_DynamicRefresh_REFRESH(n)
((uint32_t ) (n & 0x3ff))
/***********************************************************************
/***********************************************************************
* Dynamic Memory Read Configuration register (EMCDynamicReadConfig)
* Dynamic Memory Read Configuration register (EMCDynamicReadConfig)
**********************************************************************/
**********************************************************************/
/* EMCDynamicReadConfig register EMC:Read data strategy (RD) */
/* EMCDynamicReadConfig register EMC:Read data strategy (RD) */
#define EMC_DynamicReadConfig_RD(n)
((uint32_t )(n & 0x03))
#define EMC_DynamicReadConfig_RD(n)
((uint32_t )(n & 0x03))
/***********************************************************************
/***********************************************************************
* Dynamic Memory Percentage Command Period register (EMCDynamictRP)
* Dynamic Memory Percentage Command Period register (EMCDynamictRP)
**********************************************************************/
**********************************************************************/
/* EMCDynamictRP register EMC: Precharge command period (tRP). */
/* EMCDynamictRP register EMC: Precharge command period (tRP). */
#define EMC_DynamictRP_tRP(n)
((uint32_t )(n & 0x0f))
#define EMC_DynamictRP_tRP(n)
((uint32_t )(n & 0x0f))
/***********************************************************************
/***********************************************************************
* Dynamic Memory Active to Precharge Command Period register (EMCDynamictRAS)
* Dynamic Memory Active to Precharge Command Period register (EMCDynamictRAS)
**********************************************************************/
**********************************************************************/
/* EMCDynamictRAS register EMC: Active to precharge command period (tRAS) */
/* EMCDynamictRAS register EMC: Active to precharge command period (tRAS) */
#define EMC_DynamictRP_tRAS(n)
((uint32_t )(n & 0x0f))
#define EMC_DynamictRP_tRAS(n)
((uint32_t )(n & 0x0f))
/***********************************************************************
/***********************************************************************
* Dynamic Memory Last Data Out to Active Time register (EMCDynamictAPR)
* Dynamic Memory Last Data Out to Active Time register (EMCDynamictAPR)
**********************************************************************/
**********************************************************************/
/* EMCDynamictAPR register EMC: Last-data-out to active command time (tAPR) */
/* EMCDynamictAPR register EMC: Last-data-out to active command time (tAPR) */
#define EMC_DynamictAPR_tAPR(n)
((uint32_t )(n & 0x0f))
#define EMC_DynamictAPR_tAPR(n)
((uint32_t )(n & 0x0f))
/***********************************************************************
/***********************************************************************
* Dynamic Memory Data-in to Active Command Time register (EMCDynamictDAL)
* Dynamic Memory Data-in to Active Command Time register (EMCDynamictDAL)
**********************************************************************/
**********************************************************************/
/* EMCDynamictDAL register EMC: Data-in to active command (tDAL)*/
/* EMCDynamictDAL register EMC: Data-in to active command (tDAL)*/
#define EMC_DynamictDAL_tDAL(n)
((uint32_t )(n & 0x0f))
#define EMC_DynamictDAL_tDAL(n)
((uint32_t )(n & 0x0f))
/***********************************************************************
/***********************************************************************
* Dynamic Memory Write Recovery Time register (EMCDynamictWR)
* Dynamic Memory Write Recovery Time register (EMCDynamictWR)
**********************************************************************/
**********************************************************************/
/* EMCDynamictWR register EMC: Write recovery time (tWR)*/
/* EMCDynamictWR register EMC: Write recovery time (tWR)*/
#define EMC_DynamictWR_tWR(n)
(uint32_t )(n & 0x0f)
#define EMC_DynamictWR_tWR(n)
(uint32_t )(n & 0x0f)
/***********************************************************************
/***********************************************************************
* Dynamic Memory Active to Active Command Period register (EMCDynamictRC)
* Dynamic Memory Active to Active Command Period register (EMCDynamictRC)
**********************************************************************/
**********************************************************************/
/* EMCDynamictRC register EMC: Active to active command period (tRC)*/
/* EMCDynamictRC register EMC: Active to active command period (tRC)*/
#define EMC_DynamictRC_tRC(n)
(uint32_t )(n & 0x1f)
#define EMC_DynamictRC_tRC(n)
(uint32_t )(n & 0x1f)
/***********************************************************************
/***********************************************************************
* Dynamic Memory Auto-refresh Period register (EMCDynamictRFC)
* Dynamic Memory Auto-refresh Period register (EMCDynamictRFC)
**********************************************************************/
**********************************************************************/
/* EMCDynamictRFC register EMC: Auto-refresh period and auto-refresh to active command period (tRFC)*/
/* EMCDynamictRFC register EMC: Auto-refresh period and auto-refresh to active command period (tRFC)*/
#define EMC_DynamictRFC_tRFC(n)
((uint32_t )(n & 0x1f))
#define EMC_DynamictRFC_tRFC(n)
((uint32_t )(n & 0x1f))
/***********************************************************************
/***********************************************************************
* Dynamic Memory Exit Self-refresh register (EMCDynamictXSR)
* Dynamic Memory Exit Self-refresh register (EMCDynamictXSR)
**********************************************************************/
**********************************************************************/
/* EMCDynamictXSR register EMC: Exit self-refresh to active command time (tXSR)*/
/* EMCDynamictXSR register EMC: Exit self-refresh to active command time (tXSR)*/
#define EMC_DynamictXSR_tXSR(n)
((uint32_t )(n & 0x1f))
#define EMC_DynamictXSR_tXSR(n)
((uint32_t )(n & 0x1f))
/***********************************************************************
/***********************************************************************
* Dynamic Memory Active Bank A to Active Bank B Time register (EMCDynamictRRD)
* Dynamic Memory Active Bank A to Active Bank B Time register (EMCDynamictRRD)
**********************************************************************/
**********************************************************************/
/* EMCDynamictRRD register EMC: Active bank A to active bank B latency (tRRD )*/
/* EMCDynamictRRD register EMC: Active bank A to active bank B latency (tRRD )*/
#define EMC_DynamictRRD_tRRD(n)
((uint32_t )(n & 0x0f))
#define EMC_DynamictRRD_tRRD(n)
((uint32_t )(n & 0x0f))
/***********************************************************************
/***********************************************************************
Dynamic Memory Load Mode register to Active Command Time (EMCDynamictMRD)
Dynamic Memory Load Mode register to Active Command Time (EMCDynamictMRD)
**********************************************************************/
**********************************************************************/
/* EMCDynamictMRD register EMC: Load mode register to active command time (tMRD)*/
/* EMCDynamictMRD register EMC: Load mode register to active command time (tMRD)*/
#define EMC_DynamictMRD_tMRD(n)
((uint32_t )(n & 0x1f))
#define EMC_DynamictMRD_tMRD(n)
((uint32_t )(n & 0x1f))
/***********************************************************************
/***********************************************************************
* Static Memory Extended Wait Register (EMCStaticExtendedWait)
* Static Memory Extended Wait Register (EMCStaticExtendedWait)
**********************************************************************/
**********************************************************************/
/* StaticExtendedWait register EMC: External wait time out. */
/* StaticExtendedWait register EMC: External wait time out. */
#define EMC_StaticExtendedWait_EXTENDEDWAIT(n)
((uint32_t )(n & 0x3ff))
#define EMC_StaticExtendedWait_EXTENDEDWAIT(n)
((uint32_t )(n & 0x3ff))
/***********************************************************************
/***********************************************************************
* Dynamic Memory Configuration registers (EMCDynamicConfig0-3)
* Dynamic Memory Configuration registers (EMCDynamicConfig0-3)
**********************************************************************/
**********************************************************************/
/* DynamicConfig register EMC: Memory device (MD). */
/* DynamicConfig register EMC: Memory device (MD). */
#define EMC_DynamicConfig_MD(n)
((uint32_t )(n << 3))
#define EMC_DynamicConfig_MD(n)
((uint32_t )(n << 3))
/* DynamicConfig register EMC: Address mapping (AM) */
/* DynamicConfig register EMC: Address mapping (AM) */
#define EMC_DynamicConfig_AM1(n)
((uint32_t )(n << 7))
#define EMC_DynamicConfig_AM1(n)
((uint32_t )(n << 7))
/* DynamicConfig register EMC: Address mapping (AM) */
/* DynamicConfig register EMC: Address mapping (AM) */
#define EMC_DynamicConfig_AM2(n)
((uint32_t )(1 << 14))
#define EMC_DynamicConfig_AM2(n)
((uint32_t )(1 << 14))
/* DynamicConfig register EMC: Buffer enable */
/* DynamicConfig register EMC: Buffer enable */
#define EMC_DynamicConfig_B
((uint32_t )(1 << 19))
#define EMC_DynamicConfig_B
((uint32_t )(1 << 19))
/* DynamicConfig register EMC: Write protect (P) */
/* DynamicConfig register EMC: Write protect (P) */
#define EMC_DynamicConfig_P
((uint32_t )(1 << 20))
#define EMC_DynamicConfig_P
((uint32_t )(1 << 20))
/***********************************************************************
/***********************************************************************
* Dynamic Memory RAS & CAS Delay registers (EMCDynamicRASCAS0-3)
* Dynamic Memory RAS & CAS Delay registers (EMCDynamicRASCAS0-3)
**********************************************************************/
**********************************************************************/
/* DynamicRASCAS register EMC: RAS latency (active to read/write delay) (RAS). */
/* DynamicRASCAS register EMC: RAS latency (active to read/write delay) (RAS). */
#define EMC_DynamicConfig_RAS(n)
((uint32_t )(n & 0x03))
#define EMC_DynamicConfig_RAS(n)
((uint32_t )(n & 0x03))
/* DynamicRASCAS register EMC: CAS latency (CAS)*/
/* DynamicRASCAS register EMC: CAS latency (CAS)*/
#define EMC_DynamicConfig_CAS(n)
((uint32_t )(n << 8))
#define EMC_DynamicConfig_CAS(n)
((uint32_t )(n << 8))
/***********************************************************************
/***********************************************************************
* Static Memory Configuration registers (EMCStaticConfig0-3)
* Static Memory Configuration registers (EMCStaticConfig0-3)
**********************************************************************/
**********************************************************************/
/* StaticConfig register EMC: Memory width (MW). */
/* StaticConfig register EMC: Memory width (MW). */
#define EMC_StaticConfig_MW(n)
((uint32_t )(n & 0x03))
#define EMC_StaticConfig_MW(n)
((uint32_t )(n & 0x03))
/* StaticConfig register EMC: Memory width 8bit . */
/* StaticConfig register EMC: Memory width 8bit . */
#define EMC_StaticConfig_MW_8BITS
(EMC_StaticConfig_MW(0))
#define EMC_StaticConfig_MW_8BITS
(EMC_StaticConfig_MW(0))
/* StaticConfig register EMC: Memory width 16bit . */
/* StaticConfig register EMC: Memory width 16bit . */
#define EMC_StaticConfig_MW_16BITS
(EMC_StaticConfig_MW(1))
#define EMC_StaticConfig_MW_16BITS
(EMC_StaticConfig_MW(1))
/* StaticConfig register EMC: Memory width 32bit . */
/* StaticConfig register EMC: Memory width 32bit . */
#define EMC_StaticConfig_MW_32BITS
(EMC_StaticConfig_MW(2))
#define EMC_StaticConfig_MW_32BITS
(EMC_StaticConfig_MW(2))
/* StaticConfig register EMC: Page mode (PM) */
/* StaticConfig register EMC: Page mode (PM) */
#define EMC_StaticConfig_PM
((uint32_t )(1 << 3))
#define EMC_StaticConfig_PM
((uint32_t )(1 << 3))
/* StaticConfig register EMC: Chip select polarity (PC) */
/* StaticConfig register EMC: Chip select polarity (PC) */
#define EMC_StaticConfig_PC
((uint32_t )(1 << 6))
#define EMC_StaticConfig_PC
((uint32_t )(1 << 6))
/* StaticConfig register EMC: Byte lane state (PB) */
/* StaticConfig register EMC: Byte lane state (PB) */
#define EMC_StaticConfig_PB
((uint32_t )(1 << 7))
#define EMC_StaticConfig_PB
((uint32_t )(1 << 7))
/* StaticConfig register EMC: Extended wait (EW) */
/* StaticConfig register EMC: Extended wait (EW) */
#define EMC_StaticConfig_EW
((uint32_t )(1 << 8))
#define EMC_StaticConfig_EW
((uint32_t )(1 << 8))
/* StaticConfig register EMC: Buffer enable (B) */
/* StaticConfig register EMC: Buffer enable (B) */
#define EMC_StaticConfig_B
((uint32_t )(1 << 19))
#define EMC_StaticConfig_B
((uint32_t )(1 << 19))
/* StaticConfig register EMC: Write protect (P) */
/* StaticConfig register EMC: Write protect (P) */
#define EMC_StaticConfig_P
((uint32_t )(1 << 20))
#define EMC_StaticConfig_P
((uint32_t )(1 << 20))
/***********************************************************************
/***********************************************************************
* Static Memory Write Enable Delay registers (EMCStaticWaitWen0-3)
* Static Memory Write Enable Delay registers (EMCStaticWaitWen0-3)
**********************************************************************/
**********************************************************************/
/* StaticWaitWen register EMC: Wait write enable (WAITWEN). */
/* StaticWaitWen register EMC: Wait write enable (WAITWEN). */
#define EMC_StaticWaitWen_WAITWEN(n)
((uint32_t )(n & 0x0f))
#define EMC_StaticWaitWen_WAITWEN(n)
((uint32_t )(n & 0x0f))
/***********************************************************************
/***********************************************************************
* Static Memory Output Enable Delay registers (EMCStaticWaitOen0-3)
* Static Memory Output Enable Delay registers (EMCStaticWaitOen0-3)
**********************************************************************/
**********************************************************************/
/* StaticWaitOen register EMC: Wait output enable (WAITOEN). */
/* StaticWaitOen register EMC: Wait output enable (WAITOEN). */
#define EMC_StaticWaitOen_WAITOEN(n)
((uint32_t )(n & 0x0f))
#define EMC_StaticWaitOen_WAITOEN(n)
((uint32_t )(n & 0x0f))
/***********************************************************************
/***********************************************************************
* Static Memory Read Delay registers (EMCStaticWaitRd0-3)
* Static Memory Read Delay registers (EMCStaticWaitRd0-3)
**********************************************************************/
**********************************************************************/
/* StaticWaitRd register EMC: Non-page mode read wait states or asynchronous page mode
/* StaticWaitRd register EMC: Non-page mode read wait states or asynchronous page mode
read first access wait state (WAITRD) */
read first access wait state (WAITRD) */
#define EMC_StaticWaitRd_WAITRD(n)
((uint32_t )(n & 0x1f))
#define EMC_StaticWaitRd_WAITRD(n)
((uint32_t )(n & 0x1f))
/***********************************************************************
/***********************************************************************
* Static Memory Page Mode Read Delay registers (EMCStaticwaitPage0-3)
* Static Memory Page Mode Read Delay registers (EMCStaticwaitPage0-3)
**********************************************************************/
**********************************************************************/
/* StaticwaitPage register EMC: Asynchronous page mode read after the first
/* StaticwaitPage register EMC: Asynchronous page mode read after the first
read wait states (WAITPAGE). */
read wait states (WAITPAGE). */
#define EMC_StaticwaitPage_WAITPAGE(n)
((uint32_t )(n & 0x1f))
#define EMC_StaticwaitPage_WAITPAGE(n)
((uint32_t )(n & 0x1f))
/***********************************************************************
/***********************************************************************
* Static Memory Write Delay registers (EMCStaticWaitwr0-3)
* Static Memory Write Delay registers (EMCStaticWaitwr0-3)
**********************************************************************/
**********************************************************************/
/* StaticWaitwr register EMC: Write wait states (WAITWR). */
/* StaticWaitwr register EMC: Write wait states (WAITWR). */
#define EMC_StaticWaitwr_WAITWR(n)
((uint32_t )(n & 0x1f))
#define EMC_StaticWaitwr_WAITWR(n)
((uint32_t )(n & 0x1f))
/***********************************************************************
/***********************************************************************
* Static Memory Turn Round Delay registers (EMCStaticWaitTurn0-3)
* Static Memory Turn Round Delay registers (EMCStaticWaitTurn0-3)
**********************************************************************/
**********************************************************************/
/* StaticWaitTurn register EMC: Bus turnaround cycles (WAITTURN). */
/* StaticWaitTurn register EMC: Bus turnaround cycles (WAITTURN). */
#define EMC_StaticWaitTurn_WAITTURN(n)
((uint32_t )(n & 0x0f))
#define EMC_StaticWaitTurn_WAITTURN(n)
((uint32_t )(n & 0x0f))
/***********************************************************************
/***********************************************************************
* Delay Control register (EMCDLYCTL)
* Delay Control register (EMCDLYCTL)
**********************************************************************/
**********************************************************************/
#define EMC_DLYCTL_CMDDLY(n)
((uint32_t)(n&0x1F))
#define EMC_DLYCTL_CMDDLY(n)
((uint32_t)(n&0x1F))
#define EMC_DLYCTL_FBCLKDLY(n)
((uint32_t)((n&0x1F)<<8))
#define EMC_DLYCTL_FBCLKDLY(n)
((uint32_t)((n&0x1F)<<8))
#define EMC_DLYCTL_CLKOUT0DLY(n)
((uint32_t)((n&0x1F)<<16))
#define EMC_DLYCTL_CLKOUT0DLY(n)
((uint32_t)((n&0x1F)<<16))
#define EMC_DLYCTL_CLKOUT1DLY(n)
((uint32_t)((n&0x1F)<<24))
#define EMC_DLYCTL_CLKOUT1DLY(n)
((uint32_t)((n&0x1F)<<24))
/***********************************************************************
/***********************************************************************
* EMC Calibration register (EMCCAL)
* EMC Calibration register (EMCCAL)
**********************************************************************/
**********************************************************************/
#define EMC_CAL_CALVALUE(n)
((uint32_t)(n&0xFF))
#define EMC_CAL_CALVALUE(n)
((uint32_t)(n&0xFF))
#define EMC_CAL_START
((uint32_t)(1<<14))
#define EMC_CAL_START
((uint32_t)(1<<14))
#define EMC_CAL_DONE
((uint32_t)(1<<15))
#define EMC_CAL_DONE
((uint32_t)(1<<15))
#define EMC_LITTLE_ENDIAN_MODE
((uint32_t)(0))
#define EMC_LITTLE_ENDIAN_MODE
((uint32_t)(0))
#define EMC_BIG_ENDIAN_MODE
((uint32_t)(1))
#define EMC_BIG_ENDIAN_MODE
((uint32_t)(1))
/**
/**
* @}
* @}
...
...
bsp/lpc178x/drivers/lpc177x_8x_pinsel.c
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bsp/lpc178x/drivers/lpc177x_8x_uart.h
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bsp/lpc178x/drivers/lpc17xx_lcd.c
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bsp/lpc178x/drivers/lpc_types.h
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/**********************************************************************
/**********************************************************************
* $Id$
lpc_types.h
2011-06-02
* $Id$
lpc_types.h
2011-06-02
*//**
*//**
* @file
lpc_types.h
* @file
lpc_types.h
* @brief
Contains the NXP ABL typedefs for C standard types.
* @brief
Contains the NXP ABL typedefs for C standard types.
*
It is intended to be used in ISO C conforming development
*
It is intended to be used in ISO C conforming development
*
environments and checks for this insofar as it is possible
*
environments and checks for this insofar as it is possible
*
to do so.
*
to do so.
* @version
1.0
* @version
1.0
* @date
02. June. 2011
* @date
02. June. 2011
* @author
NXP MCU SW Application Team
* @author
NXP MCU SW Application Team
*
*
* Copyright(C) 2011, NXP Semiconductor
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
* All rights reserved.
*
*
...
@@ -37,7 +37,7 @@
...
@@ -37,7 +37,7 @@
* @ingroup LPC177x_8xCMSIS_FwLib_Drivers
* @ingroup LPC177x_8xCMSIS_FwLib_Drivers
* @{
* @{
*/
*/
/* Public Types --------------------------------------------------------------- */
/* Public Types --------------------------------------------------------------- */
/** @defgroup LPC_Types_Public_Types Basic Public Data Types
/** @defgroup LPC_Types_Public_Types Basic Public Data Types
* @{
* @{
...
@@ -71,8 +71,8 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
...
@@ -71,8 +71,8 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} Status;
*/
*/
typedef
enum
typedef
enum
{
{
NONE_BLOCKING
=
0
,
/**< None Blocking type */
NONE_BLOCKING
=
0
,
/**< None Blocking type */
BLOCKING
,
/**< Blocking type */
BLOCKING
,
/**< Blocking type */
}
TRANSFER_BLOCK_Type
;
}
TRANSFER_BLOCK_Type
;
...
@@ -98,7 +98,7 @@ typedef int32_t(*PFI)();
...
@@ -98,7 +98,7 @@ typedef int32_t(*PFI)();
*/
*/
#undef _BIT
#undef _BIT
/** Set bit macro */
/** Set bit macro */
#define _BIT(n)
(1<<n)
#define _BIT(n)
(1<<n)
/** _SBF(f,v) sets the bit field starting at position "f" to value "v".
/** _SBF(f,v) sets the bit field starting at position "f" to value "v".
* _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
* _SBF(f,v) is intended to be used in "OR" and "AND" expressions:
...
@@ -161,16 +161,16 @@ typedef uint8_t UNS_8;
...
@@ -161,16 +161,16 @@ typedef uint8_t UNS_8;
typedef
int8_t
INT_8
;
typedef
int8_t
INT_8
;
/** SMA type for 16 bit unsigned value */
/** SMA type for 16 bit unsigned value */
typedef
uint16_t
UNS_16
;
typedef
uint16_t
UNS_16
;
/** SMA type for 16 bit signed value */
/** SMA type for 16 bit signed value */
typedef
int16_t
INT_16
;
typedef
int16_t
INT_16
;
/** SMA type for 32 bit unsigned value */
/** SMA type for 32 bit unsigned value */
typedef
uint32_t
UNS_32
;
typedef
uint32_t
UNS_32
;
/** SMA type for 32 bit signed value */
/** SMA type for 32 bit signed value */
typedef
int32_t
INT_32
;
typedef
int32_t
INT_32
;
/** SMA type for 64 bit signed value */
/** SMA type for 64 bit signed value */
typedef
int64_t
INT_64
;
typedef
int64_t
INT_64
;
...
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bsp/lpc178x/drivers/sdram.c
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bsp/lpc178x/drivers/sdram.h
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/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#ifndef SDRAM_H_INCLUDED
#ifndef SDRAM_H_INCLUDED
#define SDRAM_H_INCLUDED
#define SDRAM_H_INCLUDED
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bsp/lpc2148/applications/application.c
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/*
/*
* Copyright (c) 2006-20
18
, RT-Thread Development Team
* Copyright (c) 2006-20
21
, RT-Thread Development Team
*
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-License-Identifier: Apache-2.0
*
*
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