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6e3c629c
编写于
11月 15, 2017
作者:
T
tanek liang
提交者:
Bernard Xiong
11月 16, 2017
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差异文件
[bsp] lpc54608 update CMSIS lib to V5.0.3
上级
dcce8489
变更
21
展开全部
隐藏空白更改
内联
并排
Showing
21 changed file
with
15190 addition
and
1499 deletion
+15190
-1499
bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/arm_common_tables.h
...SDK_2.2_LPCXpresso54608/CMSIS/Include/arm_common_tables.h
+54
-69
bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/arm_const_structs.h
...SDK_2.2_LPCXpresso54608/CMSIS/Include/arm_const_structs.h
+27
-40
bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/arm_math.h
...CXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/arm_math.h
+280
-177
bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_armcc.h
...resso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_armcc.h
+125
-45
bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_armclang.h
...so/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_armclang.h
+1802
-0
bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_compiler.h
...so/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_compiler.h
+353
-0
bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_gcc.h
...Xpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_gcc.h
+785
-179
bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_version.h
...sso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_version.h
+39
-0
bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_armv8mbl.h
...sso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_armv8mbl.h
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-0
bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_armv8mml.h
...sso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_armv8mml.h
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bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm0.h
...CXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm0.h
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-120
bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm0plus.h
...esso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm0plus.h
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-124
bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm23.h
...Xpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm23.h
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bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm3.h
...CXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm3.h
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bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm33.h
...Xpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm33.h
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bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm4.h
...CXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm4.h
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bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm7.h
...CXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_cm7.h
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bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_sc000.h
...presso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_sc000.h
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-122
bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_sc300.h
...presso/SDK_2.2_LPCXpresso54608/CMSIS/Include/core_sc300.h
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bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/mpu_armv7.h
...Xpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/mpu_armv7.h
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bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/tz_context.h
...presso/SDK_2.2_LPCXpresso54608/CMSIS/Include/tz_context.h
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未找到文件。
bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/arm_common_tables.h
浏览文件 @
6e3c629c
/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 19. October 2015
* $Revision: V.1.4.5 a
*
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
*
* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
* Project: CMSIS DSP Library
* Title: arm_common_tables.h
* Description: Extern declaration for common tables
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _ARM_COMMON_TABLES_H
#define _ARM_COMMON_TABLES_H
...
...
@@ -46,8 +34,6 @@
extern
const
uint16_t
armBitRevTable
[
1024
];
extern
const
q15_t
armRecipTableQ15
[
64
];
extern
const
q31_t
armRecipTableQ31
[
64
];
/* extern const q31_t realCoefAQ31[1024]; */
/* extern const q31_t realCoefBQ31[1024]; */
extern
const
float32_t
twiddleCoef_16
[
32
];
extern
const
float32_t
twiddleCoef_32
[
64
];
extern
const
float32_t
twiddleCoef_64
[
128
];
...
...
@@ -85,45 +71,44 @@ extern const float32_t twiddleCoef_rfft_1024[1024];
extern
const
float32_t
twiddleCoef_rfft_2048
[
2048
];
extern
const
float32_t
twiddleCoef_rfft_4096
[
4096
];
/* floating-point bit reversal tables */
#define ARMBITREVINDEXTABLE_
_16_TABLE_LENGTH ((uint16_t)20
)
#define ARMBITREVINDEXTABLE_
_32_TABLE_LENGTH ((uint16_t)48
)
#define ARMBITREVINDEXTABLE_
_64_TABLE_LENGTH ((uint16_t)56
)
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208
)
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440
)
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448
)
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
#define ARMBITREVINDEXTABLE_
16_TABLE_LENGTH ((uint16_t)20
)
#define ARMBITREVINDEXTABLE_
32_TABLE_LENGTH ((uint16_t)48
)
#define ARMBITREVINDEXTABLE_
64_TABLE_LENGTH ((uint16_t)56
)
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
#define ARMBITREVINDEXTABLE
_
1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE
_
2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE
_
4096_TABLE_LENGTH ((uint16_t)4032)
extern
const
uint16_t
armBitRevIndexTable16
[
ARMBITREVINDEXTABLE_
_
16_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable32
[
ARMBITREVINDEXTABLE_
_
32_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable64
[
ARMBITREVINDEXTABLE_
_
64_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable16
[
ARMBITREVINDEXTABLE_16_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable32
[
ARMBITREVINDEXTABLE_32_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable64
[
ARMBITREVINDEXTABLE_64_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable128
[
ARMBITREVINDEXTABLE_128_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable256
[
ARMBITREVINDEXTABLE_256_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable512
[
ARMBITREVINDEXTABLE_512_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable1024
[
ARMBITREVINDEXTABLE1024_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable2048
[
ARMBITREVINDEXTABLE2048_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable4096
[
ARMBITREVINDEXTABLE4096_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable1024
[
ARMBITREVINDEXTABLE
_
1024_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable2048
[
ARMBITREVINDEXTABLE
_
2048_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable4096
[
ARMBITREVINDEXTABLE
_
4096_TABLE_LENGTH
];
/* fixed-point bit reversal tables */
#define ARMBITREVINDEXTABLE_FIXED_
__16_TABLE_LENGTH ((uint16_t)12
)
#define ARMBITREVINDEXTABLE_FIXED_
__32_TABLE_LENGTH ((uint16_t)24
)
#define ARMBITREVINDEXTABLE_FIXED_
__64_TABLE_LENGTH ((uint16_t)56
)
#define ARMBITREVINDEXTABLE_FIXED_
_128_TABLE_LENGTH ((uint16_t)112
)
#define ARMBITREVINDEXTABLE_FIXED_
_256_TABLE_LENGTH ((uint16_t)240
)
#define ARMBITREVINDEXTABLE_FIXED_
_512_TABLE_LENGTH ((uint16_t)480
)
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992
)
#define ARMBITREVINDEXTABLE_FIXED_
16_TABLE_LENGTH ((uint16_t)12
)
#define ARMBITREVINDEXTABLE_FIXED_
32_TABLE_LENGTH ((uint16_t)24
)
#define ARMBITREVINDEXTABLE_FIXED_
64_TABLE_LENGTH ((uint16_t)56
)
#define ARMBITREVINDEXTABLE_FIXED_
128_TABLE_LENGTH ((uint16_t)112
)
#define ARMBITREVINDEXTABLE_FIXED_
256_TABLE_LENGTH ((uint16_t)240
)
#define ARMBITREVINDEXTABLE_FIXED_
512_TABLE_LENGTH ((uint16_t)480
)
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
extern
const
uint16_t
armBitRevIndexTable_fixed_16
[
ARMBITREVINDEXTABLE_FIXED_
__
16_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable_fixed_32
[
ARMBITREVINDEXTABLE_FIXED_
__
32_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable_fixed_64
[
ARMBITREVINDEXTABLE_FIXED_
__
64_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable_fixed_128
[
ARMBITREVINDEXTABLE_FIXED_
_
128_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable_fixed_256
[
ARMBITREVINDEXTABLE_FIXED_
_
256_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable_fixed_512
[
ARMBITREVINDEXTABLE_FIXED_
_
512_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable_fixed_16
[
ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable_fixed_32
[
ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable_fixed_64
[
ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable_fixed_128
[
ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable_fixed_256
[
ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable_fixed_512
[
ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable_fixed_1024
[
ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable_fixed_2048
[
ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable_fixed_4096
[
ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH
];
...
...
bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/arm_const_structs.h
浏览文件 @
6e3c629c
/* ----------------------------------------------------------------------
* Copyright (C) 2010-2014 ARM Limited. All rights reserved.
*
* $Date: 19. March 2015
* $Revision: V.1.4.5
*
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
*
* Description: This file has constant structs that are initialized for
* user convenience. For example, some can be given as
* arguments to the arm_cfft_f32() function.
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
* Project: CMSIS DSP Library
* Title: arm_const_structs.h
* Description: Constant structs that are initialized for user convenience.
* For example, some can be given as arguments to the arm_cfft_f32() function.
*
* $Date: 27. January 2017
* $Revision: V.1.5.1
*
* Target Processor: Cortex-M cores
* -------------------------------------------------------------------- */
/*
* Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _ARM_CONST_STRUCTS_H
#define _ARM_CONST_STRUCTS_H
...
...
bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/arm_math.h
浏览文件 @
6e3c629c
此差异已折叠。
点击以展开。
bsp/lpc54608-LPCXpresso/SDK_2.2_LPCXpresso54608/CMSIS/Include/cmsis_armcc.h
浏览文件 @
6e3c629c
/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS
Cortex-M Core Function/Instruction Header F
ile
* @version V
4.30
* @date
20. October 2015
* @brief CMSIS
compiler ARMCC (ARM compiler V5) header f
ile
* @version V
5.0.2
* @date
13. February 2017
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
...
...
@@ -40,13 +30,93 @@
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32
/* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
...
...
@@ -181,7 +251,8 @@ __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
}
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
...
...
@@ -256,13 +327,14 @@ __STATIC_INLINE uint32_t __get_FAULTMASK(void)
__STATIC_INLINE
void
__set_FAULTMASK
(
uint32_t
faultMask
)
{
register
uint32_t
__regFaultMask
__ASM
(
"faultmask"
);
__regFaultMask
=
(
faultMask
&
(
uint32_t
)
1
);
__regFaultMask
=
(
faultMask
&
(
uint32_t
)
1
U
);
}
#endif
/* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
#endif
/* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
#if
(__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U
)
#if
((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))
)
/**
\brief Get FPSCR
...
...
@@ -271,7 +343,8 @@ __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
*/
__STATIC_INLINE
uint32_t
__get_FPSCR
(
void
)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register
uint32_t
__regfpscr
__ASM
(
"fpscr"
);
return
(
__regfpscr
);
#else
...
...
@@ -287,13 +360,16 @@ __STATIC_INLINE uint32_t __get_FPSCR(void)
*/
__STATIC_INLINE
void
__set_FPSCR
(
uint32_t
fpscr
)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register
uint32_t
__regfpscr
__ASM
(
"fpscr"
);
__regfpscr
=
(
fpscr
);
#else
(
void
)
fpscr
;
#endif
}
#endif
/* (
__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U
) */
#endif
/* (
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))
) */
...
...
@@ -392,6 +468,7 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
}
#endif
/**
\brief Reverse byte order in signed short value
\details Reverses the byte order in a signed short value with sign extension to integer.
...
...
@@ -410,8 +487,8 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in]
value
Value to rotate
\param [in]
value
Number of Bits to rotate
\param [in]
op1
Value to rotate
\param [in]
op2
Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
...
...
@@ -433,13 +510,14 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
\param [in] value Value to reverse
\return Reversed value
*/
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__
((
always_inline
))
__STATIC_INLINE
uint32_t
__RBIT
(
uint32_t
value
)
{
uint32_t
result
;
int32_t
s
=
4
/*sizeof(v)*/
*
8
-
1
;
/* extra shift needed at end */
int32_t
s
=
(
4
/*sizeof(v)*/
*
8
)
-
1
;
/* extra shift needed at end */
result
=
value
;
/* r will be reversed bits of v; first get LSB of v */
for
(
value
>>=
1U
;
value
;
value
>>=
1U
)
...
...
@@ -463,7 +541,8 @@ __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
#define __CLZ __clz
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
...
...
@@ -645,7 +724,8 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
*/
#define __STRT(value, ptr) __strt(value, ptr)
#endif
/* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
#endif
/* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/
/* end of group CMSIS_Core_InstructionInterface */
...
...
@@ -656,7 +736,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
@{
*/
#if (
__CORTEX_M >= 0x04U)
/* only for Cortex-M4 and above */
#if (
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
...
...
@@ -727,7 +807,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif
/* (
__CORTEX_M >= 0x04
) */
#endif
/* (
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))
) */
/*@} end of group CMSIS_SIMD_intrinsics */
...
...
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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.2
* @date 13. February 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* ARM Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* ARM Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#include <cmsis_iar.h>
/* CMSIS compiler control architecture macros */
#if (__CORE__ == __ARM6M__) || (__CORE__ == __ARM6SM__)
#ifndef __ARM_ARCH_6M__
#define __ARM_ARCH_6M__ 1
#endif
#elif (__CORE__ == __ARM7M__)
#ifndef __ARM_ARCH_7M__
#define __ARM_ARCH_7M__ 1
#endif
#elif (__CORE__ == __ARM7EM__)
#ifndef __ARM_ARCH_7EM__
#define __ARM_ARCH_7EM__ 1
#endif
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __noreturn
#endif
#ifndef __USED
#define __USED __root
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED __packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32
/* deprecated */
__packed
struct
T_UINT32
{
uint32_t
v
;
};
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT
T_UINT16_WRITE
{
uint16_t
v
;
};
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT
T_UINT16_READ
{
uint16_t
v
;
};
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT
T_UINT32_WRITE
{
uint32_t
v
;
};
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT
T_UINT32_READ
{
uint32_t
v
;
};
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
// Workaround for missing __CLZ intrinsic in
// various versions of the IAR compilers.
// __IAR_FEATURE_CLZ__ should be defined by
// the compiler that supports __CLZ internally.
#if (defined (__ARM_ARCH_6M__)) && (__ARM_ARCH_6M__ == 1) && (!defined (__IAR_FEATURE_CLZ__))
__STATIC_INLINE
uint32_t
__CLZ
(
uint32_t
data
)
{
if
(
data
==
0u
)
{
return
32u
;
}
uint32_t
count
=
0
;
uint32_t
mask
=
0x80000000
;
while
((
data
&
mask
)
==
0
)
{
count
+=
1u
;
mask
=
mask
>>
1u
;
}
return
(
count
);
}
#endif
/*
* TI ARM Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32
/* deprecated */
struct
__attribute__
((
packed
))
T_UINT32
{
uint32_t
v
;
};
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT
T_UINT16_WRITE
{
uint16_t
v
;
};
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT
T_UINT16_READ
{
uint16_t
v
;
};
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT
T_UINT32_WRITE
{
uint32_t
v
;
};
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT
T_UINT32_READ
{
uint32_t
v
;
};
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32
/* deprecated */
struct
__packed__
T_UINT32
{
uint32_t
v
;
};
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT
T_UINT16_WRITE
{
uint16_t
v
;
};
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT
T_UINT16_READ
{
uint16_t
v
;
};
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT
T_UINT32_WRITE
{
uint32_t
v
;
};
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT
T_UINT32_READ
{
uint32_t
v
;
};
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32
/* deprecated */
@
packed
struct
T_UINT32
{
uint32_t
v
;
};
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT
T_UINT16_WRITE
{
uint16_t
v
;
};
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT
T_UINT16_READ
{
uint16_t
v
;
};
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT
T_UINT32_WRITE
{
uint32_t
v
;
};
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT
T_UINT32_READ
{
uint32_t
v
;
};
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif
/* __CMSIS_COMPILER_H */
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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include
/* treat file as system include file for MISRA check */
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header
/* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U)
/*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 0U)
/*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB )
/*!< CMSIS Core(M) version number */
#endif
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/*
* Copyright (c) 2015-2016 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* ----------------------------------------------------------------------------
*
* $Date: 21. September 2016
* $Revision: V1.0
*
* Project: TrustZone for ARMv8-M
* Title: Context Management for ARMv8-M TrustZone
*
* Version 1.0
* Initial Release
*---------------------------------------------------------------------------*/
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef
uint32_t
TZ_ModuleId_t
;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef
uint32_t
TZ_MemoryId_t
;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t
TZ_InitContextSystem_S
(
void
);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t
TZ_AllocModuleContext_S
(
TZ_ModuleId_t
module
);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t
TZ_FreeModuleContext_S
(
TZ_MemoryId_t
id
);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t
TZ_LoadContext_S
(
TZ_MemoryId_t
id
);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t
TZ_StoreContext_S
(
TZ_MemoryId_t
id
);
#endif // TZ_CONTEXT_H
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