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提交 6aa24264 编写于 作者: A ardafu
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1. [bsp][sam9260] Fix the bug that auto reset after boot 20s. Disable watchdog... 

1. [bsp][sam9260] Fix the bug that auto reset after boot 20s. Disable watchdog in rt_lovel_level_init function.
2. [bsp][sam9260] Modify SCONS scripts to support IAR tool chain.
3. [bsp][sam9260] Move link strips in to folder link_scripts.
4. [libcpu][arm926] Add copy right to source file and format code.
上级 f435a214
隐藏空白更改
内联 并排
Showing with 668 addition and 259 deletion
bsp/at91sam9260/applications/startup.c
浏览文件 @ 6aa24264
......@@ -47,13 +47,18 @@ extern void rt_application_init(void);
/*@{*/
#if defined(__CC_ARM)
extern int Image$$ER_ZI$$ZI$$Limit;
extern int Image$$ER_ZI$$ZI$$Limit;
#define HEAP_START ((void*)&Image$$ER_ZI$$ZI$$Limit)
#elif (defined (__GNUC__))
extern unsigned char __bss_end__;
extern unsigned char __bss_end__;
#define HEAP_START ((void*)&__bss_end__)
#elif (defined (__ICCARM__))
#pragma section="HEAP"
#pragma section="HEAP"
#define HEAP_START (__section_begin("HEAP"))
#endif
#define HEAP_END ((void*)0x24000000)
#ifdef RT_USING_FINSH
extern void finsh_system_init(void);
#endif
......@@ -90,13 +95,7 @@ void rtthread_startup(void)
rt_system_timer_init();
/* initialize heap memory system */
#ifdef __CC_ARM
rt_system_heap_init((void*)&Image$$ER_ZI$$ZI$$Limit, (void*)0x24000000);
#elif (defined (__GNUC__))
rt_system_heap_init((void*)&__bss_end__, (void*)0x23f00000);
#elif (defined (__ICCARM__))
rt_system_heap_init(__section_begin("HEAP"),(void*)0x23f00000);
#endif
rt_system_heap_init(HEAP_START, HEAP_END);
#ifdef RT_USING_MODULE
/* initialize module system*/
......
bsp/at91sam9260/link_scripts/at91sam9260_ram.icf 0 → 100644
浏览文件 @ 6aa24264
//*****************************************************************************
//
// blinky.icf - Linker configuration file for blinky.
//
// Copyright (c) 2013-2014 Texas Instruments Incorporated. All rights reserved.
// Software License Agreement
//
// Texas Instruments (TI) is supplying this software for use solely and
// exclusively on TI's microcontroller products. The software is owned by
// TI and/or its suppliers, and is protected under applicable copyright
// laws. You may not combine this software with "viral" open-source
// software in order to form a larger program.
//
// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
// DAMAGES, FOR ANY REASON WHATSOEVER.
//
// This is part of revision 2.1.0.12573 of the DK-TM4C129X Firmware Package.
//
//*****************************************************************************
//
// Define a memory region that covers the entire 4 GB addressible space of the
// processor.
//
define memory mem with size = 4G;
//
// Define a region for the on-chip flash.
//
define region FLASH = mem:[from 0x20000000 to 0x207FFFFF];
//
// Define a region for the on-chip SRAM.
//
define region SRAM = mem:[from 0x20800000 to 0x23FFFFFF];
//
// Define a block for the heap. The size should be set to something other
// than zero if things in the C library that require the heap are used.
//
define block HEAP with alignment = 8, size = 0x02000000 { };
//
// Indicate that the read/write values should be initialized by copying from
// flash.
//
initialize by copy { readwrite };
//
// Indicate that the noinit values should be left alone. This includes the
// stack, which if initialized will destroy the return address from the
// initialization code, causing the processor to branch to zero and fault.
//
do not initialize { section .noinit };
//
// Place the interrupt vectors at the start of flash.
//
place at start of FLASH { readonly section .intvec };
//
// Place the remainder of the read-only items into flash.
//
place in FLASH { readonly };
//
// Place the RAM vector table at the start of SRAM.
//
place at start of SRAM { section VTABLE };
//
// Place all read/write items into SRAM.
//
place in SRAM { readwrite, block HEAP };
keep { section FSymTab };
keep { section VSymTab };
keep { section .rti_fn* };
bsp/at91sam9260/link_scripts/at91sam9260_ram.ld 0 → 100644
浏览文件 @ 6aa24264
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(entry)
SECTIONS
{
. = 0x20000000;
. = ALIGN(4);
.text :
{
*(.init)
*(.text)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
/* section information for modules */
. = ALIGN(4);
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
}
. = ALIGN(4);
.rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) *(.eh_frame) }
. = ALIGN(4);
.ctors :
{
PROVIDE(__ctors_start__ = .);
KEEP(*(SORT(.ctors.*)))
KEEP(*(.ctors))
PROVIDE(__ctors_end__ = .);
}
.dtors :
{
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
}
. = ALIGN(4);
.data :
{
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
}
. = ALIGN(4);
.nobss : { *(.nobss) }
. = ALIGN(4);
__bss_start__ = .;
.bss : { *(.bss)}
__bss_end__ = .;
/* stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
_end = .;
}
bsp/at91sam9260/link_scripts/at91sam9260_ram.scat 0 → 100644
浏览文件 @ 6aa24264
; * ----------------------------------------------------------------------------
; * ATMEL Microcontroller Software Support
; * ----------------------------------------------------------------------------
; * Copyright (c) 2008, Atmel Corporation
; *
; * All rights reserved.
; *
; * Redistribution and use in source and binary forms, with or without
; * modification, are permitted provided that the following conditions are met:
; *
; * - Redistributions of source code must retain the above copyright notice,
; * this list of conditions and the disclaimer below.
; *
; * Atmel's name may not be used to endorse or promote products derived from
; * this software without specific prior written permission.
; *
; * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
; * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
; * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
; * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
; * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
; * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
; * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
; * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
; * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; * ----------------------------------------------------------------------------
; *------------------------------------------------------------------------------
; * Linker scatter for running in external SDRAM on the AT91SAM9260
; *----------------------------------------------------------------------------*/
Load_region 0x20000000 0x00800000
{
Fixed_region 0x20000000
{
* (RESET +First)
.ANY (+RO +RW)
}
ER_ZI +0
{
* (+ZI)
} ; Application ZI data (.bss)
;Relocate_region 0x200000 0x1000
;{
; *.o (VECTOR, +First)
;}
ARM_LIB_HEAP 0x21FFE000 EMPTY 0x1000
{
}
ARM_LIB_STACK 0x22000000 EMPTY -0x1000
{
}
}
bsp/at91sam9260/platform/rt_low_level_gcc.inc
浏览文件 @ 6aa24264
//;--------- Stack size of CPU modes -------------------------------------------
/*
* File : rt_low_level_gcc.inc
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2015-04-14 ArdaFu first version
*/
/*--------- Stack size of CPU modes ------------------------------------------*/
.equ UND_STK_SIZE, 2048
.equ SVC_STK_SIZE, 4096
.equ ABT_STK_SIZE, 2048
......
bsp/at91sam9260/platform/rt_low_level_iar.inc
浏览文件 @ 6aa24264
;--------- Stack size of CPU modes --------------------------------------------
/*
* File : rt_low_level_iar.inc
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2015-04-14 ArdaFu first version
*/
/*-------- Stack size of CPU modes -------------------------------------------*/
#define UND_STK_SIZE 512
#define SVC_STK_SIZE 4096
#define ABT_STK_SIZE 512
......
bsp/at91sam9260/platform/rt_low_level_init.c
浏览文件 @ 6aa24264
#define write_reg(a,v) (*(volatile unsigned int *)(a) = (v))
/*
* File : rt_low_level_init.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2015-04-14 ArdaFu first version
*/
/* write register a=address, v=value */
#define write_reg(a,v) (*(volatile unsigned int *)(a) = (v))
/* Processor Reset */
#define AT91_RSTC_PROCRST (1 << 0)
#define AT91_RSTC_PERRST (1 << 2)
#define AT91_RSTC_KEY (0xa5 << 24)
#define AT91_MATRIX_BASE (0XFFFFEE00)
#define AT91_RSTC_PROCRST (1 << 0)
#define AT91_RSTC_PERRST (1 << 2)
#define AT91_RSTC_KEY (0xa5 << 24)
#define AT91_MATRIX_BASE (0XFFFFEE00)
/* Master Remap Control Register */
#define AT91_MATRIX_MRCR (AT91_MATRIX_BASE + 0x100)
#define AT91_MATRIX_MRCR (AT91_MATRIX_BASE + 0x100)
/* Remap Command for AHB Master 0 (ARM926EJ-S InSTRuction Master) */
#define AT91_MATRIX_RCB0 (1 << 0)
#define AT91_MATRIX_RCB0 (1 << 0)
/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_RCB1 (1 << 1)
#define AT91_AIC_BASE (0XFFFFF000)
#define AT91_MATRIX_RCB1 (1 << 1)
#define AT91_AIC_BASE (0XFFFFF000)
/* Interrupt DisaBLe Command Register */
#define AT91_AIC_IDCR (0x124)
#define AT91_AIC_IDCR (AT91_AIC_BASE + 0x124)
/* Interrupt Clear Command Register */
#define AT91_AIC_ICCR (0x128)
#define AT91_AIC_ICCR (AT91_AIC_BASE + 0x128)
#define AT91_WDT_BASE (0XFFFFFD40)
#define AT91_WDT_CR (AT91_WDT_BASE + 0x00)
#define AT91_WDT_CR_KEY (0xA5000000)
#define AT91_WDT_CR_WDRSTT (0x00000001)
#define AT91_WDT_MR (AT91_WDT_BASE + 0x04)
#define AT91_WDT_MR_WDDIS (0x00008000)
void rt_low_level_init(void)
{
// Mask all IRQs by clearing all bits in the INTMRS
write_reg(AT91_AIC_BASE + AT91_AIC_IDCR, 0xFFFFFFFF);
write_reg(AT91_AIC_BASE + AT91_AIC_ICCR, 0xFFFFFFFF);
write_reg(AT91_AIC_IDCR, 0xFFFFFFFF);
write_reg(AT91_AIC_ICCR, 0xFFFFFFFF);
// Remap internal ram to 0x00000000 Address
write_reg(AT91_MATRIX_MRCR, AT91_MATRIX_RCB0 | AT91_MATRIX_RCB1);
// Disable the watchdog
write_reg(AT91_WDT_CR, AT91_WDT_CR_KEY|AT91_WDT_CR_WDRSTT);
write_reg(AT91_WDT_MR, AT91_WDT_MR_WDDIS);
}
bsp/at91sam9260/platform/rt_low_level_keil.inc
浏览文件 @ 6aa24264
;--------- Stack size of CPU modes --------------------------------------------
;/*
; * File : rt_low_level_keil.inc
; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
; *
; * This program is free software; you can redistribute it and/or modify
; * it under the terms of the GNU General Public License as published by
; * the Free Software Foundation; either version 2 of the License, or
; * (at your option) any later version.
; *
; * This program is distributed in the hope that it will be useful,
; * but WITHOUT ANY WARRANTY; without even the implied warranty of
; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; * GNU General Public License for more details.
; *
; * You should have received a copy of the GNU General Public License along
; * with this program; if not, write to the Free Software Foundation, Inc.,
; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
; *
; * Change Logs:
; * Date Author Notes
; * 2015-04-14 ArdaFu first version
; */
;/*-------- Stack size of CPU modes ------------------------------------------*/
UND_STK_SIZE EQU 512
SVC_STK_SIZE EQU 4096
ABT_STK_SIZE EQU 512
IRQ_STK_SIZE EQU 1024
FIQ_STK_SIZE EQU 1024
SYS_STK_SIZE EQU 512
END
\ No newline at end of file
END
bsp/at91sam9260/rtconfig.py
浏览文件 @ 6aa24264
import os
# toolchains options
ARCH = 'arm'
CPU = 'arm926'
TextBase = '0x20000000'
CROSS_TOOL = 'gcc'
# toolchains options
CROSS_TOOL = 'iar'
#------- toolchains path -------------------------------------------------------
if os.getenv('RTT_CC'):
CROSS_TOOL = os.getenv('RTT_CC')
if CROSS_TOOL == 'gcc':
PLATFORM = 'gcc'
#EXEC_PATH = 'D:/ArdaArmTools/Sourcery_Lite/bin'
EXEC_PATH = 'D:/ArdaArmTools/GNUARM_4.9_2015q1/bin'
#EXEC_PATH = 'D:/ArdaArmTools/Sourcery_Lite'
EXEC_PATH = 'D:/ArdaArmTools/GNUARM_4.9_2015q1'
elif CROSS_TOOL == 'keil':
PLATFORM = 'armcc'
EXEC_PATH = 'C:/Keil_v5'
elif CROSS_TOOL == 'iar':
print '================ERROR============================'
print 'Not support yet!'
print '================================================='
exit(0)
PLATFORM = 'iar'
IAR_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.0'
if os.getenv('RTT_EXEC_PATH'):
EXEC_PATH = os.getenv('RTT_EXEC_PATH')
......@@ -29,6 +25,12 @@ if os.getenv('RTT_EXEC_PATH'):
#BUILD = 'debug'
BUILD = 'release'
CORE = 'arm926ej-s'
MAP_FILE = 'rtthread_at91sam9260.map'
LINK_FILE = 'link_scripts/at91sam9260_ram'
TARGET_NAME = 'rtthread.bin'
#------- GCC settings ----------------------------------------------------------
if PLATFORM == 'gcc':
# toolchains
PREFIX = 'arm-none-eabi-'
......@@ -41,11 +43,15 @@ if PLATFORM == 'gcc':
SIZE = PREFIX + 'size'
OBJDUMP = PREFIX + 'objdump'
OBJCPY = PREFIX + 'objcopy'
EXEC_PATH += '/bin/'
DEVICE = ' -mcpu=arm926ej-s'
CFLAGS = DEVICE
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp' + ' -Iplatform'+' -DTEXT_BASE=' + TextBase
LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread_at91sam9260.map,-cref,-u,_start -T at91sam9260_ram.ld' + ' -Ttext ' + TextBase
AFLAGS = '-c'+ DEVICE + ' -x assembler-with-cpp'
AFLAGS += ' -Iplatform'
LFLAGS = DEVICE
LFLAGS += ' -Wl,--gc-sections,-cref,-Map=' + MAP_FILE
LFLAGS += ' -T ' + LINK_FILE + '.ld'
CPATH = ''
LPATH = ''
......@@ -56,8 +62,9 @@ if PLATFORM == 'gcc':
else:
CFLAGS += ' -O2'
POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
POST_ACTION = OBJCPY + ' -O binary $TARGET ' + TARGET_NAME + '\n'
POST_ACTION += SIZE + ' $TARGET\n'
#------- Keil settings ---------------------------------------------------------
elif PLATFORM == 'armcc':
# toolchains
CC = 'armcc'
......@@ -65,16 +72,15 @@ elif PLATFORM == 'armcc':
AR = 'armar'
LINK = 'armlink'
TARGET_EXT = 'axf'
EXEC_PATH += '/arm/armcc/bin/'
DEVICE = ' --cpu=ARM926EJ-S'
DEVICE = ' --cpu=' + CORE
CFLAGS = DEVICE + ' --apcs=interwork --diag_suppress=870'
AFLAGS = DEVICE + ' -Iplatform'
LFLAGS = DEVICE + ' --strict --info sizes --info totals --info unused --info veneers --list rtthread-at91sam9260.map --ro-base 0x20000000 --entry Entry_Point --first Entry_Point'
CFLAGS += ' -I"' + EXEC_PATH + '/ARM/RV31/INC"'
LFLAGS += ' --libpath "' + EXEC_PATH + '/ARM/RV31/LIB"'
EXEC_PATH += '/arm/bin40/'
LFLAGS = DEVICE + ' --strict'
LFLAGS += ' --info sizes --info totals --info unused --info veneers'
LFLAGS += ' --list ' + MAP_FILE
LFLAGS += ' --scatter ' + LINK_FILE + '.scat'
if BUILD == 'debug':
CFLAGS += ' -g -O0'
......@@ -82,4 +88,53 @@ elif PLATFORM == 'armcc':
else:
CFLAGS += ' -O2'
POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
POST_ACTION = 'fromelf --bin $TARGET --output ' + TARGET_NAME + ' \n'
POST_ACTION += 'fromelf -z $TARGET\n'
#------- IAR settings ----------------------------------------------------------
elif PLATFORM == 'iar':
# toolchains
CC = 'iccarm'
AS = 'iasmarm'
AR = 'iarchive'
LINK = 'ilinkarm'
TARGET_EXT = 'out'
DEVICE = CORE
CFLAGS = '--cpu=' + DEVICE
CFLAGS += ' --diag_suppress Pa050'
CFLAGS += ' --no_cse'
CFLAGS += ' --no_unroll'
CFLAGS += ' --no_inline'
CFLAGS += ' --no_code_motion'
CFLAGS += ' --no_tbaa'
CFLAGS += ' --no_clustering'
CFLAGS += ' --no_scheduling'
CFLAGS += ' --endian=little'
CFLAGS += ' -e'
CFLAGS += ' --fpu=none'
CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
CFLAGS += ' --silent'
AFLAGS = '--cpu '+ DEVICE
AFLAGS += ' -s+'
AFLAGS += ' -w+'
AFLAGS += ' -r'
AFLAGS += ' --fpu none'
AFLAGS += ' -S'
AFLAGS += ' -Iplatform'
if BUILD == 'debug':
CFLAGS += ' --debug'
CFLAGS += ' -On'
else:
CFLAGS += ' -Oh'
LFLAGS = '--config ' + LINK_FILE +'.icf'
LFLAGS += ' --entry __iar_program_start'
LFLAGS += ' --map ' + MAP_FILE
LFLAGS += ' --silent'
EXEC_PATH = IAR_PATH + '/arm/bin/'
POST_ACTION = 'ielftool --silent --bin $TARGET ' + TARGET_NAME
libcpu/arm/arm926/context_iar.S
浏览文件 @ 6aa24264
......@@ -19,7 +19,8 @@
; *
; * Change Logs:
; * Date Author Notes
; * 2011-08-14 weety copy from mini2440
; * 2011-08-14 weety copy from mini2440
; * 2015-04-15 ArdaFu convert from context_gcc.s
; */
#define NOINT 0xc0
......
libcpu/arm/arm926/cpuport.c
浏览文件 @ 6aa24264
......@@ -20,6 +20,7 @@
* Change Logs:
* Date Author Notes
* 2011-01-13 weety modified from mini2440
* 2015-04-15 ArdaFu Add code for IAR
*/
#include <rthw.h>
......@@ -42,24 +43,24 @@ rt_inline rt_uint32_t cp15_rd(void)
rt_inline void cache_enable(rt_uint32_t bit)
{
__asm__ __volatile__( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"orr r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
__asm__ __volatile__(\
"mrc p15,0,r0,c1,c0,0\n\t" \
"orr r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
rt_inline void cache_disable(rt_uint32_t bit)
{
__asm__ __volatile__( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"bic r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
__asm__ __volatile__(\
"mrc p15,0,r0,c1,c0,0\n\t" \
"bic r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
#endif
......@@ -112,24 +113,24 @@ rt_inline rt_uint32_t cp15_rd(void)
rt_inline void cache_enable(rt_uint32_t bit)
{
asm volatile( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"orr r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
asm volatile(\
"mrc p15,0,r0,c1,c0,0\n\t" \
"orr r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
rt_inline void cache_disable(rt_uint32_t bit)
{
asm volatile( \
"mrc p15,0,r0,c1,c0,0\n\t" \
"bic r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
asm volatile(\
"mrc p15,0,r0,c1,c0,0\n\t" \
"bic r0,r0,%0\n\t" \
"mcr p15,0,r0,c1,c0,0" \
: \
:"r" (bit) \
:"memory");
}
#endif
......@@ -193,7 +194,7 @@ rt_base_t rt_hw_cpu_dcache_status()
*/
void rt_hw_cpu_reset()
{
rt_kprintf("Restarting system...\n");
machine_reset();
......@@ -221,13 +222,13 @@ void rt_hw_cpu_shutdown()
#ifdef RT_USING_CPU_FFS
/**
* This function finds the first bit set (beginning with the least significant bit)
* This function finds the first bit set (beginning with the least significant bit)
* in value and return the index of that bit.
*
* Bits are numbered starting at 1 (the least significant bit). A return value of
* Bits are numbered starting at 1 (the least significant bit). A return value of
* zero from any of these functions means that the argument was zero.
*
* @return return the index of the first bit set. If value is 0, then this function
*
* @return return the index of the first bit set. If value is 0, then this function
* shall return 0.
*/
#if defined(__CC_ARM)
......@@ -237,7 +238,7 @@ int __rt_ffs(int value)
if (value == 0)
return value;
__asm
{
rsb x, value, #0
......@@ -248,7 +249,7 @@ int __rt_ffs(int value)
return x;
}
#elif defined(__IAR_SYSTEMS_ICC__)
#elif defined(__ICCARM__)
int __rt_ffs(int value)
{
if (value == 0)
......
libcpu/arm/arm926/mmu.c
浏览文件 @ 6aa24264
......@@ -19,6 +19,7 @@
*
* Change Logs:
* Date Author Notes
* 2015-04-15 ArdaFu Add code for IAR
*/
#include "mmu.h"
......@@ -28,11 +29,11 @@ void mmu_setttbase(rt_uint32_t i)
{
register rt_uint32_t value;
/* Invalidates all TLBs.Domain access is selected as
* client by configuring domain access register,
* in that case access controlled by permission value
* set by page table entry
*/
/* Invalidates all TLBs.Domain access is selected as
* client by configuring domain access register,
* in that case access controlled by permission value
* set by page table entry
*/
value = 0;
__asm
{
......@@ -247,11 +248,11 @@ void mmu_setttbase(register rt_uint32_t i)
{
register rt_uint32_t value;
/* Invalidates all TLBs.Domain access is selected as
* client by configuring domain access register,
* in that case access controlled by permission value
* set by page table entry
*/
/* Invalidates all TLBs.Domain access is selected as
* client by configuring domain access register,
* in that case access controlled by permission value
* set by page table entry
*/
value = 0;
asm ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
......@@ -433,11 +434,11 @@ void mmu_setttbase(register rt_uint32_t i)
{
register rt_uint32_t value;
/* Invalidates all TLBs.Domain access is selected as
* client by configuring domain access register,
* in that case access controlled by permission value
* set by page table entry
*/
/* Invalidates all TLBs.Domain access is selected as
* client by configuring domain access register,
* in that case access controlled by permission value
* set by page table entry
*/
value = 0;
asm ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
......@@ -621,16 +622,18 @@ void mmu_invalidate_dcache_all()
#pragma data_alignment=(16*1024)
static volatile unsigned int _page_table[4*1024];;
#else
static volatile unsigned int _page_table[4*1024] __attribute__((aligned(16*1024)));
static volatile unsigned int _page_table[4*1024] \
__attribute__((aligned(16*1024)));
#endif
void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrStart, rt_uint32_t attr)
void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd,
rt_uint32_t paddrStart, rt_uint32_t attr)
{
volatile rt_uint32_t *pTT;
volatile int nSec;
int i = 0;
pTT=(rt_uint32_t *)_page_table+(vaddrStart>>20);
nSec=(vaddrEnd>>20)-(vaddrStart>>20);
for(i=0;i<=nSec;i++)
for(i=0; i<=nSec; i++)
{
*pTT = attr |(((paddrStart>>20)+i)<<20);
pTT++;
......@@ -648,8 +651,8 @@ void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size)
/* set page table */
for (; size > 0; size--)
{
mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end,
mdesc->paddr_start, mdesc->attr);
mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end,
mdesc->paddr_start, mdesc->attr);
mdesc++;
}
......@@ -668,4 +671,3 @@ void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size)
mmu_invalidate_icache();
mmu_invalidate_dcache_all();
}
libcpu/arm/arm926/mmu.h
浏览文件 @ 6aa24264
......@@ -26,31 +26,32 @@
#include <rtthread.h>
#define CACHE_LINE_SIZE 32
#define DESC_SEC (0x2|(1<<4))
#define CB (3<<2) //cache_on, write_back
#define CNB (2<<2) //cache_on, write_through
#define NCB (1<<2) //cache_off,WR_BUF on
#define NCNB (0<<2) //cache_off,WR_BUF off
#define AP_RW (3<<10) //supervisor=RW, user=RW
#define AP_RO (2<<10) //supervisor=RW, user=RO
#define DOMAIN_FAULT (0x0)
#define DOMAIN_CHK (0x1)
#define DOMAIN_NOTCHK (0x3)
#define DOMAIN0 (0x0<<5)
#define DOMAIN1 (0x1<<5)
#define DOMAIN0_ATTR (DOMAIN_CHK<<0)
#define DOMAIN1_ATTR (DOMAIN_FAULT<<2)
#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */
#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */
#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */
#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */
struct mem_desc {
#define CACHE_LINE_SIZE 32
#define DESC_SEC (0x2|(1<<4))
#define CB (3<<2) //cache_on, write_back
#define CNB (2<<2) //cache_on, write_through
#define NCB (1<<2) //cache_off,WR_BUF on
#define NCNB (0<<2) //cache_off,WR_BUF off
#define AP_RW (3<<10) //supervisor=RW, user=RW
#define AP_RO (2<<10) //supervisor=RW, user=RO
#define DOMAIN_FAULT (0x0)
#define DOMAIN_CHK (0x1)
#define DOMAIN_NOTCHK (0x3)
#define DOMAIN0 (0x0<<5)
#define DOMAIN1 (0x1<<5)
#define DOMAIN0_ATTR (DOMAIN_CHK<<0)
#define DOMAIN1_ATTR (DOMAIN_FAULT<<2)
#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */
#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */
#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */
#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */
struct mem_desc
{
rt_uint32_t vaddr_start;
rt_uint32_t vaddr_end;
rt_uint32_t paddr_start;
......@@ -60,4 +61,3 @@ struct mem_desc {
void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size);
#endif
libcpu/arm/arm926/stack.c
浏览文件 @ 6aa24264
......@@ -27,49 +27,48 @@
/* CPU Mode */
/*****************************/
#define USERMODE 0x10
#define FIQMODE 0x11
#define IRQMODE 0x12
#define SVCMODE 0x13
#define ABORTMODE 0x17
#define UNDEFMODE 0x1b
#define FIQMODE 0x11
#define IRQMODE 0x12
#define SVCMODE 0x13
#define ABORTMODE 0x17
#define UNDEFMODE 0x1b
#define MODEMASK 0x1f
#define NOINT 0xc0
#define NOINT 0xc0
/**
* This function will initialize thread stack
*
* @param tentry the entry of thread
* @param parameter the parameter of entry
* @param parameter the parameter of entry
* @param stack_addr the beginning stack address
* @param texit the function will be called when thread exit
*
* @return stack address
*/
rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
rt_uint8_t *stack_addr, void *texit)
rt_uint8_t *stack_addr, void *texit)
{
rt_uint32_t *stk;
stk = (rt_uint32_t*)stack_addr;
*(stk) = (rt_uint32_t)tentry; /* entry point */
*(--stk) = (rt_uint32_t)texit; /* lr */
*(--stk) = 0; /* r12 */
*(--stk) = 0; /* r11 */
*(--stk) = 0; /* r10 */
*(--stk) = 0; /* r9 */
*(--stk) = 0; /* r8 */
*(--stk) = 0; /* r7 */
*(--stk) = 0; /* r6 */
*(--stk) = 0; /* r5 */
*(--stk) = 0; /* r4 */
*(--stk) = 0; /* r3 */
*(--stk) = 0; /* r2 */
*(--stk) = 0; /* r1 */
*(--stk) = (rt_uint32_t)parameter; /* r0 : argument */
*(--stk) = SVCMODE; /* cpsr */
*(--stk) = SVCMODE; /* spsr */
*(stk) = (rt_uint32_t)tentry; /* entry point */
*(--stk) = (rt_uint32_t)texit; /* lr */
*(--stk) = 0; /* r12 */
*(--stk) = 0; /* r11 */
*(--stk) = 0; /* r10 */
*(--stk) = 0; /* r9 */
*(--stk) = 0; /* r8 */
*(--stk) = 0; /* r7 */
*(--stk) = 0; /* r6 */
*(--stk) = 0; /* r5 */
*(--stk) = 0; /* r4 */
*(--stk) = 0; /* r3 */
*(--stk) = 0; /* r2 */
*(--stk) = 0; /* r1 */
*(--stk) = (rt_uint32_t)parameter; /* r0 : argument */
*(--stk) = SVCMODE; /* cpsr */
*(--stk) = SVCMODE; /* spsr */
/* return task's current stack address */
return (rt_uint8_t *)stk;
}
libcpu/arm/arm926/start_gcc.S
浏览文件 @ 6aa24264
/*
* File : start.S
* File : start_gcc.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......@@ -20,8 +20,9 @@
* Change Logs:
* Date Author Notes
* 2011-01-13 weety first version
* 2015-04-15 ArdaFu Split from AT91SAM9260 BSP
*/
#define CONFIG_STACKSIZE 512
#define S_FRAME_SIZE (18*4) //72
@#define S_SPSR (17*4) //SPSR
......@@ -55,7 +56,7 @@
.include "rt_low_level_gcc.inc"
@; stack table-----------------------------------------------------------------
@;----------------------- Stack and Heap Definitions ---------------------------
.section .nobss, "w"
.space UND_STK_SIZE
......@@ -88,8 +89,7 @@ FIQ_STACK_START:
SYS_STACK_START:
@; Jump vector table-----------------------------------------------------------
@;--------------Jump vector table-----------------------------------------------
.section .init, "ax"
.arm
......@@ -179,7 +179,6 @@ Setup_Stack:
MSR CPSR_cxsf, R1 @; SVC mode
LDR SP, =SVC_STACK_START
@; clear .bss
MOV R0, #0 @; get a zero
LDR R1, =__bss_start__ @; bss start
......@@ -203,8 +202,8 @@ ctor_loop:
BX R2
LDMFD SP!, {R0-R1}
B ctor_loop
ctor_end:
@; Enter the C code
LDR R0, =main
BLX R0
......
libcpu/arm/arm926/start_iar.S
浏览文件 @ 6aa24264
......@@ -20,6 +20,7 @@
; * Change Logs:
; * Date Author Notes
; * 2011-01-13 weety first version
; * 2015-04-15 ArdaFu Split from AT91SAM9260 BSP
; */
#define S_FRAME_SIZE (18*4) ;72
......@@ -55,6 +56,7 @@
#include "rt_low_level_iar.inc"
;----------------------- Stack and Heap Definitions ----------------------------
MODULE ?cstartup
SECTION .noinit:DATA:NOROOT(3)
DATA
......
libcpu/arm/arm926/start_rvds.S
浏览文件 @ 6aa24264
......@@ -20,11 +20,9 @@
; * Change Logs:
; * Date Author Notes
; * 2011-08-14 weety first version
; * 2015-04-15 ArdaFu Split from AT91SAM9260 BSP
; */
; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
S_FRAME_SIZE EQU (18*4) ;72
;S_SPSR EQU (17*4) ;SPSR
;S_CPSR EQU (16*4) ;CPSR
......@@ -58,11 +56,9 @@ MODEMASK EQU 0X1F
NOINT EQU 0xC0
;----------------------- Stack and Heap Definitions ----------------------------
AREA STACK, NOINIT, READWRITE, ALIGN=3
GET rt_low_level_keil.inc
;-------------- stack area -----------------------------------------------------
;----------------------- Stack and Heap Definitions ----------------------------
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem
......@@ -103,11 +99,7 @@ Heap_Mem
SPACE Heap_Size
__heap_limit
;----------------------- CODE --------------------------------------------------
PRESERVE8
; Area Definition and Entry Point
; Startup Code must be linked first at Address at which it expects to run.
;--------------Jump vector table------------------------------------------------
EXPORT Entry_Point
AREA RESET, CODE, READONLY
......@@ -331,7 +323,7 @@ rt_hw_context_switch_interrupt_do PROC
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, = (Stack_Mem + SYS_STK_SIZE)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDIF
......
libcpu/arm/arm926/trap.c
浏览文件 @ 6aa24264
/*
* File : trap.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
......@@ -20,17 +20,13 @@
* Change Logs:
* Date Author Notes
* 2011-01-13 weety modified from mini2440
* 2015-04-15 ArdaFu Split from AT91SAM9260 BSP
*/
#include <rtthread.h>
#include <rthw.h>
#include <interrupt.h>
/**
* @addtogroup AT91SAM926X
*/
/*@{*/
extern struct rt_thread *rt_current_thread;
#ifdef RT_USING_FINSH
......@@ -39,24 +35,24 @@ extern long list_thread(void);
struct rt_hw_register
{
rt_uint32_t r0;
rt_uint32_t r1;
rt_uint32_t r2;
rt_uint32_t r3;
rt_uint32_t r4;
rt_uint32_t r5;
rt_uint32_t r6;
rt_uint32_t r7;
rt_uint32_t r8;
rt_uint32_t r9;
rt_uint32_t r10;
rt_uint32_t fp;
rt_uint32_t ip;
rt_uint32_t sp;
rt_uint32_t lr;
rt_uint32_t pc;
rt_uint32_t cpsr;
rt_uint32_t ORIG_r0;
rt_uint32_t r0;
rt_uint32_t r1;
rt_uint32_t r2;
rt_uint32_t r3;
rt_uint32_t r4;
rt_uint32_t r5;
rt_uint32_t r6;
rt_uint32_t r7;
rt_uint32_t r8;
rt_uint32_t r9;
rt_uint32_t r10;
rt_uint32_t fp;
rt_uint32_t ip;
rt_uint32_t sp;
rt_uint32_t lr;
rt_uint32_t pc;
rt_uint32_t cpsr;
rt_uint32_t ORIG_r0;
};
/**
......@@ -67,13 +63,18 @@ struct rt_hw_register
void rt_hw_show_register (struct rt_hw_register *regs)
{
rt_kprintf("Execption:\n");
rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
rt_kprintf("Execption:\n");
rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n",
regs->r0, regs->r1, regs->r2, regs->r3);
rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n",
regs->r4, regs->r5, regs->r6, regs->r7);
rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n",
regs->r8, regs->r9, regs->r10);
rt_kprintf("fp :0x%08x ip :0x%08x\n",
regs->fp, regs->ip);
rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n",
regs->sp, regs->lr, regs->pc);
rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
}
/**
......@@ -86,15 +87,15 @@ void rt_hw_show_register (struct rt_hw_register *regs)
*/
void rt_hw_trap_udef(struct rt_hw_register *regs)
{
rt_hw_show_register(regs);
rt_hw_show_register(regs);
rt_kprintf("undefined instruction\n");
rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
rt_kprintf("undefined instruction\n");
rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
#ifdef RT_USING_FINSH
list_thread();
list_thread();
#endif
rt_hw_cpu_shutdown();
rt_hw_cpu_shutdown();
}
/**
......@@ -108,10 +109,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs)
*/
void rt_hw_trap_swi(struct rt_hw_register *regs)
{
rt_hw_show_register(regs);
rt_hw_show_register(regs);
rt_kprintf("software interrupt\n");
rt_hw_cpu_shutdown();
rt_kprintf("software interrupt\n");
rt_hw_cpu_shutdown();
}
/**
......@@ -124,15 +125,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs)
*/
void rt_hw_trap_pabt(struct rt_hw_register *regs)
{
rt_hw_show_register(regs);
rt_hw_show_register(regs);
rt_kprintf("prefetch abort\n");
rt_kprintf("thread - %s stack:\n", RT_NAME_MAX, rt_current_thread->name);
rt_kprintf("prefetch abort\n");
rt_kprintf("thread - %s stack:\n", RT_NAME_MAX, rt_current_thread->name);
#ifdef RT_USING_FINSH
list_thread();
list_thread();
#endif
rt_hw_cpu_shutdown();
rt_hw_cpu_shutdown();
}
/**
......@@ -145,15 +146,15 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs)
*/
void rt_hw_trap_dabt(struct rt_hw_register *regs)
{
rt_hw_show_register(regs);
rt_hw_show_register(regs);
rt_kprintf("data abort\n");
rt_kprintf("thread - %s stack:\n", RT_NAME_MAX, rt_current_thread->name);
rt_kprintf("data abort\n");
rt_kprintf("thread - %s stack:\n", RT_NAME_MAX, rt_current_thread->name);
#ifdef RT_USING_FINSH
list_thread();
list_thread();
#endif
rt_hw_cpu_shutdown();
rt_hw_cpu_shutdown();
}
/**
......@@ -165,45 +166,65 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs)
*/
void rt_hw_trap_resv(struct rt_hw_register *regs)
{
rt_kprintf("not used\n");
rt_hw_show_register(regs);
rt_hw_cpu_shutdown();
rt_kprintf("not used\n");
rt_hw_show_register(regs);
rt_hw_cpu_shutdown();
}
extern struct rt_irq_desc irq_desc[];
rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq, rt_uint32_t* id);
extern void rt_hw_interrupt_ack(rt_uint32_t fiq_irq);
void rt_hw_trap_irq()
{
rt_isr_handler_t isr_func;
rt_uint32_t irqstat, irq;
void *param;
//rt_kprintf("irq interrupt request\n");
/* get irq number */
irqstat = rt_hw_interrupt_get_active(INT_IRQ, &irq);
if (irqstat == 0)
{
rt_kprintf("No interrupt occur\n");
rt_hw_interrupt_ack(INT_IRQ);
return;
}
/* get interrupt service routine */
isr_func = irq_desc[irq].handler;
param = irq_desc[irq].param;
/* turn to interrupt service routine */
isr_func(irq, param);
// EIOCR must be write any value after interrupt,
// or else can't response next interrupt
rt_hw_interrupt_ack(INT_IRQ);
rt_isr_handler_t isr_func;
rt_uint32_t irqstat;
rt_uint32_t irq;
void *param;
extern struct rt_irq_desc irq_desc[];
/* get irq number */
irqstat = rt_hw_interrupt_get_active(INT_IRQ, &irq);
if (irqstat == 0)
{
rt_kprintf("No interrupt occur\n");
rt_hw_interrupt_ack(INT_IRQ);
return;
}
/* get interrupt service routine */
isr_func = irq_desc[irq].handler;
param = irq_desc[irq].param;
/* turn to interrupt service routine */
isr_func(irq, param);
rt_hw_interrupt_ack(INT_IRQ);
irq_desc[irq].counter ++;
}
void rt_hw_trap_fiq()
{
rt_kprintf("fast interrupt request\n");
rt_isr_handler_t isr_func;
rt_uint32_t irqstat;
rt_uint32_t irq;
void *param;
extern struct rt_irq_desc irq_desc[];
/* get irq number */
irqstat = rt_hw_interrupt_get_active(INT_FIQ, &irq);
if (irqstat == 0)
{
rt_kprintf("No interrupt occur\n");
rt_hw_interrupt_ack(INT_FIQ);
return;
}
/* get interrupt service routine */
isr_func = irq_desc[irq].handler;
param = irq_desc[irq].param;
/* turn to interrupt service routine */
isr_func(irq, param);
rt_hw_interrupt_ack(INT_FIQ);
irq_desc[irq].counter ++;
}
/*@}*/
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