Merge pull request #11 from RT-Thread/master

update

bsp/CME_M7/drivers/emac.c

@@ -312,8 +312,19 @@ struct pbuf *rt_cme_eth_rx(rt_device_t dev)
     ETH_RX_DESC *desc;
     uint32_t framelength;
     struct rt_cme_eth * cme_eth = (struct rt_cme_eth *)dev;
+    rt_err_t result;
 
-    rt_mutex_take(&cme_eth->lock, RT_WAITING_FOREVER);
+    result = rt_mutex_take(&cme_eth->lock, RT_WAITING_FOREVER);
+    if (result == -RT_ETIMEOUT)
+    {
+        rt_kprintf("Take mutex time out.\n");
+        goto _exit;
+    }
+    else if (result == -RT_ERROR)
+    {
+        rt_kprintf("Take mutex error.\n");
+        goto _exit;
+    }
 
     desc = ETH_AcquireFreeRxDesc();
     if(desc == RT_NULL)

bsp/fh8620/drivers/i2c.c

@@ -87,7 +87,10 @@ static rt_size_t fh_i2c_xfer(struct rt_i2c_bus_device *dev,
 
     rt_completion_init(&i2c_drv->transfer_completion);
 
-	ret = rt_mutex_take(i2c_drv->lock, RT_WAITING_FOREVER );
+    ret = rt_mutex_take(i2c_drv->lock, RT_WAITING_FOREVER);
+	if (ret != RT_EOK) {
+		goto done;
+	}
 
 	i2c_drv->msgs = msgs;
 	i2c_drv->msgs_num = num;

bsp/gd32103c-eval/Kconfig

+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+    
+# you can change the RTT_ROOT default: "rt-thread"
+# example : default "F:/git_repositories/rt-thread"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_SERIES_GD32F1
+    bool
+    default y
+
+config SOC_GD32103C
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select SOC_SERIES_GD32F1
+    default y
+
+menu "On-chip Peripheral Drivers"
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART0
+                bool "using uart0"
+                default n
+            config BSP_USING_UART1
+                bool "using uart1"
+                default n
+            config BSP_USING_UART2
+                bool "using uart2"
+                default y
+            config BSP_USING_UART3
+                bool "using uart3"
+                default n
+            config BSP_USING_UART4
+                bool "using uart4"
+                default n
+        endif
+    menuconfig BSP_USING_ADC
+        bool "Enable ADC"
+        default n
+        select RT_USING_ADC
+        if BSP_USING_ADC
+            config BSP_USING_ADC0
+                bool "using adc0"
+                default n
+            config BSP_USING_ADC1
+                bool "using adc1"
+                default n
+        endif
+
+endmenu

bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/gd32f10x_conf.h

+/**
+  ******************************************************************************
+  * @brief   Configuration file.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __GD32F10X_CONF_H
+#define __GD32F10X_CONF_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Comment the line below to disable peripheral header file inclusion */
+#include "gd32f10x_adc.h"
+#include "gd32f10x_bkp.h"
+#include "gd32f10x_can.h"
+#include "gd32f10x_crc.h"
+#include "gd32f10x_dac.h"
+#include "gd32f10x_dma.h"
+#include "gd32f10x_eth.h"
+#include "gd32f10x_exmc.h"
+#include "gd32f10x_exti.h"
+#include "gd32f10x_fmc.h"
+#include "gd32f10x_gpio.h"
+#include "gd32f10x_i2c.h"
+#include "gd32f10x_iwdg.h"
+#include "gd32f10x_mcudbg.h"
+#include "gd32f10x_misc.h"
+#include "gd32f10x_pwr.h"
+#include "gd32f10x_rcc.h"
+#include "gd32f10x_rcu.h"
+#include "gd32f10x_rtc.h"
+#include "gd32f10x_sdio.h"
+#include "gd32f10x_spi.h"
+#include "gd32f10x_timer.h"
+#include "gd32f10x_usart.h"
+#include "gd32f10x_wwdg.h"
+
+#endif /* __GD32F10X_CONF_H */
+

bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/system_gd32f10x.h

+/**
+  ******************************************************************************
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup GD32F10x_system
+  * @{
+  */
+
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_GD32F10X_H
+#define __SYSTEM_GD32F10X_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup GD32F10x_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup GD32F10x_System_Exported_types
+  * @{
+  */
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+/**
+  * @}
+  */
+
+/** @addtogroup GD32F10x_System_Exported_Functions
+  * @{
+  */
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_GD32F10X_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+

bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Source/GCC/isr_tab.s

+/*
+ * File      : isr_tab.s
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2021, RT-Thread Development Team
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-01-02     iysheng      first implementation
+ */
+
+.syntax unified
+.cpu cortex-m3
+.fpu softvfp
+.thumb
+
+.global  g_isr_vectors
+    .section  .isr_vector,"a",%progbits
+    .type  g_isr_vectors, STT_OBJECT
+
+.weak Reset_Handler
+g_isr_vectors:
+    .word     _estack                           /* Top of Stack */
+    .word     Reset_Handler                     /* Reset Handler */
+    .word     NMI_Handler                       /* NMI Handler */
+    .word     HardFault_Handler                 /* Hard Fault Handler */
+    .word     MemManage_Handler                 /* MPU Fault Handler */
+    .word     BusFault_Handler                  /* Bus Fault Handler */
+    .word     UsageFault_Handler                /* Usage Fault Handler */
+    .word     0                                 /* Reserved */
+    .word     0                                 /* Reserved */
+    .word     0                                 /* Reserved */
+    .word     0                                 /* Reserved */
+    .word     SVC_Handler                       /* SVCall Handler */
+    .word     DebugMon_Handler                  /* Debug Monitor Handler */
+    .word     0                                 /* Reserved */
+    .word     PendSV_Handler                    /* PendSV Handler */
+    .word     SysTick_Handler                   /* SysTick Handler */
+
+    /* external interrupts handler */
+    .word     WWDGT_IRQHandler                  /* 16:Window Watchdog Timer */
+    .word     LVD_IRQHandler                    /* 17:LVD through EXTI Line detect */
+    .word     TAMPER_IRQHandler                 /* 18:Tamper through EXTI Line detect */
+    .word     RTC_IRQHandler                    /* 19:RTC through EXTI Line */
+    .word     FMC_IRQHandler                    /* 20:FMC */
+    .word     RCU_CTC_IRQHandler                /* 21:RCU and CTC */
+    .word     EXTI0_IRQHandler                  /* 22:EXTI Line 0 */
+    .word     EXTI1_IRQHandler                  /* 23:EXTI Line 1 */
+    .word     EXTI2_IRQHandler                  /* 24:EXTI Line 2 */
+    .word     EXTI3_IRQHandler                  /* 25:EXTI Line 3 */
+    .word     EXTI4_IRQHandler                  /* 26:EXTI Line 4 */
+    .word     DMA0_Channel0_IRQHandler          /* 27:DMA0 Channel0 */
+    .word     DMA0_Channel1_IRQHandler          /* 28:DMA0 Channel1 */
+    .word     DMA0_Channel2_IRQHandler          /* 29:DMA0 Channel2 */
+    .word     DMA0_Channel3_IRQHandler          /* 30:DMA0 Channel3 */
+    .word     DMA0_Channel4_IRQHandler          /* 31:DMA0 Channel4 */
+    .word     DMA0_Channel5_IRQHandler          /* 32:DMA0 Channel5 */
+    .word     DMA0_Channel6_IRQHandler          /* 33:DMA0 Channel6 */
+    .word     ADC0_1_IRQHandler                 /* 34:ADC0 and ADC1 */
+    .word     USBD_HP_CAN0_TX_IRQHandler        /* 35:USBD HP and CAN0 TX */
+    .word     USBD_LP_CAN0_RX0_IRQHandler       /* 36:USBD LP and CAN0 RX0 */
+    .word     CAN0_RX1_IRQHandler               /* 37:CAN0 RX1 */
+    .word     CAN0_EWMC_IRQHandler              /* 38:CAN0 EWMC */
+    .word     EXTI5_9_IRQHandler                /* 39:EXTI5 to EXTI9 */
+    .word     TIMER0_BRK_IRQHandler             /* 40:TIMER0 Break */
+    .word     TIMER0_UP_IRQHandler              /* 41:TIMER0 Update */
+    .word     TIMER0_TRG_CMT_IRQHandler         /* 42:TIMER0 Trigger and Commutation  */
+    .word     TIMER0_Channel_IRQHandler         /* 43:TIMER0 Channel Capture Compare */
+    .word     TIMER1_IRQHandler                 /* 44:TIMER1 */
+    .word     TIMER2_IRQHandler                 /* 45:TIMER2 */
+    .word     TIMER3_IRQHandler                 /* 46:TIMER3 */
+    .word     I2C0_EV_IRQHandler                /* 47:I2C0 Event */
+    .word     I2C0_ER_IRQHandler                /* 48:I2C0 Error */
+    .word     I2C1_EV_IRQHandler                /* 49:I2C1 Event */
+    .word     I2C1_ER_IRQHandler                /* 50:I2C1 Error */
+    .word     SPI0_IRQHandler                   /* 51:SPI0 */
+    .word     SPI1_IRQHandler                   /* 52:SPI1 */
+    .word     USART0_IRQHandler                 /* 53:USART0 */
+    .word     USART1_IRQHandler                 /* 54:USART1 */
+    .word     USART2_IRQHandler                 /* 55:USART2 */
+    .word     EXTI10_15_IRQHandler              /* 56:EXTI10 to EXTI15 */
+    .word     RTC_Alarm_IRQHandler              /* 57:RTC Alarm */
+    .word     USBD_WKUP_IRQHandler              /* 58:USBD Wakeup */
+    .word     TIMER7_BRK_IRQHandler             /* 59:TIMER7 Break  */
+    .word     TIMER7_UP_IRQHandler              /* 60:TIMER7 Update  */
+    .word     TIMER7_TRG_CMT_IRQHandler         /* 61:TIMER7 Trigger and Commutation */
+    .word     TIMER7_Channel_IRQHandler         /* 62:TIMER7 Channel Capture Compare */
+    .word     ADC2_IRQHandler                   /* 63:ADC2 */
+    .word     EXMC_IRQHandler                   /* 64:EXMC */
+    .word     SDIO_IRQHandler                   /* 65:SDIO */
+    .word     TIMER4_IRQHandler                 /* 66:TIMER4 */
+    .word     SPI2_IRQHandler                   /* 67:SPI2 */
+    .word     UART3_IRQHandler                  /* 68:UART3 */
+    .word     UART4_IRQHandler                  /* 69:UART4 */
+    .word     TIMER5_IRQHandler                 /* 70:TIMER5  */
+    .word     TIMER6_IRQHandler                 /* 71:TIMER6 */
+    .word     DMA1_Channel0_IRQHandler          /* 72:DMA1 Channel0 */
+    .word     DMA1_Channel1_IRQHandler          /* 73:DMA1 Channel1 */
+    .word     DMA1_Channel2_IRQHandler          /* 74:DMA1 Channel2 */
+    .word     DMA1_Channel3_4_IRQHandler        /* 75:DMA1 Channel3 and Channel4 */
+
+    /* Exception Handlers */
+    .weak   NMI_Handler
+    .type   NMI_Handler, STT_FUNC
+NMI_Handler:
+    b       .
+
+    .weak   MemManage_Handler
+    .type   MemManage_Handler, STT_FUNC
+MemManage_Handler:
+    b       .
+
+    .weak   BusFault_Handler
+    .type   BusFault_Handler, STT_FUNC
+BusFault_Handler:
+    b       .
+
+    .weak   UsageFault_Handler
+    .type   UsageFault_Handler, STT_FUNC
+UsageFault_Handler:
+    b       .
+
+    .weak   SVC_Handler
+    .type   SVC_Handler, STT_FUNC
+SVC_Handler:
+    b       .
+
+    .weak   DebugMon_Handler
+    .type   DebugMon_Handler, STT_FUNC
+DebugMon_Handler:
+    b       .
+
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, STT_FUNC
+PendSV_Handler:
+    b       .
+
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, STT_FUNC
+SysTick_Handler:
+    b       .
+
+.global  default_irq_handler
+    .section  .text.default_irq_handler,"ax",%progbits
+    .type  default_irq_handler, STT_FUNC
+default_irq_handler:
+    b  .
+
+    .macro  IRQ handler
+    .weak   \handler
+    .set    \handler, default_irq_handler
+    .endm
+
+    /* IQR Handler */
+    IRQ WWDGT_IRQHandler
+    IRQ LVD_IRQHandler
+    IRQ TAMPER_IRQHandler
+    IRQ RTC_IRQHandler
+    IRQ FMC_IRQHandler
+    IRQ RCU_CTC_IRQHandler
+    IRQ EXTI0_IRQHandler
+    IRQ EXTI1_IRQHandler
+    IRQ EXTI2_IRQHandler
+    IRQ EXTI3_IRQHandler
+    IRQ EXTI4_IRQHandler
+    IRQ DMA0_Channel0_IRQHandler
+    IRQ DMA0_Channel1_IRQHandler
+    IRQ DMA0_Channel2_IRQHandler
+    IRQ DMA0_Channel3_IRQHandler
+    IRQ DMA0_Channel4_IRQHandler
+    IRQ DMA0_Channel5_IRQHandler
+    IRQ DMA0_Channel6_IRQHandler
+    IRQ ADC0_1_IRQHandler
+    IRQ USBD_HP_CAN0_TX_IRQHandler
+    IRQ USBD_LP_CAN0_RX0_IRQHandler
+    IRQ CAN0_RX1_IRQHandler
+    IRQ CAN0_EWMC_IRQHandler
+    IRQ EXTI5_9_IRQHandler
+    IRQ TIMER0_BRK_IRQHandler
+    IRQ TIMER0_UP_IRQHandler
+    IRQ TIMER0_TRG_CMT_IRQHandler
+    IRQ TIMER0_Channel_IRQHandler
+    IRQ TIMER1_IRQHandler
+    IRQ TIMER2_IRQHandler
+    IRQ TIMER3_IRQHandler
+    IRQ I2C0_EV_IRQHandler
+    IRQ I2C0_ER_IRQHandler
+    IRQ I2C1_EV_IRQHandler
+    IRQ I2C1_ER_IRQHandler
+    IRQ SPI0_IRQHandler
+    IRQ SPI1_IRQHandler
+    IRQ USART0_IRQHandler
+    IRQ USART1_IRQHandler
+    IRQ USART2_IRQHandler
+    IRQ EXTI10_15_IRQHandler
+    IRQ RTC_Alarm_IRQHandler
+    IRQ USBD_WKUP_IRQHandler
+    IRQ TIMER7_BRK_IRQHandler
+    IRQ TIMER7_UP_IRQHandler
+    IRQ TIMER7_TRG_CMT_IRQHandler
+    IRQ TIMER7_Channel_IRQHandler
+    IRQ ADC2_IRQHandler
+    IRQ EXMC_IRQHandler
+    IRQ SDIO_IRQHandler
+    IRQ TIMER4_IRQHandler
+    IRQ SPI2_IRQHandler
+    IRQ UART3_IRQHandler
+    IRQ UART4_IRQHandler
+    IRQ TIMER5_IRQHandler
+    IRQ TIMER6_IRQHandler
+    IRQ DMA1_Channel0_IRQHandler
+    IRQ DMA1_Channel1_IRQHandler
+    IRQ DMA1_Channel2_IRQHandler
+    IRQ DMA1_Channel3_4_IRQHandler

bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Source/GCC/startup_gd32.s

+/*
+ * File      : startup_gd32f10x_hd.s
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2021, RT-Thread Development Team
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-01-02     iysheng      first implementation
+ */
+
+.syntax unified
+.cpu cortex-m3
+.fpu softvfp
+.thumb
+
+.global  Reset_Handler
+    .section  .text.Reset_Handler
+    .type  Reset_Handler, STT_FUNC
+Reset_Handler:
+    ldr r1, =_sidata
+    ldr r2, =_sdata
+    ldr r3, =_edata
+
+    subs r3, r2
+    ble fill_bss_start
+
+loop_copy_data:
+    subs r3, #4
+    ldr r0, [r1,r3]
+    str r0, [r2,r3]
+    bgt loop_copy_data
+
+fill_bss_start:
+    ldr r1, =__bss_start
+    ldr r2, =__bss_end
+    movs r0, 0
+    subs r2, r1
+    ble startup_enter
+
+loop_fill_bss:
+    subs r2, #4
+    str r0, [r1, r2]
+    bgt loop_fill_bss
+
+startup_enter:
+    bl SystemInit
+    bl entry
+

bsp/gd32103c-eval/Libraries/CMSIS/core_cm3.c

+/**************************************************************************//**
+ * @file     core_cm3.c
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Source File
+ * @version  V1.30
+ * @date     30. October 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include <stdint.h>
+
+/* define compiler specific symbols */
+#if defined ( __CC_ARM   )
+    #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+    #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+    #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+    #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined   (  __GNUC__  )
+    #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+    #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined   (  __TASKING__  )
+    #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+    #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+
+#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+__ASM uint32_t __get_PSP(void)
+{
+    mrs r0, psp
+    bx lr
+}
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+__ASM void __set_PSP(uint32_t topOfProcStack)
+{
+    msr psp, r0
+    bx lr
+}
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+__ASM uint32_t __get_MSP(void)
+{
+    mrs r0, msp
+    bx lr
+}
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+__ASM void __set_MSP(uint32_t mainStackPointer)
+{
+    msr msp, r0
+    bx lr
+}
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param   value  value to reverse
+ * @return         reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+__ASM uint32_t __REV16(uint16_t value)
+{
+    rev16 r0, r0
+    bx lr
+}
+
+/**
+ * @brief  Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param   value  value to reverse
+ * @return         reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+__ASM int32_t __REVSH(int16_t value)
+{
+    revsh r0, r0
+    bx lr
+}
+
+
+#if (__ARMCC_VERSION < 400000)
+
+/**
+ * @brief  Remove the exclusive lock created by ldrex
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+__ASM void __CLREX(void)
+{
+    clrex
+}
+
+/**
+ * @brief  Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+__ASM uint32_t  __get_BASEPRI(void)
+{
+    mrs r0, basepri
+    bx lr
+}
+
+/**
+ * @brief  Set the Base Priority value
+ *
+ * @param  basePri  BasePriority
+ *
+ * Set the base priority register
+ */
+__ASM void __set_BASEPRI(uint32_t basePri)
+{
+    msr basepri, r0
+    bx lr
+}
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+__ASM uint32_t __get_PRIMASK(void)
+{
+    mrs r0, primask
+    bx lr
+}
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param  priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+__ASM void __set_PRIMASK(uint32_t priMask)
+{
+    msr primask, r0
+    bx lr
+}
+
+/**
+ * @brief  Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+__ASM uint32_t  __get_FAULTMASK(void)
+{
+    mrs r0, faultmask
+    bx lr
+}
+
+/**
+ * @brief  Set the Fault Mask value
+ *
+ * @param  faultMask  faultMask value
+ *
+ * Set the fault mask register
+ */
+__ASM void __set_FAULTMASK(uint32_t faultMask)
+{
+    msr faultmask, r0
+    bx lr
+}
+
+/**
+ * @brief  Return the Control Register value
+ *
+ * @return Control value
+ *
+ * Return the content of the control register
+ */
+__ASM uint32_t __get_CONTROL(void)
+{
+    mrs r0, control
+    bx lr
+}
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+__ASM void __set_CONTROL(uint32_t control)
+{
+    msr control, r0
+    bx lr
+}
+
+#endif /* __ARMCC_VERSION  */
+
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#pragma diag_suppress=Pe940
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void)
+{
+    __ASM("mrs r0, psp");
+    __ASM("bx lr");
+}
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack)
+{
+    __ASM("msr psp, r0");
+    __ASM("bx lr");
+}
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void)
+{
+    __ASM("mrs r0, msp");
+    __ASM("bx lr");
+}
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack)
+{
+    __ASM("msr msp, r0");
+    __ASM("bx lr");
+}
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+    __ASM("rev16 r0, r0");
+    __ASM("bx lr");
+}
+
+/**
+ * @brief  Reverse bit order of value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+    __ASM("rbit r0, r0");
+    __ASM("bx lr");
+}
+
+/**
+ * @brief  LDR Exclusive (8 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 8 bit values)
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+    __ASM("ldrexb r0, [r0]");
+    __ASM("bx lr");
+}
+
+/**
+ * @brief  LDR Exclusive (16 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+    __ASM("ldrexh r0, [r0]");
+    __ASM("bx lr");
+}
+
+/**
+ * @brief  LDR Exclusive (32 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+    __ASM("ldrex r0, [r0]");
+    __ASM("bx lr");
+}
+
+/**
+ * @brief  STR Exclusive (8 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+    __ASM("strexb r0, r0, [r1]");
+    __ASM("bx lr");
+}
+
+/**
+ * @brief  STR Exclusive (16 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+    __ASM("strexh r0, r0, [r1]");
+    __ASM("bx lr");
+}
+
+/**
+ * @brief  STR Exclusive (32 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+    __ASM("strex r0, r0, [r1]");
+    __ASM("bx lr");
+}
+
+#pragma diag_default=Pe940
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void) __attribute__((naked));
+uint32_t __get_PSP(void)
+{
+    uint32_t result = 0;
+
+    __ASM volatile("MRS %0, psp\n\t"
+                   "MOV r0, %0 \n\t"
+                   "BX  lr     \n\t"  : "=r"(result));
+    return (result);
+}
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack) __attribute__((naked));
+void __set_PSP(uint32_t topOfProcStack)
+{
+    __ASM volatile("MSR psp, %0\n\t"
+                   "BX  lr     \n\t" : : "r"(topOfProcStack));
+}
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void) __attribute__((naked));
+uint32_t __get_MSP(void)
+{
+    uint32_t result = 0;
+
+    __ASM volatile("MRS %0, msp\n\t"
+                   "MOV r0, %0 \n\t"
+                   "BX  lr     \n\t"  : "=r"(result));
+    return (result);
+}
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack) __attribute__((naked));
+void __set_MSP(uint32_t topOfMainStack)
+{
+    __ASM volatile("MSR msp, %0\n\t"
+                   "BX  lr     \n\t" : : "r"(topOfMainStack));
+}
+
+/**
+ * @brief  Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+uint32_t __get_BASEPRI(void)
+{
+    uint32_t result = 0;
+
+    __ASM volatile("MRS %0, basepri_max" : "=r"(result));
+    return (result);
+}
+
+/**
+ * @brief  Set the Base Priority value
+ *
+ * @param  basePri  BasePriority
+ *
+ * Set the base priority register
+ */
+void __set_BASEPRI(uint32_t value)
+{
+    __ASM volatile("MSR basepri, %0" : : "r"(value));
+}
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+uint32_t __get_PRIMASK(void)
+{
+    uint32_t result = 0;
+
+    __ASM volatile("MRS %0, primask" : "=r"(result));
+    return (result);
+}
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param  priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+void __set_PRIMASK(uint32_t priMask)
+{
+    __ASM volatile("MSR primask, %0" : : "r"(priMask));
+}
+
+/**
+ * @brief  Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+uint32_t __get_FAULTMASK(void)
+{
+    uint32_t result = 0;
+
+    __ASM volatile("MRS %0, faultmask" : "=r"(result));
+    return (result);
+}
+
+/**
+ * @brief  Set the Fault Mask value
+ *
+ * @param  faultMask  faultMask value
+ *
+ * Set the fault mask register
+ */
+void __set_FAULTMASK(uint32_t faultMask)
+{
+    __ASM volatile("MSR faultmask, %0" : : "r"(faultMask));
+}
+
+/**
+ * @brief  Return the Control Register value
+*
+*  @return Control value
+ *
+ * Return the content of the control register
+ */
+uint32_t __get_CONTROL(void)
+{
+    uint32_t result = 0;
+
+    __ASM volatile("MRS %0, control" : "=r"(result));
+    return (result);
+}
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+void __set_CONTROL(uint32_t control)
+{
+    __ASM volatile("MSR control, %0" : : "r"(control));
+}
+
+
+/**
+ * @brief  Reverse byte order in integer value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in integer value
+ */
+uint32_t __REV(uint32_t value)
+{
+    uint32_t result = 0;
+
+    __ASM volatile("rev %0, %1" : "=r"(result) : "r"(value));
+    return (result);
+}
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+    uint32_t result = 0;
+
+    __ASM volatile("rev16 %0, %1" : "=r"(result) : "r"(value));
+    return (result);
+}
+
+/**
+ * @brief  Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+int32_t __REVSH(int16_t value)
+{
+    uint32_t result = 0;
+
+    __ASM volatile("revsh %0, %1" : "=r"(result) : "r"(value));
+    return (result);
+}
+
+/**
+ * @brief  Reverse bit order of value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+    uint32_t result = 0;
+
+    __ASM volatile("rbit %0, %1" : "=r"(result) : "r"(value));
+    return (result);
+}
+
+/**
+ * @brief  LDR Exclusive (8 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 8 bit value
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+    uint8_t result = 0;
+
+    __ASM volatile("ldrexb %0, [%1]" : "=r"(result) : "r"(addr));
+    return (result);
+}
+
+/**
+ * @brief  LDR Exclusive (16 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+    uint16_t result = 0;
+
+    __ASM volatile("ldrexh %0, [%1]" : "=r"(result) : "r"(addr));
+    return (result);
+}
+
+/**
+ * @brief  LDR Exclusive (32 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+    uint32_t result = 0;
+
+    __ASM volatile("ldrex %0, [%1]" : "=r"(result) : "r"(addr));
+    return (result);
+}
+
+/**
+ * @brief  STR Exclusive (8 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+    uint32_t result = 0;
+
+    __ASM volatile("strexb %0, %2, [%1]" : "=r"(result) : "r"(addr), "r"(value));
+    return (result);
+}
+
+/**
+ * @brief  STR Exclusive (16 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+    uint32_t result = 0;
+
+    __ASM volatile("strexh %0, %2, [%1]" : "=r"(result) : "r"(addr), "r"(value));
+    return (result);
+}
+
+/**
+ * @brief  STR Exclusive (32 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+    uint32_t result = 0;
+
+    __ASM volatile("strex %0, %2, [%1]" : "=r"(result) : "r"(addr), "r"(value));
+    return (result);
+}
+
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif

bsp/gd32103c-eval/Libraries/CMSIS/core_cmFunc.h

+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V3.01
+ * @date     06. March 2012
+ *
+ * @note
+ * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+    #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+    register uint32_t __regControl         __ASM("control");
+    return (__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+    register uint32_t __regControl         __ASM("control");
+    __regControl = control;
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+    register uint32_t __regIPSR          __ASM("ipsr");
+    return (__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+    register uint32_t __regAPSR          __ASM("apsr");
+    return (__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+    register uint32_t __regXPSR          __ASM("xpsr");
+    return (__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+    register uint32_t __regProcessStackPointer  __ASM("psp");
+    return (__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+    register uint32_t __regProcessStackPointer  __ASM("psp");
+    __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+    register uint32_t __regMainStackPointer     __ASM("msp");
+    return (__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+    register uint32_t __regMainStackPointer     __ASM("msp");
+    __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+    register uint32_t __regPriMask         __ASM("primask");
+    return (__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+    register uint32_t __regPriMask         __ASM("primask");
+    __regPriMask = (priMask);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+    register uint32_t __regBasePri         __ASM("basepri");
+    return (__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+    register uint32_t __regBasePri         __ASM("basepri");
+    __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+    register uint32_t __regFaultMask       __ASM("faultmask");
+    return (__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+    register uint32_t __regFaultMask       __ASM("faultmask");
+    __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    register uint32_t __regfpscr         __ASM("fpscr");
+    return (__regfpscr);
+#else
+    return (0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    register uint32_t __regfpscr         __ASM("fpscr");
+    __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
+/* TI CCS specific functions */
+
+#include <cmsis_ccs.h>
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
+{
+    __ASM volatile("cpsie i");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
+{
+    __ASM volatile("cpsid i");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, control" : "=r"(result));
+    return (result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+    __ASM volatile("MSR control, %0" : : "r"(control));
+}
+
+
+/** \brief  Get IPSR Register
+
+    This function returns the content of the IPSR Register.
+
+    \return               IPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, ipsr" : "=r"(result));
+    return (result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, apsr" : "=r"(result));
+    return (result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, xpsr" : "=r"(result));
+    return (result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+    register uint32_t result;
+
+    __ASM volatile("MRS %0, psp\n"  : "=r"(result));
+    return (result);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+    __ASM volatile("MSR psp, %0\n" : : "r"(topOfProcStack));
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+    register uint32_t result;
+
+    __ASM volatile("MRS %0, msp\n" : "=r"(result));
+    return (result);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+    __ASM volatile("MSR msp, %0\n" : : "r"(topOfMainStack));
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, primask" : "=r"(result));
+    return (result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+    __ASM volatile("MSR primask, %0" : : "r"(priMask));
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
+{
+    __ASM volatile("cpsie f");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
+{
+    __ASM volatile("cpsid f");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, basepri_max" : "=r"(result));
+    return (result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
+{
+    __ASM volatile("MSR basepri, %0" : : "r"(value));
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+    uint32_t result;
+
+    __ASM volatile("MRS %0, faultmask" : "=r"(result));
+    return (result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+    __ASM volatile("MSR faultmask, %0" : : "r"(faultMask));
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    uint32_t result;
+
+    __ASM volatile("VMRS %0, fpscr" : "=r"(result));
+    return (result);
+#else
+    return (0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    __ASM volatile("VMSR fpscr, %0" : : "r"(fpscr));
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */

bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_adc.h

+/**
+  ******************************************************************************
+  * @brief   ADC header file of the firmware library.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __GD32F10X_ADC_H
+#define __GD32F10X_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum { FALSE = 0, TRUE } BOOL;
+/* Includes ------------------------------------------------------------------*/
+#include "gd32f10x.h"
+/** @addtogroup GD32F10x_Firmware
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */
+
+/** @defgroup ADC_Exported_Types
+  * @{
+  */
+
+/**
+  * @brief  ADC Init structure definition
+  */
+
+typedef struct {
+    uint32_t ADC_Trig_External;         /*!< AD conversion of regular channels trigger.  */
+    uint8_t ADC_Channel_Number;         /*!< The number of converted ADC channels .
+                                             This parameter must range from 1 to 16. */
+    uint32_t ADC_Data_Align;            /*!< ADC data alignment,left or right. */
+
+    TypeState ADC_Mode_Scan;            /*!< AD conversion mode,multichannels mode or Single channel mode.
+                                             This parameter can be ENABLE or DISABLE */
+    uint32_t ADC_Mode;                  /*!< AD operation mode,independent mode or dual mode.
+                                             This parameter can be a value of @ref ADC_mode */
+    TypeState ADC_Mode_Continuous;      /*!< AD perform mode,continuous mode or single mode.
+                                             This parameter can be ENABLE or DISABLE. */
+} ADC_InitPara;
+
+/**
+  * @}
+  */
+/** @defgroup ADC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup ADC_external_trigger
+  * @{
+  */
+#define ADC_EXTERNAL_TRIGGER_MODE_T1_CC1             ((uint32_t)0x00000000) /*!< Only used in ADC1 and ADC2 */
+#define ADC_EXTERNAL_TRIGGER_MODE_T1_CC2             ((uint32_t)0x00020000) /*!< Only used in ADC1 and ADC2 */
+#define ADC_EXTERNAL_TRIGGER_MODE_T2_CC2             ((uint32_t)0x00060000) /*!< Only used in ADC1 and ADC2 */
+#define ADC_EXTERNAL_TRIGGER_MODE_T3_TRGO            ((uint32_t)0x00080000) /*!< Only used in ADC1 and ADC2 */
+#define ADC_EXTERNAL_TRIGGER_MODE_T4_CC4             ((uint32_t)0x000A0000) /*!< Only used in ADC1 and ADC2 */
+#define ADC_EXTERNAL_TRIGGER_MODE_EXT_IT11_T8_TRGO   ((uint32_t)0x000C0000) /*!< Only used in ADC1 and ADC2 */
+#define ADC_EXTERNAL_TRIGGER_MODE_T1_CC3             ((uint32_t)0x00040000) /*!< Used in ADC1,ADC2 and ADC3 */
+#define ADC_EXTERNAL_TRIGGER_MODE_NONE               ((uint32_t)0x000E0000) /*!< Used in ADC1,ADC2 and ADC3 */
+#define ADC_EXTERNAL_TRIGGER_MODE_T3_CC1             ((uint32_t)0x00000000) /*!< Only used in ADC3 */
+#define ADC_EXTERNAL_TRIGGER_MODE_T2_CC3             ((uint32_t)0x00020000) /*!< Only used in ADC3 */
+#define ADC_EXTERNAL_TRIGGER_MODE_T8_CC1             ((uint32_t)0x00060000) /*!< Only used in ADC3 */
+#define ADC_EXTERNAL_TRIGGER_MODE_T8_TRGO            ((uint32_t)0x00080000) /*!< Only used in ADC3 */
+#define ADC_EXTERNAL_TRIGGER_MODE_T5_CC1             ((uint32_t)0x000A0000) /*!< Only used in ADC3 */
+#define ADC_EXTERNAL_TRIGGER_MODE_T5_CC3             ((uint32_t)0x000C0000) /*!< Only used in ADC3 */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_channels
+  * @{
+  */
+#define ADC_CHANNEL_0                                ((uint8_t)0x00)
+#define ADC_CHANNEL_1                                ((uint8_t)0x01)
+#define ADC_CHANNEL_2                                ((uint8_t)0x02)
+#define ADC_CHANNEL_3                                ((uint8_t)0x03)
+#define ADC_CHANNEL_4                                ((uint8_t)0x04)
+#define ADC_CHANNEL_5                                ((uint8_t)0x05)
+#define ADC_CHANNEL_6                                ((uint8_t)0x06)
+#define ADC_CHANNEL_7                                ((uint8_t)0x07)
+#define ADC_CHANNEL_8                                ((uint8_t)0x08)
+#define ADC_CHANNEL_9                                ((uint8_t)0x09)
+#define ADC_CHANNEL_10                               ((uint8_t)0x0A)
+#define ADC_CHANNEL_11                               ((uint8_t)0x0B)
+#define ADC_CHANNEL_12                               ((uint8_t)0x0C)
+#define ADC_CHANNEL_13                               ((uint8_t)0x0D)
+#define ADC_CHANNEL_14                               ((uint8_t)0x0E)
+#define ADC_CHANNEL_15                               ((uint8_t)0x0F)
+#define ADC_CHANNEL_16                               ((uint8_t)0x10)
+#define ADC_CHANNEL_17                               ((uint8_t)0x11)
+#define ADC_CHANNEL_TEMPSENSOR                       ((uint8_t)ADC_CHANNEL_16)
+#define ADC_CHANNEL_VREFINT                          ((uint8_t)ADC_CHANNEL_17)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_data_align
+  * @{
+  */
+#define ADC_DATAALIGN_RIGHT                          ((uint32_t)0x00000000)
+#define ADC_DATAALIGN_LEFT                           ((uint32_t)0x00000800)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_mode
+  * @{
+  */
+#define ADC_MODE_INDEPENDENT                         ((uint32_t)0x00000000)
+#define ADC_MODE_REGINSERTSIMULT                     ((uint32_t)0x00010000)
+#define ADC_MODE_REGSIMULT_ALTERTRIG                 ((uint32_t)0x00020000)
+#define ADC_MODE_INSERTSIMULT_FASTINTERL             ((uint32_t)0x00030000)
+#define ADC_MODE_INSERTSIMULT_SLOWINTERL             ((uint32_t)0x00040000)
+#define ADC_MODE_INSERTSIMULT                        ((uint32_t)0x00050000)
+#define ADC_MODE_REGSIMULT                           ((uint32_t)0x00060000)
+#define ADC_MODE_FASTINTERL                          ((uint32_t)0x00070000)
+#define ADC_MODE_SLOWINTERL                          ((uint32_t)0x00080000)
+#define ADC_MODE_ALTERTRIG                           ((uint32_t)0x00090000)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_sampling_time
+  * @{
+  */
+#define ADC_SAMPLETIME_1POINT5                       ((uint8_t)0x00)
+#define ADC_SAMPLETIME_7POINT5                       ((uint8_t)0x01)
+#define ADC_SAMPLETIME_13POINT5                      ((uint8_t)0x02)
+#define ADC_SAMPLETIME_28POINT5                      ((uint8_t)0x03)
+#define ADC_SAMPLETIME_41POINT5                      ((uint8_t)0x04)
+#define ADC_SAMPLETIME_55POINT5                      ((uint8_t)0x05)
+#define ADC_SAMPLETIME_71POINT5                      ((uint8_t)0x06)
+#define ADC_SAMPLETIME_239POINT5                     ((uint8_t)0x07)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_external_trigger_sources_for_inserted_channels_conversion
+  * @{
+  */
+#define ADC_EXTERNAL_TRIG_INSERTCONV_T2_TRGO         ((uint32_t)0x00002000) /*!< Only used in ADC1 and ADC2 */
+#define ADC_EXTERNAL_TRIG_INSERTCONV_T2_CC1          ((uint32_t)0x00003000) /*!< Only used in ADC1 and ADC2 */
+#define ADC_EXTERNAL_TRIG_INSERTCONV_T3_CC4          ((uint32_t)0x00004000) /*!< Only used in ADC1 and ADC2 */
+#define ADC_EXTERNAL_TRIG_INSERTCONV_T4_TRGO         ((uint32_t)0x00005000) /*!< Only used in ADC1 and ADC2 */
+#define ADC_EXTERNAL_TRIG_INSERTCONV_EXT_IT15_T8_CC4 ((uint32_t)0x00006000) /*!< Only used in ADC1 and ADC2 */
+#define ADC_EXTERNAL_TRIG_INSERTCONV_T1_TRIG         ((uint32_t)0x00000000) /*!< Used in ADC1,ADC2 and ADC3 */
+#define ADC_EXTERNAL_TRIG_INSERTCONV_T1_CC4          ((uint32_t)0x00001000) /*!< Used in ADC1,ADC2 and ADC3 */
+#define ADC_EXTERNAL_TRIG_INSERTCONV_NONE            ((uint32_t)0x00007000) /*!< Used in ADC1,ADC2 and ADC3 */
+#define ADC_EXTERNAL_TRIG_INSERTCONV_T4_CC3          ((uint32_t)0x00002000) /*!< Only used in ADC3 */
+#define ADC_EXTERNAL_TRIG_INSERTCONV_T8_CC2          ((uint32_t)0x00003000) /*!< Only used in ADC3 */
+#define ADC_EXTERNAL_TRIG_INSERTCONV_T8_CC4          ((uint32_t)0x00004000) /*!< Only used in ADC3 */
+#define ADC_EXTERNAL_TRIG_INSERTCONV_T5_TRGO         ((uint32_t)0x00005000) /*!< Only used in ADC3 */
+#define ADC_EXTERNAL_TRIG_INSERTCONV_T5_CC4          ((uint32_t)0x00006000) /*!< Only used in ADC3 */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_inserted_channel_selection
+  * @{
+  */
+#define ADC_INSERTEDCHANNEL_1                        ((uint8_t)0x14)
+#define ADC_INSERTEDCHANNEL_2                        ((uint8_t)0x18)
+#define ADC_INSERTEDCHANNEL_3                        ((uint8_t)0x1C)
+#define ADC_INSERTEDCHANNEL_4                        ((uint8_t)0x20)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_analog_watchdog_selection
+  * @{
+  */
+#define ADC_ANALOGWATCHDOG_SINGLEREGENABLE           ((uint32_t)0x00800200)
+#define ADC_ANALOGWATCHDOG_SINGLEINSERTENABLE        ((uint32_t)0x00400200)
+#define ADC_ANALOGWATCHDOG_SINGLEREGORINSERTENABLE   ((uint32_t)0x00C00200)
+#define ADC_ANALOGWATCHDOG_ALLREGENABLE              ((uint32_t)0x00800000)
+#define ADC_ANALOGWATCHDOG_ALLINSERTENABLE           ((uint32_t)0x00400000)
+#define ADC_ANALOGWATCHDOG_ALLREGALLINSERTENABLE     ((uint32_t)0x00C00000)
+#define ADC_ANALOGWATCHDOG_NONE                      ((uint32_t)0x00000000)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_interrupts_definition
+  * @{
+  */
+#define ADC_INT_EOC                                  ((uint16_t)0x0220)
+#define ADC_INT_AWE                                  ((uint16_t)0x0140)
+#define ADC_INT_EOIC                                 ((uint16_t)0x0480)
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_flags_definition
+  * @{
+  */
+#define ADC_FLAG_AWE                                 ((uint8_t)0x01)
+#define ADC_FLAG_EOC                                 ((uint8_t)0x02)
+#define ADC_FLAG_EOIC                                ((uint8_t)0x04)
+#define ADC_FLAG_STIC                                ((uint8_t)0x08)
+#define ADC_FLAG_STRC                                ((uint8_t)0x10)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup ADC_Exported_Functions
+  * @{
+  */
+void ADC_DeInit(ADC_TypeDef *ADCx, ADC_InitPara *ADC_InitParaStruct);
+void ADC_Init(ADC_TypeDef *ADCx, ADC_InitPara *ADC_InitParaStruct);
+void ADC_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
+void ADC_DMA_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
+void ADC_INTConfig(ADC_TypeDef *ADCx, uint16_t ADC_INT, TypeState NewValue);
+void ADC_Calibration(ADC_TypeDef *ADCx);
+void ADC_SoftwareStartConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
+TypeState ADC_GetSoftwareStartConvBitState(ADC_TypeDef *ADCx);
+void ADC_DiscModeChannelCount_Config(ADC_TypeDef *ADCx, uint8_t Number);
+void ADC_DiscMode_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
+void ADC_RegularChannel_Config(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_ExternalTrigConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
+uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx);
+uint32_t ADC_GetDualModeConversionValue(void);
+void ADC_AutoInsertedConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
+void ADC_InsertedDiscMode_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
+void ADC_ExternalTrigInsertedConv_Config(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInsertConv);
+void ADC_ExternalTrigInsertedConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
+void ADC_SoftwareStartInsertedConv_Enable(ADC_TypeDef *ADCx, TypeState NewValue);
+TypeState ADC_GetSoftwareStartInsertedConvCmdBitState(ADC_TypeDef *ADCx);
+void ADC_InsertedChannel_Config(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_InsertedSequencerLength_Config(ADC_TypeDef *ADCx, uint8_t Length);
+void ADC_SetInsertedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InsertedChannel, uint16_t Offset);
+uint16_t ADC_GetInsertedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InsertedChannel);
+void ADC_AnalogWatchdog_Enable(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholds_Config(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void ADC_AnalogWatchdogSingleChannel_Config(ADC_TypeDef *ADCx, uint8_t ADC_Channel);
+void ADC_TempSensorVrefint_Enable(TypeState NewValue);
+TypeState ADC_GetBitState(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
+void ADC_ClearBitState(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
+TypeState ADC_GetIntState(ADC_TypeDef *ADCx, uint16_t ADC_INT);
+void ADC_ClearIntBitState(ADC_TypeDef *ADCx, uint16_t ADC_INT);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__GD32F10X_ADC_H */

bsp/gd32103c-eval/Libraries/GD32F1xx_standard_peripheral/Include/gd32f10x_crc.h

+/**
+  ******************************************************************************
+  * @brief   CRC header file of the firmware library.
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __GD32F10X_CRC_H
+#define __GD32F10X_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "gd32f10x.h"
+
+/** @addtogroup GD32F10x_Firmware
+  * @{
+  */
+
+/** @addtogroup CRC
+  * @{
+  */
+
+/** @defgroup CRC_Exported_Functions
+  * @{
+  */
+
+void CRC_ResetDTR(void);
+uint32_t CRC_CalcSingleData(uint32_t CRC_data);
+uint32_t CRC_CalcDataFlow(uint32_t pbuffer[], uint32_t buffer_length);
+uint32_t CRC_ReadDTR(void);
+void CRC_WriteFDTR(uint8_t CRC_fdtr);
+uint8_t CRC_ReadFDTR(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__GD32F10X_CRC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */

bsp/gd32103c-eval/Libraries/SConscript

+import rtconfig
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+# The set of source files associated with this SConscript file.
+
+src = Glob('GD32F1xx_standard_peripheral/Source/*.c')
+src += [cwd + '/CMSIS/GD/GD32F1xx/Source/system_gd32f1xx.c']
+
+#add for startup script
+if rtconfig.CROSS_TOOL == 'gcc':
+    src += [cwd + '/CMSIS/GD/GD32F1xx/Source/GCC/startup_gd32.s']
+    src += [cwd + '/CMSIS/GD/GD32F1xx/Source/GCC/isr_tab.s']
+
+path = [
+    cwd + '/CMSIS/GD/GD32F1xx/Include',
+    cwd + '/CMSIS',
+    cwd + '/GD32F1xx_standard_peripheral/Include',]
+
+CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'GD32F1XX']
+
+group = DefineGroup('GD32_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/gd32103c-eval/SConscript

+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/gd32103c-eval/applications/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/stm32/stm32f103-blue-pill/board/CubeMX_Config/Inc/stm32f1xx_it.h

@@ -24,7 +24,7 @@
 
 #ifdef __cplusplus
  extern "C" {
-#endif 
+#endif
 
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */