Merge pull request #1137 from SummerGGift/upfate_fh8620

[bsp] : modify some rt_inline function to adapt the new compiler

bsp/fh8620/libraries/driverlib/fh_i2c.c

@@ -157,26 +157,6 @@ static int I2C_SetSpeedCount(struct fh_i2c_obj *i2c_obj)
     return 0;
 }
 
-inline UINT8 I2C_GetData(struct fh_i2c_obj *i2c_obj)
-{
-    return GET_REG(i2c_obj->base + OFFSET_I2C_DATA_CMD) & 0xff;
-}
-
-inline void I2C_SetDataCmd(struct fh_i2c_obj *i2c_obj, UINT32 reg)
-{
-    SET_REG(i2c_obj->base + OFFSET_I2C_DATA_CMD, reg);
-}
-
-inline void I2C_SetInterruptMask(struct fh_i2c_obj *i2c_obj, UINT32 mask)
-{
-    SET_REG(i2c_obj->base + OFFSET_I2C_INTR_MASK, mask);
-}
-
-inline UINT32 I2C_GetInterruptMask(struct fh_i2c_obj *i2c_obj)
-{
-    return GET_REG(i2c_obj->base + OFFSET_I2C_INTR_MASK);
-}
-
 UINT32 I2C_ClearAndGetInterrupts(struct fh_i2c_obj *i2c_obj)
 {
     UINT32 stat;
@@ -256,37 +236,6 @@ int I2C_HandleTxAbort(struct fh_i2c_obj *i2c_obj)
         return 0;
 }
 
-inline UINT32 I2C_SetTransmitThreshold(struct fh_i2c_obj *i2c_obj, int txtl)
-{
-    return SET_REG(i2c_obj->base + OFFSET_I2C_TX_TL, txtl);
-}
-
-
-inline UINT32 I2C_GetReceiveFifoLevel(struct fh_i2c_obj *i2c_obj)
-{
-    return GET_REG(i2c_obj->base + OFFSET_I2C_RXFLR);
-}
-
-inline UINT32 I2C_GetTransmitFifoLevel(struct fh_i2c_obj *i2c_obj)
-{
-    return GET_REG(i2c_obj->base + OFFSET_I2C_TXFLR);
-}
-
-inline void I2C_SetSlaveAddress(struct fh_i2c_obj *i2c_obj, rt_uint16_t addr)
-{
-    UINT32 reg;
-    reg = GET_REG(i2c_obj->base + OFFSET_I2C_TAR);
-    reg &= ~(0x3ff);
-    reg |= addr & 0x3ff;
-    SET_REG(i2c_obj->base + OFFSET_I2C_TAR, reg);
-}
-
-inline void I2C_Enable(struct fh_i2c_obj *i2c_obj, int enable)
-{
-    SET_REG(i2c_obj->base + OFFSET_I2C_ENABLE, enable);
-}
-
-
 void I2C_Init(struct fh_i2c_obj *i2c_obj)
 {
     UINT32 ic_con;

bsp/fh8620/libraries/driverlib/fh_mmc.c

@@ -28,31 +28,7 @@
 
 // *1: card off
 // *0: card on
-inline rt_uint32_t MMC_GetCardStatus(struct fh_mmc_obj *mmc_obj)
-{
-    rt_uint32_t card_status = GET_REG(mmc_obj->base + OFFSET_SDC_CDETECT);
-
-    return card_status & 0x1;
-}
-
-inline void MMC_StartDma(struct fh_mmc_obj *mmc_obj)
-{
-    rt_uint32_t reg;
-
-    SET_REG(mmc_obj->base + OFFSET_SDC_DBADDR, (rt_uint32_t)mmc_obj->descriptors);
-    reg = GET_REG(mmc_obj->base + OFFSET_SDC_BMOD);
-    reg |= 1 << 7;
-    SET_REG(mmc_obj->base + OFFSET_SDC_BMOD, reg);
-}
 
-inline void MMC_StopDma(struct fh_mmc_obj *mmc_obj)
-{
-    rt_uint32_t reg;
-
-    reg = GET_REG(mmc_obj->base + OFFSET_SDC_BMOD);
-    reg &= ~(1 << 7);
-    SET_REG(mmc_obj->base + OFFSET_SDC_BMOD, reg);
-}
 
 void MMC_InitDescriptors(struct fh_mmc_obj *mmc_obj, rt_uint32_t *buf, rt_uint32_t size)
 {
@@ -80,67 +56,6 @@ void MMC_InitDescriptors(struct fh_mmc_obj *mmc_obj, rt_uint32_t *buf, rt_uint32
     desc[desc_cnt-1].desc3.bit.buffer_addr1 = 0;
 }
 
-
-inline rt_uint32_t MMC_GetWaterlevel(struct fh_mmc_obj *mmc_obj)
-{
-    return (GET_REG(mmc_obj->base + OFFSET_SDC_STATUS) >> 17) & 0x1fff;
-}
-
-inline rt_uint32_t MMC_GetStatus(struct fh_mmc_obj *mmc_obj)
-{
-    return GET_REG(mmc_obj->base + OFFSET_SDC_STATUS);
-}
-
-inline rt_uint32_t MMC_GetRawInterrupt(struct fh_mmc_obj *mmc_obj)
-{
-    return GET_REG(mmc_obj->base + OFFSET_SDC_RINTSTS);
-}
-
-inline rt_uint32_t MMC_GetUnmaskedInterrupt(struct fh_mmc_obj *mmc_obj)
-{
-    return GET_REG(mmc_obj->base + OFFSET_SDC_MINTSTS);
-}
-
-inline rt_uint32_t MMC_ClearRawInterrupt(struct fh_mmc_obj *mmc_obj, rt_uint32_t interrupts)
-{
-    return SET_REG(mmc_obj->base + OFFSET_SDC_RINTSTS, interrupts);
-}
-
-inline rt_uint32_t MMC_GetInterruptMask(struct fh_mmc_obj *mmc_obj)
-{
-    return GET_REG(mmc_obj->base + OFFSET_SDC_INTMASK);
-}
-
-inline rt_uint32_t MMC_SetInterruptMask(struct fh_mmc_obj *mmc_obj, rt_uint32_t mask)
-{
-    return SET_REG(mmc_obj->base + OFFSET_SDC_INTMASK, mask);
-}
-
-inline void MMC_SetByteCount(struct fh_mmc_obj *mmc_obj, rt_uint32_t bytes)
-{
-    SET_REG(mmc_obj->base + OFFSET_SDC_BYTCNT, bytes);
-}
-
-inline void MMC_SetBlockSize(struct fh_mmc_obj *mmc_obj, rt_uint32_t size)
-{
-    SET_REG(mmc_obj->base + OFFSET_SDC_BLKSIZ, size);
-}
-
-inline rt_uint32_t MMC_GetResponse(struct fh_mmc_obj *mmc_obj, int resp_num)
-{
-    return GET_REG(mmc_obj->base + OFFSET_SDC_RESP0 + resp_num * 4);
-}
-
-inline rt_uint32_t MMC_IsFifoEmpty(struct fh_mmc_obj *mmc_obj)
-{
-    return (GET_REG(mmc_obj->base + OFFSET_SDC_STATUS) >> 2) & 0x1;
-}
-
-inline rt_uint32_t MMC_IsDataStateBusy(struct fh_mmc_obj *mmc_obj)
-{
-    return (GET_REG(mmc_obj->base + OFFSET_SDC_STATUS) >> 10) & 0x1;
-}
-
 int MMC_WriteData(struct fh_mmc_obj *mmc_obj, rt_uint32_t *buf, rt_uint32_t size)
 {
     int filled = 0, fifo_available, i, retries;

bsp/fh8620/libraries/driverlib/fh_wdt.c

@@ -31,12 +31,6 @@ void WDT_Enable(struct fh_wdt_obj *wdt_obj, int enable)
     SET_REG(wdt_obj->base + WDOG_CONTROL_REG_OFFSET, enable);
 }
 
-inline int WDT_IsEnable(struct fh_wdt_obj *wdt_obj)
-{
-    return GET_REG(wdt_obj->base + WDOG_CONTROL_REG_OFFSET) &
-        WDOG_CONTROL_REG_WDT_EN_MASK;
-}
-
 void WDT_SetTopValue(struct fh_wdt_obj *wdt_obj, int top)
 {
     SET_REG(wdt_obj->base + WDOG_TIMEOUT_RANGE_REG_OFFSET, top);

bsp/fh8620/libraries/inc/fh_i2c.h

@@ -208,18 +208,58 @@ struct fh_i2c_obj
 
 };
 
+rt_inline UINT32 I2C_SetTransmitThreshold(struct fh_i2c_obj *i2c_obj, int txtl)
+{
+    return SET_REG(i2c_obj->base + OFFSET_I2C_TX_TL, txtl);
+}
+
+rt_inline UINT32 I2C_GetReceiveFifoLevel(struct fh_i2c_obj *i2c_obj)
+{
+    return GET_REG(i2c_obj->base + OFFSET_I2C_RXFLR);
+}
+
+rt_inline UINT32 I2C_GetTransmitFifoLevel(struct fh_i2c_obj *i2c_obj)
+{
+    return GET_REG(i2c_obj->base + OFFSET_I2C_TXFLR);
+}
+
+rt_inline void I2C_SetSlaveAddress(struct fh_i2c_obj *i2c_obj, rt_uint16_t addr)
+{
+    UINT32 reg;
+    reg = GET_REG(i2c_obj->base + OFFSET_I2C_TAR);
+    reg &= ~(0x3ff);
+    reg |= addr & 0x3ff;
+    SET_REG(i2c_obj->base + OFFSET_I2C_TAR, reg);
+}
+
+rt_inline void I2C_Enable(struct fh_i2c_obj *i2c_obj, int enable)
+{
+    SET_REG(i2c_obj->base + OFFSET_I2C_ENABLE, enable);
+}
+
+rt_inline UINT8 I2C_GetData(struct fh_i2c_obj *i2c_obj)
+{
+    return GET_REG(i2c_obj->base + OFFSET_I2C_DATA_CMD) & 0xff;
+}
+
+rt_inline void I2C_SetDataCmd(struct fh_i2c_obj *i2c_obj, UINT32 reg)
+{
+    SET_REG(i2c_obj->base + OFFSET_I2C_DATA_CMD, reg);
+}
+
+rt_inline void I2C_SetInterruptMask(struct fh_i2c_obj *i2c_obj, UINT32 mask)
+{
+    SET_REG(i2c_obj->base + OFFSET_I2C_INTR_MASK, mask);
+}
+
+rt_inline UINT32 I2C_GetInterruptMask(struct fh_i2c_obj *i2c_obj)
+{
+    return GET_REG(i2c_obj->base + OFFSET_I2C_INTR_MASK);
+}
+
 void I2C_Init(struct fh_i2c_obj *i2c_obj);
-inline void I2C_Enable(struct fh_i2c_obj *i2c_obj, int enable);
-inline void I2C_SetSlaveAddress(struct fh_i2c_obj *i2c_obj, rt_uint16_t addr);
-inline UINT32 I2C_GetTransmitFifoLevel(struct fh_i2c_obj *i2c_obj);
-inline UINT32 I2C_GetReceiveFifoLevel(struct fh_i2c_obj *i2c_obj);
-inline UINT32 I2C_SetTransmitThreshold(struct fh_i2c_obj *i2c_obj, int txtl);
 int I2C_HandleTxAbort(struct fh_i2c_obj *i2c_obj);
 UINT32 I2C_ClearAndGetInterrupts(struct fh_i2c_obj *i2c_obj);
-inline void I2C_SetInterruptMask(struct fh_i2c_obj *i2c_obj, UINT32 mask);
-inline UINT32 I2C_GetInterruptMask(struct fh_i2c_obj *i2c_obj);
-inline void I2C_SetDataCmd(struct fh_i2c_obj *i2c_obj, UINT32 reg);
-inline UINT8 I2C_GetData(struct fh_i2c_obj *i2c_obj);
 int I2C_WaitMasterIdle(struct fh_i2c_obj *i2c_obj);
 int I2C_WaitDeviceIdle(struct fh_i2c_obj *i2c_obj);
 

bsp/fh8620/libraries/inc/fh_mmc.h

@@ -197,18 +197,92 @@ struct fh_mmc_obj
     MMC_DMA_Descriptors     *descriptors;
     void                    (*mmc_reset)(struct fh_mmc_obj *);
 };
-inline void MMC_SetBlockSize(struct fh_mmc_obj *mmc_obj, rt_uint32_t size);
-inline void MMC_SetByteCount(struct fh_mmc_obj *mmc_obj, rt_uint32_t bytes);
-inline rt_uint32_t MMC_GetWaterlevel(struct fh_mmc_obj *mmc_obj);
-inline rt_uint32_t MMC_GetResponse(struct fh_mmc_obj *mmc_obj, int resp_num);
-inline rt_uint32_t MMC_GetRegCmd(struct fh_mmc_obj *mmc_obj);
-inline rt_uint32_t MMC_GetRegCtrl(struct fh_mmc_obj *mmc_obj);
-inline rt_uint32_t MMC_SetInterruptMask(struct fh_mmc_obj *mmc_obj, rt_uint32_t mask);
-inline rt_uint32_t MMC_GetInterruptMask(struct fh_mmc_obj *mmc_obj);
-inline rt_uint32_t MMC_ClearRawInterrupt(struct fh_mmc_obj *mmc_obj, rt_uint32_t interrupts);
-inline rt_uint32_t MMC_GetRawInterrupt(struct fh_mmc_obj *mmc_obj);
-inline rt_uint32_t MMC_GetStatus(struct fh_mmc_obj *mmc_obj);
-inline rt_uint32_t MMC_GetCardStatus(struct fh_mmc_obj *mmc_obj);
+
+rt_inline rt_uint32_t MMC_GetCardStatus(struct fh_mmc_obj *mmc_obj)
+{
+    rt_uint32_t card_status = GET_REG(mmc_obj->base + OFFSET_SDC_CDETECT);
+
+    return card_status & 0x1;
+}
+
+rt_inline void MMC_StartDma(struct fh_mmc_obj *mmc_obj)
+{
+    rt_uint32_t reg;
+
+    SET_REG(mmc_obj->base + OFFSET_SDC_DBADDR, (rt_uint32_t)mmc_obj->descriptors);
+    reg = GET_REG(mmc_obj->base + OFFSET_SDC_BMOD);
+    reg |= 1 << 7;
+    SET_REG(mmc_obj->base + OFFSET_SDC_BMOD, reg);
+}
+
+rt_inline void MMC_StopDma(struct fh_mmc_obj *mmc_obj)
+{
+    rt_uint32_t reg;
+
+    reg = GET_REG(mmc_obj->base + OFFSET_SDC_BMOD);
+    reg &= ~(1 << 7);
+    SET_REG(mmc_obj->base + OFFSET_SDC_BMOD, reg);
+}
+
+rt_inline rt_uint32_t MMC_GetWaterlevel(struct fh_mmc_obj *mmc_obj)
+{
+    return (GET_REG(mmc_obj->base + OFFSET_SDC_STATUS) >> 17) & 0x1fff;
+}
+
+rt_inline rt_uint32_t MMC_GetStatus(struct fh_mmc_obj *mmc_obj)
+{
+    return GET_REG(mmc_obj->base + OFFSET_SDC_STATUS);
+}
+
+rt_inline rt_uint32_t MMC_GetRawInterrupt(struct fh_mmc_obj *mmc_obj)
+{
+    return GET_REG(mmc_obj->base + OFFSET_SDC_RINTSTS);
+}
+
+rt_inline rt_uint32_t MMC_GetUnmaskedInterrupt(struct fh_mmc_obj *mmc_obj)
+{
+    return GET_REG(mmc_obj->base + OFFSET_SDC_MINTSTS);
+}
+
+rt_inline rt_uint32_t MMC_ClearRawInterrupt(struct fh_mmc_obj *mmc_obj, rt_uint32_t interrupts)
+{
+    return SET_REG(mmc_obj->base + OFFSET_SDC_RINTSTS, interrupts);
+}
+
+rt_inline rt_uint32_t MMC_GetInterruptMask(struct fh_mmc_obj *mmc_obj)
+{
+    return GET_REG(mmc_obj->base + OFFSET_SDC_INTMASK);
+}
+
+rt_inline rt_uint32_t MMC_SetInterruptMask(struct fh_mmc_obj *mmc_obj, rt_uint32_t mask)
+{
+    return SET_REG(mmc_obj->base + OFFSET_SDC_INTMASK, mask);
+}
+
+rt_inline void MMC_SetByteCount(struct fh_mmc_obj *mmc_obj, rt_uint32_t bytes)
+{
+    SET_REG(mmc_obj->base + OFFSET_SDC_BYTCNT, bytes);
+}
+
+rt_inline void MMC_SetBlockSize(struct fh_mmc_obj *mmc_obj, rt_uint32_t size)
+{
+    SET_REG(mmc_obj->base + OFFSET_SDC_BLKSIZ, size);
+}
+
+rt_inline rt_uint32_t MMC_GetResponse(struct fh_mmc_obj *mmc_obj, int resp_num)
+{
+    return GET_REG(mmc_obj->base + OFFSET_SDC_RESP0 + resp_num * 4);
+}
+
+rt_inline rt_uint32_t MMC_IsFifoEmpty(struct fh_mmc_obj *mmc_obj)
+{
+    return (GET_REG(mmc_obj->base + OFFSET_SDC_STATUS) >> 2) & 0x1;
+}
+
+rt_inline rt_uint32_t MMC_IsDataStateBusy(struct fh_mmc_obj *mmc_obj)
+{
+    return (GET_REG(mmc_obj->base + OFFSET_SDC_STATUS) >> 10) & 0x1;
+}
 
 void MMC_Init(struct fh_mmc_obj *mmc_obj);
 int MMC_ResetFifo(struct fh_mmc_obj *mmc_obj);

bsp/fh8620/libraries/inc/fh_wdt.h

@@ -56,7 +56,13 @@ struct fh_wdt_obj
 };
 
 void WDT_Enable(struct fh_wdt_obj *wdt_obj, int enable);
-inline int WDT_IsEnable(struct fh_wdt_obj *wdt_obj);
+
+rt_inline int WDT_IsEnable(struct fh_wdt_obj *wdt_obj)
+{
+    return GET_REG(wdt_obj->base + WDOG_CONTROL_REG_OFFSET) &
+        WDOG_CONTROL_REG_WDT_EN_MASK;
+}
+
 void WDT_SetTopValue(struct fh_wdt_obj *wdt_obj, int top);
 void WDT_SetCtrl(struct fh_wdt_obj *wdt_obj, UINT32 reg);
 void WDT_Kick(struct fh_wdt_obj *wdt_obj);