Signed-off-by: NLuca Barbato <lu_zero@gentoo.org>

This fixes builds with --disable-vfp.

Checking for the armv6 cpu flag is incorrect, since vfpv2 isn't
armv6 specific.
Signed-off-by: NMartin Storsjö <martin@martin.st>

This is disabled on iOS, since iOS uses a slightly different ABI
for vararg parameters.
Signed-off-by: NMartin Storsjö <martin@martin.st>

Use two separate functions, depending on whether VFP/NEON is available.

This is set to require armv5te - it uses blx, which is only available
since armv5t, but we don't have a separate configure item for that.
(It also uses ldrd, which requires armv5te, but this could be avoided
if necessary.)
Signed-off-by: NMartin Storsjö <martin@martin.st>

The previous check only caught sizes from -AV_INPUT_BUFFER_PADDING_SIZE
to -1.

This fixes ubsan runtime error: signed integer overflow: 2147483647 + 32
cannot be represented in type 'int'
Signed-off-by: NAndreas Cadhalpun <Andreas.Cadhalpun@googlemail.com>
Signed-off-by: NAnton Khirnov <anton@khirnov.net>

Signed-off-by: NAnton Khirnov <anton@khirnov.net>

Both avio_skip and detect_unknown_subobject use int64_t for the size
parameter.

This fixes a segmentation fault due to infinite recursion.
Signed-off-by: NAndreas Cadhalpun <Andreas.Cadhalpun@googlemail.com>
Signed-off-by: NAlexandra Hájková <alexandra.khirnova@gmail.com>
Signed-off-by: NAnton Khirnov <anton@khirnov.net>

Otherwise invalid values are used unchecked in the next run.
This can cause NULL pointer dereferencing.
Signed-off-by: NAndreas Cadhalpun <Andreas.Cadhalpun@googlemail.com>
Signed-off-by: NAlexandra Hájková <alexandra.khirnova@gmail.com>
Signed-off-by: NAnton Khirnov <anton@khirnov.net>

This makes sure all the frames are returned at the end.
Found-By: NMaxym Dmytrychenko <maxym.dmytrychenko@intel.com>

Same as what is done in 3b6473b4.
Signed-off-by: NAnton Khirnov <anton@khirnov.net>

EAGAIN is already managed in poll_filters().
Signed-off-by: NLuca Barbato <lu_zero@gentoo.org>

Signed-off-by: NLuca Barbato <lu_zero@gentoo.org>

Signed-off-by: NAnton Khirnov <anton@khirnov.net>

Use 8 B-frames and modify the GOP size to be a multiple of the B-frame
count.
Signed-off-by: NAnton Khirnov <anton@khirnov.net>

Before 741b494f, when the reference list
modification description was invalid, the code would substitute the
corresponding reference from the initial ("default") reference list.
After that commit, it will just return an error.

Since there are apparently invalid samples in the wild that used to play
fine with the old code, it is a good idea to re-add some sort of error
resilience here. So, when the reference list modification results in a
missing frame, substitute a previous reference frame for it. The
relevant sample again decodes fine with the same output as previously.

Signed-off-by: NJanne Grunau <janne-libav@jannau.net>

Intel's Instruction Set Reference (as of September 2015) clearly states
that cvtpi2ps switches to MMX state. Actual CPUs do not switch if the
source is a memory location. The Instruction Set Reference from 1999
(Order Number 243191) describes this behaviour but all later versions
I've seen have make no distinction whether MMX registers or memory is
used as source.
The documentation for the matching SSE2 instruction to convert to double
(cvtpi2pd) was fixed (see the valgrind bug
https://bugs.kde.org/show_bug.cgi?id=210264).

It will take time to get a clarification and fixes in place. In the
meantime it makes sense to change ff_int32_to_float_fmul_scalar_sse to
be correct according to the documentation. The vast majority of users
will have SSE2 so a change to the SSE version has little effect.

Fixes fate-checkasm on x86 valgrind targets.

Valgrind 'bug' reported as https://bugs.kde.org/show_bug.cgi?id=357059

Check the full FPU tag word instead of only the lower half and simplify
the comparison.
Use upper-case function base name as macro name to instantiate both
checked_call variants.

This reverts commit 5dfe4eda.

They were superseded with their integer equivalents. Rename integer
decode_hf to decode_hf.

The DCA core decoder converts integer coefficients read from the
bitstream to floats just after reading them (along with dequantization).
All the other steps of the audio reconstruction are done with floats
which makes the output for the DTS lossless extension (XLL)
actually lossy.
This patch changes the DCA core to work with integer coefficients
until QMF. At this point the integer coefficients are converted to floats.
The coefficients for the LFE channel (lfe_data) are not touched.
This is the first step for the really lossless XLL decoding.

They will be used by the integer core decoder.

Not every asm routine is expected clear the MMX state after returning.
It is however a requisite for testing floating point code in checkasm.
Annotate functions requiring cleanup with declare_func_emms() and issue
emms after the call. The remaining functions are checked for having  a
cleared MMX state after return.

Fix related register order issue in ff_h264_idct_add_neon.
Found-by: Nzjh8890 <243186085@qq.com>

This macro unconditionally used out[-1], which causes an out of bounds
read, if out is the very beginning of the buffer.
Signed-off-by: NAndreas Cadhalpun <Andreas.Cadhalpun@googlemail.com>
Signed-off-by: NLuca Barbato <lu_zero@gentoo.org>

Due to this typo max_center can be too large, causing nlsf to be set to
too large values, which in turn can cause nlsf[i - 1] + min_delta[i] to
overflow to a negative value, which is not allowed for nlsf and can
cause an out of bounds read in silk_lsf2lpc.
Signed-off-by: NAndreas Cadhalpun <Andreas.Cadhalpun@googlemail.com>
Signed-off-by: NLuca Barbato <lu_zero@gentoo.org>

Quite a bit faster than int32_to_float_fmul_array8_c calling
ff_int32_to_float_fmul_scalar_neon through FmtConvertContext.
Number of cycles per int32_to_float_fmul_array8 call while decoding
padded.dts on exynos5422:

               before  after   change
cortex-a7:     1270     951    -25%
cortex-a15:     434     285    -34%

checkasm --bench cycle counts:     cortex-a15   cortex-a7
int32_to_float_fmul_array8_c:      1730.4       4384.5
int32_to_float_fmul_array8_neon_c:  571.5       1694.3
int32_to_float_fmul_array8_neon:    374.0       1448.8

Interesting are the differences between
int32_to_float_fmul_array8_neon_c and int32_to_float_fmul_array8_neon.
The former is current behaviour of calling
ff_int32_to_float_fmul_scalar_neon repeatedly from the c function,
The raw numbers differ since checkasm uses different lengths than the
dca decoder.

3% faster dts decoding on a cortex-a57.

                                 cortex-a57   cortex-a53
int32_to_float_fmul_array8_c:    1270.9       4475.6
int32_to_float_fmul_array8_neon:  328.6        569.2
int32_to_float_fmul_scalar_c:     928.5       4119.6
int32_to_float_fmul_scalar_neon:  309.1        524.1

~25% faster dts decoding overall. The checkasm CPU cycles numbers are
not that useful since synth_filter_float() calls FFTContext.imdct_half().

                         cortex-a57   cortex-a53
synth_filter_float_c:    1866.2       3490.9
synth_filter_float_neon:  915.0       1531.5

With fftc.imdct_half forced to imdct_half_neon:
                         cortex-a57   cortex-a53
synth_filter_float_c:    1718.4       3025.3
synth_filter_float_neon:  926.2       1530.1

~2% faster dts decoding overall.

                    cortex-a57   cortex-a53
dca_decode_hf_c:    474.8        1659.9
dca_decode_hf_neon: 225.2         301.1
dca_lfe_fir0_c:     913.2        1537.7
dca_lfe_fir0_neon:  286.8         451.9
dca_lfe_fir1_c:     848.7        1711.5
dca_lfe_fir1_neon:  387.1         506.4

The vector mode was deprecated in ARMv7-A/VFPv3 and various cpu
implementations do not support it in hardware. Vector mode code will
depending the OS either be emulated in software or result in an illegal
instruction on cpus which does not support it. This was not really
problem in practice since NEON implementations of the same functions are
preferred. It will however become a problem for checkasm which tests
every cpu flag separately.

Since this is a cpu feature newer cpu do not support anymore the
behaviour of this flag differs from the other flags. It can be only
activated by runtime cpu feature selection.