1. 15 5月, 2010 1 次提交
  2. 25 2月, 2010 1 次提交
  3. 24 2月, 2010 1 次提交
    • J
      x86/PCI: Moorestown PCI support · a712ffbc
      Jesse Barnes 提交于
      The Moorestown platform only has a few devices that actually support
      PCI config cycles.  The rest of the devices use an in-RAM MCFG space
      for the purposes of device enumeration and initialization.
      
      There are a few uglies in the fake support, like BAR sizes that aren't
      a power of two, sizing detection, and writes to the real devices, but
      other than that it's pretty straightforward.
      
      Another way to think of this is not really as PCI at all, but just a
      table in RAM describing which devices are present, their capabilities
      and their offsets in MMIO space.  This could have been done with a
      special new firmware table on this platform, but given that we do have
      some real PCI devices too, simply describing things in an MCFG type
      space was pretty simple.
      Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
      LKML-Reference: <43F901BD926A4E43B106BF17856F07559FB80D08@orsmsx508.amr.corp.intel.com>
      Signed-off-by: NJacob Pan <jacob.jun.pan@intel.com>
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      a712ffbc