- 06 12月, 2010 1 次提交
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由 Chris Wilson 提交于
There's not much we can do here but hope for the best. However the first failure happens quite frequently and if often remedied by the second attempt to reset HEAD. So only print the error if that attempt also fails. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=19802Reported-by: NThomas Meyer <thomas@m3y3r.de> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
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- 08 11月, 2010 1 次提交
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由 Chris Wilson 提交于
My Sandybridge only reports 0 for the ring buffer registers, causing it to hang as soon as we exhaust the available ring. As a workaround, take advantage of our huge ring buffers and use the auto-reporting mechanism to update the status page with the HEAD location every 64 KiB. Cherry-picked from 6aa56062. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=31404Tested-by: NZhao Jian <jian.j.zhao@intel.com> Cc: stable@kernel.org Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 02 11月, 2010 1 次提交
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由 Chris Wilson 提交于
On some stepping of SNB cpu, the first command to be parsed in BLT command streamer should be MI_BATCHBUFFER_START otherwise the GPU may hang. (cherry picked from commit 8d19215b) Conflicts: drivers/gpu/drm/i915/intel_ringbuffer.c drivers/gpu/drm/i915/intel_ringbuffer.h Signed-off-by: NZou Nan hai <nanhai.zou@intel.com> Cc: stable@kernel.org Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 25 10月, 2010 1 次提交
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由 Chris Wilson 提交于
... to prevent flush processing of an idle (or even absent) ring. This fixes a regression during suspend from 87acb0a5. Reported-and-tested-by: NAlexey Fisher <bug-track@fisher-privat.net> Tested-by: NPeter Clifton <pcjc2@cam.ac.uk> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 23 10月, 2010 1 次提交
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由 Chris Wilson 提交于
This should fix the error along the reset path were we tried to clear the tail register by setting it to 0, but were in fact setting it to the current value and complaining when it did not reset to 0. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 22 10月, 2010 4 次提交
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由 Chris Wilson 提交于
So remove the redundant bit in the capabilities block and s/IS_IRONLAKE/IS_GEN5/. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
Based on an original patch by Zhenyu Wang, this initializes the BLT ring for SandyBridge and enables support for user execbuffers. Cc: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
... before someone tries to use it. The code both calls intel_ring_begin/advance() and open-codes the bookkeeping performed by those two functions. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
In commit 8187a2b7, the number of dwords used in the ringbuffer for executing the batch buffer was erroneously changed from 2 to 4. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 19 10月, 2010 1 次提交
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由 Chris Wilson 提交于
If userspace is submitting so many long running batches that the ring becomes full, throttle by sleeping for a 1ms before checking for free space. Simply yielding was causing excessive scheduler overhead whilst making no progress. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 30 9月, 2010 1 次提交
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由 Chris Wilson 提交于
... and check more regularly. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 25 9月, 2010 5 次提交
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由 Daniel Vetter 提交于
It's the same code, essentially, so kill all copies safe one unified version. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Daniel Vetter 提交于
All functions are extremely similar, so fold them into one generic implementation. This function isn't used anyway, because there's not yet a bsd ring error state dumper. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Daniel Vetter 提交于
Two macros that use a base address for HWS_PGA were missing, add them. Also switch the remaining users of *_ACTHD to the ring-base one. Kill the other ring-specific macros because they're now unused. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> [ickle: And silence checkpatch whilst in the vicinity] Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Daniel Vetter 提交于
This was mixed up in the following patch: commit a6c45cf0 Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Fri Sep 17 00:32:17 2010 +0100 drm/i915: INTEL_INFO->gen supercedes i8xx, i9xx, i965g Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
Avoid cause latencies in other clients by not taking the global struct mutex and moving the per-client request manipulation a local per-client mutex. For example, this allows a compositor to schedule a page-flip (through X) whilst an OpenGL application is monopolising the GPU. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 21 9月, 2010 15 次提交
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由 Chris Wilson 提交于
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Daniel Vetter 提交于
Always PAGE_SIZE and only complicates the code. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Daniel Vetter 提交于
The compiler happily does that for us. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Daniel Vetter 提交于
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Daniel Vetter 提交于
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Daniel Vetter 提交于
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Daniel Vetter 提交于
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Daniel Vetter 提交于
Documentation explicitly mentions that the ring registers are designed to have the same offsets relative to a base registers. Use this to fight the code beaurocratic in intel_ringbuffer.c. No code changes in this patch, just the new definitions. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Xiang, Haihao 提交于
This ring buffer is used for video decoding/encoding on Sandybridge. Signed-off-by: NXiang, Haihao <haihao.xiang@intel.com> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
As noted by Zhenyu, we can now simply replace the existing advance hook by calling the new set_tail function pointer directly. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Xiang, Haihao 提交于
This is prepared for video codec ring buffer on Sandybridge. It is needed to read/write more than one register to move the tail pointer of the video codec ring on Sandybridge. Signed-off-by: NXiang, Haihao <haihao.xiang@intel.com> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Xiang, Haihao 提交于
Introduce intel_init_render_ring_buffer(), intel_init_bsd_ring_buffer for ring initialization. Signed-off-by: NXiang, Haihao <haihao.xiang@intel.com> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
When flushing the GPU domains,we emit a flush on *both* rings, even though they share a unified cache. Only emit the flush on the currently active ring. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Chris Wilson 提交于
Avoid confusion between i965g meaning broadwater and the gen4+ chipset families. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 15 9月, 2010 1 次提交
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由 Chris Wilson 提交于
This can always be re-added should somebody find a use... Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 08 9月, 2010 1 次提交
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由 Daniel Vetter 提交于
... instead of threading flush_domains through the execbuf code to i915_add_request. With this change 2 small cleanups are possible (likewise the majority of the patch): - The flush_domains parameter of i915_add_request is always 0. Drop it and the corresponding logic. - Ditto for the seqno param of i915_gem_process_flushing_list. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 07 9月, 2010 1 次提交
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由 Zhenyu Wang 提交于
MI_FLUSH is being deprecated, but still available on Sandybridge. Make sure it's enabled as userspace still uses MI_FLUSH. Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Cc: stable@kernel.org Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 10 8月, 2010 6 次提交
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由 Zou Nan hai 提交于
This is required by the spec, and without this some 3D programs will hang after resume from RC6 we enable that. Signed-off-by: NZou Nan hai <nanhai.zou@intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Chris Wilson 提交于
The cleanup path for early abort failed to nullify the gem_buffer. The likely consequence of this is zero, since a failure here should mean aborting the module load. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Chris Wilson 提交于
This will be used by the eviction logic to maintain fairness between the rings. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Chris Wilson 提交于
As the function has been reduced to a store plus increment, the body is now smaller than the call so inline it. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Chris Wilson 提交于
As we check that the ringbuffer will not wrap upon emission, we do not need to check that incrementing the tail wrapped every time. However, we do upon advancing just in case the tail is now pointing at the very end of the ring. Likewise we can account for the space used during emission in begin() and avoid decrementing it for every emit. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Chris Wilson 提交于
The tail is quadword aligned, so we can add two MI_NOOP as a time. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NEric Anholt <eric@anholt.net>
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