Many interrupts that share a single mask source but are on different
hardware vectors will have an associated register tied to an INTEVT that
denotes the precise cause for the interrupt exception being triggered.

This introduces the concept of IRQ subgroups in the intc core, where
a virtual IRQ map is constructed for each of the pre-defined cause bits,
and a higher level chained handler takes control of the parent INTEVT.
This enables CPUs with heavily muxed IRQ vectors (especially across
disjoint blocks) to break things out in to a series of managed chained
handlers while being able to dynamically lookup and adopt the IRQs
created for them.

This is largely an opt-in interface, requiring CPUs to manually submit
IRQs for subgroup splitting, in addition to providing identifiers in
their enum maps that can be used for lazy lookup via the radix tree.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This implements a scheme roughly analogous to the PowerPC virtual to
hardware IRQ mapping, which we use for IRQ to per-controller ID mapping.
This makes it possible for drivers to use the IDs directly for lookup
instead of hardcoding the vector.

The main motivation for this work is as a building block for dynamically
allocating virtual IRQs for demuxing INTC events sharing a single INTEVT
in addition to a common masking source.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Some controllers will need to be initialized lazily due to pinmux
constraints, while others may simply have no need to be brought online if
there are no backing devices for them attached. In this case it's still
necessary to be able to reserve their hardware vector map before dynamic
IRQs get a hold of them.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Wrapping pr_fmt to the KBUILD_MODNAME prefix seems to be the trendy
thing to do these days, so just do that instead of manually tidying
up the stragglers.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This implements support for hardware-managed IRQ balancing as implemented
by SH-X3 cores (presently only hooked up for SH7786, but can probably be
carried over to other SH-X3 cores, too).

CPUs need to specify their distribution register along with the mask
definitions, as these follow the same format. Peripheral IRQs that don't
opt out of balancing will be automatically distributed at the whim of the
hardware block, while each CPU needs to verify whether it is handling the
IRQ or not, especially before clearing the mask.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds support for hardware-assisted userspace irq masking for
special priority levels. Due to the SR.IMASK interactivity, only some
platforms implement this in hardware (including but not limited to
SH-4A interrupt controllers, and ARM-based SH-Mobile CPUs). Each CPU
needs to wire this up on its own, for now only SH7786 is wired up as an
example.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The printk loglevels are all over the place, make them a bit more
coherent, and add some registration notification while we're at it.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Presently the sysdevs are simply numbered based on the list position,
without having any direct way of figuring out which controller these are
actually mapping to. This provides a name attr for mapping out the chip
name.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h

percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files.  percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.

percpu.h -> slab.h dependency is about to be removed.  Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability.  As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.

  http://userweb.kernel.org/~tj/misc/slabh-sweep.py

The script does the followings.

* Scan files for gfp and slab usages and update includes such that
  only the necessary includes are there.  ie. if only gfp is used,
  gfp.h, if slab is used, slab.h.

* When the script inserts a new include, it looks at the include
  blocks and try to put the new include such that its order conforms
  to its surrounding.  It's put in the include block which contains
  core kernel includes, in the same order that the rest are ordered -
  alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
  doesn't seem to be any matching order.

* If the script can't find a place to put a new include (mostly
  because the file doesn't have fitting include block), it prints out
  an error message indicating which .h file needs to be added to the
  file.

The conversion was done in the following steps.

1. The initial automatic conversion of all .c files updated slightly
   over 4000 files, deleting around 700 includes and adding ~480 gfp.h
   and ~3000 slab.h inclusions.  The script emitted errors for ~400
   files.

2. Each error was manually checked.  Some didn't need the inclusion,
   some needed manual addition while adding it to implementation .h or
   embedding .c file was more appropriate for others.  This step added
   inclusions to around 150 files.

3. The script was run again and the output was compared to the edits
   from #2 to make sure no file was left behind.

4. Several build tests were done and a couple of problems were fixed.
   e.g. lib/decompress_*.c used malloc/free() wrappers around slab
   APIs requiring slab.h to be added manually.

5. The script was run on all .h files but without automatically
   editing them as sprinkling gfp.h and slab.h inclusions around .h
   files could easily lead to inclusion dependency hell.  Most gfp.h
   inclusion directives were ignored as stuff from gfp.h was usually
   wildly available and often used in preprocessor macros.  Each
   slab.h inclusion directive was examined and added manually as
   necessary.

6. percpu.h was updated not to include slab.h.

7. Build test were done on the following configurations and failures
   were fixed.  CONFIG_GCOV_KERNEL was turned off for all tests (as my
   distributed build env didn't work with gcov compiles) and a few
   more options had to be turned off depending on archs to make things
   build (like ipr on powerpc/64 which failed due to missing writeq).

   * x86 and x86_64 UP and SMP allmodconfig and a custom test config.
   * powerpc and powerpc64 SMP allmodconfig
   * sparc and sparc64 SMP allmodconfig
   * ia64 SMP allmodconfig
   * s390 SMP allmodconfig
   * alpha SMP allmodconfig
   * um on x86_64 SMP allmodconfig

8. percpu.h modifications were reverted so that it could be applied as
   a separate patch and serve as bisection point.

Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: NTejun Heo <tj@kernel.org>
Guess-its-ok-by: NChristoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>

Extend the INTC code with ioremap() support V2.

Support INTC controllers that are not accessible through
a 1:1 virt:phys window. Needed by SH-Mobile ARM INTCS.

The INTC code behaves as usual if the io window resource
is omitted. The slow phys->virt lookup only happens during
setup. The fast path code operates on virtual addresses.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Extend the INTC code to warn and return an error code
in the case of memory allocation failure.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This hooks up the ->set_affinity() for the INTC controllers, which can be
done as just a simple copy of the cpumask. The enable/disable paths
already handle SMP register strides, so we just test the affinity mask in
these paths to determine which strides to skip over.

The early enable/disable path happens prior to the IRQs being registered,
so we have no affinity mask established at that point, in which case we
just default to CPU_MASK_ALL. This is left as it is to permit the force
enable/disable code to retain existing semantics.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Presently there's an ordering issue with the chained handler change
which places the set_irq_chip() after set_irq_chained_handler(). This
causes a warning to be emitted as the IRQ chip needs to be set first.
However, there is the caveat that redirect IRQs can't use the parent
IRQ's irq chip as they are just dummy redirects, resulting in
intc_enable() blowing up when set_irq_chained_handler() attempts to
start up the redirect IRQ. In these cases we can just use dummy_irq_chip
directly, as we already extract the parent IRQ and chip from the redirect
handler.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Extend the shared INTC code with force_disable support to
allow keeping mask bits statically disabled. Needed for
SDHI support to mask out unsupported interrupt sources.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch updates the shared INTC code to use
set_irq_chained_handler() for intc_redirect_irq().

With this in place request_irq() on a merged irq
which has been redirected will now return -EINVAL
instead of 0 together with a crash. This thanks to
the protection of the IRQ_NOREQUEST flag set for
chained interrupt handlers.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Extend the shared INTC code with force_enable support to
allow keeping mask bits statically enabled. Needed by
upcoming INTC SDHI patches that mux together a bunch of
vectors to a single linux interrupt which is masked by
a priority register, but needs individual mask bits
constantly enabled.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch updates the INTC code by moving all vectors,
groups and registers from struct intc_desc to struct
intc_hw_desc.

The idea is that INTC tables should go from using the
macro(s) DECLARE_INTC_DESC..() only to using struct
intc_desc with name and hw initialized using the macro
INTC_HW_DESC(). This move makes it easy to initialize
an extended struct intc_desc in the future.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Reuse the SuperH INTC code on ARM by using set_irq_flags()
to set IRQF_VALID on ARM platforms.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This just reworks the existing create_irq_on_node() in to the new
create_irq_nr() which is generally exposed. This permits boards that
haven't converted over to sparseirq to try and use their existing ranges,
rather than having arbitrary vectors assigned to them.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The resume from hibernation patch introduced build failure, fix it up..
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch fixes the resume from hibernation
in the intc sysdev device when it manages 'redirect' irq
Signed-off-by: NFrancesco Virlinzi <francesco.virlinzi@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Different CPUs will have different starting vectors, with varying
amounts of reserved or unusable vector space prior to the first slot.
This introduces a legacy vector reservation system that inserts itself in
between the CPU vector map registration and the platform specific IRQ
setup. This works fine in practice as the only new vectors that boards
need to establish on their own should be dynamically allocated rather
than arbitrarily assigned. As a plus, this also makes all of the
converted platforms sparseirq ready.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds support for dynamic IRQ allocation/deallocation for all parts
using the SH-style vectored IRQs. While this is not inherently
INTC-specific, the INTC code is the main tie-in for vectored IRQ
registration, and is the only place that a full view of the utilized
vector map is possible.

The implementation is fairly straightforward, implementing a flat IRQ map
where each registered vector is reserved, allowing us to scan for holes
and dynamically wire up IRQs lazily later on in the boot stage. This
piggybacks on top of sparseirq in order to make the best use of the
available vector space.

Dynamic IRQs can be used for any number of things, ranging from MSI in
the SH-X3 PCIe case down to demux vectors for board FPGAs and system
controllers that presently allocate an arbitrary range. In the latter
case, this also allows those platforms to use sparseirq without blowing
up, which brings us one step closer to enabling sparseirq as the default
for all platform and CPU combinations.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Currently this is ifdef'ed under SH-3 and SH-4A, but there are other CPUs
that will need this as well. Given the size of the existing data
structures, this doesn't cause any additional cacheline utilization for
the existing users, so has no direct impact on the data structures.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This fixes up the simplified multi-evt handling when sparseirq support is
enabled. While vectors are redirected through the single unique masking
source, each one of the redirected vectors still requires its own backing
irq_desc, which needs to be manually allocated in the sparseirq case.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch changes the way in which "multi-evt" interrups are handled.
The intc_evt2irq_table and related intc_evt2irq() have been removed and
the "redirecting" handler is installed for the coupled interrupts.

Thanks to that the do_IRQ() function don't have to use another level
of indirection for all the interrupts...
Signed-off-by: NPawel Moll <pawel.moll@st.com>
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

It is possible for the CPU to re-enable it's interrupt block bit
before the write to the interrupt controller has actually masked out
the external interupt at the controller. We get around this by
reading back from the interrupt controller which will ensure the
write has happened.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Now that the slab allocators are available much earlier, this triggers a
the slab_is_available() warning when registering the interrupt
controller. Convert to kzalloc() with GFP_NOWAIT, as per the generic
changes.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Now that the dependent patches are merged, we are ready to enable
sparseirq support. This simply adds the Kconfig option, and then converts
from the _cpu to the _node allocation routines to follow the upstream
sparseirq API changes.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

irq_to_desc_alloc_cpu() has been renamed to irq_to_desc_alloc_node() in
-next, but as we can not presently enable SPARSE_IRQ without the early
irq_desc alloc patch, protect it with an ifdef until the interface has
settled and we are ready to enable it system-wide.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This hooks in irq_to_desc_alloc_cpu() to the necessary code paths in the
intc and ipr controller registration paths. As these are the primary call
paths for all SH CPUs, this alone will make all CPUs sparse IRQ ready.

There is the added benefit now that each CPU contains specific IPR and
INTC tables, so only the vectors with interrupt sources backing them will
ever see an irq_desc instantiation. This effectively packs irq_desc
down to match the CPU, rather than padding NR_IRQS out to cover the valid
vector range.

Boards with extra sources will still have to fiddle with the nr_irqs
setting, but they can continue doing so through the machvec as before.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

It's required for all modules loaded in the previous runtime
session because not initilized duing the kernel start-up.
Signed-off-by: NFrancesco Virlinzi <francesco.virlinzi@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Add set_irq_wake() support to intc using sysdev and suspend.

The intc controllers are put on a list at registration time
and registered as sysdev devices later on during the boot.

The sysdev class suspend callback is used to find irqs with
wakeup enabled belonging to our intc controller. Such irqs
are simply enabled so wakeup interrupts may reach the cpu.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Modify the intc code to install a disable callback. The current
solution without a disable callback results in use of the
generic default_disable() function. This function is a no-op
so suspend_device_irqs() will not disable any intc interrupts
at suspend time without this patch. Also, install enable and
shutdown callbacks while at it.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This includes the IRQ number in addition to the vector, as not all
platforms wrap in with INTC_VECT().
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Instead of keeping the single vector -> single linux irq mapping
we extend the intc code to support merging of vectors to a single
linux irq. This helps processors such as sh7750, sh7780 and sh7785
which have more vectors than masking ability. With this patch in
place we can modify the intc tables to use one irq per maskable
irq source. Please note the following:

 - If multiple vectors share the same enum then only the
   first vector will be available as a linux irq.

 - Drivers may need to be rewritten to get pending irq
   source from the hardware block instead of irq number.

This patch together with the sh7785 specific intc tables solves
DMA controller irq issues related to buggy interrupt masking.
Reported-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The INTC code will be re-used across different architectures, so move
this out to drivers/sh/ and include/linux/sh_intc.h respectively.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

bit is unsigned, so test before subtraction
Signed-off-by: NRoel Kluin <roel.kluin@gmail.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This patch is based on interrupt acknowledge code for external
interrupt sources on sh3 processors and adds on sh4a processors.
Signed-off-by: NYoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>