- 02 8月, 2010 4 次提交
-
-
由 Chris Wilson 提交于
drivers/gpu/drm/i915/i915_drv.h|676 col 19| warning: dubious bitfield without explicit `signed' or `unsigned' drivers/gpu/drm/i915/i915_drv.h|712 col 19| warning: dubious bitfield without explicit `signed' or `unsigned' Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NEric Anholt <eric@anholt.net>
-
由 Chris Wilson 提交于
Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NEric Anholt <eric@anholt.net>
-
由 Zhao Yakui 提交于
About 0.2W power can be saved on one HP laptop. Signed-off-by: NZhao Yakui <yakui.zhao@intel.com> Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
-
由 Zhao Yakui 提交于
For self-refresh mode WM calculation's "line time" should use mode's htotal instead of hdisplay. "surface width" is the hdisplay for display plane and 64 for cursor plane. Signed-off-by: NZhao Yakui <yakui.zhao@intel.com> Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
-
- 19 6月, 2010 1 次提交
-
-
由 Jesse Barnes 提交于
Gen3 chips have slightly different flip commands, and also contain a bit that indicates whether a "flip pending" interrupt means the flip has been queued or has been completed. So implement support for the gen3 flip command, and make sure we use the flip pending interrupt correctly depending on the value of ECOSKPD bit 0. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NEric Anholt <eric@anholt.net>
-
- 15 6月, 2010 1 次提交
-
-
由 Zou Nan hai 提交于
The ring_begin API was taking a number of bytes, while all of our other begin/end macros take number of dwords. Change the API over to dwords to prevent future bugs. Signed-off-by: NZou Nan hai <nanhai.zou@intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
-
- 08 6月, 2010 1 次提交
-
-
由 Dave Airlie 提交于
(regression fix since fbdev/kms rework). My fb rework didn't remember about the 84/65s. Reported-by: NOndrej Zary <linux@rainbow-software.org> Tested-by: NOndrej Zary <linux@rainbow-software.org> Signed-off-by: NDave Airlie <airlied@redhat.com>
-
- 27 5月, 2010 9 次提交
-
-
由 Eric Anholt 提交于
Fixes /debug/dri/0/i915_gem_interrupt output for status page. Signed-off-by: NEric Anholt <eric@anholt.net>
-
由 Li Peng 提交于
Pineview with DDR3 memory has different latencies to enable CxSR. This patch updates CxSR latency table to add Pineview DDR3 latency configuration. It also adds one flag "is_ddr3" for checking DDR3 setting in MCHBAR. Cc: Shaohua Li <shaohua.li@intel.com> Cc: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: NLi Peng <peng.li@intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
-
由 Daniel Vetter 提交于
This saves a whooping 7 dwords. Zero functional changes. Because some of the refcounts are rather tightly calculated, I've put BUG_ONs in the code to check for overflows. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NEric Anholt <eric@anholt.net>
-
由 Jesse Barnes 提交于
Add power monitoring support to the i915 driver for use by the IPS driver. Export the available power info to the IPS driver through a few new inter-driver hooks. When used together, the IPS driver and this patch can significantly increase graphics performance on Ironlake class chips. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> [anholt: Fixed 32-bit compile. stupid obfuscating div_u64()] Signed-off-by: NEric Anholt <eric@anholt.net>
-
由 Zou Nan hai 提交于
The BSD (bit stream decoder) ring is used for accessing the BSD engine which decodes video bitstream for H.264 and VC1 on G45+. It is asynchronous with the render ring and has access to separate parts of the GPU from it, though the render cache is coherent between the two. Signed-off-by: NZou Nan hai <nanhai.zou@intel.com> Signed-off-by: NXiang Hai hao <haihao.xiang@intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
-
由 Zou Nan hai 提交于
The active list and request list move into the ringbuffer structure, so each can track its active objects in the order they are in that ring. The flushing list does not, as it doesn't matter which ring caused data to end up in the render cache. Objects gain a pointer to the ring they are active on (if any). Signed-off-by: NZou Nan hai <nanhai.zou@intel.com> Signed-off-by: NXiang Hai hao <haihao.xiang@intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
-
由 Zou Nan hai 提交于
Introduces a more complete intel_ring_buffer structure with callbacks for setup and management of a particular ringbuffer, and converts the render ring buffer consumers to use it. Signed-off-by: NZou Nan hai <nanhai.zou@intel.com> Signed-off-by: NXiang Hai hao <haihao.xiang@intel.com> [anholt: Fixed up whitespace fail and rebased against prep patches] Signed-off-by: NEric Anholt <eric@anholt.net>
-
由 Eric Anholt 提交于
With the advent of the BSD ring, be clear about which ring this is. The docs are pretty consistent with calling this the Render engine at this point.
-
由 Eric Anholt 提交于
This is preparation for supporting multiple ringbuffers on Ironlake. The non-copy-and-paste changes are: - de-staticing functions - I915_GEM_GPU_DOMAINS moving to i915_drv.h to be used by both files. - i915_gem_add_request had only half its implementation copy-and-pasted out of the middle of it.
-
- 11 5月, 2010 2 次提交
-
-
由 Daniel Vetter 提交于
This lru tracks fences, not objects, so move it to where it belongs. As a side effect, this nicely shrinks drm_i915_gem_object by two pointers. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NEric Anholt <eric@anholt.net>
-
由 Adam Jackson 提交于
Multifunction SDVO cards stopped working after 14571b4c, and would report something that looked remarkably like an ADD2 SPD ROM instead of EDID. This appears to be because DDC bus selection was utterly horked by that commit; controlled_output was no longer always a single bit, so intel_sdvo_select_ddc_bus would pick bus 0, which is (unsurprisingly) the SPD ROM bus, not a DDC bus. So, instead of that, let's just use the DDC bus the child device table tells us to use. I'm guessing at the bitmask and shifting from VBIOS dumps, but it can't possibly be worse. cf. https://bugzilla.redhat.com/584229Signed-off-by: NAdam Jackson <ajax@redhat.com> Signed-off-by: NEric Anholt <eric@anholt.net>
-
- 08 5月, 2010 1 次提交
-
-
由 Adam Jackson 提交于
Signed-off-by: NAdam Jackson <ajax@redhat.com> Signed-off-by: NEric Anholt <eric@anholt.net>
-
- 23 4月, 2010 2 次提交
-
-
由 Jesse Barnes 提交于
Since 965, the hardware has supported the PIPE_CONTROL command, which provides fine grained GPU cache flushing control. On recent chipsets, this instruction is required for reliable interrupt and sequence number reporting in the driver. So add support for this instruction, including workarounds, on Ironlake and Sandy Bridge hardware. https://bugs.freedesktop.org/show_bug.cgi?id=27108Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Tested-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NEric Anholt <eric@anholt.net>
-
由 Jesse Barnes 提交于
This keeps the memory manager from complaining when we take it down. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NEric Anholt <eric@anholt.net>
-
- 20 4月, 2010 4 次提交
-
-
由 Daniel Vetter 提交于
Luckily the change is quite a little bit less invasive than I've feared. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Acked-by: NEric Anholt <eric@anholt.net> Signed-off-by: NDave Airlie <airlied@redhat.com>
-
由 Daniel Vetter 提交于
Thanks to the to_intel_bo helper, this change is rather trivial. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Acked-by: NEric Anholt <eric@anholt.net> Signed-off-by: NDave Airlie <airlied@redhat.com>
-
由 Daniel Vetter 提交于
Just embed it and adjust the pointers, No other changes (that's for later patches). Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Acked-by: NEric Anholt <eric@anholt.net> Signed-off-by: NDave Airlie <airlied@redhat.com>
-
由 Daniel Vetter 提交于
Just preparation, no functional change. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Acked-by: NEric Anholt <eric@anholt.net> Signed-off-by: NDave Airlie <airlied@redhat.com>
-
- 19 4月, 2010 1 次提交
-
-
由 Adam Jackson 提交于
pci.ids and the datasheet both say it's 358e, not 35e8. Signed-off-by: NAdam Jackson <ajax@redhat.com> Signed-off-by: NEric Anholt <eric@anholt.net>
-
- 13 4月, 2010 3 次提交
-
-
由 Zhenyu Wang 提交于
DP on Cougarpoint has new training pattern definitions, and new transcoder DP control register is used to determine the mapping for transcoder and DP digital output. And eDP for Sandybridge has new voltage and pre-emphasis level definitions. Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
-
由 Zhenyu Wang 提交于
PCH is the new name for south bridge from Ironlake/Sandybridge, which contains most of the display outputs except eDP. This one adds a probe function to detect current PCH type, and method to detect Cougarpoint PCH. Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
-
由 Zhenyu Wang 提交于
Integrated TV is deprecated in new chips from Ironlake. Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
-
- 10 4月, 2010 1 次提交
-
-
由 Zhao Yakui 提交于
This trys to shut up complains about invalid LVDS EDID during mode probe, but uses fixed panel mode directly for panels with broken EDID. https://bugs.freedesktop.org/show_bug.cgi?id=23099 https://bugs.freedesktop.org/show_bug.cgi?id=26395Signed-off-by: NZhao Yakui <yakui.zhao@intel.com> Tested-by: NSitsofe Wheeler <sitsofe@yahoo.com> Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
-
- 07 4月, 2010 2 次提交
-
-
由 Dave Airlie 提交于
This move to using the list of crtcs in the fb helper and cleans up the whole picking code, now we store the crtc/connectors we want directly into the modeset and we use the modeset directly to set the mode. Fixes from James Simmons and Ben Skeggs. Signed-off-by: NDave Airlie <airlied@redhat.com>
-
由 Dave Airlie 提交于
The fbdev layer in the kms code should act like a consumer of the kms services and avoid having relying on information being store in the kms core structures in order for it to work. This patch a) removes the info pointer/psuedo palette from the core drm_framebuffer structure and moves it to the fbdev helper layer, it also removes the core drm keeping a list of kernel kms fbdevs. b) migrated all the fb helper functions out of the crtc helper file into the fb helper file. c) pushed the fb probing/hotplug control into the driver d) makes the surface sizes into a structure for ease of passing This changes the intel/radeon/nouveau drivers to use the new helper. Signed-off-by: NDave Airlie <airlied@redhat.com>
-
- 26 3月, 2010 1 次提交
-
-
由 Daniel Vetter 提交于
This is a purely cosmetic change to make changes in this area easier. And hey, it's not only clearer and typechecked, but actually shorter, too! [anholt: To clarify, this is a change to let us later make drm_i915_gem_object subclass drm_gem_object, instead of having drm_gem_object have a pointer to i915's private data] Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Acked-by: NDave Airlie <airlied@gmail.com> Signed-off-by: NEric Anholt <eric@anholt.net>
-
- 18 3月, 2010 1 次提交
-
-
由 Zhenyu Wang 提交于
IS_GEN6 missed to include SandyBridge mobile chip, which failed in i915_probe_agp() for memory config detection. Fix it with a device info flag. Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
-
- 01 3月, 2010 1 次提交
-
-
由 Dave Airlie 提交于
Many new laptops now come with 2 gpus, one to be used for low power modes and one for gaming/on-ac applications. These GPUs are typically wired to the laptop panel and VGA ports via a multiplexer unit which is controlled via ACPI methods. 4 combinations of systems typically exist - with 2 ACPI methods. Intel/ATI - Lenovo W500/T500 - use ATPX ACPI method ATI/ATI - some ASUS - use ATPX ACPI Method Intel/Nvidia - - use _DSM ACPI method Nvidia/Nvidia - - use _DSM ACPI method. TODO: This patch adds support for the ATPX method and initial bits for the _DSM methods that need to written by someone with access to the hardware. Add a proper non-debugfs interface - need to get some proper testing first. v2: add power up/down support for both devices on W500 puts i915/radeon into D3 and cuts power to radeon. v3: redo probing methods, no DMI list, drm devices call to register with switcheroo, it tries to find an ATPX method on any device and once there is two devices + ATPX it inits the switcher. v4: ATPX msg handling using buffers - should work on more machines v5: rearchitect after more mjg59 discussion - move ATPX handling to radeon driver. v6: add file headers + initial nouveau bits (to be filled out). v7: merge delayed switcher code. v8: avoid suspend/resume of gpu that is off v9: rearchitect - mjg59 is always right. - move all ATPX code to radeon, should allow simpler DSM also proper ATRM handling v10: add ATRM support for radeon BIOS, add mutex to lock vgasr_priv v11: fix bug in resuming Intel for 2nd time. v12: start fixing up nvidia code blindly. v13: blindly guess at finishing nvidia code v14: remove radeon audio hacks - fix up intel resume more like upstream v15: clean up printks + remove unnecessary igd/dis pointers mount debugfs /sys/kernel/debug/vgaswitcheroo/switch - should exist if ATPX detected + 2 cards. DIS - immediate change to discrete IGD - immediate change to IGD DDIS - delayed change to discrete DIGD - delayed change to IGD ON - turn on not in use OFF - turn off not in use Tested on W500 (Intel/ATI) and T500 (Intel/ATI) Signed-off-by: NDave Airlie <airlied@redhat.com>
-
- 27 2月, 2010 1 次提交
-
-
由 Eric Anholt 提交于
Signed-off-by: NEric Anholt <eric@anholt.net>
-
- 23 2月, 2010 4 次提交
-
-
由 Chris Wilson 提交于
In order to improve our diagnostic capabilities following a GPU hang and subsequent reset, we need to record the batch buffer that triggered the error. We assume that the current batch buffer, plus a few details about what else is on the active list, will be sufficient -- at the very least an improvement over nothing. The extra information is stored in /debug/dri/.../i915_error_state following an error, and may be decoded using intel_gpu_tools/tools/intel_error_decode. v2: Avoid excessive work under spinlocks. v3: Include ringbuffer for later analysis. v4: Use kunmap correctly and record more buffer state. v5: Search ringbuffer for current batch buffer v6: Use a work fn for the impossible IRQ error case. v7: Avoid non-atomic paths whilst in IRQ context. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NEric Anholt <eric@anholt.net>
-
由 Owain Ainsworth 提交于
i915_gem_object_fenceable was mostly just a repeat of the i915_gem_object_fence_offset_ok, but also checking the size (which was checkecd when we allowed that BO to be tiled in the first place). So instead, export the latter function and use it in place. Signed-Off-By: NOwain G. Ainsworth <oga@openbsd.org> Signed-off-by: NEric Anholt <eric@anholt.net>
-
由 Jesse Barnes 提交于
Tools like powertop want to check the current FBC status and report it to the user. So add a debugfs file indicating whether FBC is enabled, and if not, why. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NEric Anholt <eric@anholt.net>
-
由 Matthew Garrett 提交于
The ironlake render p-state support includes some rather odd variable names. Clean them up in order to improve the readability of the code. Signed-off-by: NMatthew Garrett <mjg@redhat.com> Signed-off-by: NEric Anholt <eric@anholt.net>
-