All the prerequisites are there now, so we can move sirf into multiplatform.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This moves the two sirf clocksource drivers to drivers/clocksource
and integrates them into the framework for locating the clock sources
automatically.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Tested-by: NBarry Song <Baohua.Song@csr.com>
Cc: John Stultz <john.stultz@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>

This updates the irqchip drier for prima2 to the current practices by
moving it into drivers/irqchip and integrating it into the irqchip_init
infrastructure. We also now use a linear irq domain as a preparation
for sparse IRQ suport.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Cc: Thomas Gleixner <tglx@linutronix.de>

this patch adds tick timer, smp entries and generic DT machine
for SiRFmarco dual-core SMP chips.

with the added marco, we change the defconfig, using the same
defconfig, we get a zImage which can work on both prima2 and
marco.
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Cc: Mark Rutland <mark.rutland@arm.com>

Marco timer has different timer IP with prima2, so rename the current timer
to timer-prima2 so that we can add timer-marco.

at the same time, if we don't find prima2 timer node in dt, don't panic the
system as we will make prima2 and marco use same kernel image.
Signed-off-by: NBarry Song <Baohua.Song@csr.com>

New MARCO and POLO SoC use GIC, so make irq.c optional and enable it
only if we enable ARCH_PRIMA2 in Kconfig
Signed-off-by: NBarry Song <Baohua.Song@csr.com>

we will have SiRFMarco and SiRFPolo, all of them will be in the
generic board.
Signed-off-by: NBarry Song <Baohua.Song@csr.com>

Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch adds suspend-to-mem support for prima2. It will make prima2
enter DEEPSLEEP mode while accepting PM_SUSPEND_MEM command.
Signed-off-by: NRongjun Ying <rongjun.ying@csr.com>
Signed-off-by: NBarry Song <baohua.song@csr.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

The module is a bridge between the RTC clock domain and the CPU interface
clock domain. ARM access the register of SYSRTC, GPSRTC and PWRC through
this module.
Signed-off-by: NZhiwu Song <zhiwu.song@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Reviewed-by: NJamie Iles <jamie@jamieiles.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Signed-off-by: NRongjun Ying <rongjun.ying@csr.com>
Signed-off-by: NBarry Song <baohua.song@csr.com>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>

Signed-off-by: NBarry Song <baohua.song@csr.com>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>

SiRFprimaII is the latest generation application processor from CSR’s
Multifunction SoC product family. Designed around an ARM cortex A9 core,
high-speed memory bus, advanced 3D accelerator and full-HD multi-format
video decoder, SiRFprimaII is able to meet the needs of complicated
applications for modern multifunction devices that require heavy concurrent
applications and fluid user experience. Integrated with GPS baseband,
analog and PMU, this new platform is designed to provide a cost effective
solution for Automotive and Consumer markets.

This patch adds the basic support for this SoC and EVB board based on device
tree. It is following the ZYNQ of Xilinx in some degree.
Signed-off-by: NBinghua Duan <Binghua.Duan@csr.com>
Signed-off-by: NRongjun Ying <Rongjun.Ying@csr.com>
Signed-off-by: NZhiwu Song <Zhiwu.Song@csr.com>
Signed-off-by: NYuping Luo <Yuping.Luo@csr.com>
Signed-off-by: NBin Shi <Bin.Shi@csr.com>
Signed-off-by: NHuayi Li <Huayi.Li@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>