1. 15 5月, 2015 1 次提交
  2. 12 3月, 2015 1 次提交
  3. 01 3月, 2015 1 次提交
  4. 05 1月, 2015 2 次提交
  5. 28 12月, 2014 1 次提交
  6. 01 12月, 2014 2 次提交
  7. 24 11月, 2014 2 次提交
  8. 14 9月, 2014 2 次提交
  9. 09 9月, 2014 1 次提交
  10. 04 9月, 2014 1 次提交
  11. 01 9月, 2014 1 次提交
  12. 07 5月, 2014 1 次提交
  13. 14 4月, 2014 1 次提交
  14. 13 4月, 2014 3 次提交
  15. 06 4月, 2014 1 次提交
    • E
      iwlwifi: pcie: don't leave the new NICs awake for commands · e7f76340
      Emmanuel Grumbach 提交于
      A hardware bug had been discovered on 7260 / 3160 and 7265
      and the workaround for this bug is to force the NIC to stay
      awake as long as we have host commands in flight. This
      workaround has been introduced for all NICs in a previous
      patch:
      
      b9439491 ("iwlwifi: pcie: keep the NIC awake when commands are in flight")
      
      In newer NICs, this bug is solved, so we can let the NIC go
      to sleep even when we send commands. The hardware will wake
      up when we increment the scheduler write pointer.
      Make the workaround conditional to only use it on affected
      hardware.
      Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
      e7f76340
  16. 10 3月, 2014 1 次提交
    • A
      iwlwifi: pcie: enable LP XTAL to reduce power consumption · a812cba9
      Alexander Bondar 提交于
      1. Enable LP XTAL to avoid HW bug where device may consume much
      power if FW is not loaded after device reset. LP XTAL is
      disabled by default after device HW reset. Configure device's
      "persistence" mode to avoid resetting XTAL again when SHRD_HW_RST
      occurs in S3.
      
      2. Add methods to access SHR (shared block memory space) directly from PCI
      bus w/o need to power up MAC HW.
      
      Shared internal registers (e.g. SHR_APMG_GP1, SHR_APMG_XTAL_CFG)can be
      accessed directly from PCI bus through SHR arbiter even when MAC HW is
      powered down. This is possible due to indirect read/write via
      HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and HEEP_CTRL_WRD_PCIEX_DATA (0xF4)
      registers.
      
      Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW
      need not be powered up so no "grab inc access" is required.
      
      For example, to read from SHR_APMG_GP1 register (0x1DC),
      first, write to the control register:
      HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
      HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access)
      second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0].
      
      To write the register, first, write to the data register
      HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then:
      HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
      HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access)
      Signed-off-by: NAlexander Bondar <alexander.bondar@intel.com>
      Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
      a812cba9
  17. 04 2月, 2014 3 次提交
  18. 01 1月, 2014 1 次提交
  19. 18 12月, 2013 2 次提交
  20. 26 11月, 2013 3 次提交
  21. 11 10月, 2013 1 次提交
  22. 31 7月, 2013 1 次提交
  23. 16 7月, 2013 1 次提交
  24. 17 6月, 2013 1 次提交
  25. 27 5月, 2013 1 次提交
  26. 14 5月, 2013 2 次提交
  27. 06 3月, 2013 2 次提交