1. 30 4月, 2008 2 次提交
  2. 24 4月, 2008 2 次提交
  3. 23 4月, 2008 1 次提交
    • E
      [MTD] [NAND] support for pxa3xx · fe69af00
      eric miao 提交于
      This is preliminary since:
      
      1. It supports only _one_ chip select at the moment. As there is no
         existing platforms available using two chip selects of the NAND
         controller, it shall really not include code for supporting the
         2nd chip select for now, as such code cannot be verified.
      
      2. It resorts to the default and simpliest memory based badblock
         table
      
      3. Only limited types of nand flash are currently supported. Most
         PXA3xx processors come with on-chip NAND flash dies, so there
         isn't much flexibility for other types of NAND.
      
      4. The NAND controller should be configured to detect the device's
         ID, thus making it difficult to use nand_scan_ident() to assist
         the detection process (though it's not impossible)
      
      TODO: fix all the above limitations of cuz :-)
      Signed-off-by: Neric miao <eric.miao@marvell.com>
      Cc: Sergey Podstavin <spodstavin@ru.mvista.com>
      Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>
      fe69af00
  4. 21 4月, 2008 1 次提交
  5. 20 4月, 2008 1 次提交
  6. 19 4月, 2008 19 次提交
  7. 01 3月, 2008 2 次提交
  8. 24 2月, 2008 1 次提交
    • N
      spi: pxa2xx_spi clock polarity fix · b97c74bd
      Ned Forrester 提交于
      Fixes a sequencing bug in spi driver pxa2xx_spi.c in which the chip select
      for a transfer may be asserted before the clock polarity is set on the
      interface.  As a result of this bug, the clock signal may have the wrong
      polarity at transfer start, so it may need to make an extra half transition
      before the intended clock/data signals begin.  (This probably means all
      transfers are one bit out of sequence.)
      
      This only occurs on the first transfer following a change in clock polarity
      in systems using more than one more than one such polarity.  The fix
      assures that the clock mode is properly set before asserting chip select.
      
      This bug was introduced in a patch merged on 2006/12/10, kernel 2.6.20.
      The patch defines an additional bit in: include/asm-arm/arch-pxa/regs-ssp.h
      for 2.6.25 and newer kernels but this addition must be made in:
      include/asm-arm/arch-pxa/pxa-regs.h for kernels between 2.6.20 and 2.6.24,
      inclusive
      Signed-off-by: NNed Forrester <nforrester@whoi.edu>
      Signed-off-by: NDavid Brownell <dbrownell@users.sourceforge.net>
      Cc: Russell King <rmk@arm.linux.org.uk>
      Cc: <stable@kernel.org>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      b97c74bd
  9. 06 2月, 2008 1 次提交
  10. 04 2月, 2008 1 次提交
  11. 03 2月, 2008 1 次提交
  12. 01 2月, 2008 1 次提交
    • T
      [ALSA] Remove sound/driver.h · 9004acc7
      Takashi Iwai 提交于
      This header file exists only for some hacks to adapt alsa-driver
      tree.  It's useless for building in the kernel.  Let's move a few
      lines in it to sound/core.h and remove it.
      With this patch, sound/driver.h isn't removed but has just a single
      compile warning to include it.  This should be really killed in
      future.
      Signed-off-by: NTakashi Iwai <tiwai@suse.de>
      Signed-off-by: NJaroslav Kysela <perex@perex.cz>
      9004acc7
  13. 31 1月, 2008 6 次提交
  14. 28 1月, 2008 1 次提交