1. 24 1月, 2016 5 次提交
    • M
      MIPS: math-emu: Make microMIPS branch delay slot emulation work · 733b8bc1
      Maciej W. Rozycki 提交于
      Complement commit 102cedc3 ("MIPS: microMIPS: Floating point
      support.") which introduced microMIPS FPU emulation, but did not adjust
      the encoding of the BREAK instruction used to terminate the branch delay
      slot emulation frame.  Consequently the execution of any such frame is
      indeterminate and, depending on CPU configuration, will result in random
      code execution or an offending program being terminated with SIGILL.
      
      This is because the regular MIPS BREAK instruction is encoded with the 0
      major and the 0xd minor opcode, however in the microMIPS instruction set
      this major/minor opcode pair denotes an encoding reserved for the DSP
      ASE.  Instead the microMIPS BREAK instruction is encoded with the 0
      major and the 0x7 minor opcode.
      
      Use the correct BREAK encoding for microMIPS FPU emulation then.
      Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com>
      Cc: Aurelien Jarno <aurelien@aurel32.net>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/12174/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      733b8bc1
    • M
      MIPS: math-emu: dsemul: Fix ill formatting of microMIPS part · a87265cf
      Maciej W. Rozycki 提交于
      Correct formatting breakage introduced with commit 102cedc3 ("MIPS:
      microMIPS: Floating point support."), so that further changes to this
      code can be consistent.
      Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com>
      Cc: Aurelien Jarno <aurelien@aurel32.net>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/12173/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      a87265cf
    • M
      MIPS: math-emu: Correctly handle NOP emulation · e4553573
      Maciej W. Rozycki 提交于
      Fix an issue introduced with commit 9ab4471c ("MIPS: math-emu:
      Correct delay-slot exception propagation") where the emulation of a NOP
      instruction signals the need to terminate the emulation loop.  This in
      turn, if the PC has not changed from the entry to the loop, will cause
      the kernel to terminate the program with SIGILL.
      
      Consider this program:
      
      static double div(double d)
      {
      	do
      		d /= 2.0;
      	while (d > .5);
      	return d;
      }
      
      int main(int argc, char **argv)
      {
      	return div(argc);
      }
      
      which gets compiled to the following binary code:
      
      00400490 <main>:
        400490:	44840000 	mtc1	a0,$f0
        400494:	3c020040 	lui	v0,0x40
        400498:	d44207f8 	ldc1	$f2,2040(v0)
        40049c:	46800021 	cvt.d.w	$f0,$f0
        4004a0:	46220002 	mul.d	$f0,$f0,$f2
        4004a4:	4620103c 	c.lt.d	$f2,$f0
        4004a8:	4501fffd 	bc1t	4004a0 <main+0x10>
        4004ac:	00000000 	nop
        4004b0:	4620000d 	trunc.w.d	$f0,$f0
        4004b4:	03e00008 	jr	ra
        4004b8:	44020000 	mfc1	v0,$f0
        4004bc:	00000000 	nop
      
      Where the FPU emulator is used, depending on the number of command-line
      arguments this code will either run to completion or terminate with
      SIGILL.
      
      If no arguments are specified, then BC1T will not be taken, NOP will not
      be emulated and code will complete successfully.
      
      If one argument is specified, then BC1T will be taken once and NOP will
      be emulated.  At this point the entry PC value will be 0x400498 and the
      new PC value, set by `mips_dsemul' will be 0x4004a0, the target of BC1T.
      The emulation loop will terminate, but SIGILL will not be issued,
      because the PC has changed.  The FPU emulator will be entered again and
      on the second execution BC1T will not be taken, NOP will not be emulated
      and code will complete successfully.
      
      If two or more arguments are specified, then the first execution of BC1T
      will proceed as above.  Upon reentering the FPU emulator the emulation
      loop will continue to BC1T, at which point the branch will be taken and
      NOP emulated again.  At this point however the entry PC value will be
      0x4004a0, the same as the target of BC1T.  This will make the emulator
      conclude that execution has not advanced and therefore an unsupported
      FPU instruction has been encountered, and SIGILL will be sent to the
      process.
      
      Fix the problem by extending the internal API of `mips_dsemul', making
      it return -1 if no delay slot emulation frame has been made, the
      instruction has been handled and execution of the emulation loop needs
      to continue as if nothing happened.  Remove code from `mips_dsemul' to
      reproduce steps made by the emulation loop at the conclusion of each
      iteration, as those will be reached normally now.  Adjust call sites
      accordingly.  Document the API.
      Signed-off-by: NMaciej W. Rozycki <macro@imgtec.com>
      Cc: Aurelien Jarno <aurelien@aurel32.net>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/12172/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      e4553573
    • H
      MIPS: Fix some missing CONFIG_CPU_MIPSR6 #ifdefs · 4f33f6c5
      Huacai Chen 提交于
      Commit be0c37c9 (MIPS: Rearrange PTE bits into fixed positions.)
      defines fixed PTE bits for MIPS R2. Then, commit d7b63141
      (MIPS: pgtable-bits: Fix XPA damage to R6 definitions.) adds the MIPS
      R6 definitions in the same way as MIPS R2. But some R6 #ifdefs in the
      later commit are missing, so in this patch I fix that.
      Signed-off-by: NHuacai Chen <chenhc@lemote.com>
      Cc: Aurelien Jarno <aurelien@aurel32.net>
      Cc: Steven J. Hill <Steven.Hill@imgtec.com>
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Cc: linux-mips@linux-mips.org
      Cc: stable@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/12164/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      4f33f6c5
    • H
      MIPS: sync-r4k: reduce skew while synchronization · db0dbd57
      Huacai Chen 提交于
      While synchronization, count register will go backwards for the master.
      If synchronise_count_master() runs before synchronise_count_slave(),
      skew becomes even more. The skew is very harmful for CPU hotplug (CPU0
      do synchronization with CPU1, then CPU0 do synchronization with CPU2
      and CPU0's count goes backwards, so it will be out of sync with CPU1).
      
      After the commit cf9bfe55 (MIPS: Synchronize MIPS count one
      CPU at a time), we needn't evaluate count_reference at the beginning of
      synchronise_count_master() any more. Thus, we evaluate the initcount (It
      seems like count_reference is redundant) in the 2nd loop. Since we write
      the count register in the last loop, we don't need additional barriers
      (the existing memory barriers are enough).
      
      Moreover, I think we loop 3 times is enough to get a primed instruction
      cache, this can also get less skew than looping 5 times.
      
      Comments are also updated in this patch.
      Signed-off-by: NHuacai Chen <chenhc@lemote.com>
      Cc: Aurelien Jarno <aurelien@aurel32.net>
      Cc: Steven J. Hill <Steven.Hill@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Patchwork: https://patchwork.linux-mips.org/patch/12163/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      db0dbd57
  2. 22 1月, 2016 4 次提交
    • H
      MIPS: hpet: Choose a safe value for the ETIME check · 5610b125
      Huacai Chen 提交于
      This patch is borrowed from x86 hpet driver and explaind below:
      
      Due to the overly intelligent design of HPETs, we need to workaround
      the problem that the compare value which we write is already behind
      the actual counter value at the point where the value hits the real
      compare register. This happens for two reasons:
      
      1) We read out the counter, add the delta and write the result to the
         compare register. When a NMI hits between the read out and the write
         then the counter can be ahead of the event already.
      
      2) The write to the compare register is delayed by up to two HPET
         cycles in AMD chipsets.
      
      We can work around this by reading back the compare register to make
      sure that the written value has hit the hardware. But that is bad
      performance wise for the normal case where the event is far enough in
      the future.
      
      As we already know that the write can be delayed by up to two cycles
      we can avoid the read back of the compare register completely if we
      make the decision whether the delta has elapsed already or not based
      on the following calculation:
      
        cmp = event - actual_count;
      
      If cmp is less than 64 HPET clock cycles, then we decide that the event
      has happened already and return -ETIME. That covers the above #1 and #2
      problems which would cause a wait for HPET wraparound (~306 seconds).
      Signed-off-by: NHuacai Chen <chenhc@lemote.com>
      Cc: Aurelien Jarno <aurelien@aurel32.net>
      Cc: Steven J. Hill <Steven.Hill@imgtec.com>
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: linux-mips@linux-mips.org
      Cc: stable@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/12162/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      5610b125
    • H
      MIPS: Loongson-3: Fix SMP_ASK_C0COUNT IPI handler · 57548432
      Huacai Chen 提交于
      When Core-0 handle SMP_ASK_C0COUNT IPI, we should make other cores to
      see the result as soon as possible (especially when Store-Fill-Buffer
      is enabled). Otherwise, C0_Count syncronization makes no sense.
      
      BTW, array is more suitable than per-cpu variable for syncronization,
      and there is a corner case should be avoid: C0_Count of Core-0 can be
      really 0.
      Signed-off-by: NHuacai Chen <chenhc@lemote.com>
      Cc: Aurelien Jarno <aurelien@aurel32.net>
      Cc: Steven J. Hill <Steven.Hill@imgtec.com>
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Cc: Huacai Chen <chenhc@lemote.com>
      Cc: linux-mips@linux-mips.org
      Cc: <stable@vger.kernel.org>
      Patchwork: https://patchwork.linux-mips.org/patch/12160/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      57548432
    • H
      MIPS: Loongson-3: Improve -march option and move it to Platform · 5188129b
      Huacai Chen 提交于
      If GCC >= 4.9 and Binutils >=2.25, we use -march=loongson3a, otherwise
      we use -march=mips64r2, this can slightly improve performance. Besides,
      arch/mips/loongson64/Platform is a better location rather than arch/
      mips/Makefile.
      Signed-off-by: NHuacai Chen <chenhc@lemote.com>
      Cc: Aurelien Jarno <aurelien@aurel32.net>
      Cc: Steven J. Hill <Steven.Hill@imgtec.com>
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/12161/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      5188129b
    • H
      MIPS: Cleanup the unused __arch_local_irq_restore() function · 6e526844
      Huacai Chen 提交于
      In history, __arch_local_irq_restore() is only used by SMTC. However,
      SMTC support has been removed since 3.16, this patch remove the unused
      function.
      Signed-off-by: NHuacai Chen <chenhc@lemote.com>
      Cc: Aurelien Jarno <aurelien@aurel32.net>
      Cc: Steven J. Hill <Steven.Hill@imgtec.com>
      Cc: Fuxin Zhang <zhangfx@lemote.com>
      Cc: Zhangjin Wu <wuzhangjin@gmail.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/12159/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      6e526844
  3. 20 1月, 2016 20 次提交
  4. 04 1月, 2016 11 次提交