- 25 6月, 2009 1 次提交
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由 Ralf Baechle 提交于
Some of the were relying into smp.h being dragged in by another header which of course is fragile. <asm/cpu-info.h> uses smp_processor_id() only in macros and including smp.h there leads to an include loop, so don't change cpu-info.h. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 12 3月, 2009 1 次提交
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由 Shinya Kuribayashi 提交于
Current VR5500 processor support lacks of some functions which are expected to be configured/synthesized on arch initialization. Here're some VR5500A spec notes: * All execution hazards are handled in hardware. * Once VR5500A stops the operation of the pipeline by WAIT instruction, it could return from the standby mode only when either a reset, NMI request, or all enabled interrupts is/are detected. In other words, if interrupts are disabled by Status.IE=0, it keeps in standby mode even when interrupts are internally asserted. Notes on WAIT: The operation of the processor is undefined if WAIT insn is in the branch delay slot. The operation is also undefined if WAIT insn is executed when Status.EXL and Status.ERL are set to 1. * VR5500A core only implements the Load prefetch. With these changes, it boots fine. Signed-off-by: NShinya Kuribayashi <shinya.kuribayashi@necel.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 09 7月, 2008 1 次提交
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由 Thomas Bogendoerfer 提交于
The generated copy_page for R4k CPU with a 128 byte cache line size used Create Dirty Exclusive cache line operations even if only part of the cache line was filled. This change avoids generating cache operations, if only part of the cache line size is copied in one loop. It also increases the maxmimum loop size, because the generated code even fits into the available space for r4k CPUs with 128 byte cache line size. Signed-off-by: NThomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 16 6月, 2008 1 次提交
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由 Atsushi Nemoto 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 06 6月, 2008 1 次提交
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由 Yoichi Yuasa 提交于
Signed-off-by: NYoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 29 4月, 2008 1 次提交
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由 Thiemo Seufer 提交于
Fold the SB-1 specific implementation of clear_page/copy_page in the generic version, and rewrite that one in tlbex style. The immediate benefits: - It converts the compile-time workaround for SB-1 pass 1 prefetches to a more efficient run-time check. - It allows adjustment of loop unfolling, which helps to reduce the number of redundant cdex cache ops. - It fixes some esoteric cornercases (the cache line length calculations can go wrong, and support for 64k pages without prefetch instructions will overflow the addiu immediate). - Somewhat better guesses of "good" prefetch values. Signed-off-by: NThiemo Seufer <ths@networkno.de> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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