- 16 10月, 2009 1 次提交
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由 Jesse Barnes 提交于
Turns out some machines, like the ThinkPad X40 don't come back if you don't save/restore this register. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NEric Anholt <eric@anholt.net>
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- 14 10月, 2009 2 次提交
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由 Zhenyu Wang 提交于
FDI M/N calculation hasn't taken the current pipe color depth into account, but always set as 24bpp. This one checks current pipe color depth setting, and change FDI M/N calculation a little to use bits_per_pixel first, then convert to bytes_per_pixel later. This fixes display corrupt issue on Arrandle LVDS with 1600x900 panel in 18bpp dual-channel mode. Cc: Stable Team <stable@kernel.org> Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Zhao Yakui 提交于
According to the spec the LVDS_BORDER_ENABLE bit decides whether the border data should be included in the active display and data sent to the panel. Border should be used when in VGA centered (un-scaled) mode or when scaling a 4:3 source image to a wide screen panel (typical 16:9). So when the LVDS scaling is used, decide whether the LVDS_BORDER should be enabled or not according to the current scaling mode. At the same time fix the typo error in LVDS center scaling mode. https://bugs.freedesktop.org/show_bug.cgi?id=23789Signed-off-by: NZhao Yakui <yakui.zhao@intel.com> tested-by: NZhao Jian <jian.zhao@intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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- 22 9月, 2009 1 次提交
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由 Jesse Barnes 提交于
Add support for framebuffer compression on GM45 and above. Removes some unnecessary I915_HAS_FBC checks as well (this is now part of the FBC display function). Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NEric Anholt <eric@anholt.net>
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- 21 9月, 2009 1 次提交
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由 Dave Airlie 提交于
VGA arb requires DRM support for non-kms drivers, to turn on/off irqs when disabling the mem/io regions. VGA arb requires KMS support for GPUs where we can turn off VGA decoding. Currently we know how to do this for intel and radeon kms drivers, which allows them to be removed from the arbiter. This patch comes from Fedora rawhide kernel. Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 18 9月, 2009 2 次提交
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由 Ben Gamari 提交于
This patch puts in place the machinery to attempt to reset the GPU. This will be used when attempting to recover from a GPU hang. Signed-off-by: NOwain G. Ainsworth <oga@openbsd.org> Signed-off-by: NBen Gamari <bgamari.foss@gmail.com> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
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由 Zhenyu Wang 提交于
Arrandale has new window based method for panel fitting. This one enables full screen aspect scaling on LVDS. It fixes standard mode display failure on LVDS for Arrandale. Cc: Stable Team <stable@kernel.org> Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
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- 11 9月, 2009 1 次提交
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由 Jesse Barnes 提交于
This patch adds framebuffer compression (good for about ~0.5W power savings in the best case) support for pre-GM45 chips. GM45+ have a new, more flexible FBC scheme that will be added in a separate patch. FBC can't always be enabled: the compressed buffer must be physically contiguous and reside in stolen space. So if you have a large display and a small amount of stolen memory, you may not be able to take advantage of FBC. In some cases, a BIOS setting controls how much stolen space is available. Increasing this to 8 or 16M can help. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NEric Anholt <eric@anholt.net>
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- 05 9月, 2009 3 次提交
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由 Zhenyu Wang 提交于
It seems that on IGDNG the same swizzling setup always applys. And front buffer tiling needs to set address swizzle in display arb control too. Fix plane tricle feed setting in v1 which should be disable bit, and always setup address swizzle to let hardware care for buffer tiling in all cases. Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Jesse Barnes 提交于
There are several sources of unnecessary power consumption on Intel graphics systems. The first is the LVDS clock. TFTs don't suffer from persistence issues like CRTs, and so we can reduce the LVDS refresh rate when the screen is idle. It will be automatically upclocked when userspace triggers graphical activity. Beyond that, we can enable memory self refresh. This allows the memory to go into a lower power state when the graphics are idle. Finally, we can drop some clocks on the gpu itself. All of these things can be reenabled between frames when GPU activity is triggered, and so there should be no user visible graphical changes. Signed-off-by: NJesse Barnes <jesse.barnes@intel.com> Signed-off-by: NMatthew Garrett <mjg@redhat.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Shaohua Li 提交于
In the event that any one of the DAC analog outputs (R,G,B) were driven at full-scale (white video) or some analog level close to full-scale voltage, and if the video cable were then disconnected, the analog video voltage level would exceed the maximum electrical overstress limit of the native (thin-oxide) transistors thus causing a long-term reliability concern. The electrical overstress condition occurs in this particular case. This patch address the IGD EOS (electrical overstress condition) issue. When the EOS interrupt occurs, OS should disable DAC and then disable EOS, then the normal hotplug operation follows. TODO: it appears the normal unplug interrupt is missed as reported by Li Peng, need more checks here. Signed-off-by: NShaohua Li <shaohua.li@intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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- 30 7月, 2009 3 次提交
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由 Zhenyu Wang 提交于
This adds embedded DisplayPort support on next mobile chip which aims to replace origin LVDS port. VBT's driver feature block has been used to determine the type of current internal panel for eDP or LVDS. Currently no panel fitting support for eDP and backlight control would be added in future. Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Zhenyu Wang 提交于
Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Zhenyu Wang 提交于
During pipe DPMS off, instead of busy waiting pipe off, insert delays during wait and don't loop after enough tries which matches spec requirement. Also try to match DPMS on path by disable FDI TX PLL in DPMS off. Disable PF by writing PF_WIN_SZ which really trigger the update. Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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- 15 7月, 2009 1 次提交
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由 Jesse Barnes 提交于
I discovered several bugs in the FIFO code that was recently applied. Some of them fell into the "how did this ever work" category, since in some cases we were using the wrong FIFO size values, and the calculations ended up being way off. This patch fixes all the bugs I found, and works well on my GM45, 915GM and 855GM test machines; but as usual with these sorts of patches broader testing is definitely requested (in particular this patch affects 830, 845 and 865 for which I don't have test hardware). Overall, the patch clarifies the watermark calculation function by adding some comments and debug info, and making the variable names a bit clearer. The "get FIFO size" portion of the code has also been corrected, so we should be able to properly detect the FIFO allocations for each pipe, for use in the watermark calculation. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NEric Anholt <eric@anholt.net>
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- 02 7月, 2009 2 次提交
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由 Shaohua Li 提交于
This patch from jbarnes and myself adds FIFO watermark control to the driver. This is needed for both power saving features on new platforms with the so-called "big FIFO" and for controlling FIFO allocation between pipes in multi-head configurations. It's also necessary infrastructure to support things like framebuffer compression and configuration supportability checks (i.e. checking a configuration against available bandwidth). Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NShaohua Li <shaohua.li@intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Jesse Barnes 提交于
This patch enables error detection by enabling several types of error interrupts. When an error interrupt is received, the interrupt handler captures the error state; hopefully resulting in an accurate set of error data (error type, active head pointer, etc.). The new record is then available from sysfs. The current code will also dump the error state to the system log. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NEric Anholt <eric@anholt.net>
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- 23 6月, 2009 1 次提交
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由 Zhao Yakui 提交于
Previously the driver would always scale the chosen video mode to fill the panel. This adds 1:1 and maintain-aspect-ratio scaling modes. v2: the drm_calloc/drm_free is replaced by kzalloc/kfree based on Eric's suggestion. Signed-off-by: NZhao Yakui <yakui.zhao@intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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- 19 6月, 2009 1 次提交
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由 Keith Packard 提交于
The CLKCFG register holds information about the GMCH plls and input clock values. Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 05 6月, 2009 3 次提交
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由 Keith Packard 提交于
This adds the register definitions for the display port enable register along with those for the GMCH and Link M/N ratios required to drive display port outputs. Signed-off-by: NKeith Packard <keithp@keithp.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Ma Ling 提交于
We detect TV connect status by setting DAC voltage level override values as 0.7 voltage for DAC_A/B/C. The corresponding 2-bits shold be 0x2, In order correctly to set last bit as 0, at first we must clean it. It fixed freedesktop.org bug #21204 Signed-off-by: NMa Ling <ling.ma@intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Zhenyu Wang 提交于
Signed-off-by: NZhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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- 27 5月, 2009 1 次提交
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由 Eric Anholt 提交于
The pitch field is an exponent on pre-965, so we were rejecting buffers on 8xx that we shouldn't have. 915 got lucky in that the largest legal value happened to match (8KB / 512 = 0x10), but 8xx has a smaller tile width. Additionally, we programmed that bad value into the register on 8xx, so the only pitch that would work correctly was 4096 (512-1023 pixels), while others would probably give bad rendering or hangs. Signed-off-by: NEric Anholt <eric@anholt.net> fd.o bug #20473.
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- 23 5月, 2009 1 次提交
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由 Jesse Barnes 提交于
For some reason we never added 8xx desktop cursor support to the kernel. This patch fixes that. [krh: Also set the size on pre-i915 hw.] Tested-by: NKristian Høgsberg <krh@redhat.com> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NEric Anholt <eric@anholt.net>
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- 15 5月, 2009 1 次提交
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由 Shaohua Li 提交于
In IGD, DPCUNIT_CLOCK_GATE_DISABLE bit should be set, otherwise i2c access will be wrong. v2: Disable CLOCK_GATE_DISABLE bit after bit bashing as suggested by Eric. Signed-off-by: NShaohua Li <shaohua.li@intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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- 17 4月, 2009 1 次提交
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由 Jesse Barnes 提交于
This patch corrects a pretty big oversight in the KMS code for 965+ chips. The current code is missing tiled surface register programming, so userland can allocate a tiled surface and use it for mode setting, resulting in corruption. This patch fixes that, allowing for tiled front buffers on 965+. Cc: stable@kernel.org Tested-by: NArkadiusz Miskiewicz <arekm@maven.pl> Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NEric Anholt <eric@anholt.net>
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- 02 4月, 2009 2 次提交
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由 Jesse Barnes 提交于
Add VGA port hotplug detection to the i915 driver. When KMS is enabled, plugging in or removing a VGA cable from the VGA connector will generate a uevent, which indicates to userspace that it should re-probe outputs on this device (to determine modes, etc.). Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> [anholt: dropped extra PORT_HOTPLUG_STAT clear with ack from jbarnes] Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Daniel Vetter 提交于
This fixes all the tiling problems with the 2d ddx. glxgears still doesn't work. Changes: - fix a copy&paste error in i8xx fence reg setup. It resulted in an at most a 512KB offset of the fence reg window, so was only visible sometimes. - add tests for stride and object size constrains (also for i915 and 1965 class hw). Userspace seems to have an of-by-one bug there, which changes the fence size by at most 512KB due to an overflow. - because i8xx hw is quite old (and therefore not as well-tested) I left 2 debug WARN_ONs in the i8xx fence reg setup code to hopefully catch any further overflows in the bit-fields. Lastly there's one small change to make the alignment checks more consistent. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=20289Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: NEric Anholt <eric@anholt.net>
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- 28 3月, 2009 3 次提交
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由 Zhenyu Wang 提交于
Fix TV control save register for untouched bits, and color knobs different definition for 945 and 965 chips. Signed-off-by: NZhenyu Wang <zhenyu.z.wang@intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Zhao Yakui 提交于
This covers: Use long crt hotplug activation time on GM45. Signed-off-by: NZhao Yakui <yakui.zhao@intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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由 Shaohua Li 提交于
This is a G33-like desktop and mobile chipset. Signed-off-by: NShaohua Li <shaohua.li@intel.com> Signed-off-by: NEric Anholt <eric@anholt.net>
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- 12 3月, 2009 1 次提交
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由 Eric Anholt 提交于
The last 8 fence registers sit at a different offset, so when we went to set fence number 8 in the lower offset, we instead set PGETBL_CTL, and the GPU got all sorts of angry at us. fd.o bug #20567. Easily reproducible by running glxgears and killing it about 6 times. Signed-off-by: NEric Anholt <eric@anholt.net>
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- 08 2月, 2009 2 次提交
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由 Jesse Barnes 提交于
As discussed in the long thread about vblank related timeouts, it turns out GM45 has different frame count registers than previous chips. This patch adds support for them, which prevents us from waiting on really stale sequence values in drm_wait_vblank (which rather than returning immediately ends up timing out or getting interrupted). Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NDave Airlie <airlied@linux.ie>
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由 Jesse Barnes 提交于
Adds code to set up fence registers at execbuf time on pre-965 chips as necessary. Also fixes up a few bugs in the pre-965 tile register support (get_order != ffs). The number of fences available to the kernel defaults to the hw limit minus 3 (for legacy X front/back/depth), but a new parameter allows userspace to override that as needed. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NEric Anholt <eric@anholt.net> Signed-off-by: NDave Airlie <airlied@linux.ie>
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- 07 1月, 2009 2 次提交
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由 Eric Anholt 提交于
fd.o bug #19336. Signed-off-by: NEric Anholt <eric@anholt.net> Signed-off-by: NDave Airlie <airlied@linux.ie>
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由 Eric Anholt 提交于
This is ported directly from the userland 2D driver code. The HDMI audio bits aren't hooked up yet. Signed-off-by: NEric Anholt <eric@anholt.net> Signed-off-by: NDave Airlie <airlied@linux.ie>
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- 29 12月, 2008 1 次提交
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由 Jesse Barnes 提交于
Use the new core GEM object mapping code to allow GTT mapping of GEM objects on i915. The fault handler will make sure a fence register is allocated too, if the object in question is tiled. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NEric Anholt <eric@anholt.net> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 04 12月, 2008 1 次提交
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由 Eric Anholt 提交于
This fixes readpixels and buffer corruption when swapped out and in by disabling tiling on them. Now that we know that the bit 17 mode isn't just a mistake of older chipsets, we'll need to work on a clever fix so that we can get the performance of tiling on these chipsets, but that will require intrusive changes targeted at the next kernel release, not this one. Signed-off-by: NEric Anholt <eric@anholt.net> Signed-off-by: NDave Airlie <airlied@redhat.com>
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- 11 11月, 2008 1 次提交
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由 Keith Packard 提交于
This register is set by the 2D driver to prevent lockups, and so it needs to be preserved across suspend/resume too. This makes my X200s work. Signed-off-by: NKeith Packard <keithp@keithp.com> Signed-off-by: NEric Anholt <eric@anholt.net> Signed-off-by: NDave Airlie <airlied@linux.ie>
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- 18 10月, 2008 1 次提交
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由 Eric Anholt 提交于
GEM allows the creation of persistent buffer objects accessible by the graphics device through new ioctls for managing execution of commands on the device. The userland API is almost entirely driver-specific to ensure that any driver building on this model can easily map the interface to individual driver requirements. GEM is used by the 2d driver for managing its internal state allocations and will be used for pixmap storage to reduce memory consumption and enable zero-copy GLX_EXT_texture_from_pixmap, and in the 3d driver is used to enable GL_EXT_framebuffer_object and GL_ARB_pixel_buffer_object. Signed-off-by: NEric Anholt <eric@anholt.net> Signed-off-by: NDave Airlie <airlied@redhat.com>
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