- 12 11月, 2015 6 次提交
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由 Jisheng Zhang 提交于
hw_breakpoint_restore is only used within suspend.c, so it can be declared static. Signed-off-by: NJisheng Zhang <jszhang@marvell.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Jisheng Zhang 提交于
split_pud and fixup_executable are only called from within mmu.c, so they can be declared static. Signed-off-by: NJisheng Zhang <jszhang@marvell.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Jisheng Zhang 提交于
of_parse_and_init_cpus is only called from within smp.c, so it can be declared static. Signed-off-by: NJisheng Zhang <jszhang@marvell.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Arnd Bergmann 提交于
We should always use linux/types.h instead of asm/types.h for consistency, and Kbuild actually warns about it: ./usr/include/asm/kvm.h:35: include of <linux/types.h> is preferred over <asm/types.h> This patch does as Kbuild asks us. Signed-off-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Arnd Bergmann 提交于
On a cross-toolchain without glibc support, libgcov may not be available, and attempting to build an arm64 kernel with GCOV enabled then results in a build error: /home/arnd/cross-gcc/lib/gcc/aarch64-linux/5.2.1/../../../../aarch64-linux/bin/ld: cannot find -lgcov We don't really want to link libgcov into the vdso anyway, so this patch just disables GCOV in the vdso directory, just as we do for most other architectures. Signed-off-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Arnd Bergmann 提交于
cpus_have_hwcap() is defined as a 'static' function an only used in one place that is inside of an #ifdef, so we get a warning when the only user is disabled: arch/arm64/kernel/cpufeature.c:699:13: warning: 'cpus_have_hwcap' defined but not used [-Wunused-function] This marks the function as __maybe_unused, so the compiler knows that it can drop the function definition without warning about it. Signed-off-by: NArnd Bergmann <arnd@arndb.de> Fixes: 37b01d53 ("arm64/HWCAP: Use system wide safe values") Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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- 10 11月, 2015 1 次提交
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由 Yang Shi 提交于
FRAME_POINTER is defined in lib/Kconfig.debug, it is unnecessary to redefine it in arch/arm64/Kconfig.debug. ARM64 depends on frame pointer to get correct stack trace (also selecting ARCH_WANT_FRAME_POINTERS). However, the lib/Kconfig.debug definition allows such option to be disabled. This patch forces FRAME_POINTER always on on arm64. Signed-off-by: NYang Shi <yang.shi@linaro.org> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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- 09 11月, 2015 2 次提交
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由 Ard Biesheuvel 提交于
The mapping permissions of the FDT are set to 'PAGE_KERNEL | PTE_RDONLY' in an attempt to map the FDT as read-only. However, not only does this break at build time under STRICT_MM_TYPECHECKS (since the two terms are of different types in that case), it also results in both the PTE_WRITE and PTE_RDONLY attributes to be set, which means the region is still writable under ARMv8.1 DBM (and an attempted write will simply clear the PT_RDONLY bit). So instead, define PAGE_KERNEL_RO (which already has an established meaning across architectures) and use that instead. Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Ard Biesheuvel 提交于
The new page table code that manipulates the PTE_CONT flags does so in a way that is inconsistent with STRICT_MM_TYPECHECKS. Fix it by using the correct combination of __pgprot() and pgprot_val(). Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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- 07 11月, 2015 3 次提交
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由 Zi Shen Lim 提交于
Turns out in the case of modulo by zero in a BPF program: A = A % X; (X == 0) the expected behavior is to terminate with return value 0. The bug in JIT is exposed by a new test case [1]. [1] https://lkml.org/lkml/2015/11/4/499Signed-off-by: NZi Shen Lim <zlim.lnx@gmail.com> Reported-by: NYang Shi <yang.shi@linaro.org> Reported-by: NXi Wang <xi.wang@gmail.com> CC: Alexei Starovoitov <ast@plumgrid.com> Fixes: e54bcde3 ("arm64: eBPF JIT compiler") Cc: <stable@vger.kernel.org> # 3.18+ Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Zi Shen Lim 提交于
In the case of division by zero in a BPF program: A = A / X; (X == 0) the expected behavior is to terminate with return value 0. This is confirmed by the test case introduced in commit 86bf1721 ("test_bpf: add tests checking that JIT/interpreter sets A and X to 0."). Reported-by: NYang Shi <yang.shi@linaro.org> Tested-by: NYang Shi <yang.shi@linaro.org> CC: Xi Wang <xi.wang@gmail.com> CC: Alexei Starovoitov <ast@plumgrid.com> CC: linux-arm-kernel@lists.infradead.org CC: linux-kernel@vger.kernel.org Fixes: e54bcde3 ("arm64: eBPF JIT compiler") Cc: <stable@vger.kernel.org> # 3.18+ Signed-off-by: NZi Shen Lim <zlim.lnx@gmail.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Catalin Marinas 提交于
CONFIG_CRYPTO_CRC32_ARM64 has been around since commit f6f203fa ("crypto: crc32 - Add ARM64 CRC32 hw accelerated module") but defconfig did not automatically enable it. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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- 06 11月, 2015 1 次提交
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由 Lorenzo Pieralisi 提交于
The current arm64 __cmpxchg_double{_mb} implementations carry out the compare exchange by first comparing the old values passed in to the values read from the pointer provided and by stashing the cumulative bitwise difference in a 64-bit register. By comparing the register content against 0, it is possible to detect if the values read differ from the old values passed in, so that the compare exchange detects whether it has to bail out or carry on completing the operation with the exchange. Given the current implementation, to detect the cmpxchg operation status, the __cmpxchg_double{_mb} functions should return the 64-bit stashed bitwise difference so that the caller can detect cmpxchg failure by comparing the return value content against 0. The current implementation declares the return value as an int, which means that the 64-bit value stashing the bitwise difference is truncated before being returned to the __cmpxchg_double{_mb} callers, which means that any bitwise difference present in the top 32 bits goes undetected, triggering false positives and subsequent kernel failures. This patch fixes the issue by declaring the arm64 __cmpxchg_double{_mb} return values as a long, so that the bitwise difference is properly propagated on failure, restoring the expected behaviour. Fixes: e9a4b795 ("arm64: cmpxchg_dbl: patch in lse instructions when supported by the CPU") Cc: <stable@vger.kernel.org> # 4.3+ Cc: Marc Zyngier <marc.zyngier@arm.com> Acked-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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- 02 11月, 2015 1 次提交
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由 Ard Biesheuvel 提交于
Now that we strictly forbid absolute relocations in libstub code, make sure that we don't emit any when CONFIG_MODVERSIONS is enabled, by stripping the kcrctab sections from the object file. This fixes a build problem under CONFIG_MODVERSIONS=y. Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: NMatt Fleming <matt@codeblueprint.co.uk> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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- 31 10月, 2015 2 次提交
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由 Dietmar Eggemann 提交于
Make sure that the task scheduler domain hierarchy is set-up correctly on systems with single or multi-cluster topology. Signed-off-by: NDietmar Eggemann <dietmar.eggemann@arm.com> Acked-by: NPunit Agrawal <punit.agrawal@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Ard Biesheuvel 提交于
Now that we added special handling to the C files in libstub, move the one remaining arm64 specific EFI stub C file to libstub as well, so that it gets the same treatment. This should prevent future changes from resulting in binaries that may execute incorrectly in UEFI context. With efi-entry.S the only remaining EFI stub source file under arch/arm64, we can also simplify the Makefile logic somewhat. Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: NMatt Fleming <matt@codeblueprint.co.uk> Tested-by: NJeremy Linton <jeremy.linton@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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- 30 10月, 2015 3 次提交
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由 Mark Rutland 提交于
A kernel built with DEBUG_RO_DATA && !CONFIG_DEBUG_ALIGN_RODATA doesn't have .text aligned to a page boundary, though fixup_executable works at page-granularity thanks to its use of create_mapping. If .text is not page-aligned, the first page it exists in may be marked non-executable, leading to failures when an attempt is made to execute code in said page. This patch upgrades ALIGN_DEBUG_RO and ALIGN_DEBUG_RO_MIN to force page alignment for DEBUG_RO_DATA && !CONFIG_DEBUG_ALIGN_RODATA kernels, ensuring that all sections with specific RWX permission requirements are mapped with the correct permissions. Signed-off-by: NMark Rutland <mark.rutland@arm.com> Reported-by: NJeremy Linton <jeremy.linton@arm.com> Reviewed-by: NLaura Abbott <laura@labbott.name> Acked-by: NArd Biesheuvel <ard.biesheuvel@linaro.org> Cc: Suzuki Poulose <suzuki.poulose@arm.com> Cc: Will Deacon <will.deacon@arm.com> Fixes: da141706 ("arm64: add better page protections to arm64") Cc: <stable@vger.kernel.org> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Robin Murphy 提交于
Trying to build with CONFIG_ZONE_DMA=n leaves visible references to the now-undefined ZONE_DMA, resulting in a syntax error. Hide the references behind an #ifdef instead of using IS_ENABLED. Signed-off-by: NRobin Murphy <robin.murphy@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Robin Murphy 提交于
For reasons not entirely apparent, but now enshrined in history, the architectural mapping of AArch32 banked registers to AArch64 registers actually orders SP_<mode> and LR_<mode> backwards compared to the intuitive r13/r14 order, for all modes except FIQ. Fix the compat_<reg>_<mode> macros accordingly, in the hope of avoiding subtle bugs with KVM and AArch32 guests. Signed-off-by: NRobin Murphy <robin.murphy@arm.com> Acked-by: NWill Deacon <will.deacon@arm.com> Cc: <stable@vger.kernel.org> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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- 29 10月, 2015 6 次提交
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由 Tirumalesh Chalamarla 提交于
Increase the standard cacheline size to avoid having locks in the same cacheline. Cavium's ThunderX core implements cache lines of 128 byte size. With current granulare size of 64 bytes (L1_CACHE_SHIFT=6) two locks could share the same cache line leading a performance degradation. Increasing the size fixes that. Increasing the size has no negative impact to cache invalidation on systems with a smaller cache line. There is an impact on memory usage, but that's not too important for arm64 use cases. Signed-off-by: NTirumalesh Chalamarla <tchalamarla@cavium.com> Signed-off-by: NRobert Richter <rrichter@cavium.com> Acked-by: NTimur Tabi <timur@codeaurora.org> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Ard Biesheuvel 提交于
The comparison between TASK_SIZE_64 and MODULES_VADDR does not make any sense on arm64, it is simply something that has been carried over from the ARM port which arm64 is based on. So drop it. Signed-off-by: NArd Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Kefeng Wang 提交于
It allows a selectable timer interrupt frequency of 100, 250, 300 and 1000 HZ. We will get better performance when choose a suitable frequency in some scene. Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: NKefeng Wang <wangkefeng.wang@huawei.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Alexander Kuleshov 提交于
The <linux/mm.h> already provides the PAGE_ALIGNED macro. Let's use this macro instead of IS_ALIGNED and passing PAGE_SIZE directly. Signed-off-by: NAlexander Kuleshov <kuleshovmail@gmail.com> Acked-by: NLaura Abbott <laura@labbott.name> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Will Deacon 提交于
test_bit and set_bit take the bit number to operate on, rather than a mask. This patch fixes the ICACHEF_* definitions so that they represent the bit index in __icache_flags as opposed to the mask returned by the BIT macro. Signed-off-by: NWill Deacon <will.deacon@arm.com> Reviewed-by: NMark Rutland <mark.rutland@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Will Deacon 提交于
enable_cpu_capabilities is only called from within cpufeature.c, so it can be declared static. Signed-off-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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- 23 10月, 2015 1 次提交
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip由 Catalin Marinas 提交于
This is an incremental fix for a patch previously pulled from tip irq/for-arm. * 'irq/for-arm' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: genirq: Make the cpuhotplug migration code less noisy
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- 22 10月, 2015 1 次提交
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由 Thomas Gleixner 提交于
The original arm code has a pr_debug() statement for the case where the irq chip has no set_affinity() callback. That's sufficient for debugging and we really don't want to spam dmesg with useless warnings for the normal case. Fixes: f1e0bb0a: "genirq: Introduce generic irq migration for cpu hotunplug" Reported-by: NGeert Uytterhoeven <geert@linux-m68k.org> Requested-by: NRussell King <linux@arm.linux.org.uk> Signed-off-by: NThomas Gleixner <tglx@linutronix.de> Cc: Yang Yingliang <yangyingliang@huawei.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Hanjun Guo <hanjun.guo@linaro.org> Cc: Jiang Liu <jiang.liu@linux.intel.com>
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- 21 10月, 2015 13 次提交
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由 Dave Martin 提交于
The hwcap string arrays used for generating the contents of /proc/cpuinfo are currently arrays of non-const pointers. There's no need for these pointers to be mutable, so this patch makes them const so that they can be moved to .rodata. Signed-off-by: NDave Martin <Dave.Martin@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Suzuki K. Poulose 提交于
Use the system wide safe value from the new API for safer decisions Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: kvmarm@lists.cs.columbia.edu Signed-off-by: NSuzuki K. Poulose <suzuki.poulose@arm.com> Acked-by: NChristoffer Dall <christoffer.dall@linaro.org> Tested-by: NDave Martin <Dave.Martin@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Suzuki K. Poulose 提交于
Use the system wide value of ID_AA64DFR0 to make safer decisions Signed-off-by: NSuzuki K. Poulose <suzuki.poulose@arm.com> Tested-by: NDave Martin <Dave.Martin@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Suzuki K. Poulose 提交于
The FP/ASIMD is detected in fpsimd_init(), which is built-in unconditionally. Lets move the hwcap handling to the central place. Signed-off-by: NSuzuki K. Poulose <suzuki.poulose@arm.com> Tested-by: NDave Martin <Dave.Martin@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Suzuki K. Poulose 提交于
Extend struct arm64_cpu_capabilities to handle the HWCAP detection and make use of the system wide value of the feature registers for a reliable set of HWCAPs. Signed-off-by: NSuzuki K. Poulose <suzuki.poulose@arm.com> Tested-by: NDave Martin <Dave.Martin@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Suzuki K. Poulose 提交于
Now that we can reliably read the system wide safe value for a feature register, use that to compute the system capability. This patch also replaces the 'feature-register-specific' methods with a generic routine to check the capability. Signed-off-by: NSuzuki K. Poulose <suzuki.poulose@arm.com> Tested-by: NDave Martin <Dave.Martin@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Suzuki K. Poulose 提交于
At the moment we run through the arm64_features capability list for each CPU and set the capability if one of the CPU supports it. This could be problematic in a heterogeneous system with differing capabilities. Delay the CPU feature checks until all the enabled CPUs are up(i.e, smp_cpus_done(), so that we can make better decisions based on the overall system capability. Once we decide and advertise the capabilities the alternatives can be applied. From this state, we cannot roll back a feature to disabled based on the values from a new hotplugged CPU, due to the runtime patching and other reasons. So, for all new CPUs, we need to make sure that they have the established system capabilities. Failing which, we bring the CPU down, preventing it from turning online. Once the capabilities are decided, any new CPU booting up goes through verification to ensure that it has all the enabled capabilities and also invokes the respective enable() method on the CPU. The CPU errata checks are not delayed and is still executed per-CPU to detect the respective capabilities. If we ever come across a non-errata capability that needs to be checked on each-CPU, we could introduce them via a new capability table(or introduce a flag), which can be processed per CPU. The next patch will make the feature checks use the system wide safe value of a feature register. NOTE: The enable() methods associated with the capability is scheduled on all the CPUs (which is the only use case at the moment). If we need a different type of 'enable()' which only needs to be run once on any CPU, we should be able to handle that when needed. Signed-off-by: NSuzuki K. Poulose <suzuki.poulose@arm.com> Tested-by: NDave Martin <Dave.Martin@arm.com> [catalin.marinas@arm.com: static variable and coding style fixes] Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Suzuki K. Poulose 提交于
check_cpu_capabilities runs through a given list of caps and checks if the system has the cap, updates the system capability bitmap and also runs any enable() methods associated with them. All of this is not quite obvious from the name 'check'. This patch splits the check_cpu_capabilities into two parts : 1) update_cpu_capabilities => Runs through the given list and updates the system wide capability map. 2) enable_cpu_capabilities => Runs through the given list and invokes enable() (if any) for the caps enabled on the system. Cc: Andre Przywara <andre.przywara@arm.com> Cc: Will Deacon <will.deacon@arm.com> Suggested-by: NCatalin Marinas <catalin.marinsa@arm.com> Signed-off-by: NSuzuki K. Poulose <suzuki.poulose@arm.com> Tested-by: NDave Martin <Dave.Martin@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Suzuki K. Poulose 提交于
Make use of the system wide safe register to decide the support for mixed endian. Signed-off-by: NSuzuki K. Poulose <suzuki.poulose@arm.com> Tested-by: NDave Martin <Dave.Martin@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Suzuki K. Poulose 提交于
Add an API for reading the safe CPUID value across the system from the new infrastructure. Signed-off-by: NSuzuki K. Poulose <suzuki.poulose@arm.com> Tested-by: NDave Martin <Dave.Martin@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Suzuki K. Poulose 提交于
This patch consolidates the CPU Sanity check to the new infrastructure. Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: NSuzuki K. Poulose <suzuki.poulose@arm.com> Tested-by: NDave Martin <Dave.Martin@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Suzuki K. Poulose 提交于
This patch adds an infrastructure to keep track of the CPU feature registers on the system. For each register, the infrastructure keeps track of the system wide safe value of the feature bits. Also, tracks the which fields of a register should be matched strictly across all the CPUs on the system for the SANITY check infrastructure. The feature bits are classified into following 3 types depending on the implication of the possible values. This information is used to decide the safe value for a feature. LOWER_SAFE - The smaller value is safer HIGHER_SAFE - The bigger value is safer EXACT - We can't decide between the two, so a predefined safe_value is used. This infrastructure will be later used to make better decisions for: - Kernel features (e.g, KVM, Debug) - SANITY Check - CPU capability - ELF HWCAP - Exposing CPU Feature register to userspace. Signed-off-by: NSuzuki K. Poulose <suzuki.poulose@arm.com> Tested-by: NDave Martin <Dave.Martin@arm.com> [catalin.marinas@arm.com: whitespace fix] Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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由 Suzuki K. Poulose 提交于
Introduce a helper to extract cpuid feature for any given width. Signed-off-by: NSuzuki K. Poulose <suzuki.poulose@arm.com> Tested-by: NDave Martin <Dave.Martin@arm.com> Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
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