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提交 3f00d3e8 编写于 作者: L Linus Torvalds
浏览文件
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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

上级 407cf84f a637a114
展开全部 隐藏空白更改
内联 并排
Showing with 1896 addition and 917 deletion
arch/mips/Kconfig
浏览文件 @ 3f00d3e8
......@@ -958,7 +958,7 @@ config SOC_PNX8550
bool
select DMA_NONCOHERENT
select HW_HAS_PCI
select SYS_HAS_CPU_R4X00
select SYS_HAS_CPU_MIPS32_R1
select SYS_SUPPORTS_32BIT_KERNEL
config SWAP_IO_SPACE
......
arch/mips/boot/.gitignore 0 → 100644
浏览文件 @ 3f00d3e8
mkboot
elf2ecoff
zImage
zImage.tmp
arch/mips/configs/pnx8550-jbs_defconfig
浏览文件 @ 3f00d3e8
......@@ -129,7 +129,7 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
#
# CPU selection
#
# CONFIG_CPU_MIPS32_R1 is not set
CONFIG_CPU_MIPS32_R1=y
# CONFIG_CPU_MIPS32_R2 is not set
# CONFIG_CPU_MIPS64_R1 is not set
# CONFIG_CPU_MIPS64_R2 is not set
......@@ -137,7 +137,7 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_CPU_R4300 is not set
CONFIG_CPU_R4X00=y
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
......@@ -148,10 +148,11 @@ CONFIG_CPU_R4X00=y
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_RM9000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_SYS_HAS_CPU_R4X00=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_CPU_MIPS32=y
CONFIG_CPU_MIPSR1=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
#
# Kernel type
......@@ -162,11 +163,11 @@ CONFIG_PAGE_SIZE_4KB=y
# CONFIG_PAGE_SIZE_8KB is not set
# CONFIG_PAGE_SIZE_16KB is not set
# CONFIG_PAGE_SIZE_64KB is not set
CONFIG_CPU_HAS_PREFETCH=y
# CONFIG_MIPS_MT is not set
# CONFIG_64BIT_PHYS_ADDR is not set
# CONFIG_CPU_ADVANCED is not set
CONFIG_CPU_HAS_LLSC=y
CONFIG_CPU_HAS_LLDSCD=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_IRQ_PROBE=y
......
arch/mips/configs/pnx8550-v2pci_defconfig
浏览文件 @ 3f00d3e8
......@@ -128,7 +128,7 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
#
# CPU selection
#
# CONFIG_CPU_MIPS32_R1 is not set
CONFIG_CPU_MIPS32_R1=y
# CONFIG_CPU_MIPS32_R2 is not set
# CONFIG_CPU_MIPS64_R1 is not set
# CONFIG_CPU_MIPS64_R2 is not set
......@@ -136,7 +136,7 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5
# CONFIG_CPU_TX39XX is not set
# CONFIG_CPU_VR41XX is not set
# CONFIG_CPU_R4300 is not set
CONFIG_CPU_R4X00=y
# CONFIG_CPU_R4X00 is not set
# CONFIG_CPU_TX49XX is not set
# CONFIG_CPU_R5000 is not set
# CONFIG_CPU_R5432 is not set
......@@ -147,10 +147,11 @@ CONFIG_CPU_R4X00=y
# CONFIG_CPU_RM7000 is not set
# CONFIG_CPU_RM9000 is not set
# CONFIG_CPU_SB1 is not set
CONFIG_SYS_HAS_CPU_R4X00=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_CPU_MIPS32=y
CONFIG_CPU_MIPSR1=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
#
# Kernel type
......@@ -161,6 +162,7 @@ CONFIG_PAGE_SIZE_4KB=y
# CONFIG_PAGE_SIZE_8KB is not set
# CONFIG_PAGE_SIZE_16KB is not set
# CONFIG_PAGE_SIZE_64KB is not set
CONFIG_CPU_HAS_PREFETCH=y
# CONFIG_MIPS_MT is not set
# CONFIG_64BIT_PHYS_ADDR is not set
CONFIG_CPU_ADVANCED=y
......
arch/mips/ddb5xxx/common/rtc_ds1386.c
浏览文件 @ 3f00d3e8
......@@ -41,7 +41,9 @@ rtc_ds1386_get_time(void)
u8 byte;
u8 temp;
unsigned int year, month, day, hour, minute, second;
unsigned long flags;
spin_lock_irqsave(&rtc_lock, flags);
/* let us freeze external registers */
byte = READ_RTC(0xB);
byte &= 0x3f;
......@@ -60,6 +62,7 @@ rtc_ds1386_get_time(void)
/* enable time transfer */
byte |= 0x80;
WRITE_RTC(0xB, byte);
spin_unlock_irqrestore(&rtc_lock, flags);
/* calc hour */
if (temp & 0x40) {
......@@ -81,7 +84,9 @@ rtc_ds1386_set_time(unsigned long t)
u8 byte;
u8 temp;
u8 year, month, day, hour, minute, second;
unsigned long flags;
spin_lock_irqsave(&rtc_lock, flags);
/* let us freeze external registers */
byte = READ_RTC(0xB);
byte &= 0x3f;
......@@ -133,6 +138,7 @@ rtc_ds1386_set_time(unsigned long t)
if (second != READ_RTC(0x1)) {
WRITE_RTC(0x1, second);
}
spin_unlock_irqrestore(&rtc_lock, flags);
return 0;
}
......
arch/mips/dec/time.c
浏览文件 @ 3f00d3e8
......@@ -37,10 +37,25 @@
#include <asm/dec/machtype.h>
/*
* Returns true if a clock update is in progress
*/
static inline unsigned char dec_rtc_is_updating(void)
{
unsigned char uip;
unsigned long flags;
spin_lock_irqsave(&rtc_lock, flags);
uip = (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP);
spin_unlock_irqrestore(&rtc_lock, flags);
return uip;
}
static unsigned long dec_rtc_get_time(void)
{
unsigned int year, mon, day, hour, min, sec, real_year;
int i;
unsigned long flags;
/* The Linux interpretation of the DS1287 clock register contents:
* When the Update-In-Progress (UIP) flag goes from 1 to 0, the
......@@ -49,11 +64,12 @@ static unsigned long dec_rtc_get_time(void)
*/
/* read RTC exactly on falling edge of update flag */
for (i = 0; i < 1000000; i++) /* may take up to 1 second... */
if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
if (dec_rtc_is_updating())
break;
for (i = 0; i < 1000000; i++) /* must try at least 2.228 ms */
if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
if (!dec_rtc_is_updating())
break;
spin_lock_irqsave(&rtc_lock, flags);
/* Isn't this overkill? UIP above should guarantee consistency */
do {
sec = CMOS_READ(RTC_SECONDS);
......@@ -77,6 +93,7 @@ static unsigned long dec_rtc_get_time(void)
* of unused BBU RAM locations.
*/
real_year = CMOS_READ(RTC_DEC_YEAR);
spin_unlock_irqrestore(&rtc_lock, flags);
year += real_year - 72 + 2000;
return mktime(year, mon, day, hour, min, sec);
......@@ -95,6 +112,8 @@ static int dec_rtc_set_mmss(unsigned long nowtime)
int real_seconds, real_minutes, cmos_minutes;
unsigned char save_control, save_freq_select;
/* irq are locally disabled here */
spin_lock(&rtc_lock);
/* tell the clock it's being set */
save_control = CMOS_READ(RTC_CONTROL);
CMOS_WRITE((save_control | RTC_SET), RTC_CONTROL);
......@@ -141,6 +160,7 @@ static int dec_rtc_set_mmss(unsigned long nowtime)
*/
CMOS_WRITE(save_control, RTC_CONTROL);
CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
spin_unlock(&rtc_lock);
return retval;
}
......
arch/mips/jmr3927/common/rtc_ds1742.c
浏览文件 @ 3f00d3e8
......@@ -57,7 +57,9 @@ rtc_ds1742_get_time(void)
{
unsigned int year, month, day, hour, minute, second;
unsigned int century;
unsigned long flags;
spin_lock_irqsave(&rtc_lock, flags);
CMOS_WRITE(RTC_READ, RTC_CONTROL);
second = BCD2BIN(CMOS_READ(RTC_SECONDS) & RTC_SECONDS_MASK);
minute = BCD2BIN(CMOS_READ(RTC_MINUTES));
......@@ -67,6 +69,7 @@ rtc_ds1742_get_time(void)
year = BCD2BIN(CMOS_READ(RTC_YEAR));
century = BCD2BIN(CMOS_READ(RTC_CENTURY) & RTC_CENTURY_MASK);
CMOS_WRITE(0, RTC_CONTROL);
spin_unlock_irqrestore(&rtc_lock, flags);
year += century * 100;
......@@ -81,7 +84,9 @@ rtc_ds1742_set_time(unsigned long t)
u8 year, month, day, hour, minute, second;
u8 cmos_year, cmos_month, cmos_day, cmos_hour, cmos_minute, cmos_second;
int cmos_century;
unsigned long flags;
spin_lock_irqsave(&rtc_lock, flags);
CMOS_WRITE(RTC_READ, RTC_CONTROL);
cmos_second = (u8)(CMOS_READ(RTC_SECONDS) & RTC_SECONDS_MASK);
cmos_minute = (u8)CMOS_READ(RTC_MINUTES);
......@@ -139,6 +144,7 @@ rtc_ds1742_set_time(unsigned long t)
/* RTC_CENTURY and RTC_CONTROL share same address... */
CMOS_WRITE(cmos_century, RTC_CONTROL);
spin_unlock_irqrestore(&rtc_lock, flags);
return 0;
}
......
arch/mips/kernel/irixsig.c
浏览文件 @ 3f00d3e8
......@@ -502,8 +502,7 @@ asmlinkage int irix_sigpoll_sys(unsigned long __user *set,
while(1) {
long tmp = 0;
current->state = TASK_INTERRUPTIBLE;
expire = schedule_timeout(expire);
expire = schedule_timeout_interruptible(expire);
for (i=0; i<=4; i++)
tmp |= (current->pending.signal.sig[i] & kset.sig[i]);
......
arch/mips/kernel/rtlx.c
浏览文件 @ 3f00d3e8
......@@ -20,42 +20,42 @@
#include <linux/module.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <asm/uaccess.h>
#include <linux/slab.h>
#include <linux/list.h>
#include <linux/vmalloc.h>
#include <linux/elf.h>
#include <linux/seq_file.h>
#include <linux/syscalls.h>
#include <linux/moduleloader.h>
#include <linux/interrupt.h>
#include <linux/poll.h>
#include <linux/sched.h>
#include <linux/wait.h>
#include <asm/mipsmtregs.h>
#include <asm/cacheflush.h>
#include <asm/atomic.h>
#include <asm/bitops.h>
#include <asm/cpu.h>
#include <asm/processor.h>
#include <asm/system.h>
#include <asm/rtlx.h>
#include <asm/uaccess.h>
#define RTLX_MAJOR 64
#define RTLX_TARG_VPE 1
struct rtlx_info *rtlx;
static struct rtlx_info *rtlx;
static int major;
static char module_name[] = "rtlx";
static inline int spacefree(int read, int write, int size);
static struct irqaction irq;
static int irq_num;
static inline int spacefree(int read, int write, int size)
{
if (read == write) {
/*
* never fill the buffer completely, so indexes are always
* equal if empty and only empty, or !equal if data available
*/
return size - 1;
}
return ((read + size - write) % size) - 1;
}
static struct chan_waitqueues {
wait_queue_head_t rt_queue;
wait_queue_head_t lx_queue;
} channel_wqs[RTLX_CHANNELS];
static struct irqaction irq;
static int irq_num;
extern void *vpe_get_shared(int index);
static void rtlx_dispatch(struct pt_regs *regs)
......@@ -63,9 +63,8 @@ static void rtlx_dispatch(struct pt_regs *regs)
do_IRQ(MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ, regs);
}
irqreturn_t rtlx_interrupt(int irq, void *dev_id, struct pt_regs *regs)
static irqreturn_t rtlx_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
irqreturn_t r = IRQ_HANDLED;
int i;
for (i = 0; i < RTLX_CHANNELS; i++) {
......@@ -75,30 +74,7 @@ irqreturn_t rtlx_interrupt(int irq, void *dev_id, struct pt_regs *regs)
wake_up_interruptible(&channel_wqs[i].lx_queue);
}
return r;
}
void dump_rtlx(void)
{
int i;
printk("id 0x%lx state %d\n", rtlx->id, rtlx->state);
for (i = 0; i < RTLX_CHANNELS; i++) {
struct rtlx_channel *chan = &rtlx->channel[i];
printk(" rt_state %d lx_state %d buffer_size %d\n",
chan->rt_state, chan->lx_state, chan->buffer_size);
printk(" rt_read %d rt_write %d\n",
chan->rt_read, chan->rt_write);
printk(" lx_read %d lx_write %d\n",
chan->lx_read, chan->lx_write);
printk(" rt_buffer <%s>\n", chan->rt_buffer);
printk(" lx_buffer <%s>\n", chan->lx_buffer);
}
return IRQ_HANDLED;
}
/* call when we have the address of the shared structure from the SP side. */
......@@ -108,7 +84,7 @@ static int rtlx_init(struct rtlx_info *rtlxi)
if (rtlxi->id != RTLX_ID) {
printk(KERN_WARNING "no valid RTLX id at 0x%p\n", rtlxi);
return (-ENOEXEC);
return -ENOEXEC;
}
/* initialise the wait queues */
......@@ -120,9 +96,8 @@ static int rtlx_init(struct rtlx_info *rtlxi)
/* set up for interrupt handling */
memset(&irq, 0, sizeof(struct irqaction));
if (cpu_has_vint) {
if (cpu_has_vint)
set_vi_handler(MIPS_CPU_RTLX_IRQ, rtlx_dispatch);
}
irq_num = MIPSCPU_INT_BASE + MIPS_CPU_RTLX_IRQ;
irq.handler = rtlx_interrupt;
......@@ -132,7 +107,8 @@ static int rtlx_init(struct rtlx_info *rtlxi)
setup_irq(irq_num, &irq);
rtlx = rtlxi;
return (0);
return 0;
}
/* only allow one open process at a time to open each channel */
......@@ -147,36 +123,36 @@ static int rtlx_open(struct inode *inode, struct file *filp)
if (rtlx == NULL) {
struct rtlx_info **p;
if( (p = vpe_get_shared(RTLX_TARG_VPE)) == NULL) {
printk(" vpe_get_shared is NULL. Has an SP program been loaded?\n");
return (-EFAULT);
printk(KERN_ERR "vpe_get_shared is NULL. "
"Has an SP program been loaded?\n");
return -EFAULT;
}
if (*p == NULL) {
printk(" vpe_shared %p %p\n", p, *p);
return (-EFAULT);
printk(KERN_ERR "vpe_shared %p %p\n", p, *p);
return -EFAULT;
}
if ((ret = rtlx_init(*p)) < 0)
return (ret);
return ret;
}
chan = &rtlx->channel[minor];
/* already open? */
if (chan->lx_state == RTLX_STATE_OPENED)
return (-EBUSY);
if (test_and_set_bit(RTLX_STATE_OPENED, &chan->lx_state))
return -EBUSY;
chan->lx_state = RTLX_STATE_OPENED;
return (0);
return 0;
}
static int rtlx_release(struct inode *inode, struct file *filp)
{
int minor;
int minor = MINOR(inode->i_rdev);
minor = MINOR(inode->i_rdev);
rtlx->channel[minor].lx_state = RTLX_STATE_UNUSED;
return (0);
clear_bit(RTLX_STATE_OPENED, &rtlx->channel[minor].lx_state);
smp_mb__after_clear_bit();
return 0;
}
static unsigned int rtlx_poll(struct file *file, poll_table * wait)
......@@ -199,12 +175,13 @@ static unsigned int rtlx_poll(struct file *file, poll_table * wait)
if (spacefree(chan->rt_read, chan->rt_write, chan->buffer_size))
mask |= POLLOUT | POLLWRNORM;
return (mask);
return mask;
}
static ssize_t rtlx_read(struct file *file, char __user * buffer, size_t count,
loff_t * ppos)
{
unsigned long failed;
size_t fl = 0L;
int minor;
struct rtlx_channel *lx;
......@@ -216,7 +193,7 @@ static ssize_t rtlx_read(struct file *file, char __user * buffer, size_t count,
/* data available? */
if (lx->lx_write == lx->lx_read) {
if (file->f_flags & O_NONBLOCK)
return (0); // -EAGAIN makes cat whinge
return 0; /* -EAGAIN makes cat whinge */
/* go to sleep */
add_wait_queue(&channel_wqs[minor].lx_queue, &wait);
......@@ -232,39 +209,39 @@ static ssize_t rtlx_read(struct file *file, char __user * buffer, size_t count,
}
/* find out how much in total */
count = min( count,
(size_t)(lx->lx_write + lx->buffer_size - lx->lx_read) % lx->buffer_size);
count = min(count,
(size_t)(lx->lx_write + lx->buffer_size - lx->lx_read) % lx->buffer_size);
/* then how much from the read pointer onwards */
fl = min( count, (size_t)lx->buffer_size - lx->lx_read);
fl = min(count, (size_t)lx->buffer_size - lx->lx_read);
copy_to_user (buffer, &lx->lx_buffer[lx->lx_read], fl);
failed = copy_to_user (buffer, &lx->lx_buffer[lx->lx_read], fl);
if (failed) {
count = fl - failed;
goto out;
}
/* and if there is anything left at the beginning of the buffer */
if ( count - fl )
copy_to_user (buffer + fl, lx->lx_buffer, count - fl);
if (count - fl) {
failed = copy_to_user (buffer + fl, lx->lx_buffer, count - fl);
if (failed) {
count -= failed;
goto out;
}
}
out:
/* update the index */
lx->lx_read += count;
lx->lx_read %= lx->buffer_size;
return (count);
}
static inline int spacefree(int read, int write, int size)
{
if (read == write) {
/* never fill the buffer completely, so indexes are always equal if empty
and only empty, or !equal if data available */
return (size - 1);
}
return ((read + size - write) % size) - 1;
return count;
}
static ssize_t rtlx_write(struct file *file, const char __user * buffer,
size_t count, loff_t * ppos)
{
unsigned long failed;
int minor;
struct rtlx_channel *rt;
size_t fl;
......@@ -277,7 +254,7 @@ static ssize_t rtlx_write(struct file *file, const char __user * buffer,
if (!spacefree(rt->rt_read, rt->rt_write, rt->buffer_size)) {
if (file->f_flags & O_NONBLOCK)
return (-EAGAIN);
return -EAGAIN;
add_wait_queue(&channel_wqs[minor].rt_queue, &wait);
set_current_state(TASK_INTERRUPTIBLE);
......@@ -290,52 +267,64 @@ static ssize_t rtlx_write(struct file *file, const char __user * buffer,
}
/* total number of bytes to copy */
count = min( count, (size_t)spacefree(rt->rt_read, rt->rt_write, rt->buffer_size) );
count = min(count, (size_t)spacefree(rt->rt_read, rt->rt_write, rt->buffer_size) );
/* first bit from write pointer to the end of the buffer, or count */
fl = min(count, (size_t) rt->buffer_size - rt->rt_write);
copy_from_user(&rt->rt_buffer[rt->rt_write], buffer, fl);
failed = copy_from_user(&rt->rt_buffer[rt->rt_write], buffer, fl);
if (failed) {
count = fl - failed;
goto out;
}
/* if there's any left copy to the beginning of the buffer */
if( count - fl )
copy_from_user(rt->rt_buffer, buffer + fl, count - fl);
if (count - fl) {
failed = copy_from_user(rt->rt_buffer, buffer + fl, count - fl);
if (failed) {
count -= failed;
goto out;
}
}
out:
rt->rt_write += count;
rt->rt_write %= rt->buffer_size;
return(count);
return count;
}
static struct file_operations rtlx_fops = {
.owner = THIS_MODULE,
.open = rtlx_open,
.release = rtlx_release,
.write = rtlx_write,
.read = rtlx_read,
.poll = rtlx_poll
.owner = THIS_MODULE,
.open = rtlx_open,
.release = rtlx_release,
.write = rtlx_write,
.read = rtlx_read,
.poll = rtlx_poll
};
static int rtlx_module_init(void)
static char register_chrdev_failed[] __initdata =
KERN_ERR "rtlx_module_init: unable to register device\n";
static int __init rtlx_module_init(void)
{
if ((major = register_chrdev(RTLX_MAJOR, module_name, &rtlx_fops)) < 0) {
printk("rtlx_module_init: unable to register device\n");
return (-EBUSY);
major = register_chrdev(0, module_name, &rtlx_fops);
if (major < 0) {
printk(register_chrdev_failed);
return major;
}
if (major == 0)
major = RTLX_MAJOR;
return (0);
return 0;
}
static void rtlx_module_exit(void)
static void __exit rtlx_module_exit(void)
{
unregister_chrdev(major, module_name);
}
module_init(rtlx_module_init);
module_exit(rtlx_module_exit);
MODULE_DESCRIPTION("MIPS RTLX");
MODULE_AUTHOR("Elizabeth Clarke, MIPS Technologies, Inc");
MODULE_AUTHOR("Elizabeth Clarke, MIPS Technologies, Inc.");
MODULE_LICENSE("GPL");
arch/mips/kernel/signal.c
浏览文件 @ 3f00d3e8
......@@ -384,9 +384,6 @@ int setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs,
return 0;
}
extern void setup_rt_frame_n32(struct k_sigaction * ka,
struct pt_regs *regs, int signr, sigset_t *set, siginfo_t *info);
static inline int handle_signal(unsigned long sig, siginfo_t *info,
struct k_sigaction *ka, sigset_t *oldset, struct pt_regs *regs)
{
......
arch/mips/kernel/signal32.c
浏览文件 @ 3f00d3e8
......@@ -647,8 +647,8 @@ static inline void *get_sigframe(struct k_sigaction *ka, struct pt_regs *regs,
return (void *)((sp - frame_size) & ALMASK);
}
void setup_frame_32(struct k_sigaction * ka, struct pt_regs *regs,
int signr, sigset_t *set)
int setup_frame_32(struct k_sigaction * ka, struct pt_regs *regs,
int signr, sigset_t *set)
{
struct sigframe *frame;
int err = 0;
......@@ -694,13 +694,15 @@ void setup_frame_32(struct k_sigaction * ka, struct pt_regs *regs,
current->comm, current->pid,
frame, regs->cp0_epc, frame->sf_code);
#endif
return;
return 1;
give_sigsegv:
force_sigsegv(signr, current);
return 0;
}
void setup_rt_frame_32(struct k_sigaction * ka, struct pt_regs *regs, int signr, sigset_t *set, siginfo_t *info)
int setup_rt_frame_32(struct k_sigaction * ka, struct pt_regs *regs,
int signr, sigset_t *set, siginfo_t *info)
{
struct rt_sigframe32 *frame;
int err = 0;
......@@ -763,10 +765,11 @@ void setup_rt_frame_32(struct k_sigaction * ka, struct pt_regs *regs, int signr,
current->comm, current->pid,
frame, regs->cp0_epc, frame->rs_code);
#endif
return;
return 1;
give_sigsegv:
force_sigsegv(signr, current);
return 0;
}
static inline int handle_signal(unsigned long sig, siginfo_t *info,
......
arch/mips/kernel/vpe.c
浏览文件 @ 3f00d3e8
......@@ -58,10 +58,6 @@
typedef void *vpe_handle;
// defined here because the kernel module loader doesn't have
// anything to do with it.
#define SHN_MIPS_SCOMMON 0xff03
#ifndef ARCH_SHF_SMALL
#define ARCH_SHF_SMALL 0
#endif
......@@ -69,11 +65,8 @@ typedef void *vpe_handle;
/* If this is set, the section belongs in the init part of the module */
#define INIT_OFFSET_MASK (1UL << (BITS_PER_LONG-1))
// temp number,
#define VPE_MAJOR 63
static char module_name[] = "vpe";
static int major = 0;
static int major;
/* grab the likely amount of memory we will need. */
#ifdef CONFIG_MIPS_VPE_LOADER_TOM
......@@ -98,22 +91,7 @@ enum tc_state {
TC_STATE_DYNAMIC
};
struct vpe;
typedef struct tc {
enum tc_state state;
int index;
/* parent VPE */
struct vpe *pvpe;
/* The list of TC's with this VPE */
struct list_head tc;
/* The global list of tc's */
struct list_head list;
} tc_t;
typedef struct vpe {
struct vpe {
enum vpe_state state;
/* (device) minor associated with this vpe */
......@@ -135,7 +113,21 @@ typedef struct vpe {
/* shared symbol address */
void *shared_ptr;
} vpe_t;
};
struct tc {
enum tc_state state;
int index;
/* parent VPE */
struct vpe *pvpe;
/* The list of TC's with this VPE */
struct list_head tc;
/* The global list of tc's */
struct list_head list;
};
struct vpecontrol_ {
/* Virtual processing elements */
......@@ -146,7 +138,7 @@ struct vpecontrol_ {
} vpecontrol;
static void release_progmem(void *ptr);
static void dump_vpe(vpe_t * v);
static void dump_vpe(struct vpe * v);
extern void save_gp_address(unsigned int secbase, unsigned int rel);
/* get the vpe associated with this minor */
......@@ -197,13 +189,11 @@ struct vpe *alloc_vpe(int minor)
{
struct vpe *v;
if ((v = kmalloc(sizeof(struct vpe), GFP_KERNEL)) == NULL) {
if ((v = kzalloc(sizeof(struct vpe), GFP_KERNEL)) == NULL) {
printk(KERN_WARNING "VPE: alloc_vpe no mem\n");
return NULL;
}
memset(v, 0, sizeof(struct vpe));
INIT_LIST_HEAD(&v->tc);
list_add_tail(&v->list, &vpecontrol.vpe_list);
......@@ -216,13 +206,11 @@ struct tc *alloc_tc(int index)
{
struct tc *t;
if ((t = kmalloc(sizeof(struct tc), GFP_KERNEL)) == NULL) {
if ((t = kzalloc(sizeof(struct tc), GFP_KERNEL)) == NULL) {
printk(KERN_WARNING "VPE: alloc_tc no mem\n");
return NULL;
}
memset(t, 0, sizeof(struct tc));
INIT_LIST_HEAD(&t->tc);
list_add_tail(&t->list, &vpecontrol.tc_list);
......@@ -412,16 +400,17 @@ static int apply_r_mips_26(struct module *me, uint32_t *location,
return -ENOEXEC;
}
/* Not desperately convinced this is a good check of an overflow condition
anyway. But it gets in the way of handling undefined weak symbols which
we want to set to zero.
if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) {
printk(KERN_ERR
"module %s: relocation overflow\n",
me->name);
return -ENOEXEC;
}
*/
/*
* Not desperately convinced this is a good check of an overflow condition
* anyway. But it gets in the way of handling undefined weak symbols which
* we want to set to zero.
* if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) {
* printk(KERN_ERR
* "module %s: relocation overflow\n",
* me->name);
* return -ENOEXEC;
* }
*/
*location = (*location & ~0x03ffffff) |
((*location + (v >> 2)) & 0x03ffffff);
......@@ -681,7 +670,7 @@ static void dump_tclist(void)
}
/* We are prepared so configure and start the VPE... */
int vpe_run(vpe_t * v)
int vpe_run(struct vpe * v)
{
unsigned long val;
struct tc *t;
......@@ -772,7 +761,7 @@ int vpe_run(vpe_t * v)
return 0;
}
static unsigned long find_vpe_symbols(vpe_t * v, Elf_Shdr * sechdrs,
static unsigned long find_vpe_symbols(struct vpe * v, Elf_Shdr * sechdrs,
unsigned int symindex, const char *strtab,
struct module *mod)
{
......@@ -792,10 +781,12 @@ static unsigned long find_vpe_symbols(vpe_t * v, Elf_Shdr * sechdrs,
return 0;
}
/* Allocates a VPE with some program code space(the load address), copies the contents
of the program (p)buffer performing relocatations/etc, free's it when finished.
/*
* Allocates a VPE with some program code space(the load address), copies
* the contents of the program (p)buffer performing relocatations/etc,
* free's it when finished.
*/
int vpe_elfload(vpe_t * v)
int vpe_elfload(struct vpe * v)
{
Elf_Ehdr *hdr;
Elf_Shdr *sechdrs;
......@@ -931,7 +922,7 @@ int vpe_elfload(vpe_t * v)
return err;
}
static void dump_vpe(vpe_t * v)
static void dump_vpe(struct vpe * v)
{
struct tc *t;
......@@ -947,7 +938,7 @@ static void dump_vpe(vpe_t * v)
static int vpe_open(struct inode *inode, struct file *filp)
{
int minor;
vpe_t *v;
struct vpe *v;
/* assume only 1 device at the mo. */
if ((minor = MINOR(inode->i_rdev)) != 1) {
......@@ -1001,7 +992,7 @@ static int vpe_open(struct inode *inode, struct file *filp)
static int vpe_release(struct inode *inode, struct file *filp)
{
int minor, ret = 0;
vpe_t *v;
struct vpe *v;
Elf_Ehdr *hdr;
minor = MINOR(inode->i_rdev);
......@@ -1035,7 +1026,7 @@ static ssize_t vpe_write(struct file *file, const char __user * buffer,
{
int minor;
size_t ret = count;
vpe_t *v;
struct vpe *v;
minor = MINOR(file->f_dentry->d_inode->i_rdev);
if ((v = get_vpe(minor)) == NULL)
......@@ -1180,14 +1171,11 @@ static int __init vpe_module_init(void)
return -ENODEV;
}
if ((major = register_chrdev(VPE_MAJOR, module_name, &vpe_fops) < 0)) {
if ((major = register_chrdev(0, module_name, &vpe_fops) < 0)) {
printk("VPE loader: unable to register character device\n");
return -EBUSY;
return major;
}
if (major == 0)
major = VPE_MAJOR;
dmt();
dvpe();
......
arch/mips/lasat/ds1603.c
浏览文件 @ 3f00d3e8
......@@ -8,6 +8,7 @@
#include <asm/lasat/lasat.h>
#include <linux/delay.h>
#include <asm/lasat/ds1603.h>
#include <asm/time.h>
#include "ds1603.h"
......@@ -138,19 +139,27 @@ static void rtc_end_op(void)
unsigned long ds1603_read(void)
{
unsigned long word;
unsigned long flags;
spin_lock_irqsave(&rtc_lock, flags);
rtc_init_op();
rtc_write_byte(READ_TIME_CMD);
word = rtc_read_word();
rtc_end_op();
spin_unlock_irqrestore(&rtc_lock, flags);
return word;
}
int ds1603_set(unsigned long time)
{
unsigned long flags;
spin_lock_irqsave(&rtc_lock, flags);
rtc_init_op();
rtc_write_byte(SET_TIME_CMD);
rtc_write_word(time);
rtc_end_op();
spin_unlock_irqrestore(&rtc_lock, flags);
return 0;
}
......
arch/mips/momentum/jaguar_atx/setup.c
浏览文件 @ 3f00d3e8
......@@ -149,7 +149,9 @@ arch_initcall(per_cpu_mappings);
unsigned long m48t37y_get_time(void)
{
unsigned int year, month, day, hour, min, sec;
unsigned long flags;
spin_lock_irqsave(&rtc_lock, flags);
/* stop the update */
rtc_base[0x7ff8] = 0x40;
......@@ -166,6 +168,7 @@ unsigned long m48t37y_get_time(void)
/* start the update */
rtc_base[0x7ff8] = 0x00;
spin_unlock_irqrestore(&rtc_lock, flags);
return mktime(year, month, day, hour, min, sec);
}
......@@ -173,11 +176,13 @@ unsigned long m48t37y_get_time(void)
int m48t37y_set_time(unsigned long sec)
{
struct rtc_time tm;
unsigned long flags;
/* convert to a more useful format -- note months count from 0 */
to_tm(sec, &tm);
tm.tm_mon += 1;
spin_lock_irqsave(&rtc_lock, flags);
/* enable writing */
rtc_base[0x7ff8] = 0x80;
......@@ -201,6 +206,7 @@ int m48t37y_set_time(unsigned long sec)
/* disable writing */
rtc_base[0x7ff8] = 0x00;
spin_unlock_irqrestore(&rtc_lock, flags);
return 0;
}
......
arch/mips/momentum/ocelot_3/setup.c
浏览文件 @ 3f00d3e8
......@@ -135,7 +135,9 @@ void setup_wired_tlb_entries(void)
unsigned long m48t37y_get_time(void)
{
unsigned int year, month, day, hour, min, sec;
unsigned long flags;
spin_lock_irqsave(&rtc_lock, flags);
/* stop the update */
rtc_base[0x7ff8] = 0x40;
......@@ -152,6 +154,7 @@ unsigned long m48t37y_get_time(void)
/* start the update */
rtc_base[0x7ff8] = 0x00;
spin_unlock_irqrestore(&rtc_lock, flags);
return mktime(year, month, day, hour, min, sec);
}
......@@ -159,11 +162,13 @@ unsigned long m48t37y_get_time(void)
int m48t37y_set_time(unsigned long sec)
{
struct rtc_time tm;
unsigned long flags;
/* convert to a more useful format -- note months count from 0 */
to_tm(sec, &tm);
tm.tm_mon += 1;
spin_lock_irqsave(&rtc_lock, flags);
/* enable writing */
rtc_base[0x7ff8] = 0x80;
......@@ -187,6 +192,7 @@ int m48t37y_set_time(unsigned long sec)
/* disable writing */
rtc_base[0x7ff8] = 0x00;
spin_unlock_irqrestore(&rtc_lock, flags);
return 0;
}
......
arch/mips/momentum/ocelot_c/setup.c
浏览文件 @ 3f00d3e8
......@@ -140,7 +140,9 @@ unsigned long m48t37y_get_time(void)
unsigned char* rtc_base = (unsigned char*)0xfc800000;
#endif
unsigned int year, month, day, hour, min, sec;
unsigned long flags;
spin_lock_irqsave(&rtc_lock, flags);
/* stop the update */
rtc_base[0x7ff8] = 0x40;
......@@ -157,6 +159,7 @@ unsigned long m48t37y_get_time(void)
/* start the update */
rtc_base[0x7ff8] = 0x00;
spin_unlock_irqrestore(&rtc_lock, flags);
return mktime(year, month, day, hour, min, sec);
}
......@@ -169,11 +172,13 @@ int m48t37y_set_time(unsigned long sec)
unsigned char* rtc_base = (unsigned char*)0xfc800000;
#endif
struct rtc_time tm;
unsigned long flags;
/* convert to a more useful format -- note months count from 0 */
to_tm(sec, &tm);
tm.tm_mon += 1;
spin_lock_irqsave(&rtc_lock, flags);
/* enable writing */
rtc_base[0x7ff8] = 0x80;
......@@ -197,6 +202,7 @@ int m48t37y_set_time(unsigned long sec)
/* disable writing */
rtc_base[0x7ff8] = 0x00;
spin_unlock_irqrestore(&rtc_lock, flags);
return 0;
}
......
arch/mips/pmc-sierra/yosemite/setup.c
浏览文件 @ 3f00d3e8
......@@ -73,7 +73,9 @@ void __init bus_error_init(void)
unsigned long m48t37y_get_time(void)
{
unsigned int year, month, day, hour, min, sec;
unsigned long flags;
spin_lock_irqsave(&rtc_lock, flags);
/* Stop the update to the time */
m48t37_base->control = 0x40;
......@@ -88,6 +90,7 @@ unsigned long m48t37y_get_time(void)
/* Start the update to the time again */
m48t37_base->control = 0x00;
spin_unlock_irqrestore(&rtc_lock, flags);
return mktime(year, month, day, hour, min, sec);
}
......@@ -95,11 +98,13 @@ unsigned long m48t37y_get_time(void)
int m48t37y_set_time(unsigned long sec)
{
struct rtc_time tm;
unsigned long flags;
/* convert to a more useful format -- note months count from 0 */
to_tm(sec, &tm);
tm.tm_mon += 1;
spin_lock_irqsave(&rtc_lock, flags);
/* enable writing */
m48t37_base->control = 0x80;
......@@ -123,6 +128,7 @@ int m48t37y_set_time(unsigned long sec)
/* disable writing */
m48t37_base->control = 0x00;
spin_unlock_irqrestore(&rtc_lock, flags);
return 0;
}
......
arch/mips/sgi-ip22/ip22-time.c
浏览文件 @ 3f00d3e8
......@@ -35,7 +35,9 @@ static unsigned long indy_rtc_get_time(void)
{
unsigned int yrs, mon, day, hrs, min, sec;
unsigned int save_control;
unsigned long flags;
spin_lock_irqsave(&rtc_lock, flags);
save_control = hpc3c0->rtcregs[RTC_CMD] & 0xff;
hpc3c0->rtcregs[RTC_CMD] = save_control | RTC_TE;
......@@ -47,6 +49,7 @@ static unsigned long indy_rtc_get_time(void)
yrs = BCD2BIN(hpc3c0->rtcregs[RTC_YEAR] & 0xff);
hpc3c0->rtcregs[RTC_CMD] = save_control;
spin_unlock_irqrestore(&rtc_lock, flags);
if (yrs < 45)
yrs += 30;
......@@ -60,6 +63,7 @@ static int indy_rtc_set_time(unsigned long tim)
{
struct rtc_time tm;
unsigned int save_control;
unsigned long flags;
to_tm(tim, &tm);
......@@ -68,6 +72,7 @@ static int indy_rtc_set_time(unsigned long tim)
if (tm.tm_year >= 100)
tm.tm_year -= 100;
spin_lock_irqsave(&rtc_lock, flags);
save_control = hpc3c0->rtcregs[RTC_CMD] & 0xff;
hpc3c0->rtcregs[RTC_CMD] = save_control | RTC_TE;
......@@ -80,6 +85,7 @@ static int indy_rtc_set_time(unsigned long tim)
hpc3c0->rtcregs[RTC_HUNDREDTH_SECOND] = 0;
hpc3c0->rtcregs[RTC_CMD] = save_control;
spin_unlock_irqrestore(&rtc_lock, flags);
return 0;
}
......
arch/mips/sibyte/swarm/rtc_m41t81.c
浏览文件 @ 3f00d3e8
......@@ -144,6 +144,7 @@ static int m41t81_write(uint8_t addr, int b)
int m41t81_set_time(unsigned long t)
{
struct rtc_time tm;
unsigned long flags;
to_tm(t, &tm);
......@@ -153,6 +154,7 @@ int m41t81_set_time(unsigned long t)
* believe we should finish writing min within a second.
*/
spin_lock_irqsave(&rtc_lock, flags);
tm.tm_sec = BIN2BCD(tm.tm_sec);
m41t81_write(M41T81REG_SC, tm.tm_sec);
......@@ -180,6 +182,7 @@ int m41t81_set_time(unsigned long t)
tm.tm_year %= 100;
tm.tm_year = BIN2BCD(tm.tm_year);
m41t81_write(M41T81REG_YR, tm.tm_year);
spin_unlock_irqrestore(&rtc_lock, flags);
return 0;
}
......@@ -187,19 +190,23 @@ int m41t81_set_time(unsigned long t)
unsigned long m41t81_get_time(void)
{
unsigned int year, mon, day, hour, min, sec;
unsigned long flags;
/*
* min is valid if two reads of sec are the same.
*/
for (;;) {
spin_lock_irqsave(&rtc_lock, flags);
sec = m41t81_read(M41T81REG_SC);
min = m41t81_read(M41T81REG_MN);
if (sec == m41t81_read(M41T81REG_SC)) break;
spin_unlock_irqrestore(&rtc_lock, flags);
}
hour = m41t81_read(M41T81REG_HR) & 0x3f;
day = m41t81_read(M41T81REG_DT);
mon = m41t81_read(M41T81REG_MO);
year = m41t81_read(M41T81REG_YR);
spin_unlock_irqrestore(&rtc_lock, flags);
sec = BCD2BIN(sec);
min = BCD2BIN(min);
......
arch/mips/sibyte/swarm/rtc_xicor1241.c
浏览文件 @ 3f00d3e8
......@@ -113,9 +113,11 @@ int xicor_set_time(unsigned long t)
{
struct rtc_time tm;
int tmp;
unsigned long flags;
to_tm(t, &tm);
spin_lock_irqsave(&rtc_lock, flags);
/* unlock writes to the CCR */
xicor_write(X1241REG_SR, X1241REG_SR_WEL);
xicor_write(X1241REG_SR, X1241REG_SR_WEL | X1241REG_SR_RWEL);
......@@ -160,6 +162,7 @@ int xicor_set_time(unsigned long t)
xicor_write(X1241REG_HR, tmp);
xicor_write(X1241REG_SR, 0);
spin_unlock_irqrestore(&rtc_lock, flags);
return 0;
}
......@@ -167,7 +170,9 @@ int xicor_set_time(unsigned long t)
unsigned long xicor_get_time(void)
{
unsigned int year, mon, day, hour, min, sec, y2k;
unsigned long flags;
spin_lock_irqsave(&rtc_lock, flags);
sec = xicor_read(X1241REG_SC);
min = xicor_read(X1241REG_MN);
hour = xicor_read(X1241REG_HR);
......@@ -183,6 +188,7 @@ unsigned long xicor_get_time(void)
mon = xicor_read(X1241REG_MO);
year = xicor_read(X1241REG_YR);
y2k = xicor_read(X1241REG_Y2K);
spin_unlock_irqrestore(&rtc_lock, flags);
sec = BCD2BIN(sec);
min = BCD2BIN(min);
......
drivers/media/video/indycam.c
浏览文件 @ 3f00d3e8
......@@ -27,15 +27,15 @@
#include "indycam.h"
//#define INDYCAM_DEBUG
#define INDYCAM_MODULE_VERSION "0.0.3"
#define INDYCAM_MODULE_VERSION "0.0.5"
MODULE_DESCRIPTION("SGI IndyCam driver");
MODULE_VERSION(INDYCAM_MODULE_VERSION);
MODULE_AUTHOR("Mikael Nousiainen <tmnousia@cc.hut.fi>");
MODULE_LICENSE("GPL");
// #define INDYCAM_DEBUG
#ifdef INDYCAM_DEBUG
#define dprintk(x...) printk("IndyCam: " x);
#define indycam_regdump(client) indycam_regdump_debug(client)
......@@ -46,14 +46,14 @@ MODULE_LICENSE("GPL");
struct indycam {
struct i2c_client *client;
int version;
u8 version;
};
static struct i2c_driver i2c_driver_indycam;
static const unsigned char initseq[] = {
static const u8 initseq[] = {
INDYCAM_CONTROL_AGCENA, /* INDYCAM_CONTROL */
INDYCAM_SHUTTER_DEFAULT, /* INDYCAM_SHUTTER */
INDYCAM_SHUTTER_60, /* INDYCAM_SHUTTER */
INDYCAM_GAIN_DEFAULT, /* INDYCAM_GAIN */
0x00, /* INDYCAM_BRIGHTNESS (read-only) */
INDYCAM_RED_BALANCE_DEFAULT, /* INDYCAM_RED_BALANCE */
......@@ -64,12 +64,11 @@ static const unsigned char initseq[] = {
/* IndyCam register handling */
static int indycam_read_reg(struct i2c_client *client, unsigned char reg,
unsigned char *value)
static int indycam_read_reg(struct i2c_client *client, u8 reg, u8 *value)
{
int ret;
if (reg == INDYCAM_RESET) {
if (reg == INDYCAM_REG_RESET) {
dprintk("indycam_read_reg(): "
"skipping write-only register %d\n", reg);
*value = 0;
......@@ -77,24 +76,24 @@ static int indycam_read_reg(struct i2c_client *client, unsigned char reg,
}
ret = i2c_smbus_read_byte_data(client, reg);
if (ret < 0) {
printk(KERN_ERR "IndyCam: indycam_read_reg(): read failed, "
"register = 0x%02x\n", reg);
return ret;
}
*value = (unsigned char)ret;
*value = (u8)ret;
return 0;
}
static int indycam_write_reg(struct i2c_client *client, unsigned char reg,
unsigned char value)
static int indycam_write_reg(struct i2c_client *client, u8 reg, u8 value)
{
int err;
if ((reg == INDYCAM_BRIGHTNESS)
|| (reg == INDYCAM_VERSION)) {
if ((reg == INDYCAM_REG_BRIGHTNESS)
|| (reg == INDYCAM_REG_VERSION)) {
dprintk("indycam_write_reg(): "
"skipping read-only register %d\n", reg);
return 0;
......@@ -102,6 +101,7 @@ static int indycam_write_reg(struct i2c_client *client, unsigned char reg,
dprintk("Writing Reg %d = 0x%02x\n", reg, value);
err = i2c_smbus_write_byte_data(client, reg, value);
if (err) {
printk(KERN_ERR "IndyCam: indycam_write_reg(): write failed, "
"register = 0x%02x, value = 0x%02x\n", reg, value);
......@@ -109,13 +109,12 @@ static int indycam_write_reg(struct i2c_client *client, unsigned char reg,
return err;
}
static int indycam_write_block(struct i2c_client *client, unsigned char reg,
unsigned char length, unsigned char *data)
static int indycam_write_block(struct i2c_client *client, u8 reg,
u8 length, u8 *data)
{
unsigned char i;
int err;
int i, err;
for (i = reg; i < length; i++) {
for (i = 0; i < length; i++) {
err = indycam_write_reg(client, reg + i, data[i]);
if (err)
return err;
......@@ -130,7 +129,7 @@ static int indycam_write_block(struct i2c_client *client, unsigned char reg,
static void indycam_regdump_debug(struct i2c_client *client)
{
int i;
unsigned char val;
u8 val;
for (i = 0; i < 9; i++) {
indycam_read_reg(client, i, &val);
......@@ -139,76 +138,144 @@ static void indycam_regdump_debug(struct i2c_client *client)
}
#endif
static int indycam_get_controls(struct i2c_client *client,
struct indycam_control *ctrl)
static int indycam_get_control(struct i2c_client *client,
struct indycam_control *ctrl)
{
unsigned char ctrl_reg;
indycam_read_reg(client, INDYCAM_CONTROL, &ctrl_reg);
ctrl->agc = (ctrl_reg & INDYCAM_CONTROL_AGCENA)
? INDYCAM_VALUE_ENABLED
: INDYCAM_VALUE_DISABLED;
ctrl->awb = (ctrl_reg & INDYCAM_CONTROL_AWBCTL)
? INDYCAM_VALUE_ENABLED
: INDYCAM_VALUE_DISABLED;
indycam_read_reg(client, INDYCAM_SHUTTER,
(unsigned char *)&ctrl->shutter);
indycam_read_reg(client, INDYCAM_GAIN,
(unsigned char *)&ctrl->gain);
indycam_read_reg(client, INDYCAM_RED_BALANCE,
(unsigned char *)&ctrl->red_balance);
indycam_read_reg(client, INDYCAM_BLUE_BALANCE,
(unsigned char *)&ctrl->blue_balance);
indycam_read_reg(client, INDYCAM_RED_SATURATION,
(unsigned char *)&ctrl->red_saturation);
indycam_read_reg(client, INDYCAM_BLUE_SATURATION,
(unsigned char *)&ctrl->blue_saturation);
indycam_read_reg(client, INDYCAM_GAMMA,
(unsigned char *)&ctrl->gamma);
struct indycam *camera = i2c_get_clientdata(client);
u8 reg;
int ret = 0;
switch (ctrl->type) {
case INDYCAM_CONTROL_AGC:
case INDYCAM_CONTROL_AWB:
ret = indycam_read_reg(client, INDYCAM_REG_CONTROL, &reg);
if (ret)
return -EIO;
if (ctrl->type == INDYCAM_CONTROL_AGC)
ctrl->value = (reg & INDYCAM_CONTROL_AGCENA)
? 1 : 0;
else
ctrl->value = (reg & INDYCAM_CONTROL_AWBCTL)
? 1 : 0;
break;
case INDYCAM_CONTROL_SHUTTER:
ret = indycam_read_reg(client, INDYCAM_REG_SHUTTER, &reg);
if (ret)
return -EIO;
ctrl->value = ((s32)reg == 0x00) ? 0xff : ((s32)reg - 1);
break;
case INDYCAM_CONTROL_GAIN:
ret = indycam_read_reg(client, INDYCAM_REG_GAIN, &reg);
if (ret)
return -EIO;
ctrl->value = (s32)reg;
break;
case INDYCAM_CONTROL_RED_BALANCE:
ret = indycam_read_reg(client, INDYCAM_REG_RED_BALANCE, &reg);
if (ret)
return -EIO;
ctrl->value = (s32)reg;
break;
case INDYCAM_CONTROL_BLUE_BALANCE:
ret = indycam_read_reg(client, INDYCAM_REG_BLUE_BALANCE, &reg);
if (ret)
return -EIO;
ctrl->value = (s32)reg;
break;
case INDYCAM_CONTROL_RED_SATURATION:
ret = indycam_read_reg(client,
INDYCAM_REG_RED_SATURATION, &reg);
if (ret)
return -EIO;
ctrl->value = (s32)reg;
break;
case INDYCAM_CONTROL_BLUE_SATURATION:
ret = indycam_read_reg(client,
INDYCAM_REG_BLUE_SATURATION, &reg);
if (ret)
return -EIO;
ctrl->value = (s32)reg;
break;
case INDYCAM_CONTROL_GAMMA:
if (camera->version == CAMERA_VERSION_MOOSE) {
ret = indycam_read_reg(client,
INDYCAM_REG_GAMMA, &reg);
if (ret)
return -EIO;
ctrl->value = (s32)reg;
} else {
ctrl->value = INDYCAM_GAMMA_DEFAULT;
}
break;
default:
ret = -EINVAL;
}
return 0;
return ret;
}
static int indycam_set_controls(struct i2c_client *client,
struct indycam_control *ctrl)
static int indycam_set_control(struct i2c_client *client,
struct indycam_control *ctrl)
{
unsigned char ctrl_reg;
struct indycam *camera = i2c_get_clientdata(client);
u8 reg;
int ret = 0;
switch (ctrl->type) {
case INDYCAM_CONTROL_AGC:
case INDYCAM_CONTROL_AWB:
ret = indycam_read_reg(client, INDYCAM_REG_CONTROL, &reg);
if (ret)
break;
indycam_read_reg(client, INDYCAM_CONTROL, &ctrl_reg);
if (ctrl->agc != INDYCAM_VALUE_UNCHANGED) {
if (ctrl->agc)
ctrl_reg |= INDYCAM_CONTROL_AGCENA;
else
ctrl_reg &= ~INDYCAM_CONTROL_AGCENA;
}
if (ctrl->awb != INDYCAM_VALUE_UNCHANGED) {
if (ctrl->awb)
ctrl_reg |= INDYCAM_CONTROL_AWBCTL;
else
ctrl_reg &= ~INDYCAM_CONTROL_AWBCTL;
if (ctrl->type == INDYCAM_CONTROL_AGC) {
if (ctrl->value)
reg |= INDYCAM_CONTROL_AGCENA;
else
reg &= ~INDYCAM_CONTROL_AGCENA;
} else {
if (ctrl->value)
reg |= INDYCAM_CONTROL_AWBCTL;
else
reg &= ~INDYCAM_CONTROL_AWBCTL;
}
ret = indycam_write_reg(client, INDYCAM_REG_CONTROL, reg);
break;
case INDYCAM_CONTROL_SHUTTER:
reg = (ctrl->value == 0xff) ? 0x00 : (ctrl->value + 1);
ret = indycam_write_reg(client, INDYCAM_REG_SHUTTER, reg);
break;
case INDYCAM_CONTROL_GAIN:
ret = indycam_write_reg(client, INDYCAM_REG_GAIN, ctrl->value);
break;
case INDYCAM_CONTROL_RED_BALANCE:
ret = indycam_write_reg(client, INDYCAM_REG_RED_BALANCE,
ctrl->value);
break;
case INDYCAM_CONTROL_BLUE_BALANCE:
ret = indycam_write_reg(client, INDYCAM_REG_BLUE_BALANCE,
ctrl->value);
break;
case INDYCAM_CONTROL_RED_SATURATION:
ret = indycam_write_reg(client, INDYCAM_REG_RED_SATURATION,
ctrl->value);
break;
case INDYCAM_CONTROL_BLUE_SATURATION:
ret = indycam_write_reg(client, INDYCAM_REG_BLUE_SATURATION,
ctrl->value);
break;
case INDYCAM_CONTROL_GAMMA:
if (camera->version == CAMERA_VERSION_MOOSE) {
ret = indycam_write_reg(client, INDYCAM_REG_GAMMA,
ctrl->value);
}
break;
default:
ret = -EINVAL;
}
indycam_write_reg(client, INDYCAM_CONTROL, ctrl_reg);
if (ctrl->shutter >= 0)
indycam_write_reg(client, INDYCAM_SHUTTER, ctrl->shutter);
if (ctrl->gain >= 0)
indycam_write_reg(client, INDYCAM_GAIN, ctrl->gain);
if (ctrl->red_balance >= 0)
indycam_write_reg(client, INDYCAM_RED_BALANCE,
ctrl->red_balance);
if (ctrl->blue_balance >= 0)
indycam_write_reg(client, INDYCAM_BLUE_BALANCE,
ctrl->blue_balance);
if (ctrl->red_saturation >= 0)
indycam_write_reg(client, INDYCAM_RED_SATURATION,
ctrl->red_saturation);
if (ctrl->blue_saturation >= 0)
indycam_write_reg(client, INDYCAM_BLUE_SATURATION,
ctrl->blue_saturation);
if (ctrl->gamma >= 0)
indycam_write_reg(client, INDYCAM_GAMMA, ctrl->gamma);
return 0;
return ret;
}
/* I2C-interface */
......@@ -247,7 +314,8 @@ static int indycam_attach(struct i2c_adapter *adap, int addr, int kind)
if (err)
goto out_free_camera;
camera->version = i2c_smbus_read_byte_data(client, INDYCAM_VERSION);
camera->version = i2c_smbus_read_byte_data(client,
INDYCAM_REG_VERSION);
if (camera->version != CAMERA_VERSION_INDY &&
camera->version != CAMERA_VERSION_MOOSE) {
err = -ENODEV;
......@@ -260,8 +328,7 @@ static int indycam_attach(struct i2c_adapter *adap, int addr, int kind)
indycam_regdump(client);
// initialize
err = indycam_write_block(client, 0, sizeof(initseq),
(unsigned char *)&initseq);
err = indycam_write_block(client, 0, sizeof(initseq), (u8 *)&initseq);
if (err) {
printk(KERN_ERR "IndyCam initalization failed\n");
err = -EIO;
......@@ -271,11 +338,10 @@ static int indycam_attach(struct i2c_adapter *adap, int addr, int kind)
indycam_regdump(client);
// white balance
err = indycam_write_reg(client, INDYCAM_CONTROL,
err = indycam_write_reg(client, INDYCAM_REG_CONTROL,
INDYCAM_CONTROL_AGCENA | INDYCAM_CONTROL_AWBCTL);
if (err) {
printk(KERN_ERR "IndyCam white balance "
"initialization failed\n");
printk(KERN_ERR "IndyCam: White balancing camera failed\n");
err = -EIO;
goto out_detach_client;
}
......@@ -371,13 +437,11 @@ static int indycam_command(struct i2c_client *client, unsigned int cmd,
/* TODO: convert values for indycam_set_controls() */
break;
}
case DECODER_INDYCAM_GET_CONTROLS: {
struct indycam_control *ctrl = arg;
indycam_get_controls(client, ctrl);
case DECODER_INDYCAM_GET_CONTROL: {
return indycam_get_control(client, arg);
}
case DECODER_INDYCAM_SET_CONTROLS: {
struct indycam_control *ctrl = arg;
indycam_set_controls(client, ctrl);
case DECODER_INDYCAM_SET_CONTROL: {
return indycam_set_control(client, arg);
}
default:
return -EINVAL;
......@@ -388,12 +452,12 @@ static int indycam_command(struct i2c_client *client, unsigned int cmd,
static struct i2c_driver i2c_driver_indycam = {
.owner = THIS_MODULE,
.name = "indycam",
.id = I2C_DRIVERID_INDYCAM,
.flags = I2C_DF_NOTIFY,
.name = "indycam",
.id = I2C_DRIVERID_INDYCAM,
.flags = I2C_DF_NOTIFY,
.attach_adapter = indycam_probe,
.detach_client = indycam_detach,
.command = indycam_command,
.detach_client = indycam_detach,
.command = indycam_command,
};
static int __init indycam_init(void)
......
drivers/media/video/indycam.h
浏览文件 @ 3f00d3e8
......@@ -22,21 +22,21 @@
#define INDYCAM_VERSION_MINOR(x) ((x) & 0x0f)
/* Register bus addresses */
#define INDYCAM_CONTROL 0x00
#define INDYCAM_SHUTTER 0x01
#define INDYCAM_GAIN 0x02
#define INDYCAM_BRIGHTNESS 0x03 /* read-only */
#define INDYCAM_RED_BALANCE 0x04
#define INDYCAM_BLUE_BALANCE 0x05
#define INDYCAM_RED_SATURATION 0x06
#define INDYCAM_BLUE_SATURATION 0x07
#define INDYCAM_GAMMA 0x08
#define INDYCAM_VERSION 0x0e /* read-only */
#define INDYCAM_RESET 0x0f /* write-only */
#define INDYCAM_LED 0x46
#define INDYCAM_ORIENTATION 0x47
#define INDYCAM_BUTTON 0x48
#define INDYCAM_REG_CONTROL 0x00
#define INDYCAM_REG_SHUTTER 0x01
#define INDYCAM_REG_GAIN 0x02
#define INDYCAM_REG_BRIGHTNESS 0x03 /* read-only */
#define INDYCAM_REG_RED_BALANCE 0x04
#define INDYCAM_REG_BLUE_BALANCE 0x05
#define INDYCAM_REG_RED_SATURATION 0x06
#define INDYCAM_REG_BLUE_SATURATION 0x07
#define INDYCAM_REG_GAMMA 0x08
#define INDYCAM_REG_VERSION 0x0e /* read-only */
#define INDYCAM_REG_RESET 0x0f /* write-only */
#define INDYCAM_REG_LED 0x46
#define INDYCAM_REG_ORIENTATION 0x47
#define INDYCAM_REG_BUTTON 0x48
/* Field definitions of registers */
#define INDYCAM_CONTROL_AGCENA (1<<0) /* automatic gain control */
......@@ -59,13 +59,14 @@
#define INDYCAM_ORIENTATION_BOTTOM_TO_TOP 0x40
#define INDYCAM_BUTTON_RELEASED 0x10
/* Values for controls */
#define INDYCAM_SHUTTER_MIN 0x00
#define INDYCAM_SHUTTER_MAX 0xff
#define INDYCAM_GAIN_MIN 0x00
#define INDYCAM_GAIN_MAX 0xff
#define INDYCAM_RED_BALANCE_MIN 0x00 /* the effect is the opposite? */
#define INDYCAM_RED_BALANCE_MAX 0xff
#define INDYCAM_BLUE_BALANCE_MIN 0x00 /* the effect is the opposite? */
#define INDYCAM_RED_BALANCE_MIN 0x00
#define INDYCAM_RED_BALANCE_MAX 0xff
#define INDYCAM_BLUE_BALANCE_MIN 0x00
#define INDYCAM_BLUE_BALANCE_MAX 0xff
#define INDYCAM_RED_SATURATION_MIN 0x00
#define INDYCAM_RED_SATURATION_MAX 0xff
......@@ -74,34 +75,9 @@
#define INDYCAM_GAMMA_MIN 0x00
#define INDYCAM_GAMMA_MAX 0xff
/* Driver interface definitions */
#define INDYCAM_VALUE_ENABLED 1
#define INDYCAM_VALUE_DISABLED 0
#define INDYCAM_VALUE_UNCHANGED -1
/* When setting controls, a value of -1 leaves the control unchanged. */
struct indycam_control {
int agc; /* boolean */
int awb; /* boolean */
int shutter;
int gain;
int red_balance;
int blue_balance;
int red_saturation;
int blue_saturation;
int gamma;
};
#define DECODER_INDYCAM_GET_CONTROLS _IOR('d', 193, struct indycam_control)
#define DECODER_INDYCAM_SET_CONTROLS _IOW('d', 194, struct indycam_control)
/* Default values for controls */
#define INDYCAM_AGC_DEFAULT INDYCAM_VALUE_ENABLED
#define INDYCAM_AWB_DEFAULT INDYCAM_VALUE_ENABLED
#define INDYCAM_SHUTTER_DEFAULT INDYCAM_SHUTTER_60
#define INDYCAM_AGC_DEFAULT 1
#define INDYCAM_AWB_DEFAULT 0
#define INDYCAM_SHUTTER_DEFAULT 0xff
#define INDYCAM_GAIN_DEFAULT 0x80
#define INDYCAM_RED_BALANCE_DEFAULT 0x18
#define INDYCAM_BLUE_BALANCE_DEFAULT 0xa4
......@@ -109,4 +85,24 @@ struct indycam_control {
#define INDYCAM_BLUE_SATURATION_DEFAULT 0xc0
#define INDYCAM_GAMMA_DEFAULT 0x80
/* Driver interface definitions */
#define INDYCAM_CONTROL_AGC 0 /* boolean */
#define INDYCAM_CONTROL_AWB 1 /* boolean */
#define INDYCAM_CONTROL_SHUTTER 2
#define INDYCAM_CONTROL_GAIN 3
#define INDYCAM_CONTROL_RED_BALANCE 4
#define INDYCAM_CONTROL_BLUE_BALANCE 5
#define INDYCAM_CONTROL_RED_SATURATION 6
#define INDYCAM_CONTROL_BLUE_SATURATION 7
#define INDYCAM_CONTROL_GAMMA 8
struct indycam_control {
u8 type;
s32 value;
};
#define DECODER_INDYCAM_GET_CONTROL _IOR('d', 193, struct indycam_control)
#define DECODER_INDYCAM_SET_CONTROL _IOW('d', 194, struct indycam_control)
#endif
drivers/media/video/saa7191.c
浏览文件 @ 3f00d3e8
......@@ -26,71 +26,95 @@
#include "saa7191.h"
#define SAA7191_MODULE_VERSION "0.0.3"
#define SAA7191_MODULE_VERSION "0.0.5"
MODULE_DESCRIPTION("Philips SAA7191 video decoder driver");
MODULE_VERSION(SAA7191_MODULE_VERSION);
MODULE_AUTHOR("Mikael Nousiainen <tmnousia@cc.hut.fi>");
MODULE_LICENSE("GPL");
// #define SAA7191_DEBUG
#ifdef SAA7191_DEBUG
#define dprintk(x...) printk("SAA7191: " x);
#else
#define dprintk(x...)
#endif
#define SAA7191_SYNC_COUNT 30
#define SAA7191_SYNC_DELAY 100 /* milliseconds */
struct saa7191 {
struct i2c_client *client;
/* the register values are stored here as the actual
* I2C-registers are write-only */
unsigned char reg[25];
u8 reg[25];
unsigned char norm;
unsigned char input;
int input;
int norm;
};
static struct i2c_driver i2c_driver_saa7191;
static const unsigned char initseq[] = {
static const u8 initseq[] = {
0, /* Subaddress */
0x50, /* SAA7191_REG_IDEL */
0x30, /* SAA7191_REG_HSYB */
0x00, /* SAA7191_REG_HSYS */
0xe8, /* SAA7191_REG_HCLB */
0xb6, /* SAA7191_REG_HCLS */
0xf4, /* SAA7191_REG_HPHI */
0x01, /* SAA7191_REG_LUMA - chrominance trap active (CVBS) */
0x00, /* SAA7191_REG_HUEC */
0xf8, /* SAA7191_REG_CKTQ */
0xf8, /* SAA7191_REG_CKTS */
0x90, /* SAA7191_REG_PLSE */
0x90, /* SAA7191_REG_SESE */
0x00, /* SAA7191_REG_GAIN */
0x0c, /* SAA7191_REG_STDC - not SECAM, slow time constant */
0x78, /* SAA7191_REG_IOCK - chrominance from CVBS, GPSW1 & 2 off */
0x99, /* SAA7191_REG_CTL3 - automatic field detection */
0x00, /* SAA7191_REG_CTL4 */
0x2c, /* SAA7191_REG_CHCV */
0x50, /* (0x50) SAA7191_REG_IDEL */
/* 50 Hz signal timing */
0x30, /* (0x30) SAA7191_REG_HSYB */
0x00, /* (0x00) SAA7191_REG_HSYS */
0xe8, /* (0xe8) SAA7191_REG_HCLB */
0xb6, /* (0xb6) SAA7191_REG_HCLS */
0xf4, /* (0xf4) SAA7191_REG_HPHI */
/* control */
SAA7191_LUMA_APER_1, /* (0x01) SAA7191_REG_LUMA - CVBS mode */
0x00, /* (0x00) SAA7191_REG_HUEC */
0xf8, /* (0xf8) SAA7191_REG_CKTQ */
0xf8, /* (0xf8) SAA7191_REG_CKTS */
0x90, /* (0x90) SAA7191_REG_PLSE */
0x90, /* (0x90) SAA7191_REG_SESE */
0x00, /* (0x00) SAA7191_REG_GAIN */
SAA7191_STDC_NFEN | SAA7191_STDC_HRMV, /* (0x0c) SAA7191_REG_STDC
* - not SECAM,
* slow time constant */
SAA7191_IOCK_OEDC | SAA7191_IOCK_OEHS | SAA7191_IOCK_OEVS
| SAA7191_IOCK_OEDY, /* (0x78) SAA7191_REG_IOCK
* - chroma from CVBS, GPSW1 & 2 off */
SAA7191_CTL3_AUFD | SAA7191_CTL3_SCEN | SAA7191_CTL3_OFTS
| SAA7191_CTL3_YDEL0, /* (0x99) SAA7191_REG_CTL3
* - automatic field detection */
0x00, /* (0x00) SAA7191_REG_CTL4 */
0x2c, /* (0x2c) SAA7191_REG_CHCV - PAL nominal value */
0x00, /* unused */
0x00, /* unused */
0x34, /* SAA7191_REG_HS6B */
0x0a, /* SAA7191_REG_HS6S */
0xf4, /* SAA7191_REG_HC6B */
0xce, /* SAA7191_REG_HC6S */
0xf4, /* SAA7191_REG_HP6I */
/* 60 Hz signal timing */
0x34, /* (0x34) SAA7191_REG_HS6B */
0x0a, /* (0x0a) SAA7191_REG_HS6S */
0xf4, /* (0xf4) SAA7191_REG_HC6B */
0xce, /* (0xce) SAA7191_REG_HC6S */
0xf4, /* (0xf4) SAA7191_REG_HP6I */
};
/* SAA7191 register handling */
static unsigned char saa7191_read_reg(struct i2c_client *client,
unsigned char reg)
static u8 saa7191_read_reg(struct i2c_client *client,
u8 reg)
{
return ((struct saa7191 *)i2c_get_clientdata(client))->reg[reg];
}
static int saa7191_read_status(struct i2c_client *client,
unsigned char *value)
u8 *value)
{
int ret;
ret = i2c_master_recv(client, value, 1);
if (ret < 0) {
printk(KERN_ERR "SAA7191: saa7191_read_status(): read failed");
printk(KERN_ERR "SAA7191: saa7191_read_status(): read failed\n");
return ret;
}
......@@ -98,17 +122,16 @@ static int saa7191_read_status(struct i2c_client *client,
}
static int saa7191_write_reg(struct i2c_client *client, unsigned char reg,
unsigned char value)
static int saa7191_write_reg(struct i2c_client *client, u8 reg,
u8 value)
{
((struct saa7191 *)i2c_get_clientdata(client))->reg[reg] = value;
return i2c_smbus_write_byte_data(client, reg, value);
}
/* the first byte of data must be the first subaddress number (register) */
static int saa7191_write_block(struct i2c_client *client,
unsigned char length, unsigned char *data)
u8 length, u8 *data)
{
int i;
int ret;
......@@ -121,7 +144,7 @@ static int saa7191_write_block(struct i2c_client *client,
ret = i2c_master_send(client, data, length);
if (ret < 0) {
printk(KERN_ERR "SAA7191: saa7191_write_block(): "
"write failed");
"write failed\n");
return ret;
}
......@@ -132,8 +155,9 @@ static int saa7191_write_block(struct i2c_client *client,
static int saa7191_set_input(struct i2c_client *client, int input)
{
unsigned char luma = saa7191_read_reg(client, SAA7191_REG_LUMA);
unsigned char iock = saa7191_read_reg(client, SAA7191_REG_IOCK);
struct saa7191 *decoder = i2c_get_clientdata(client);
u8 luma = saa7191_read_reg(client, SAA7191_REG_LUMA);
u8 iock = saa7191_read_reg(client, SAA7191_REG_IOCK);
int err;
switch (input) {
......@@ -159,32 +183,20 @@ static int saa7191_set_input(struct i2c_client *client, int input)
if (err)
return -EIO;
decoder->input = input;
return 0;
}
static int saa7191_set_norm(struct i2c_client *client, int norm)
{
struct saa7191 *decoder = i2c_get_clientdata(client);
unsigned char stdc = saa7191_read_reg(client, SAA7191_REG_STDC);
unsigned char ctl3 = saa7191_read_reg(client, SAA7191_REG_CTL3);
unsigned char chcv = saa7191_read_reg(client, SAA7191_REG_CHCV);
u8 stdc = saa7191_read_reg(client, SAA7191_REG_STDC);
u8 ctl3 = saa7191_read_reg(client, SAA7191_REG_CTL3);
u8 chcv = saa7191_read_reg(client, SAA7191_REG_CHCV);
int err;
switch(norm) {
case SAA7191_NORM_AUTO: {
unsigned char status;
// does status depend on current norm ?
if (saa7191_read_status(client, &status))
return -EIO;
stdc &= ~SAA7191_STDC_SECS;
ctl3 &= ~SAA7191_CTL3_FSEL;
ctl3 |= SAA7191_CTL3_AUFD;
chcv = (status & SAA7191_STATUS_FIDT)
? SAA7191_CHCV_NTSC : SAA7191_CHCV_PAL;
break;
}
case SAA7191_NORM_PAL:
stdc &= ~SAA7191_STDC_SECS;
ctl3 &= ~(SAA7191_CTL3_AUFD | SAA7191_CTL3_FSEL);
......@@ -217,60 +229,335 @@ static int saa7191_set_norm(struct i2c_client *client, int norm)
decoder->norm = norm;
dprintk("ctl3: %02x stdc: %02x chcv: %02x\n", ctl3,
stdc, chcv);
dprintk("norm: %d\n", norm);
return 0;
}
static int saa7191_get_controls(struct i2c_client *client,
struct saa7191_control *ctrl)
static int saa7191_wait_for_signal(struct i2c_client *client, u8 *status)
{
unsigned char hue = saa7191_read_reg(client, SAA7191_REG_HUEC);
unsigned char stdc = saa7191_read_reg(client, SAA7191_REG_STDC);
int i = 0;
if (hue < 0x80) {
hue += 0x80;
} else {
hue -= 0x80;
dprintk("Checking for signal...\n");
for (i = 0; i < SAA7191_SYNC_COUNT; i++) {
if (saa7191_read_status(client, status))
return -EIO;
if (((*status) & SAA7191_STATUS_HLCK) == 0) {
dprintk("Signal found\n");
return 0;
}
msleep(SAA7191_SYNC_DELAY);
}
ctrl->hue = hue;
ctrl->vtrc = (stdc & SAA7191_STDC_VTRC)
? SAA7191_VALUE_ENABLED : SAA7191_VALUE_DISABLED;
dprintk("No signal\n");
return 0;
return -EBUSY;
}
static int saa7191_set_controls(struct i2c_client *client,
struct saa7191_control *ctrl)
static int saa7191_autodetect_norm_extended(struct i2c_client *client)
{
int err;
u8 stdc = saa7191_read_reg(client, SAA7191_REG_STDC);
u8 ctl3 = saa7191_read_reg(client, SAA7191_REG_CTL3);
u8 status;
int err = 0;
if (ctrl->hue >= 0) {
unsigned char hue = ctrl->hue & 0xff;
if (hue < 0x80) {
hue += 0x80;
} else {
hue -= 0x80;
dprintk("SAA7191 extended signal auto-detection...\n");
stdc &= ~SAA7191_STDC_SECS;
ctl3 &= ~(SAA7191_CTL3_FSEL);
err = saa7191_write_reg(client, SAA7191_REG_STDC, stdc);
if (err) {
err = -EIO;
goto out;
}
err = saa7191_write_reg(client, SAA7191_REG_CTL3, ctl3);
if (err) {
err = -EIO;
goto out;
}
ctl3 |= SAA7191_CTL3_AUFD;
err = saa7191_write_reg(client, SAA7191_REG_CTL3, ctl3);
if (err) {
err = -EIO;
goto out;
}
msleep(SAA7191_SYNC_DELAY);
err = saa7191_wait_for_signal(client, &status);
if (err)
goto out;
if (status & SAA7191_STATUS_FIDT) {
/* 60Hz signal -> NTSC */
dprintk("60Hz signal: NTSC\n");
return saa7191_set_norm(client, SAA7191_NORM_NTSC);
}
/* 50Hz signal */
dprintk("50Hz signal: Trying PAL...\n");
/* try PAL first */
err = saa7191_set_norm(client, SAA7191_NORM_PAL);
if (err)
goto out;
msleep(SAA7191_SYNC_DELAY);
err = saa7191_wait_for_signal(client, &status);
if (err)
goto out;
/* not 50Hz ? */
if (status & SAA7191_STATUS_FIDT) {
dprintk("No 50Hz signal\n");
err = -EAGAIN;
goto out;
}
if (status & SAA7191_STATUS_CODE) {
dprintk("PAL\n");
return 0;
}
dprintk("No color detected with PAL - Trying SECAM...\n");
/* no color detected ? -> try SECAM */
err = saa7191_set_norm(client,
SAA7191_NORM_SECAM);
if (err)
goto out;
msleep(SAA7191_SYNC_DELAY);
err = saa7191_wait_for_signal(client, &status);
if (err)
goto out;
/* not 50Hz ? */
if (status & SAA7191_STATUS_FIDT) {
dprintk("No 50Hz signal\n");
err = -EAGAIN;
goto out;
}
if (status & SAA7191_STATUS_CODE) {
/* Color detected -> SECAM */
dprintk("SECAM\n");
return 0;
}
dprintk("No color detected with SECAM - Going back to PAL.\n");
/* still no color detected ?
* -> set norm back to PAL */
err = saa7191_set_norm(client,
SAA7191_NORM_PAL);
if (err)
goto out;
out:
ctl3 = saa7191_read_reg(client, SAA7191_REG_CTL3);
if (ctl3 & SAA7191_CTL3_AUFD) {
ctl3 &= ~(SAA7191_CTL3_AUFD);
err = saa7191_write_reg(client, SAA7191_REG_CTL3, ctl3);
if (err) {
err = -EIO;
}
err = saa7191_write_reg(client, SAA7191_REG_HUEC, hue);
if (err)
return -EIO;
}
if (ctrl->vtrc >= 0) {
unsigned char stdc =
saa7191_read_reg(client, SAA7191_REG_STDC);
if (ctrl->vtrc) {
stdc |= SAA7191_STDC_VTRC;
} else {
stdc &= ~SAA7191_STDC_VTRC;
return err;
}
static int saa7191_autodetect_norm(struct i2c_client *client)
{
u8 status;
dprintk("SAA7191 signal auto-detection...\n");
dprintk("Reading status...\n");
if (saa7191_read_status(client, &status))
return -EIO;
dprintk("Checking for signal...\n");
/* no signal ? */
if (status & SAA7191_STATUS_HLCK) {
dprintk("No signal\n");
return -EBUSY;
}
dprintk("Signal found\n");
if (status & SAA7191_STATUS_FIDT) {
/* 60hz signal -> NTSC */
dprintk("NTSC\n");
return saa7191_set_norm(client, SAA7191_NORM_NTSC);
} else {
/* 50hz signal -> PAL */
dprintk("PAL\n");
return saa7191_set_norm(client, SAA7191_NORM_PAL);
}
}
static int saa7191_get_control(struct i2c_client *client,
struct saa7191_control *ctrl)
{
u8 reg;
int ret = 0;
switch (ctrl->type) {
case SAA7191_CONTROL_BANDPASS:
case SAA7191_CONTROL_BANDPASS_WEIGHT:
case SAA7191_CONTROL_CORING:
reg = saa7191_read_reg(client, SAA7191_REG_LUMA);
switch (ctrl->type) {
case SAA7191_CONTROL_BANDPASS:
ctrl->value = ((s32)reg & SAA7191_LUMA_BPSS_MASK)
>> SAA7191_LUMA_BPSS_SHIFT;
break;
case SAA7191_CONTROL_BANDPASS_WEIGHT:
ctrl->value = ((s32)reg & SAA7191_LUMA_APER_MASK)
>> SAA7191_LUMA_APER_SHIFT;
break;
case SAA7191_CONTROL_CORING:
ctrl->value = ((s32)reg & SAA7191_LUMA_CORI_MASK)
>> SAA7191_LUMA_CORI_SHIFT;
break;
}
break;
case SAA7191_CONTROL_FORCE_COLOUR:
case SAA7191_CONTROL_CHROMA_GAIN:
reg = saa7191_read_reg(client, SAA7191_REG_GAIN);
if (ctrl->type == SAA7191_CONTROL_FORCE_COLOUR)
ctrl->value = ((s32)reg & SAA7191_GAIN_COLO) ? 1 : 0;
else
ctrl->value = ((s32)reg & SAA7191_GAIN_LFIS_MASK)
>> SAA7191_GAIN_LFIS_SHIFT;
break;
case SAA7191_CONTROL_HUE:
reg = saa7191_read_reg(client, SAA7191_REG_HUEC);
if (reg < 0x80)
reg += 0x80;
else
reg -= 0x80;
ctrl->value = (s32)reg;
break;
case SAA7191_CONTROL_VTRC:
reg = saa7191_read_reg(client, SAA7191_REG_STDC);
ctrl->value = ((s32)reg & SAA7191_STDC_VTRC) ? 1 : 0;
break;
case SAA7191_CONTROL_LUMA_DELAY:
reg = saa7191_read_reg(client, SAA7191_REG_CTL3);
ctrl->value = ((s32)reg & SAA7191_CTL3_YDEL_MASK)
>> SAA7191_CTL3_YDEL_SHIFT;
if (ctrl->value >= 4)
ctrl->value -= 8;
break;
case SAA7191_CONTROL_VNR:
reg = saa7191_read_reg(client, SAA7191_REG_CTL4);
ctrl->value = ((s32)reg & SAA7191_CTL4_VNOI_MASK)
>> SAA7191_CTL4_VNOI_SHIFT;
break;
default:
ret = -EINVAL;
}
err = saa7191_write_reg(client, SAA7191_REG_STDC, stdc);
if (err)
return -EIO;
return ret;
}
static int saa7191_set_control(struct i2c_client *client,
struct saa7191_control *ctrl)
{
u8 reg;
int ret = 0;
switch (ctrl->type) {
case SAA7191_CONTROL_BANDPASS:
case SAA7191_CONTROL_BANDPASS_WEIGHT:
case SAA7191_CONTROL_CORING:
reg = saa7191_read_reg(client, SAA7191_REG_LUMA);
switch (ctrl->type) {
case SAA7191_CONTROL_BANDPASS:
reg &= ~SAA7191_LUMA_BPSS_MASK;
reg |= (ctrl->value << SAA7191_LUMA_BPSS_SHIFT)
& SAA7191_LUMA_BPSS_MASK;
break;
case SAA7191_CONTROL_BANDPASS_WEIGHT:
reg &= ~SAA7191_LUMA_APER_MASK;
reg |= (ctrl->value << SAA7191_LUMA_APER_SHIFT)
& SAA7191_LUMA_APER_MASK;
break;
case SAA7191_CONTROL_CORING:
reg &= ~SAA7191_LUMA_CORI_MASK;
reg |= (ctrl->value << SAA7191_LUMA_CORI_SHIFT)
& SAA7191_LUMA_CORI_MASK;
break;
}
ret = saa7191_write_reg(client, SAA7191_REG_LUMA, reg);
break;
case SAA7191_CONTROL_FORCE_COLOUR:
case SAA7191_CONTROL_CHROMA_GAIN:
reg = saa7191_read_reg(client, SAA7191_REG_GAIN);
if (ctrl->type == SAA7191_CONTROL_FORCE_COLOUR) {
if (ctrl->value)
reg |= SAA7191_GAIN_COLO;
else
reg &= ~SAA7191_GAIN_COLO;
} else {
reg &= ~SAA7191_GAIN_LFIS_MASK;
reg |= (ctrl->value << SAA7191_GAIN_LFIS_SHIFT)
& SAA7191_GAIN_LFIS_MASK;
}
ret = saa7191_write_reg(client, SAA7191_REG_GAIN, reg);
break;
case SAA7191_CONTROL_HUE:
reg = ctrl->value & 0xff;
if (reg < 0x80)
reg += 0x80;
else
reg -= 0x80;
ret = saa7191_write_reg(client, SAA7191_REG_HUEC, reg);
break;
case SAA7191_CONTROL_VTRC:
reg = saa7191_read_reg(client, SAA7191_REG_STDC);
if (ctrl->value)
reg |= SAA7191_STDC_VTRC;
else
reg &= ~SAA7191_STDC_VTRC;
ret = saa7191_write_reg(client, SAA7191_REG_STDC, reg);
break;
case SAA7191_CONTROL_LUMA_DELAY: {
s32 value = ctrl->value;
if (value < 0)
value += 8;
reg = saa7191_read_reg(client, SAA7191_REG_CTL3);
reg &= ~SAA7191_CTL3_YDEL_MASK;
reg |= (value << SAA7191_CTL3_YDEL_SHIFT)
& SAA7191_CTL3_YDEL_MASK;
ret = saa7191_write_reg(client, SAA7191_REG_CTL3, reg);
break;
}
case SAA7191_CONTROL_VNR:
reg = saa7191_read_reg(client, SAA7191_REG_CTL4);
reg &= ~SAA7191_CTL4_VNOI_MASK;
reg |= (ctrl->value << SAA7191_CTL4_VNOI_SHIFT)
& SAA7191_CTL4_VNOI_MASK;
ret = saa7191_write_reg(client, SAA7191_REG_CTL4, reg);
break;
default:
ret = -EINVAL;
}
return 0;
return ret;
}
/* I2C-interface */
......@@ -309,11 +596,7 @@ static int saa7191_attach(struct i2c_adapter *adap, int addr, int kind)
if (err)
goto out_free_decoder;
decoder->input = SAA7191_INPUT_COMPOSITE;
decoder->norm = SAA7191_NORM_AUTO;
err = saa7191_write_block(client, sizeof(initseq),
(unsigned char *)initseq);
err = saa7191_write_block(client, sizeof(initseq), (u8 *)initseq);
if (err) {
printk(KERN_ERR "SAA7191 initialization failed\n");
goto out_detach_client;
......@@ -321,6 +604,14 @@ static int saa7191_attach(struct i2c_adapter *adap, int addr, int kind)
printk(KERN_INFO "SAA7191 initialized\n");
decoder->input = SAA7191_INPUT_COMPOSITE;
decoder->norm = SAA7191_NORM_PAL;
err = saa7191_autodetect_norm(client);
if (err && (err != -EBUSY)) {
printk(KERN_ERR "SAA7191: Signal auto-detection failed\n");
}
return 0;
out_detach_client:
......@@ -368,7 +659,7 @@ static int saa7191_command(struct i2c_client *client, unsigned int cmd,
}
case DECODER_GET_STATUS: {
int *iarg = arg;
unsigned char status;
u8 status;
int res = 0;
if (saa7191_read_status(client, &status)) {
......@@ -404,7 +695,7 @@ static int saa7191_command(struct i2c_client *client, unsigned int cmd,
switch (*iarg) {
case VIDEO_MODE_AUTO:
return saa7191_set_norm(client, SAA7191_NORM_AUTO);
return saa7191_autodetect_norm(client);
case VIDEO_MODE_PAL:
return saa7191_set_norm(client, SAA7191_NORM_PAL);
case VIDEO_MODE_NTSC:
......@@ -446,38 +737,48 @@ static int saa7191_command(struct i2c_client *client, unsigned int cmd,
int err;
val = (pic->hue >> 8) - 0x80;
err = saa7191_write_reg(client, SAA7191_REG_HUEC, val);
if (err)
return -EIO;
break;
}
case DECODER_SAA7191_GET_STATUS: {
struct saa7191_status *status = arg;
unsigned char status_reg;
u8 status_reg;
if (saa7191_read_status(client, &status_reg))
return -EIO;
status->signal = ((status_reg & SAA7191_STATUS_HLCK) == 0)
? SAA7191_VALUE_ENABLED : SAA7191_VALUE_DISABLED;
status->ntsc = (status_reg & SAA7191_STATUS_FIDT)
? SAA7191_VALUE_ENABLED : SAA7191_VALUE_DISABLED;
status->color = (status_reg & SAA7191_STATUS_CODE)
? SAA7191_VALUE_ENABLED : SAA7191_VALUE_DISABLED;
? 1 : 0;
status->signal_60hz = (status_reg & SAA7191_STATUS_FIDT)
? 1 : 0;
status->color = (status_reg & SAA7191_STATUS_CODE) ? 1 : 0;
status->input = decoder->input;
status->norm = decoder->norm;
break;
}
case DECODER_SAA7191_SET_NORM: {
int *norm = arg;
return saa7191_set_norm(client, *norm);
switch (*norm) {
case SAA7191_NORM_AUTO:
return saa7191_autodetect_norm(client);
case SAA7191_NORM_AUTO_EXT:
return saa7191_autodetect_norm_extended(client);
default:
return saa7191_set_norm(client, *norm);
}
}
case DECODER_SAA7191_GET_CONTROLS: {
struct saa7191_control *ctrl = arg;
return saa7191_get_controls(client, ctrl);
case DECODER_SAA7191_GET_CONTROL: {
return saa7191_get_control(client, arg);
}
case DECODER_SAA7191_SET_CONTROLS: {
struct saa7191_control *ctrl = arg;
return saa7191_set_controls(client, ctrl);
case DECODER_SAA7191_SET_CONTROL: {
return saa7191_set_control(client, arg);
}
default:
return -EINVAL;
......@@ -488,12 +789,12 @@ static int saa7191_command(struct i2c_client *client, unsigned int cmd,
static struct i2c_driver i2c_driver_saa7191 = {
.owner = THIS_MODULE,
.name = "saa7191",
.id = I2C_DRIVERID_SAA7191,
.flags = I2C_DF_NOTIFY,
.name = "saa7191",
.id = I2C_DRIVERID_SAA7191,
.flags = I2C_DF_NOTIFY,
.attach_adapter = saa7191_probe,
.detach_client = saa7191_detach,
.command = saa7191_command
.detach_client = saa7191_detach,
.command = saa7191_command
};
static int saa7191_init(void)
......
drivers/media/video/saa7191.h
浏览文件 @ 3f00d3e8
......@@ -24,8 +24,8 @@
#define SAA7191_REG_HPHI 0x05
#define SAA7191_REG_LUMA 0x06
#define SAA7191_REG_HUEC 0x07
#define SAA7191_REG_CKTQ 0x08
#define SAA7191_REG_CKTS 0x09
#define SAA7191_REG_CKTQ 0x08 /* bits 3-7 */
#define SAA7191_REG_CKTS 0x09 /* bits 3-7 */
#define SAA7191_REG_PLSE 0x0a
#define SAA7191_REG_SESE 0x0b
#define SAA7191_REG_GAIN 0x0c
......@@ -43,30 +43,82 @@
/* Status Register definitions */
#define SAA7191_STATUS_CODE 0x01 /* color detected flag */
#define SAA7191_STATUS_FIDT 0x20 /* format type NTSC/PAL */
#define SAA7191_STATUS_HLCK 0x40 /* PLL unlocked/locked */
#define SAA7191_STATUS_FIDT 0x20 /* signal type 50/60 Hz */
#define SAA7191_STATUS_HLCK 0x40 /* PLL unlocked(1)/locked(0) */
#define SAA7191_STATUS_STTC 0x80 /* tv/vtr time constant */
/* Luminance Control Register definitions */
/* input mode select bit:
* 0=CVBS (chrominance trap active), 1=S-Video (trap bypassed) */
#define SAA7191_LUMA_BYPS 0x80
/* Chroma Gain Control Settings Register definitions */
/* 0=automatic colour-killer enabled, 1=forced colour on */
/* pre-filter (only when chrominance trap is active) */
#define SAA7191_LUMA_PREF 0x40
/* aperture bandpass to select different characteristics with maximums
* (bits 4-5) */
#define SAA7191_LUMA_BPSS_MASK 0x30
#define SAA7191_LUMA_BPSS_SHIFT 4
#define SAA7191_LUMA_BPSS_3 0x30
#define SAA7191_LUMA_BPSS_2 0x20
#define SAA7191_LUMA_BPSS_1 0x10
#define SAA7191_LUMA_BPSS_0 0x00
/* coring range for high frequency components according to 8-bit luminance
* (bits 2-3)
* 0=coring off, n= (+-)n LSB */
#define SAA7191_LUMA_CORI_MASK 0x0c
#define SAA7191_LUMA_CORI_SHIFT 2
#define SAA7191_LUMA_CORI_3 0x0c
#define SAA7191_LUMA_CORI_2 0x08
#define SAA7191_LUMA_CORI_1 0x04
#define SAA7191_LUMA_CORI_0 0x00
/* aperture bandpass filter weights high frequency components of luminance
* signal (bits 0-1)
* 0=factor 0, 1=0.25, 2=0.5, 3=1 */
#define SAA7191_LUMA_APER_MASK 0x03
#define SAA7191_LUMA_APER_SHIFT 0
#define SAA7191_LUMA_APER_3 0x03
#define SAA7191_LUMA_APER_2 0x02
#define SAA7191_LUMA_APER_1 0x01
#define SAA7191_LUMA_APER_0 0x00
/* Chrominance Gain Control Settings Register definitions */
/* colour on: 0=automatic colour-killer enabled, 1=forced colour on */
#define SAA7191_GAIN_COLO 0x80
/* chrominance gain control (AGC filter)
* 0=loop filter time constant slow, 1=medium, 2=fast, 3=actual gain */
#define SAA7191_GAIN_LFIS_MASK 0x60
#define SAA7191_GAIN_LFIS_SHIFT 5
#define SAA7191_GAIN_LFIS_3 0x60
#define SAA7191_GAIN_LFIS_2 0x40
#define SAA7191_GAIN_LFIS_1 0x20
#define SAA7191_GAIN_LFIS_0 0x00
/* Standard/Mode Control Register definitions */
/* tv/vtr mode bit: 0=TV mode (slow time constant),
* 1=VTR mode (fast time constant) */
#define SAA7191_STDC_VTRC 0x80
/* SAA7191B-specific functions enable (RTCO, ODD and GPSW0 outputs)
* 0=outputs set to high-impedance (circuit equals SAA7191), 1=enabled */
#define SAA7191_STDC_NFEN 0x08
/* HREF generation: 0=like SAA7191, 1=HREF is 8xLLC2 clocks earlier */
#define SAA7191_STDC_HRMV 0x04
/* general purpose switch 0
* (not used with VINO afaik) */
#define SAA7191_STDC_GPSW0 0x02
/* SECAM mode bit: 0=other standards, 1=SECAM */
#define SAA7191_STDC_SECS 0x01
/* the bit fields above must be or'd with this value */
#define SAA7191_STDC_VALUE 0x0c
/* I/O and Clock Control Register definitions */
/* horizontal clock PLL: 0=PLL closed,
* 1=PLL circuit open and horizontal freq fixed */
#define SAA7191_IOCK_HPLL 0x80
/* colour-difference output enable (outputs UV0-UV7) */
#define SAA7191_IOCK_OEDC 0x40
/* H-sync output enable */
#define SAA7191_IOCK_OEHS 0x20
/* V-sync output enable */
#define SAA7191_IOCK_OEVS 0x10
/* luminance output enable (outputs Y0-Y7) */
#define SAA7191_IOCK_OEDY 0x08
/* S-VHS bit (chrominance from CVBS or from chrominance input):
* 0=controlled by BYPS-bit, 1=from chrominance input */
#define SAA7191_IOCK_CHRS 0x04
......@@ -83,11 +135,40 @@
/* field select: (if AUFD=0)
* 0=50Hz (625 lines), 1=60Hz (525 lines) */
#define SAA7191_CTL3_FSEL 0x40
/* the bit fields above must be or'd with this value */
#define SAA7191_CTL3_VALUE 0x19
/* SECAM cross-colour reduction enable */
#define SAA7191_CTL3_SXCR 0x20
/* sync and clamping pulse enable (HCL and HSY outputs) */
#define SAA7191_CTL3_SCEN 0x10
/* output format: 0=4:1:1, 1=4:2:2 (4:2:2 for VINO) */
#define SAA7191_CTL3_OFTS 0x08
/* luminance delay compensation
* 0=0*2/LLC, 1=+1*2/LLC, 2=+2*2/LLC, 3=+3*2/LLC,
* 4=-4*2/LLC, 5=-3*2/LLC, 6=-2*2/LLC, 7=-1*2/LLC
* step size = 2/LLC = 67.8ns for 50Hz, 81.5ns for 60Hz */
#define SAA7191_CTL3_YDEL_MASK 0x07
#define SAA7191_CTL3_YDEL_SHIFT 0
#define SAA7191_CTL3_YDEL2 0x04
#define SAA7191_CTL3_YDEL1 0x02
#define SAA7191_CTL3_YDEL0 0x01
/* Miscellaneous Control #2 Register definitions */
/* select HREF position
* 0=normal, HREF is matched to YUV output port,
* 1=HREF is matched to CVBS input port */
#define SAA7191_CTL4_HRFS 0x04
/* vertical noise reduction
* 0=normal, 1=searching window, 2=auto-deflection, 3=reduction bypassed */
#define SAA7191_CTL4_VNOI_MASK 0x03
#define SAA7191_CTL4_VNOI_SHIFT 0
#define SAA7191_CTL4_VNOI_3 0x03
#define SAA7191_CTL4_VNOI_2 0x02
#define SAA7191_CTL4_VNOI_1 0x01
#define SAA7191_CTL4_VNOI_0 0x00
/* Chrominance Gain Control Register definitions
* (nominal value for UV CCIR level) */
* - for QAM-modulated input signals, effects output amplitude
* (SECAM gain fixed)
* (nominal values for UV CCIR level) */
#define SAA7191_CHCV_NTSC 0x2c
#define SAA7191_CHCV_PAL 0x59
......@@ -99,16 +180,13 @@
#define SAA7191_NORM_PAL 1
#define SAA7191_NORM_NTSC 2
#define SAA7191_NORM_SECAM 3
#define SAA7191_VALUE_ENABLED 1
#define SAA7191_VALUE_DISABLED 0
#define SAA7191_VALUE_UNCHANGED -1
#define SAA7191_NORM_AUTO_EXT 4 /* extended auto-detection */
struct saa7191_status {
/* 0=no signal, 1=signal active*/
/* 0=no signal, 1=signal detected */
int signal;
/* 0=50hz (pal) signal, 1=60hz (ntsc) signal */
int ntsc;
int signal_60hz;
/* 0=no color detected, 1=color detected */
int color;
......@@ -118,22 +196,60 @@ struct saa7191_status {
int norm;
};
#define SAA7191_HUE_MIN 0x00
#define SAA7191_HUE_MAX 0xff
#define SAA7191_HUE_DEFAULT 0x80
#define SAA7191_BANDPASS_MIN 0x00
#define SAA7191_BANDPASS_MAX 0x03
#define SAA7191_BANDPASS_DEFAULT 0x00
#define SAA7191_BANDPASS_WEIGHT_MIN 0x00
#define SAA7191_BANDPASS_WEIGHT_MAX 0x03
#define SAA7191_BANDPASS_WEIGHT_DEFAULT 0x01
#define SAA7191_CORING_MIN 0x00
#define SAA7191_CORING_MAX 0x03
#define SAA7191_CORING_DEFAULT 0x00
#define SAA7191_HUE_MIN 0x00
#define SAA7191_HUE_MAX 0xff
#define SAA7191_HUE_DEFAULT 0x80
#define SAA7191_VTRC_MIN 0x00
#define SAA7191_VTRC_MAX 0x01
#define SAA7191_VTRC_DEFAULT 0x00
#define SAA7191_FORCE_COLOUR_MIN 0x00
#define SAA7191_FORCE_COLOUR_MAX 0x01
#define SAA7191_FORCE_COLOUR_DEFAULT 0x00
#define SAA7191_CHROMA_GAIN_MIN 0x00
#define SAA7191_CHROMA_GAIN_MAX 0x03
#define SAA7191_CHROMA_GAIN_DEFAULT 0x00
#define SAA7191_LUMA_DELAY_MIN -0x04
#define SAA7191_LUMA_DELAY_MAX 0x03
#define SAA7191_LUMA_DELAY_DEFAULT 0x01
#define SAA7191_VNR_MIN 0x00
#define SAA7191_VNR_MAX 0x03
#define SAA7191_VNR_DEFAULT 0x00
#define SAA7191_VTRC_MIN 0x00
#define SAA7191_VTRC_MAX 0x01
#define SAA7191_VTRC_DEFAULT 0x00
#define SAA7191_CONTROL_BANDPASS 0
#define SAA7191_CONTROL_BANDPASS_WEIGHT 1
#define SAA7191_CONTROL_CORING 2
#define SAA7191_CONTROL_FORCE_COLOUR 3 /* boolean */
#define SAA7191_CONTROL_CHROMA_GAIN 4
#define SAA7191_CONTROL_HUE 5
#define SAA7191_CONTROL_VTRC 6 /* boolean */
#define SAA7191_CONTROL_LUMA_DELAY 7
#define SAA7191_CONTROL_VNR 8
struct saa7191_control {
int hue;
int vtrc;
u8 type;
s32 value;
};
#define DECODER_SAA7191_GET_STATUS _IOR('d', 195, struct saa7191_status)
#define DECODER_SAA7191_SET_NORM _IOW('d', 196, int)
#define DECODER_SAA7191_GET_CONTROLS _IOR('d', 197, struct saa7191_control)
#define DECODER_SAA7191_SET_CONTROLS _IOW('d', 198, struct saa7191_control)
#define DECODER_SAA7191_GET_CONTROL _IOR('d', 197, struct saa7191_control)
#define DECODER_SAA7191_SET_CONTROL _IOW('d', 198, struct saa7191_control)
#endif
drivers/media/video/vino.c
浏览文件 @ 3f00d3e8
此差异已折叠。
include/asm-mips/delay.h
浏览文件 @ 3f00d3e8
......@@ -84,4 +84,13 @@ static inline void __udelay(unsigned long usecs, unsigned long lpj)
#define udelay(usecs) __udelay((usecs),__udelay_val)
/* make sure "usecs *= ..." in udelay do not overflow. */
#if HZ >= 1000
#define MAX_UDELAY_MS 1
#elif HZ <= 200
#define MAX_UDELAY_MS 5
#else
#define MAX_UDELAY_MS (1000 / HZ)
#endif
#endif /* _ASM_DELAY_H */
include/asm-mips/errno.h
浏览文件 @ 3f00d3e8
......@@ -119,10 +119,6 @@
#define EOWNERDEAD 165 /* Owner died */
#define ENOTRECOVERABLE 166 /* State not recoverable */
/* for robust mutexes */
#define EOWNERDEAD 165 /* Owner died */
#define ENOTRECOVERABLE 166 /* State not recoverable */
#define EDQUOT 1133 /* Quota exceeded */
#ifdef __KERNEL__
......
include/asm-mips/ip32/mace.h
浏览文件 @ 3f00d3e8
......@@ -147,6 +147,29 @@ struct mace_audio {
} chan[3];
};
/* register definitions for parallel port DMA */
struct mace_parport {
/* 0 - do nothing, 1 - pulse terminal count to the device after buffer is drained */
#define MACEPAR_CONTEXT_LASTFLAG BIT(63)
/* Should not cross 4K page boundary */
#define MACEPAR_CONTEXT_DATALEN_MASK 0xfff00000000
/* Can be arbitrarily aligned on any byte boundary on output, 64 byte aligned on input */
#define MACEPAR_CONTEXT_BASEADDR_MASK 0xffffffff
volatile u64 context_a;
volatile u64 context_b;
#define MACEPAR_CTLSTAT_DIRECTION BIT(0) /* 0 - mem->device, 1 - device->mem */
#define MACEPAR_CTLSTAT_ENABLE BIT(1) /* 0 - channel frozen, 1 - channel enabled */
#define MACEPAR_CTLSTAT_RESET BIT(2) /* 0 - channel active, 1 - complete channel reset */
#define MACEPAR_CTLSTAT_CTXB_VALID BIT(3)
#define MACEPAR_CTLSTAT_CTXA_VALID BIT(4)
volatile u64 cntlstat; /* Control/Status register */
#define MACEPAR_DIAG_CTXINUSE BIT(1)
#define MACEPAR_DIAG_DMACTIVE BIT(2) /* 1 - Dma engine is enabled and processing something */
#define MACEPAR_DIAG_CTRMASK 0x3ffc /* Counter of bytes left */
volatile u64 diagnostic; /* RO: diagnostic register */
};
/* ISA Control and DMA registers */
struct mace_isactrl {
volatile unsigned long ringbase;
......@@ -199,6 +222,7 @@ struct mace_isactrl {
volatile unsigned long _pad[0x2000/8 - 4];
volatile unsigned long dp_ram[0x400];
struct mace_parport parport;
};
/* Keyboard & Mouse registers
......@@ -277,7 +301,7 @@ struct mace_perif {
*/
/* Parallel port */
struct mace_parallel { /* later... */
struct mace_parallel {
};
struct mace_ecp1284 { /* later... */
......
include/asm-mips/mach-generic/ide.h
浏览文件 @ 3f00d3e8
......@@ -168,8 +168,12 @@ static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count)
/* ide_insw calls insw, not __ide_insw. Why? */
#undef insw
#undef insl
#undef outsw
#undef outsl
#define insw(port, addr, count) __ide_insw(port, addr, count)
#define insl(port, addr, count) __ide_insl(port, addr, count)
#define outsw(port, addr, count) __ide_outsw(port, addr, count)
#define outsl(port, addr, count) __ide_outsl(port, addr, count)
#endif /* __KERNEL__ */
......
include/asm-mips/mc146818-time.h
浏览文件 @ 3f00d3e8
......@@ -33,7 +33,9 @@ static inline int mc146818_set_rtc_mmss(unsigned long nowtime)
int real_seconds, real_minutes, cmos_minutes;
unsigned char save_control, save_freq_select;
int retval = 0;
unsigned long flags;
spin_lock_irqsave(&rtc_lock, flags);
save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */
CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
......@@ -79,14 +81,30 @@ static inline int mc146818_set_rtc_mmss(unsigned long nowtime)
*/
CMOS_WRITE(save_control, RTC_CONTROL);
CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
spin_unlock_irqrestore(&rtc_lock, flags);
return retval;
}
/*
* Returns true if a clock update is in progress
*/
static inline unsigned char rtc_is_updating(void)
{
unsigned char uip;
unsigned long flags;
spin_lock_irqsave(&rtc_lock, flags);
uip = (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP);
spin_unlock_irqrestore(&rtc_lock, flags);
return uip;
}
static inline unsigned long mc146818_get_cmos_time(void)
{
unsigned int year, mon, day, hour, min, sec;
int i;
unsigned long flags;
/*
* The Linux interpretation of the CMOS clock register contents:
......@@ -97,12 +115,13 @@ static inline unsigned long mc146818_get_cmos_time(void)
/* read RTC exactly on falling edge of update flag */
for (i = 0 ; i < 1000000 ; i++) /* may take up to 1 second... */
if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
if (rtc_is_updating())
break;
for (i = 0 ; i < 1000000 ; i++) /* must try at least 2.228 ms */
if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
if (!rtc_is_updating())
break;
spin_lock_irqsave(&rtc_lock, flags);
do { /* Isn't this overkill ? UIP above should guarantee consistency */
sec = CMOS_READ(RTC_SECONDS);
min = CMOS_READ(RTC_MINUTES);
......@@ -120,6 +139,7 @@ static inline unsigned long mc146818_get_cmos_time(void)
BCD_TO_BIN(mon);
BCD_TO_BIN(year);
}
spin_unlock_irqrestore(&rtc_lock, flags);
year = mc146818_decode_year(year);
return mktime(year, mon, day, hour, min, sec);
......
include/asm-mips/module.h
浏览文件 @ 3f00d3e8
......@@ -76,43 +76,43 @@ search_module_dbetables(unsigned long addr)
#endif
#ifdef CONFIG_CPU_MIPS32_R1
#define MODULE_PROC_FAMILY "MIPS32_R1"
#define MODULE_PROC_FAMILY "MIPS32_R1 "
#elif defined CONFIG_CPU_MIPS32_R2
#define MODULE_PROC_FAMILY "MIPS32_R2"
#define MODULE_PROC_FAMILY "MIPS32_R2 "
#elif defined CONFIG_CPU_MIPS64_R1
#define MODULE_PROC_FAMILY "MIPS64_R1"
#define MODULE_PROC_FAMILY "MIPS64_R1 "
#elif defined CONFIG_CPU_MIPS64_R2
#define MODULE_PROC_FAMILY "MIPS64_R2"
#define MODULE_PROC_FAMILY "MIPS64_R2 "
#elif defined CONFIG_CPU_R3000
#define MODULE_PROC_FAMILY "R3000"
#define MODULE_PROC_FAMILY "R3000 "
#elif defined CONFIG_CPU_TX39XX
#define MODULE_PROC_FAMILY "TX39XX"
#define MODULE_PROC_FAMILY "TX39XX "
#elif defined CONFIG_CPU_VR41XX
#define MODULE_PROC_FAMILY "VR41XX"
#define MODULE_PROC_FAMILY "VR41XX "
#elif defined CONFIG_CPU_R4300
#define MODULE_PROC_FAMILY "R4300"
#define MODULE_PROC_FAMILY "R4300 "
#elif defined CONFIG_CPU_R4X00
#define MODULE_PROC_FAMILY "R4X00"
#define MODULE_PROC_FAMILY "R4X00 "
#elif defined CONFIG_CPU_TX49XX
#define MODULE_PROC_FAMILY "TX49XX"
#define MODULE_PROC_FAMILY "TX49XX "
#elif defined CONFIG_CPU_R5000
#define MODULE_PROC_FAMILY "R5000"
#define MODULE_PROC_FAMILY "R5000 "
#elif defined CONFIG_CPU_R5432
#define MODULE_PROC_FAMILY "R5432"
#define MODULE_PROC_FAMILY "R5432 "
#elif defined CONFIG_CPU_R6000
#define MODULE_PROC_FAMILY "R6000"
#define MODULE_PROC_FAMILY "R6000 "
#elif defined CONFIG_CPU_NEVADA
#define MODULE_PROC_FAMILY "NEVADA"
#define MODULE_PROC_FAMILY "NEVADA "
#elif defined CONFIG_CPU_R8000
#define MODULE_PROC_FAMILY "R8000"
#define MODULE_PROC_FAMILY "R8000 "
#elif defined CONFIG_CPU_R10000
#define MODULE_PROC_FAMILY "R10000"
#define MODULE_PROC_FAMILY "R10000 "
#elif defined CONFIG_CPU_RM7000
#define MODULE_PROC_FAMILY "RM7000"
#define MODULE_PROC_FAMILY "RM7000 "
#elif defined CONFIG_CPU_RM9000
#define MODULE_PROC_FAMILY "RM9000"
#define MODULE_PROC_FAMILY "RM9000 "
#elif defined CONFIG_CPU_SB1
#define MODULE_PROC_FAMILY "SB1"
#define MODULE_PROC_FAMILY "SB1 "
#else
#error MODULE_PROC_FAMILY undefined for your processor configuration
#endif
......
include/asm-mips/rtc.h
浏览文件 @ 3f00d3e8
......@@ -14,7 +14,6 @@
#ifdef __KERNEL__
#include <linux/spinlock.h>
#include <linux/rtc.h>
#include <asm/time.h>
......@@ -29,17 +28,13 @@
#define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
#define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */
static DEFINE_SPINLOCK(mips_rtc_lock);
static inline unsigned int get_rtc_time(struct rtc_time *time)
{
unsigned long nowtime;
spin_lock(&mips_rtc_lock);
nowtime = rtc_get_time();
to_tm(nowtime, time);
time->tm_year -= 1900;
spin_unlock(&mips_rtc_lock);
return RTC_24H;
}
......@@ -49,12 +44,10 @@ static inline int set_rtc_time(struct rtc_time *time)
unsigned long nowtime;
int ret;
spin_lock(&mips_rtc_lock);
nowtime = mktime(time->tm_year+1900, time->tm_mon+1,
time->tm_mday, time->tm_hour, time->tm_min,
time->tm_sec);
ret = rtc_set_time(nowtime);
spin_unlock(&mips_rtc_lock);
return ret;
}
......
include/asm-mips/rtlx.h
浏览文件 @ 3f00d3e8
......@@ -16,21 +16,19 @@
#define RTLX_ID (RTLX_xID | RTLX_VERSION)
#define RTLX_CHANNELS 8
enum rtlx_state {
RTLX_STATE_UNUSED = 0,
RTLX_STATE_INITIALISED,
RTLX_STATE_REMOTE_READY,
RTLX_STATE_OPENED
};
#define RTLX_BUFFER_SIZE 1024
/*
* lx_state bits
*/
#define RTLX_STATE_OPENED 1UL
/* each channel supports read and write.
linux (vpe0) reads lx_buffer and writes rt_buffer
SP (vpe1) reads rt_buffer and writes lx_buffer
*/
typedef struct rtlx_channel {
enum rtlx_state rt_state;
enum rtlx_state lx_state;
struct rtlx_channel {
unsigned long lx_state;
int buffer_size;
......@@ -43,14 +41,12 @@ typedef struct rtlx_channel {
void *queues;
} rtlx_channel_t;
};
typedef struct rtlx_info {
struct rtlx_info {
unsigned long id;
enum rtlx_state state;
struct rtlx_channel channel[RTLX_CHANNELS];
};
} rtlx_info_t;
#endif
#endif /* _RTLX_H_ */
include/asm-mips/time.h
浏览文件 @ 3f00d3e8
......@@ -20,6 +20,9 @@
#include <linux/linkage.h>
#include <linux/ptrace.h>
#include <linux/rtc.h>
#include <linux/spinlock.h>
extern spinlock_t rtc_lock;
/*
* RTC ops. By default, they point to no-RTC functions.
......
sound/oss/au1000.c
浏览文件 @ 3f00d3e8
此差异已折叠。
sound/oss/nec_vrc5477.c
浏览文件 @ 3f00d3e8
此差异已折叠。
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