• E
    [MTD] [NOR] Fix cfi_send_gen_cmd handling of x16 devices in x8 mode (v4) · 467622ef
    Eric W. Biederman 提交于
    For "unlock" cycles to 16bit devices in 8bit compatibility mode we need
    to use the byte addresses 0xaaa and 0x555. These effectively match
    the word address 0x555 and 0x2aa, except the latter has its low bit set.
    
    Most chips don't care about the value of the 'A-1' pin in x8 mode,
    but some -- like the ST M29W320D -- do. So we need to be careful to
    set it where appropriate.
    
    cfi_send_gen_cmd is only ever passed addresses where the low byte
    is 0x00, 0x55 or 0xaa. Of those, only addresses ending 0xaa are
    affected by this patch, by masking in the extra low bit when the device
    is known to be in compatibility mode.
    
    [dwmw2: Do it only when (cmd_ofs & 0xff) == 0xaa]
    v4: Fix  stupid typo in cfi_build_cmd_addr that failed to compile
        I'm writing this patch way to late at night.
    v3: Bring all of the work back into cfi_build_cmd_addr
        including calling of map_bankwidth(map) and cfi_interleave(cfi)
        So every caller doesn't need to.
    v2: Only modified the address if we our device_type is larger than our
        bus width.
    
    Cc: stable@kernel.org
    Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
    Signed-off-by: NDavid Woodhouse <David.Woodhouse@intel.com>
    467622ef
cfi.h 13.4 KB