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    MIPS, Perf-events: Use unsigned delta for right shift in event update · ba9786f3
    Deng-Cheng Zhu 提交于
    Leverage the commit for ARM by Will Deacon:
    
    - 446a5a8b
        ARM: 6205/1: perf: ensure counter delta is treated as unsigned
    
        Hardware performance counters on ARM are 32-bits wide but atomic64_t
        variables are used to represent counter data in the hw_perf_event structure.
    
        The armpmu_event_update function right-shifts a signed 64-bit delta variable
        and adds the result to the event count. This can lead to shifting in sign-bits
        if the MSB of the 32-bit counter value is set. This results in perf output
        such as:
    
         Performance counter stats for 'sleep 20':
    
         18446744073460670464  cycles             <-- 0xFFFFFFFFF12A6000
                7783773  instructions             #      0.000 IPC
                    465  context-switches
                    161  page-faults
                1172393  branches
    
           20.154242147  seconds time elapsed
    
        This patch ensures that the delta value is treated as unsigned so that the
        right shift sets the upper bits to zero.
    Acked-by: NWill Deacon <will.deacon@arm.com>
    Acked-by: NDavid Daney <ddaney@caviumnetworks.com>
    Signed-off-by: NDeng-Cheng Zhu <dengcheng.zhu@gmail.com>
    To: a.p.zijlstra@chello.nl
    To: fweisbec@gmail.com
    To: will.deacon@arm.com
    Cc: linux-mips@linux-mips.org
    Cc: linux-kernel@vger.kernel.org
    Cc: wuzhangjin@gmail.com
    Cc: paulus@samba.org
    Cc: mingo@elte.hu
    Cc: acme@redhat.com
    Cc: matt@console-pimps.org
    Cc: sshtylyov@mvista.com
    Patchwork: http://patchwork.linux-mips.org/patch/2015/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
    ba9786f3
perf_event.c 13.9 KB