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由 Josh Boyer 提交于
The PowerPC 440EP, 440GR, 440EPx, and 440GRx chips have an issue that causes the PLB3-to-PLB4 bridge to wait indefinitely for transaction requests that cross the end-of-memory-range boundary. Since the DDR controller only returns the valid portion of a read request, the bridge will prevent other PLB masters from completing their transactions. This implements the recommended workaround for this errata for chips that use older versions of firmware that do not already handle it. The last 4KiB of memory are hidden from the kernel to prevent the problem transactions from occurring. Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com> Acked-by: NStefan Roese <sr@denx.de> Signed-off-by: NJosh Boyer <jwboyer@linux.vnet.ibm.com>
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