riscv: Provide vector crypto implementation of AES-128/256-XTS mode.
To accelerate the performance of the AES-XTS mode, in this patch, we have the specialized multi-block implementation for AES-128-XTS and AES-256-XTS. Signed-off-by: NJerry Shih <jerry.shih@sifive.com> Signed-off-by: NPhoebe Chen <phoebe.chen@sifive.com> Reviewed-by: NTomas Mraz <tomas@openssl.org> Reviewed-by: NPaul Dale <pauli@openssl.org> Reviewed-by: NHugo Landau <hlandau@openssl.org> (Merged from https://github.com/openssl/openssl/pull/21923)
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