Docs: Add PMC ACPI sample for 300-series chipsets

This works around bugs in APTIO V NVRAM implementation on Z390 and above.
Based off multiple third-party contributions with additional debugging
from https://www.hackintosh-forum.de/forum/thread/46154. Also thanks
to @vandroiy2013.

closes acidanthera/bugtracker#397

Changelog.md

@@ -5,6 +5,8 @@ OpenCore Changelog
 - Fixed CPU bus ratio calculation for Nehalem and Westmere
 - Fixed CPU package calculation on MacPro5,1 and similar
 - Improved OpenCore rerun detection for new versions
+- Fixed loading picker on boot failure when it is hidden
+- Added PMC ACPI sample for 300-series chipsets
 
 #### v0.5.4
 - Added Enter key handling in boot menu for quick proceed

Docs/AcpiSamples/SSDT-ALS0.dsl

@@ -34,4 +34,3 @@ DefinitionBlock ("", "SSDT", 2, "ACDT", "ALS0", 0x00000000)
         }
     }
 }
-

Docs/AcpiSamples/SSDT-AWAC.dsl

@@ -23,4 +23,3 @@ DefinitionBlock ("", "SSDT", 2, "ACDT", "AWAC", 0x00000000)
         }
     }
 }
-

Docs/AcpiSamples/SSDT-EC-USBX.dsl

@@ -98,4 +98,3 @@ DefinitionBlock ("", "SSDT", 2, "ACDT", "SsdtEC", 0x00001000)
         }
     }
 }
-

Docs/AcpiSamples/SSDT-PLUG.dsl

@@ -48,4 +48,3 @@ DefinitionBlock ("", "SSDT", 2, "ACDT", "CpuPlug", 0x00003000)
         }
     }
 }
-

Docs/AcpiSamples/SSDT-PMC.dsl

+/*
+ * Intel 300-series PMC support for macOS
+ *
+ * Starting from Z390 chipsets PMC (D31:F2) is only available through MMIO.
+ * Since there is no standard device for PMC in ACPI, Apple introduced its
+ * own naming "APP9876" to access this device from AppleIntelPCHPMC driver.
+ * To avoid confusion we disable this device for all other operating systems,
+ * as they normally use another non-standard device with "PNP0C02" HID and
+ * "PCHRESV" UID.
+ *
+ * On certain implementations, including APTIO V, PMC MMIO mapping is required
+ * for NVRAM access. The reason for this is still quite unclear, as SPI is
+ * located in higher addresses:
+ * 0xFE000000~0xFE00FFFF - PMC MBAR
+ * 0xFE010000~0xFE010FFF - SPI BAR0
+ * 0xFE020000~0xFE035FFF - SerialIo BAR in ACPI mode
+ *
+ * PMC device has nothing to do to LPC bus, but is added to its scope for
+ * faster initialisation. If we add it to PCI0, where it normally exists,
+ * it will start in the end of PCI configuration, which is too late for
+ * NVRAM support.
+ */
+DefinitionBlock ("", "SSDT", 2, "ACDT", "PMCR", 0x00001000)
+{
+    External (_SB_.PCI0.LPCB, DeviceObj)
+
+    Scope (_SB.PCI0.LPCB)
+    {
+        Device (PMCR)
+        {
+            Name (_HID, EisaId ("APP9876"))  // _HID: Hardware ID
+            Method (_STA, 0, NotSerialized)  // _STA: Status
+            {
+                If (_OSI ("Darwin"))
+                {
+                    Return (0x0B)
+                }
+                Else
+                {
+                    Return (Zero)
+                }
+            }
+            Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
+            {
+                Memory32Fixed (ReadWrite,
+                    0xFE000000,         // Address Base
+                    0x00010000,         // Address Length
+                    )
+            })
+        }
+    }
+}

Docs/AcpiSamples/SSDT-RTC0.dsl

@@ -36,4 +36,4 @@ DefinitionBlock ("", "SSDT", 2, "ACDT", "RTC0", 0x00000000)
             }
         }
     }
-}
\ No newline at end of file
+}

Docs/AcpiSamples/SSDT-SBUS-MCHC.dsl

@@ -70,4 +70,3 @@ DefinitionBlock ("", "SSDT", 2, "ACDT", "MCHCSBUS", 0x00000000)
         Return (Zero)
     }
 }
-