提交 98ac7e10 编写于 作者: V vit9696

Docs: Improve XCPM documentation

上级 02602c8a
......@@ -1805,14 +1805,14 @@ blocking.
Normally it is only the value of \texttt{EAX} that needs to be taken care of,
since it represents the full CPUID. The remaining bytes are to be left as zeroes.
Byte order is Little Endian, so for example, \texttt{A9 06 03 00} stands for CPUID
\texttt{0x0306A9} (Ivy Bridge).
Byte order is Little Endian, so for example, \texttt{C3 06 03 00} stands for CPUID
\texttt{0x0306C3} (Haswell).
For XCPM support it is recommended to use the following combinations.
\begin{itemize}
\tightlist
\item Haswell-E (\texttt{0x306F2}) to Haswell (\texttt{0x0306C3}):\\
\item Haswell-E (\texttt{0x0306F2}) to Haswell (\texttt{0x0306C3}):\\
\texttt{Cpuid1Data}: \texttt{C3 06 03 00 00 00 00 00 00 00 00 00 00 00 00 00}\\
\texttt{Cpuid1Mask}: \texttt{FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00}
\item Broadwell-E (\texttt{0x0406F1}) to Broadwell (\texttt{0x0306D4}):\\
......@@ -1820,9 +1820,17 @@ blocking.
\texttt{Cpuid1Mask}: \texttt{FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00}
\end{itemize}
Further explanations can be found at
\href{https://github.com/acidanthera/bugtracker/issues/365}{acidanthera/bugtracker\#365}.
See \texttt{Special NOTES} for Haswell+ low-end.
Keep in mind, that the following configurations are unsupported (at least out of the box):
\begin{itemize}
\tightlist
\item Consumer Ivy Bridge (\texttt{0x0306A9}) as Apple disabled XCPM for Ivy Bridge
and recommends legacy power management for these CPUs. You will need to manually
patch \texttt{\_xcpm\_bootstrap} to force XCPM on these CPUs instead of using this option.
\item Low-end CPUs (e.g. Haswell+ Pentium) as they are not supported properly by macOS.
Legacy hacks for older models can be found in the \texttt{Special NOTES} section of
\href{https://github.com/acidanthera/bugtracker/issues/365}{acidanthera/bugtracker\#365}.
\end{itemize}
\item
\texttt{Cpuid1Mask}\\
......
\documentclass[]{article}
%DIF LATEXDIFF DIFFERENCE FILE
%DIF DEL PreviousConfiguration.tex Mon May 11 17:11:58 2020
%DIF ADD ../Configuration.tex Sat May 30 01:33:51 2020
%DIF ADD ../Configuration.tex Sat May 30 16:52:33 2020
\usepackage{lmodern}
\usepackage{amssymb,amsmath}
......@@ -2015,14 +2015,14 @@ blocking.
Normally it is only the value of \texttt{EAX} that needs to be taken care of,
since it represents the full CPUID. The remaining bytes are to be left as zeroes.
Byte order is Little Endian, so for example, \texttt{A9 06 03 00} stands for CPUID
\texttt{0x0306A9} (Ivy Bridge).
Byte order is Little Endian, so for example, \texttt{\DIFdelbegin \DIFdel{A9 }\DIFdelend \DIFaddbegin \DIFadd{C3 }\DIFaddend 06 03 00} stands for CPUID
\texttt{\DIFdelbegin \DIFdel{0x0306A9}\DIFdelend \DIFaddbegin \DIFadd{0x0306C3}\DIFaddend } (\DIFdelbegin \DIFdel{Ivy Bridge}\DIFdelend \DIFaddbegin \DIFadd{Haswell}\DIFaddend ).
For XCPM support it is recommended to use the following combinations.
\begin{itemize}
\tightlist
\item Haswell-E (\texttt{0x306F2}) to Haswell (\texttt{0x0306C3}):\\
\item Haswell-E (\texttt{\DIFdelbegin \DIFdel{0x306F2}\DIFdelend \DIFaddbegin \DIFadd{0x0306F2}\DIFaddend }) to Haswell (\texttt{0x0306C3}):\\
\texttt{Cpuid1Data}: \texttt{C3 06 03 00 00 00 00 00 00 00 00 00 00 00 00 00}\\
\texttt{Cpuid1Mask}: \texttt{FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00}
\item Broadwell-E (\texttt{0x0406F1}) to Broadwell (\texttt{0x0306D4}):\\
......@@ -2030,9 +2030,23 @@ blocking.
\texttt{Cpuid1Mask}: \texttt{FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00}
\end{itemize}
Further explanations can be found at
\href{https://github.com/acidanthera/bugtracker/issues/365}{acidanthera/bugtracker\#365}.
See \texttt{Special NOTES} for Haswell+ low-end.
\DIFdelbegin \DIFdel{Further explanations can be found at }%DIFDELCMD < \href{https://github.com/acidanthera/bugtracker/issues/365}{acidanthera/bugtracker\#365}%%%
\DIFdel{.
See }\DIFdelend \DIFaddbegin \DIFadd{Keep in mind, that the following configurations are unsupported (at least out of the box):
}
\begin{itemize}
\tightlist
\item \DIFadd{Consumer Ivy Bridge (}\DIFaddend \texttt{\DIFdelbegin \DIFdel{Special NOTES}%DIFDELCMD < \MBLOCKRIGHTBRACE %%%
\DIFdel{for }\DIFdelend \DIFaddbegin \DIFadd{0x0306A9}}\DIFadd{) as Apple disabled XCPM for Ivy Bridge
and recommends legacy power management for these CPUs. You will need to manually
patch }\texttt{\DIFadd{\_xcpm\_bootstrap}} \DIFadd{to force XCPM on these CPUs instead of using this option.
}\item \DIFadd{Low-end CPUs (e.g. }\DIFaddend Haswell+ \DIFdelbegin \DIFdel{low-end.
}\DIFdelend \DIFaddbegin \DIFadd{Pentium) as they are not supported properly by macOS.
Legacy hacks for older models can be found in the }\texttt{\DIFadd{Special NOTES}} \DIFadd{section of
}\href{https://github.com/acidanthera/bugtracker/issues/365}{acidanthera/bugtracker\#365}\DIFadd{.
}\end{itemize}
\DIFaddend
\item
\texttt{Cpuid1Mask}\\
......@@ -2473,10 +2487,11 @@ entry choice will update till next manual reconfiguration.
Designed to be filled with \texttt{plist\ string} entries containing
absolute UEFI paths to customised bootloaders, for example,
\texttt{\textbackslash EFI\textbackslash Microsoft\textbackslash Boot\textbackslash bootmgfw.efi}
for Microsoft bootloader. This allows unusual boot paths to be automaticlly
\texttt{\textbackslash EFI\textbackslash \DIFdelbegin \DIFdel{Microsoft}\DIFdelend \DIFaddbegin \DIFadd{debian}\DIFaddend \textbackslash \DIFdelbegin \DIFdel{Boot\textbackslash bootmgfw}\DIFdelend \DIFaddbegin \DIFadd{grubx64}\DIFaddend .efi}
for \DIFdelbegin \DIFdel{Microsoft }\DIFdelend \DIFaddbegin \DIFadd{Debian }\DIFaddend bootloader. This allows unusual boot paths to be automaticlly
discovered by the boot picker. Designwise they are equivalent to predefined blessed path, such as
\texttt{\textbackslash System\textbackslash Library\textbackslash CoreServices\textbackslash boot.efi},
\texttt{\textbackslash System\textbackslash Library\textbackslash CoreServices\textbackslash boot.efi}
\DIFaddbegin \DIFadd{or }\texttt{\DIFadd{\textbackslash EFI\textbackslash Microsoft\textbackslash Boot\textbackslash bootmgfw.efi}}\DIFaddend ,
but unlike predefined bless paths they have highest priority.
\item
......@@ -5791,11 +5806,15 @@ As the entries are added to the end of }\texttt{\DIFdel{BootOrder}}%DIFAUXCMD
\begin{itemize}
\item MBR (Master Boot Record) installations are legacy and will not be supported.
\item To install Windows, macOS, and OpenCore on the same drive you can specify
\item \DIFdelbegin \DIFdel{To install Windows, macOS, and OpenCore on the same drive you can specify
Windows bootloader path
(\texttt{\textbackslash EFI\textbackslash Microsoft\textbackslash Boot\textbackslash bootmgfw.efi})
in \texttt{BlessOverride} section.
\item All the modifications applied (to ACPI, NVRAM, SMBIOS, etc.) are supposed
(}\texttt{\DIFdel{\textbackslash EFI\textbackslash Microsoft\textbackslash Boot\textbackslash bootmgfw.efi}}%DIFAUXCMD
\DIFdel{)
in }\texttt{\DIFdel{BlessOverride}} %DIFAUXCMD
\DIFdel{section.
}%DIFDELCMD < \item %%%
\item%DIFAUXCMD
\DIFdelend All the modifications applied (to ACPI, NVRAM, SMBIOS, etc.) are supposed
to be operating system agnostic, i.e. apply equally regardless of the OS booted.
This enables Boot Camp software experience on Windows.
\item macOS requires the first partition to be EFI System Partition, and does
......
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