未验证 提交 71bf1be1 编写于 作者: B Bruno-366 提交者: GitHub

add nand2tetris (#6239)

* add nand2tetris

* fix formatting for nand2tetris
上级 4996cb37
......@@ -895,6 +895,7 @@
### Verilog / VHDL / SystemVerilog
* [nand2tetris](https://www.nand2tetris.org) - Shimon Schocken, Noam Nisan (Coursera)
* [SOC Verification Using SystemVerilog](http://verificationexcellence.in/online-courses/soc-verification-using-systemverilog)
* [SystemVerilog - Learn basics of SystemVerilog for Hardware Verification](https://verificationexcellence.teachable.com/p/learn-systemverilog)
* [SystemVerilog based UVM Methodology - Learn to build UVM based Testbenches in SystemVerilog](https://verificationexcellence.teachable.com/p/learn-ovm-uvm)
......
Markdown is supported
0% .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑!
想要评论请 注册