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提交 6a1657dc 编写于 作者: Y yanxiaoyong.yxy 提交者： skylarCai
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riscv adds rv32 cpu.

上级 b90d8982
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Showing with 995 addition and 4 deletion
hardware/arch/riscv/include/rv32_32gpr/k_api.h 0 → 100644
浏览文件 @ 6a1657dc
/*
* Copyright (C) 2015-2017 Alibaba Group Holding Limited
*/
#ifndef K_API_H
#define K_API_H
/** @addtogroup rhino API
* All rhino header files.
*
* @{
*/
#include <stddef.h>
#include <stdint.h>
#include <string.h>
#include <limits.h>
#include "k_config.h"
#include "k_default_config.h"
#include "k_types.h"
#include "k_err.h"
#include "k_sys.h"
#include "k_critical.h"
#include "k_spin_lock.h"
#include "k_list.h"
#if (RHINO_CONFIG_SCHED_CFS > 0)
#include "k_cfs.h"
#endif
#include "k_obj.h"
#include "k_sched.h"
#include "k_task.h"
#include "k_ringbuf.h"
#include "k_queue.h"
#include "k_buf_queue.h"
#include "k_sem.h"
#include "k_task_sem.h"
#include "k_mutex.h"
#include "k_timer.h"
#include "k_time.h"
#include "k_event.h"
#include "k_stats.h"
#if RHINO_CONFIG_MM_DEBUG
#include "k_mm_debug.h"
#endif
#include "k_mm_blk.h"
#include "k_mm_region.h"
#include "k_mm.h"
#include "k_workqueue.h"
#include "k_internal.h"
#include "k_trace.h"
#include "k_soc.h"
#include "k_hook.h"
#include "k_bitmap.h"
#include "port.h"
/** @} */
#endif /* K_API_H */
hardware/arch/riscv/include/rv32_32gpr/k_arch.h 0 → 100644
浏览文件 @ 6a1657dc
/*
* Copyright (C) 2015-2021 Alibaba Group Holding Limited
*/
#ifndef K_ARCH_H
#define K_ARCH_H
#include "riscv_csr.h"
#if __riscv_xlen == 64
#define REGISTER_LEN 8
#define OS_UDF() \
do { \
*(long *)(0xffffffffffffffff) = 1; \
} while (0)
#elif __riscv_xlen == 32
#define REGISTER_LEN 4
#define OS_UDF() \
do { \
*(long *)(0xffffffff) = 1; \
} while (0)
#else
#error Assembler did not define __riscv_xlen
#endif
/* Exception Code */
#define CAUSE_MISALIGNED_FETCH 0x0
#define CAUSE_FETCH_ACCESS 0x1
#define CAUSE_ILLEGAL_INSTRUCTION 0x2
#define CAUSE_BREAKPOINT 0x3
#define CAUSE_MISALIGNED_LOAD 0x4
#define CAUSE_LOAD_ACCESS 0x5
#define CAUSE_MISALIGNED_STORE 0x6
#define CAUSE_STORE_ACCESS 0x7
#define CAUSE_USER_ECALL 0x8
#define CAUSE_HYPERVISOR_ECALL 0x9
#define CAUSE_SUPERVISOR_ECALL 0xa
#define CAUSE_MACHINE_ECALL 0xb
#define CAUSE_FETCH_PAGE_FAULT 0xc
#define CAUSE_LOAD_PAGE_FAULT 0xd
#define CAUSE_STORE_PAGE_FAULT 0xf
#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14
#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15
#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17
#ifndef __ASSEMBLY__
typedef struct {
long X1;
long X2;
long X3;
long X4;
long X5;
long X6;
long X7;
long X8;
long X9;
long X10;
long X11;
long X12;
long X13;
long X14;
long X15;
long X16;
long X17;
long X18;
long X19;
long X20;
long X21;
long X22;
long X23;
long X24;
long X25;
long X26;
long X27;
long X28;
long X29;
long X30;
long X31;
long PC;
long MSTATUS;
#ifdef RISCV_SUPPORT_FPU
long FPU[32];
#endif
} context_t;
#else
/* Define the offset of the register in the task context */
#define BASE_CONTEXT_LEN (33 * REGISTER_LEN)
#define FLOAT_CONTEXT_LEN (32 * REGISTER_LEN)
#define X1_OFFSET 0
#define X2_OFFSET (X1_OFFSET + REGISTER_LEN)
#define X3_OFFSET (X2_OFFSET + REGISTER_LEN)
#define X4_OFFSET (X3_OFFSET + REGISTER_LEN)
#define X5_OFFSET (X4_OFFSET + REGISTER_LEN)
#define X6_OFFSET (X5_OFFSET + REGISTER_LEN)
#define X7_OFFSET (X6_OFFSET + REGISTER_LEN)
#define X8_OFFSET (X7_OFFSET + REGISTER_LEN)
#define X9_OFFSET (X8_OFFSET + REGISTER_LEN)
#define X10_OFFSET (X9_OFFSET + REGISTER_LEN)
#define X11_OFFSET (X10_OFFSET + REGISTER_LEN)
#define X12_OFFSET (X11_OFFSET + REGISTER_LEN)
#define X13_OFFSET (X12_OFFSET + REGISTER_LEN)
#define X14_OFFSET (X13_OFFSET + REGISTER_LEN)
#define X15_OFFSET (X14_OFFSET + REGISTER_LEN)
#define X16_OFFSET (X15_OFFSET + REGISTER_LEN)
#define X17_OFFSET (X16_OFFSET + REGISTER_LEN)
#define X18_OFFSET (X17_OFFSET + REGISTER_LEN)
#define X19_OFFSET (X18_OFFSET + REGISTER_LEN)
#define X20_OFFSET (X19_OFFSET + REGISTER_LEN)
#define X21_OFFSET (X20_OFFSET + REGISTER_LEN)
#define X22_OFFSET (X21_OFFSET + REGISTER_LEN)
#define X23_OFFSET (X22_OFFSET + REGISTER_LEN)
#define X24_OFFSET (X23_OFFSET + REGISTER_LEN)
#define X25_OFFSET (X24_OFFSET + REGISTER_LEN)
#define X26_OFFSET (X25_OFFSET + REGISTER_LEN)
#define X27_OFFSET (X26_OFFSET + REGISTER_LEN)
#define X28_OFFSET (X27_OFFSET + REGISTER_LEN)
#define X29_OFFSET (X28_OFFSET + REGISTER_LEN)
#define X30_OFFSET (X29_OFFSET + REGISTER_LEN)
#define X31_OFFSET (X30_OFFSET + REGISTER_LEN)
#define PC_OFFSET (X31_OFFSET + REGISTER_LEN)
#define MSTATUS_OFFSET (PC_OFFSET + REGISTER_LEN)
#define F0_OFFSET (0)
#define F1_OFFSET (F0_OFFSET + REGISTER_LEN)
#define F2_OFFSET (F1_OFFSET + REGISTER_LEN)
#define F3_OFFSET (F2_OFFSET + REGISTER_LEN)
#define F4_OFFSET (F3_OFFSET + REGISTER_LEN)
#define F5_OFFSET (F4_OFFSET + REGISTER_LEN)
#define F6_OFFSET (F5_OFFSET + REGISTER_LEN)
#define F7_OFFSET (F6_OFFSET + REGISTER_LEN)
#define F8_OFFSET (F7_OFFSET + REGISTER_LEN)
#define F9_OFFSET (F8_OFFSET + REGISTER_LEN)
#define F10_OFFSET (F9_OFFSET + REGISTER_LEN)
#define F11_OFFSET (F10_OFFSET + REGISTER_LEN)
#define F12_OFFSET (F11_OFFSET + REGISTER_LEN)
#define F13_OFFSET (F12_OFFSET + REGISTER_LEN)
#define F14_OFFSET (F13_OFFSET + REGISTER_LEN)
#define F15_OFFSET (F14_OFFSET + REGISTER_LEN)
#define F16_OFFSET (F15_OFFSET + REGISTER_LEN)
#define F17_OFFSET (F16_OFFSET + REGISTER_LEN)
#define F18_OFFSET (F17_OFFSET + REGISTER_LEN)
#define F19_OFFSET (F18_OFFSET + REGISTER_LEN)
#define F20_OFFSET (F19_OFFSET + REGISTER_LEN)
#define F21_OFFSET (F20_OFFSET + REGISTER_LEN)
#define F22_OFFSET (F21_OFFSET + REGISTER_LEN)
#define F23_OFFSET (F22_OFFSET + REGISTER_LEN)
#define F24_OFFSET (F23_OFFSET + REGISTER_LEN)
#define F25_OFFSET (F24_OFFSET + REGISTER_LEN)
#define F26_OFFSET (F25_OFFSET + REGISTER_LEN)
#define F27_OFFSET (F26_OFFSET + REGISTER_LEN)
#define F28_OFFSET (F27_OFFSET + REGISTER_LEN)
#define F29_OFFSET (F28_OFFSET + REGISTER_LEN)
#define F30_OFFSET (F29_OFFSET + REGISTER_LEN)
#define F31_OFFSET (F30_OFFSET + REGISTER_LEN)
#endif
#endif /* K_ARCH_H */
hardware/arch/riscv/include/port.h → hardware/arch/riscv/include/rv32_32gpr/port.h
浏览文件 @ 6a1657dc
......@@ -29,8 +29,8 @@ RHINO_INLINE uint8_t cpu_cur_get(void)
#define CPSR_ALLOC() cpu_cpsr_t cpsr
#define RHINO_CPU_INTRPT_DISABLE() do{cpsr = cpu_intrpt_save();}while(0)
#define RHINO_CPU_INTRPT_ENABLE() do{cpu_intrpt_restore(cpsr);}while(0)
#define RHINO_CPU_INTRPT_DISABLE() do { cpsr = cpu_intrpt_save(); } while (0)
#define RHINO_CPU_INTRPT_ENABLE() do { cpu_intrpt_restore(cpsr); } while (0)
#endif /* PORT_H */
hardware/arch/riscv/include/rv32fd_32gpr/port.h 0 → 100644
浏览文件 @ 6a1657dc
/*
* Copyright (C) 2015-2021 Alibaba Group Holding Limited
*/
#ifndef PORT_H
#define PORT_H
#include <k_types.h>
#include <k_task.h>
#ifdef CONFIG_OS_TRACE
#include <trcTrig.h>
#include <trcUser.h>
#include <trcKernelPort.h>
#endif
cpu_cpsr_t cpu_intrpt_save(void);
void cpu_intrpt_restore(cpu_cpsr_t cpsr);
void cpu_intrpt_switch(void);
void cpu_task_switch(void);
void cpu_first_task_start(void);
void *cpu_task_stack_init(cpu_stack_t *base, size_t size, void *arg, task_entry_t entry);
RHINO_INLINE uint8_t cpu_cur_get(void)
{
return 0;
}
#define CPSR_ALLOC() cpu_cpsr_t cpsr
#define RHINO_CPU_INTRPT_DISABLE() do { cpsr = cpu_intrpt_save(); } while (0)
#define RHINO_CPU_INTRPT_ENABLE() do { cpu_intrpt_restore(cpsr); } while (0)
#endif /* PORT_H */
hardware/arch/riscv/include/rv32fd_32gpr/riscv_csr.h 0 → 100644
浏览文件 @ 6a1657dc
/*
* Copyright (C) 2015-2021 Alibaba Group Holding Limited
*/
#ifndef RISCV_CSR_H
#define RISCV_CSR_H
/* Status register flags */
#define SR_SIE 0x00000002UL /* Supervisor Interrupt Enable */
#define SR_MIE 0x00000008UL /* Machine Interrupt Enable */
#define SR_SPIE 0x00000020UL /* Previous Supervisor IE */
#define SR_MPIE 0x00000080UL /* Previous Machine IE */
#define SR_SPP 0x00000100UL /* Previously Supervisor mode */
#define SR_MPP_U 0x00000000UL /* Previously User mode */
#define SR_MPP_S 0x00000800UL /* Previously Supervisor mode */
#define SR_MPP_M 0x00001800UL /* Previously Machine mode */
#define SR_SUM 0x00040000UL /* Supervisor User Memory Access */
#define SR_FS 0x00006000UL /* Floating-point Status */
#define SR_FS_OFF 0x00000000UL
#define SR_FS_INITIAL 0x00002000UL
#define SR_FS_CLEAN 0x00004000UL
#define SR_FS_DIRTY 0x00006000UL
/* Interrupt-enable Registers */
#define IE_MTIE 0x00000080UL
#define IE_MEIE 0x00000800UL
#endif
hardware/arch/riscv/include/rv64fd_32gpr/k_arch.h 0 → 100644
浏览文件 @ 6a1657dc
/*
* Copyright (C) 2015-2021 Alibaba Group Holding Limited
*/
#ifndef K_ARCH_H
#define K_ARCH_H
#include "riscv_csr.h"
#if __riscv_xlen == 64
#define REGISTER_LEN 8
#define OS_UDF() \
do { \
*(long *)(0xffffffffffffffff) = 1; \
} while (0)
#elif __riscv_xlen == 32
#define REGISTER_LEN 4
#define OS_UDF() \
do { \
*(long *)(0xffffffff) = 1; \
} while (0)
#else
#error Assembler did not define __riscv_xlen
#endif
/* Exception Code */
#define CAUSE_MISALIGNED_FETCH 0x0
#define CAUSE_FETCH_ACCESS 0x1
#define CAUSE_ILLEGAL_INSTRUCTION 0x2
#define CAUSE_BREAKPOINT 0x3
#define CAUSE_MISALIGNED_LOAD 0x4
#define CAUSE_LOAD_ACCESS 0x5
#define CAUSE_MISALIGNED_STORE 0x6
#define CAUSE_STORE_ACCESS 0x7
#define CAUSE_USER_ECALL 0x8
#define CAUSE_HYPERVISOR_ECALL 0x9
#define CAUSE_SUPERVISOR_ECALL 0xa
#define CAUSE_MACHINE_ECALL 0xb
#define CAUSE_FETCH_PAGE_FAULT 0xc
#define CAUSE_LOAD_PAGE_FAULT 0xd
#define CAUSE_STORE_PAGE_FAULT 0xf
#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14
#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15
#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17
#ifndef __ASSEMBLY__
typedef struct {
long X1;
long X4;
long X5;
long X6;
long X7;
long X8;
long X9;
long X10;
long X11;
long X12;
long X13;
long X14;
long X15;
long X16;
long X17;
long X18;
long X19;
long X20;
long X21;
long X22;
long X23;
long X24;
long X25;
long X26;
long X27;
long X28;
long X29;
long X30;
long X31;
long PC;
long MSTATUS;
long FPU[32];
} context_t;
#else
/* Define the offset of the register in the task context */
#define BASE_CONTEXT_LEN (31 * REGISTER_LEN)
#define FLOAT_CONTEXT_LEN (32 * REGISTER_LEN)
#define X1_OFFSET 0
#define X4_OFFSET (X1_OFFSET + REGISTER_LEN)
#define X5_OFFSET (X4_OFFSET + REGISTER_LEN)
#define X6_OFFSET (X5_OFFSET + REGISTER_LEN)
#define X7_OFFSET (X6_OFFSET + REGISTER_LEN)
#define X8_OFFSET (X7_OFFSET + REGISTER_LEN)
#define X9_OFFSET (X8_OFFSET + REGISTER_LEN)
#define X10_OFFSET (X9_OFFSET + REGISTER_LEN)
#define X11_OFFSET (X10_OFFSET + REGISTER_LEN)
#define X12_OFFSET (X11_OFFSET + REGISTER_LEN)
#define X13_OFFSET (X12_OFFSET + REGISTER_LEN)
#define X14_OFFSET (X13_OFFSET + REGISTER_LEN)
#define X15_OFFSET (X14_OFFSET + REGISTER_LEN)
#define X16_OFFSET (X15_OFFSET + REGISTER_LEN)
#define X17_OFFSET (X16_OFFSET + REGISTER_LEN)
#define X18_OFFSET (X17_OFFSET + REGISTER_LEN)
#define X19_OFFSET (X18_OFFSET + REGISTER_LEN)
#define X20_OFFSET (X19_OFFSET + REGISTER_LEN)
#define X21_OFFSET (X20_OFFSET + REGISTER_LEN)
#define X22_OFFSET (X21_OFFSET + REGISTER_LEN)
#define X23_OFFSET (X22_OFFSET + REGISTER_LEN)
#define X24_OFFSET (X23_OFFSET + REGISTER_LEN)
#define X25_OFFSET (X24_OFFSET + REGISTER_LEN)
#define X26_OFFSET (X25_OFFSET + REGISTER_LEN)
#define X27_OFFSET (X26_OFFSET + REGISTER_LEN)
#define X28_OFFSET (X27_OFFSET + REGISTER_LEN)
#define X29_OFFSET (X28_OFFSET + REGISTER_LEN)
#define X30_OFFSET (X29_OFFSET + REGISTER_LEN)
#define X31_OFFSET (X30_OFFSET + REGISTER_LEN)
#define PC_OFFSET (X31_OFFSET + REGISTER_LEN)
#define MSTATUS_OFFSET (PC_OFFSET + REGISTER_LEN)
#define F0_OFFSET (0)
#define F1_OFFSET (F0_OFFSET + REGISTER_LEN)
#define F2_OFFSET (F1_OFFSET + REGISTER_LEN)
#define F3_OFFSET (F2_OFFSET + REGISTER_LEN)
#define F4_OFFSET (F3_OFFSET + REGISTER_LEN)
#define F5_OFFSET (F4_OFFSET + REGISTER_LEN)
#define F6_OFFSET (F5_OFFSET + REGISTER_LEN)
#define F7_OFFSET (F6_OFFSET + REGISTER_LEN)
#define F8_OFFSET (F7_OFFSET + REGISTER_LEN)
#define F9_OFFSET (F8_OFFSET + REGISTER_LEN)
#define F10_OFFSET (F9_OFFSET + REGISTER_LEN)
#define F11_OFFSET (F10_OFFSET + REGISTER_LEN)
#define F12_OFFSET (F11_OFFSET + REGISTER_LEN)
#define F13_OFFSET (F12_OFFSET + REGISTER_LEN)
#define F14_OFFSET (F13_OFFSET + REGISTER_LEN)
#define F15_OFFSET (F14_OFFSET + REGISTER_LEN)
#define F16_OFFSET (F15_OFFSET + REGISTER_LEN)
#define F17_OFFSET (F16_OFFSET + REGISTER_LEN)
#define F18_OFFSET (F17_OFFSET + REGISTER_LEN)
#define F19_OFFSET (F18_OFFSET + REGISTER_LEN)
#define F20_OFFSET (F19_OFFSET + REGISTER_LEN)
#define F21_OFFSET (F20_OFFSET + REGISTER_LEN)
#define F22_OFFSET (F21_OFFSET + REGISTER_LEN)
#define F23_OFFSET (F22_OFFSET + REGISTER_LEN)
#define F24_OFFSET (F23_OFFSET + REGISTER_LEN)
#define F25_OFFSET (F24_OFFSET + REGISTER_LEN)
#define F26_OFFSET (F25_OFFSET + REGISTER_LEN)
#define F27_OFFSET (F26_OFFSET + REGISTER_LEN)
#define F28_OFFSET (F27_OFFSET + REGISTER_LEN)
#define F29_OFFSET (F28_OFFSET + REGISTER_LEN)
#define F30_OFFSET (F29_OFFSET + REGISTER_LEN)
#define F31_OFFSET (F30_OFFSET + REGISTER_LEN)
#endif
#endif /* K_ARCH_H */
hardware/arch/riscv/include/rv64fd_32gpr/k_types.h 0 → 100644
浏览文件 @ 6a1657dc
/*
* Copyright (C) 2015-2021 Alibaba Group Holding Limited
*/
#ifndef K_TYPES_H
#define K_TYPES_H
#include "k_compiler.h"
#if __riscv_xlen == 64
#define RHINO_TASK_STACK_OVF_MAGIC 0xdeadbeafdeadbeafull /* stack overflow magic value */
#define RHINO_INTRPT_STACK_OVF_MAGIC 0xdeadbeafdeadbeafull /* stack overflow magic value */
#define RHINO_MM_FRAG_ALLOCATED 0xabcddcababcddcabull /* 32 bit value, if 64 bit system, you need change it to 64 bit */
#define RHINO_MM_FRAG_FREE 0xfefdecdbfefdecdbull /* 32 bit value, if 64 bit system, you need change it to 64 bit */
#define RHINO_MM_CORRUPT_DYE 0xFEFEFEFEFEFEFEFEULL
#define RHINO_MM_FREE_DYE 0xABABABABABABABABULL
#define AOS_ARCH_LP64 1
typedef uint64_t cpu_stack_t;
typedef uint64_t cpu_cpsr_t;
#elif __riscv_xlen == 32
#define RHINO_TASK_STACK_OVF_MAGIC 0xdeadbeafu /* stack overflow magic value */
#define RHINO_INTRPT_STACK_OVF_MAGIC 0xdeadbeafu /* stack overflow magic value */
#define RHINO_MM_FRAG_ALLOCATED 0xabcddcabu /* 32 bit value, if 64 bit system, you need change it to 64 bit */
#define RHINO_MM_FRAG_FREE 0xfefdecdbu /* 32 bit value, if 64 bit system, you need change it to 64 bit */
#define RHINO_MM_CORRUPT_DYE 0xFEFEFEFEU
#define RHINO_MM_FREE_DYE 0xABABABABU
typedef uint32_t cpu_stack_t;
typedef uint32_t cpu_cpsr_t;
#else
#error Assembler did not define __riscv_xlen
#endif
typedef uint64_t hr_timer_t;
typedef uint64_t lr_timer_t;
#endif /* K_TYPES_H */
hardware/arch/riscv/include/rv64fd_32gpr/port.h 0 → 100644
浏览文件 @ 6a1657dc
/*
* Copyright (C) 2015-2021 Alibaba Group Holding Limited
*/
#ifndef PORT_H
#define PORT_H
#include <k_types.h>
#include <k_task.h>
#ifdef CONFIG_OS_TRACE
#include <trcTrig.h>
#include <trcUser.h>
#include <trcKernelPort.h>
#endif
cpu_cpsr_t cpu_intrpt_save(void);
void cpu_intrpt_restore(cpu_cpsr_t cpsr);
void cpu_intrpt_switch(void);
void cpu_task_switch(void);
void cpu_first_task_start(void);
void *cpu_task_stack_init(cpu_stack_t *base, size_t size, void *arg, task_entry_t entry);
RHINO_INLINE uint8_t cpu_cur_get(void)
{
return 0;
}
#define CPSR_ALLOC() cpu_cpsr_t cpsr
#define RHINO_CPU_INTRPT_DISABLE() do { cpsr = cpu_intrpt_save(); } while (0)
#define RHINO_CPU_INTRPT_ENABLE() do { cpu_intrpt_restore(cpsr); } while (0)
#endif /* PORT_H */
hardware/arch/riscv/include/rv64fd_32gpr/riscv_csr.h 0 → 100644
浏览文件 @ 6a1657dc
/*
* Copyright (C) 2015-2021 Alibaba Group Holding Limited
*/
#ifndef RISCV_CSR_H
#define RISCV_CSR_H
/* Status register flags */
#define SR_SIE 0x00000002UL /* Supervisor Interrupt Enable */
#define SR_MIE 0x00000008UL /* Machine Interrupt Enable */
#define SR_SPIE 0x00000020UL /* Previous Supervisor IE */
#define SR_MPIE 0x00000080UL /* Previous Machine IE */
#define SR_SPP 0x00000100UL /* Previously Supervisor mode */
#define SR_MPP_U 0x00000000UL /* Previously User mode */
#define SR_MPP_S 0x00000800UL /* Previously Supervisor mode */
#define SR_MPP_M 0x00001800UL /* Previously Machine mode */
#define SR_SUM 0x00040000UL /* Supervisor User Memory Access */
#define SR_FS 0x00006000UL /* Floating-point Status */
#define SR_FS_OFF 0x00000000UL
#define SR_FS_INITIAL 0x00002000UL
#define SR_FS_CLEAN 0x00004000UL
#define SR_FS_DIRTY 0x00006000UL
/* Interrupt-enable Registers */
#define IE_MTIE 0x00000080UL
#define IE_MEIE 0x00000800UL
#endif
hardware/arch/riscv/package.yaml
浏览文件 @ 6a1657dc
## 第一部分： 基础信息
name: riscv # <必选项> 包名称 （符合C语言变量命名规则），长度少于等于64字节
version: master # <必选项> 组件版本号
version: dev_aos # <必选项> 组件版本号
description: arch for riscv
type: arch # <必选项> 组件类型，为：solution, chip, board, common, sdk
......@@ -37,7 +37,7 @@ license: Apache license v2.0 # <可选项> 源代码的
# - libs # -Llibs
build_config:
include:
- include
- include/<cpu_num>
- src/<cpu_num>
asmflag: -D__ASSEMBLY__
......
hardware/arch/riscv/src/rv32_32gpr/dispatcher_c.c 0 → 100644
浏览文件 @ 6a1657dc
/*
* Copyright (C) 2015-2021 Alibaba Group Holding Limited
*/
#include <k_api.h>
#include <k_arch.h>
void dispatcher_exception(long arg, long exc_type, context_t *contex)
{
switch (exc_type) {
case CAUSE_MACHINE_ECALL:
/* This is a task scheduling request */
if (arg == 0) {
return;
}
break;
default:
break;
}
return;
}
hardware/arch/riscv/src/rv32_32gpr/dispatcher_s.S 0 → 100644
浏览文件 @ 6a1657dc
#include <k_config.h>
#include <k_arch.h>
/******************************************************************************
@ Declares the function that this file will call
@******************************************************************************/
.extern g_active_task
.extern g_preferred_ready_task
.extern krhino_stack_ovf_check
.extern krhino_task_sched_stats_get
.extern exception_stack_top
.extern dispatcher_exception
.extern dispatcher_interrupt
.global task_restore
.global _interrupt_return_address
.global ht_dispatcher
.global sys_stack_base
.global sys_stack_top
.global exception_stack_base
.global exception_stack_top
/******************************************************************************
@ Exception Vector. mtvec.mode must be set to 0, exceptions and interrupts use
@ the same vector entry
@******************************************************************************/
#define CONFIG_ARCH_INTERRUPTSTACK 4096
.section .bss
.align 3
sys_stack_base:
.space CONFIG_ARCH_INTERRUPTSTACK
sys_stack_top:
exception_stack_base:
.space CONFIG_ARCH_INTERRUPTSTACK
exception_stack_top:
.section .vectors
.align 6
.globl __Vectors
.type __Vectors, @object
__Vectors:
j ht_dispatcher
/******************************************************************************
@ Jump to this function when an exception or interrupt occurs. This function is
@ used to schedule the execution flow of exceptions, interrupts, and tasks.
@ System call 0 is used to trigger task scheduling.
@******************************************************************************/
.text
.align 8
.func
ht_dispatcher:
/* first step: save context */
#ifdef RISCV_SUPPORT_FPU
addi sp, sp, -(FLOAT_CONTEXT_LEN)
fsw f0, (F0_OFFSET)(sp)
fsw f1, (F1_OFFSET)(sp)
fsw f2, (F2_OFFSET)(sp)
fsw f3, (F3_OFFSET)(sp)
fsw f4, (F4_OFFSET)(sp)
fsw f5, (F5_OFFSET)(sp)
fsw f6, (F6_OFFSET)(sp)
fsw f7, (F7_OFFSET)(sp)
fsw f8, (F8_OFFSET)(sp)
fsw f9, (F9_OFFSET)(sp)
fsw f10,(F10_OFFSET)(sp)
fsw f11,(F11_OFFSET)(sp)
fsw f12,(F12_OFFSET)(sp)
fsw f13,(F13_OFFSET)(sp)
fsw f14,(F14_OFFSET)(sp)
fsw f15,(F15_OFFSET)(sp)
fsw f16,(F16_OFFSET)(sp)
fsw f17,(F17_OFFSET)(sp)
fsw f18,(F18_OFFSET)(sp)
fsw f19,(F19_OFFSET)(sp)
fsw f20,(F20_OFFSET)(sp)
fsw f21,(F21_OFFSET)(sp)
fsw f22,(F22_OFFSET)(sp)
fsw f23,(F23_OFFSET)(sp)
fsw f24,(F24_OFFSET)(sp)
fsw f25,(F25_OFFSET)(sp)
fsw f26,(F26_OFFSET)(sp)
fsw f27,(F27_OFFSET)(sp)
fsw f28,(F28_OFFSET)(sp)
fsw f29,(F29_OFFSET)(sp)
fsw f30,(F30_OFFSET)(sp)
fsw f31,(F31_OFFSET)(sp)
#endif
addi sp, sp, -(BASE_CONTEXT_LEN)
sw x1, (X1_OFFSET)(sp)
sw x4, (X4_OFFSET)(sp)
sw x5, (X5_OFFSET)(sp)
sw x6, (X6_OFFSET)(sp)
sw x7, (X7_OFFSET)(sp)
sw x8, (X8_OFFSET)(sp)
sw x9, (X9_OFFSET)(sp)
sw x10, (X10_OFFSET)(sp)
sw x11, (X11_OFFSET)(sp)
sw x12, (X12_OFFSET)(sp)
sw x13, (X13_OFFSET)(sp)
sw x14, (X14_OFFSET)(sp)
sw x15, (X15_OFFSET)(sp)
sw x16, (X16_OFFSET)(sp)
sw x17, (X17_OFFSET)(sp)
sw x18, (X18_OFFSET)(sp)
sw x19, (X19_OFFSET)(sp)
sw x20, (X20_OFFSET)(sp)
sw x21, (X21_OFFSET)(sp)
sw x22, (X22_OFFSET)(sp)
sw x23, (X23_OFFSET)(sp)
sw x24, (X24_OFFSET)(sp)
sw x25, (X25_OFFSET)(sp)
sw x26, (X26_OFFSET)(sp)
sw x27, (X27_OFFSET)(sp)
sw x28, (X28_OFFSET)(sp)
sw x29, (X29_OFFSET)(sp)
sw x30, (X30_OFFSET)(sp)
sw x31, (X31_OFFSET)(sp)
csrr t0, mstatus
sw t0, (MSTATUS_OFFSET)(sp)
/* g_active_task->task_stack = context region */
la a1, g_active_task
lw a1, (a1)
sw sp, (a1)
/* exception or interrupt is determined by the mcause register */
csrr t0, mcause
blt t0, x0, interrupt
/* second step: process exception. ecall 0 is used to trig task sched */
/* Save the exception return address, the lenght of instruction may be 2 or 4 byte*/
/* read the instruction which trigger the exception */
csrr t1, mepc
lb t2, 0(t1)
li t3, 0x3
and t2, t2, t3
bne t2, t3, 1f
addi t1, t1, 0x2
1:
addi t1, t1, 0x2
2:
sw t1, (PC_OFFSET)(sp)
/* use exception statck to process exception */
mv a2, sp
la sp, exception_stack_top
mv a1, t0
la t0, dispatcher_exception
jalr t0
beq x0,x0, task_sched
/* third step: process interrupt */
interrupt:
csrr t1, mepc
sw t1, (PC_OFFSET)(sp)
/* use sys statck to process interrupt */
la sp, sys_stack_top
andi a0, t0, 0x7FF
la t0, dispatcher_interrupt
jalr t0
_interrupt_return_address:
/* forth step: task sched */
task_sched:
#if (RHINO_CONFIG_TASK_STACK_OVF_CHECK > 0)
call krhino_stack_ovf_check
#endif
#if (RHINO_CONFIG_SYS_STATS > 0)
call krhino_task_sched_stats_get
#endif
/* save context: R0 = g_active_task->task_stack = context region */
la a0, g_active_task
la a1, g_preferred_ready_task
lw a2, (a1)
sw a2, (a0)
task_restore:
la a1, g_active_task
lw a1, (a1)
lw sp, (a1)
lw t0, (MSTATUS_OFFSET)(sp)
csrw mstatus, t0
lw t0, (PC_OFFSET)(sp)
csrw mepc, t0
lw x1, (X1_OFFSET)(sp)
lw x4, (X4_OFFSET)(sp)
lw x5, (X5_OFFSET)(sp)
lw x6, (X6_OFFSET)(sp)
lw x7, (X7_OFFSET)(sp)
lw x8, (X8_OFFSET)(sp)
lw x9, (X9_OFFSET)(sp)
lw x10, (X10_OFFSET)(sp)
lw x11, (X11_OFFSET)(sp)
lw x12, (X12_OFFSET)(sp)
lw x13, (X13_OFFSET)(sp)
lw x14, (X14_OFFSET)(sp)
lw x15, (X15_OFFSET)(sp)
lw x16, (X16_OFFSET)(sp)
lw x17, (X17_OFFSET)(sp)
lw x18, (X18_OFFSET)(sp)
lw x19, (X19_OFFSET)(sp)
lw x20, (X20_OFFSET)(sp)
lw x21, (X21_OFFSET)(sp)
lw x22, (X22_OFFSET)(sp)
lw x23, (X23_OFFSET)(sp)
lw x24, (X24_OFFSET)(sp)
lw x25, (X25_OFFSET)(sp)
lw x26, (X26_OFFSET)(sp)
lw x27, (X27_OFFSET)(sp)
lw x28, (X28_OFFSET)(sp)
lw x29, (X29_OFFSET)(sp)
lw x30, (X30_OFFSET)(sp)
lw x31, (X31_OFFSET)(sp)
addi sp, sp, (BASE_CONTEXT_LEN)
#ifdef RISCV_SUPPORT_FPU
flw f0, (F0_OFFSET)(sp)
flw f1, (F1_OFFSET)(sp)
flw f2, (F2_OFFSET)(sp)
flw f3, (F3_OFFSET)(sp)
flw f4, (F4_OFFSET)(sp)
flw f5, (F5_OFFSET)(sp)
flw f6, (F6_OFFSET)(sp)
flw f7, (F7_OFFSET)(sp)
flw f8, (F8_OFFSET)(sp)
flw f9, (F9_OFFSET)(sp)
flw f10,(F10_OFFSET)(sp)
flw f11,(F11_OFFSET)(sp)
flw f12,(F12_OFFSET)(sp)
flw f13,(F13_OFFSET)(sp)
flw f14,(F14_OFFSET)(sp)
flw f15,(F15_OFFSET)(sp)
flw f16,(F16_OFFSET)(sp)
flw f17,(F17_OFFSET)(sp)
flw f18,(F18_OFFSET)(sp)
flw f19,(F19_OFFSET)(sp)
flw f20,(F20_OFFSET)(sp)
flw f21,(F21_OFFSET)(sp)
flw f22,(F22_OFFSET)(sp)
flw f23,(F23_OFFSET)(sp)
flw f24,(F24_OFFSET)(sp)
flw f25,(F25_OFFSET)(sp)
flw f26,(F26_OFFSET)(sp)
flw f27,(F27_OFFSET)(sp)
flw f28,(F28_OFFSET)(sp)
flw f29,(F29_OFFSET)(sp)
flw f30,(F30_OFFSET)(sp)
flw f31,(F31_OFFSET)(sp)
addi sp, sp, (FLOAT_CONTEXT_LEN)
#endif
mret
.endfunc
hardware/arch/riscv/src/rv32_32gpr/irq_dispatcher.c 0 → 100644
浏览文件 @ 6a1657dc
#include <k_arch.h>
#include <k_api.h>
void dispatcher_interrupt(long irq)
{
krhino_intrpt_enter();
/*
add board irq handler, to do...
*/
krhino_intrpt_exit();
}
hardware/arch/riscv/src/rv32_32gpr/port_c.c 0 → 100644
浏览文件 @ 6a1657dc
/*
* Copyright (C) 2016 YunOS Project. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <k_api.h>
#include <k_arch.h>
void *cpu_task_stack_init(cpu_stack_t *stack_base, size_t stack_size,
void *arg, task_entry_t entry)
{
context_t *ctx, *ctx_prev;
register int *gp asm("x3");
ctx_prev = (context_t *)((unsigned long)(stack_base + stack_size) & ~0x0fUL);
ctx = ctx_prev - 1;
ctx->MSTATUS = (cpu_stack_t)SR_FS_INITIAL | SR_MPP_M | SR_MPIE; /* mstatus */
ctx->PC = (cpu_stack_t)entry;
ctx->X31 = (cpu_stack_t)0x31313131L; /* X31 */
ctx->X30 = (cpu_stack_t)0x30303030L; /* X30 */
ctx->X29 = (cpu_stack_t)0x29292929L; /* X29 */
ctx->X28 = (cpu_stack_t)0x28282828L; /* X28 */
ctx->X27 = (cpu_stack_t)0x27272727L; /* X27 */
ctx->X26 = (cpu_stack_t)0x26262626L; /* X26 */
ctx->X25 = (cpu_stack_t)0x25252525L; /* X25 */
ctx->X24 = (cpu_stack_t)0x24242424L; /* X24 */
ctx->X23 = (cpu_stack_t)0x23232323L; /* X23 */
ctx->X22 = (cpu_stack_t)0x22222222L; /* X22 */
ctx->X21 = (cpu_stack_t)0x21212121L; /* X21 */
ctx->X20 = (cpu_stack_t)0x20202020L; /* X20 */
ctx->X19 = (cpu_stack_t)0x19191919L; /* X19 */
ctx->X18 = (cpu_stack_t)0x18181818L; /* X18 */
ctx->X17 = (cpu_stack_t)0x17171717L; /* X17 */
ctx->X16 = (cpu_stack_t)0x16161616L; /* X16 */
ctx->X15 = (uint32_t)0x15151515L; /* X15 */
ctx->X14 = (uint32_t)0x14141414L; /* X14 */
ctx->X13 = (uint32_t)0x13131313L; /* X13 */
ctx->X12 = (uint32_t)0x12121212L; /* X12 */
ctx->X11 = (uint32_t)0x11111111L; /* X11 */
ctx->X10 = (uint32_t)arg; /* X10 */
ctx->X9 = (uint32_t)0x09090909L; /* X9 */
ctx->X8 = (uint32_t)0x08080808L; /* X8 */
ctx->X7 = (uint32_t)0x07070707L; /* X7 */
ctx->X6 = (uint32_t)0x06060606L; /* X6 */
ctx->X5 = (uint32_t)0x05050505L; /* X5 */
ctx->X4 = (uint32_t)0x04040404L; /* X4 */
ctx->X3 = (uint32_t)gp; /* X3 */
ctx->X2 = (uint32_t)ctx_prev; /* X3 */
ctx->X1 = (uint32_t)krhino_task_deathbed; /* X1 */
return (void *)ctx;
}
hardware/arch/riscv/src/rv32_32gpr/port_s.S 0 → 100644
浏览文件 @ 6a1657dc
/*
* Copyright (C) 2016 YunOS Project. All rights reserved.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Enable interrupts when returning from the handler */
#include "k_arch.h"
#define MSTATUS_PRV1 0x1880
/******************************************************************************
* Functions:
* size_t cpu_intrpt_save(void);
* void cpu_intrpt_restore(size_t psr);
******************************************************************************/
.global cpu_intrpt_save
.type cpu_intrpt_save, %function
cpu_intrpt_save:
csrr a0, mstatus
csrc mstatus, 8
ret
.global cpu_intrpt_restore
.type cpu_intrpt_restore, %function
cpu_intrpt_restore:
csrw mstatus, a0
ret
/******************************************************************************
* Functions:
* void cpu_intrpt_switch(void);
* void cpu_task_switch(void);
******************************************************************************/
.global cpu_task_switch
.type cpu_task_switch, %function
cpu_task_switch:
mv a0, x0
ecall
ret
.global cpu_intrpt_switch
.type cpu_intrpt_switch, %function
cpu_intrpt_switch:
ret
/******************************************************************************
* Functions:
* void cpu_first_task_start(void);
******************************************************************************/
.global cpu_first_task_start
.align 8
.func
cpu_first_task_start:
li t0, (IE_MTIE | IE_MEIE)
csrw mie, t0
la t0, task_restore
jr t0
.endfunc
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