Merge pull request #3255 from BernardXiong/bsp_x1000

[BSP] move libcpu/mips/x1000 to bsp/x1000/cpu

bsp/x1000/SConstruct

@@ -28,7 +28,7 @@ Export('RTT_ROOT')
 Export('rtconfig')
 
 # prepare building environment
-objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=True)
 
 if GetDepend('RT_USING_HARD_FLOAT'):
     env['CCFLAGS']   = env['CCFLAGS'].replace('-msoft-float', '-mhard-float')

bsp/x1000/cpu/SConscript

+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+Import('rtconfig')
+
+cwd   = GetCurrentDir()
+group = []
+list  = os.listdir(cwd)
+
+# add common code files
+group = group + SConscript(os.path.join('common', 'SConscript'))
+
+# cpu porting code files
+group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
+
+Return('group')

bsp/x1000/cpu/common/asm.h

+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
+ * Copyright (C) 1999 by Silicon Graphics, Inc.
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ * Copyright (C) 2002  Maciej W. Rozycki
+ *
+ * Some useful macros for MIPS assembler code
+ *
+ * Some of the routines below contain useless nops that will be optimized
+ * away by gas in -O mode. These nops are however required to fill delay
+ * slots in noreorder mode.
+ */
+#ifndef __ASM_H__
+#define __ASM_H__
+
+/*
+ * LEAF - declare leaf routine
+ */
+#define	LEAF(symbol)                        \
+		.globl	symbol;                     \
+		.align	2;                          \
+		.type	symbol,@function;           \
+		.ent	symbol,0;                   \
+symbol:		.frame	sp,0,ra
+
+/*
+ * NESTED - declare nested routine entry point
+ */
+#define	NESTED(symbol, framesize, rpc)      \
+		.globl	symbol;                     \
+		.align	2;                          \
+		.type	symbol,@function;           \
+		.ent	symbol,0;                   \
+symbol:		.frame	sp, framesize, rpc
+
+/*
+ * END - mark end of function
+ */
+#define	END(function)                       \
+		.end	function;		        	\
+		.size	function,.-function
+
+/*
+ * EXPORT - export definition of symbol
+ */
+#define EXPORT(symbol)						\
+		.globl	symbol;                     \
+symbol:
+
+/*
+ * FEXPORT - export definition of a function symbol
+ */
+#define FEXPORT(symbol)						\
+		.globl	symbol;						\
+		.type	symbol,@function;			\
+symbol:
+
+/*
+ * Global data declaration with size.
+ */
+#define EXPORTS(name,sz) 		\
+  	.globl name; 				\
+  	.type name,@object; 		\
+  	.size name,sz; 				\
+name:
+
+/*
+ * Weak data declaration with size.
+ */
+#define WEXPORT(name,sz) 		\
+  	.weakext name; 				\
+  	.type name,@object; 		\
+  	.size name,sz; 				\
+name:
+
+/*
+ * Global data reference with size.
+ */
+#define	IMPORT(name, size) 		\
+	.extern	name,size
+
+/*
+ * Global zeroed data.
+ */
+#define BSS(name,size) 			\
+  	.type name,@object; 		\
+	.comm	name,size
+
+/*
+ * Local zeroed data.
+ */
+#define LBSS(name,size) 		\
+  	.lcomm	name,size
+
+
+/*
+ * ABS - export absolute symbol
+ */
+#define	ABS(symbol,value)       \
+		.globl	symbol;         \
+symbol		=	value
+
+
+#define	TEXT(msg)               \
+		.pushsection .data;		\
+8:		.asciiz	msg;            \
+		.popsection;
+
+
+#define ENTRY(name) 			\
+  .globl name;					\
+  .align 2;						\
+  .ent name,0;					\
+  name##:
+
+/*
+ * Macros to handle different pointer/register sizes for 32/64-bit code
+ */
+
+/*
+ * Size of a register
+ */
+#define SZREG	4
+
+
+/*
+ * Use the following macros in assemblercode to load/store registers,
+ * pointers etc.
+ */
+#define REG_S		sw
+#define REG_L		lw
+#define REG_SUBU	subu
+#define REG_ADDU	addu
+
+
+/*
+ * How to add/sub/load/store/shift C int variables.
+ */
+#define INT_ADD		add
+#define INT_ADDU	addu
+#define INT_ADDI	addi
+#define INT_ADDIU	addiu
+#define INT_SUB		sub
+#define INT_SUBU	subu
+#define INT_L		lw
+#define INT_S		sw
+#define INT_SLL		sll
+#define INT_SLLV	sllv
+#define INT_SRL		srl
+#define INT_SRLV	srlv
+#define INT_SRA		sra
+#define INT_SRAV	srav
+
+
+
+/*
+ * How to add/sub/load/store/shift C long variables.
+ */
+#define LONG_ADD	add
+#define LONG_ADDU	addu
+#define LONG_ADDI	addi
+#define LONG_ADDIU	addiu
+#define LONG_SUB	sub
+#define LONG_SUBU	subu
+#define LONG_L		lw
+#define LONG_S		sw
+#define LONG_SLL	sll
+#define LONG_SLLV	sllv
+#define LONG_SRL	srl
+#define LONG_SRLV	srlv
+#define LONG_SRA	sra
+#define LONG_SRAV	srav
+
+#define LONG		.word
+#define LONGSIZE	4
+#define LONGMASK	3
+#define LONGLOG		2
+
+
+
+/*
+ * How to add/sub/load/store/shift pointers.
+ */
+#define PTR_ADD		add
+#define PTR_ADDU	addu
+#define PTR_ADDI	addi
+#define PTR_ADDIU	addiu
+#define PTR_SUB		sub
+#define PTR_SUBU	subu
+#define PTR_L		lw
+#define PTR_S		sw
+#define PTR_LA		la
+#define PTR_SLL		sll
+#define PTR_SLLV	sllv
+#define PTR_SRL		srl
+#define PTR_SRLV	srlv
+#define PTR_SRA		sra
+#define PTR_SRAV	srav
+
+#define PTR_SCALESHIFT	2
+
+#define PTR			.word
+#define PTRSIZE		4
+#define PTRLOG		2
+
+
+/*
+ * Some cp0 registers were extended to 64bit for MIPS III.
+ */
+#define MFC0		mfc0
+#define MTC0		mtc0
+
+
+#define SSNOP		sll zero, zero, 1
+
+#endif /* end of __ASM_H__ */

bsp/x1000/cpu/common/exception.h

+/*
+ * File      : cpu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2010, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-05-17     swkyer       first version
+ */
+#ifndef __EXCEPTION_H__
+#define __EXCEPTION_H__
+
+
+/*
+ * important register numbers
+ */
+#define REG_EPC				37
+#define REG_FP				72
+#define REG_SP				29
+
+/*
+ * Stack layout for the GDB exception handler
+ * Derived from the stack layout described in asm-mips/stackframe.h
+ *
+ * The first PTRSIZE*6 bytes are argument save space for C subroutines.
+ */
+#define NUMREGS				90
+
+#define GDB_FR_REG0			(PTRSIZE*6)			/* 0 */
+#define GDB_FR_REG1			((GDB_FR_REG0) + LONGSIZE)	/* 1 */
+#define GDB_FR_REG2			((GDB_FR_REG1) + LONGSIZE)	/* 2 */
+#define GDB_FR_REG3			((GDB_FR_REG2) + LONGSIZE)	/* 3 */
+#define GDB_FR_REG4			((GDB_FR_REG3) + LONGSIZE)	/* 4 */
+#define GDB_FR_REG5			((GDB_FR_REG4) + LONGSIZE)	/* 5 */
+#define GDB_FR_REG6			((GDB_FR_REG5) + LONGSIZE)	/* 6 */
+#define GDB_FR_REG7			((GDB_FR_REG6) + LONGSIZE)	/* 7 */
+#define GDB_FR_REG8			((GDB_FR_REG7) + LONGSIZE)	/* 8 */
+#define GDB_FR_REG9	        ((GDB_FR_REG8) + LONGSIZE)	/* 9 */
+#define GDB_FR_REG10		((GDB_FR_REG9) + LONGSIZE)	/* 10 */
+#define GDB_FR_REG11		((GDB_FR_REG10) + LONGSIZE)	/* 11 */
+#define GDB_FR_REG12		((GDB_FR_REG11) + LONGSIZE)	/* 12 */
+#define GDB_FR_REG13		((GDB_FR_REG12) + LONGSIZE)	/* 13 */
+#define GDB_FR_REG14		((GDB_FR_REG13) + LONGSIZE)	/* 14 */
+#define GDB_FR_REG15		((GDB_FR_REG14) + LONGSIZE)	/* 15 */
+#define GDB_FR_REG16		((GDB_FR_REG15) + LONGSIZE)	/* 16 */
+#define GDB_FR_REG17		((GDB_FR_REG16) + LONGSIZE)	/* 17 */
+#define GDB_FR_REG18		((GDB_FR_REG17) + LONGSIZE)	/* 18 */
+#define GDB_FR_REG19		((GDB_FR_REG18) + LONGSIZE)	/* 19 */
+#define GDB_FR_REG20		((GDB_FR_REG19) + LONGSIZE)	/* 20 */
+#define GDB_FR_REG21		((GDB_FR_REG20) + LONGSIZE)	/* 21 */
+#define GDB_FR_REG22		((GDB_FR_REG21) + LONGSIZE)	/* 22 */
+#define GDB_FR_REG23		((GDB_FR_REG22) + LONGSIZE)	/* 23 */
+#define GDB_FR_REG24		((GDB_FR_REG23) + LONGSIZE)	/* 24 */
+#define GDB_FR_REG25		((GDB_FR_REG24) + LONGSIZE)	/* 25 */
+#define GDB_FR_REG26		((GDB_FR_REG25) + LONGSIZE)	/* 26 */
+#define GDB_FR_REG27		((GDB_FR_REG26) + LONGSIZE)	/* 27 */
+#define GDB_FR_REG28		((GDB_FR_REG27) + LONGSIZE)	/* 28 */
+#define GDB_FR_REG29		((GDB_FR_REG28) + LONGSIZE)	/* 29 */
+#define GDB_FR_REG30		((GDB_FR_REG29) + LONGSIZE)	/* 30 */
+#define GDB_FR_REG31		((GDB_FR_REG30) + LONGSIZE)	/* 31 */
+
+/*
+ * Saved special registers
+ */
+#define GDB_FR_STATUS		((GDB_FR_REG31) + LONGSIZE)	/* 32 */
+#define GDB_FR_LO			((GDB_FR_STATUS) + LONGSIZE)	/* 33 */
+#define GDB_FR_HI			((GDB_FR_LO) + LONGSIZE)	/* 34 */
+#define GDB_FR_BADVADDR		((GDB_FR_HI) + LONGSIZE)	/* 35 */
+#define GDB_FR_CAUSE		((GDB_FR_BADVADDR) + LONGSIZE)	/* 36 */
+#define GDB_FR_EPC			((GDB_FR_CAUSE) + LONGSIZE)	/* 37 */
+
+///*
+// * Saved floating point registers
+// */
+//#define GDB_FR_FPR0		((GDB_FR_EPC) + LONGSIZE)	/* 38 */
+//#define GDB_FR_FPR1		((GDB_FR_FPR0) + LONGSIZE)	/* 39 */
+//#define GDB_FR_FPR2		((GDB_FR_FPR1) + LONGSIZE)	/* 40 */
+//#define GDB_FR_FPR3		((GDB_FR_FPR2) + LONGSIZE)	/* 41 */
+//#define GDB_FR_FPR4		((GDB_FR_FPR3) + LONGSIZE)	/* 42 */
+//#define GDB_FR_FPR5		((GDB_FR_FPR4) + LONGSIZE)	/* 43 */
+//#define GDB_FR_FPR6		((GDB_FR_FPR5) + LONGSIZE)	/* 44 */
+//#define GDB_FR_FPR7		((GDB_FR_FPR6) + LONGSIZE)	/* 45 */
+//#define GDB_FR_FPR8		((GDB_FR_FPR7) + LONGSIZE)	/* 46 */
+//#define GDB_FR_FPR9		((GDB_FR_FPR8) + LONGSIZE)	/* 47 */
+//#define GDB_FR_FPR10		((GDB_FR_FPR9) + LONGSIZE)	/* 48 */
+//#define GDB_FR_FPR11		((GDB_FR_FPR10) + LONGSIZE)	/* 49 */
+//#define GDB_FR_FPR12		((GDB_FR_FPR11) + LONGSIZE)	/* 50 */
+//#define GDB_FR_FPR13		((GDB_FR_FPR12) + LONGSIZE)	/* 51 */
+//#define GDB_FR_FPR14		((GDB_FR_FPR13) + LONGSIZE)	/* 52 */
+//#define GDB_FR_FPR15		((GDB_FR_FPR14) + LONGSIZE)	/* 53 */
+//#define GDB_FR_FPR16		((GDB_FR_FPR15) + LONGSIZE)	/* 54 */
+//#define GDB_FR_FPR17		((GDB_FR_FPR16) + LONGSIZE)	/* 55 */
+//#define GDB_FR_FPR18		((GDB_FR_FPR17) + LONGSIZE)	/* 56 */
+//#define GDB_FR_FPR19		((GDB_FR_FPR18) + LONGSIZE)	/* 57 */
+//#define GDB_FR_FPR20		((GDB_FR_FPR19) + LONGSIZE)	/* 58 */
+//#define GDB_FR_FPR21		((GDB_FR_FPR20) + LONGSIZE)	/* 59 */
+//#define GDB_FR_FPR22		((GDB_FR_FPR21) + LONGSIZE)	/* 60 */
+//#define GDB_FR_FPR23		((GDB_FR_FPR22) + LONGSIZE)	/* 61 */
+//#define GDB_FR_FPR24		((GDB_FR_FPR23) + LONGSIZE)	/* 62 */
+//#define GDB_FR_FPR25		((GDB_FR_FPR24) + LONGSIZE)	/* 63 */
+//#define GDB_FR_FPR26		((GDB_FR_FPR25) + LONGSIZE)	/* 64 */
+//#define GDB_FR_FPR27		((GDB_FR_FPR26) + LONGSIZE)	/* 65 */
+//#define GDB_FR_FPR28		((GDB_FR_FPR27) + LONGSIZE)	/* 66 */
+//#define GDB_FR_FPR29		((GDB_FR_FPR28) + LONGSIZE)	/* 67 */
+//#define GDB_FR_FPR30		((GDB_FR_FPR29) + LONGSIZE)	/* 68 */
+//#define GDB_FR_FPR31		((GDB_FR_FPR30) + LONGSIZE)	/* 69 */
+//
+//#define GDB_FR_FSR		((GDB_FR_FPR31) + LONGSIZE)	/* 70 */
+//#define GDB_FR_FIR		((GDB_FR_FSR) + LONGSIZE)	/* 71 */
+//#define GDB_FR_FRP		((GDB_FR_FIR) + LONGSIZE)	/* 72 */
+//
+//#define GDB_FR_DUMMY		((GDB_FR_FRP) + LONGSIZE)	/* 73, unused ??? */
+//
+///*
+// * Again, CP0 registers
+// */
+//#define GDB_FR_CP0_INDEX	((GDB_FR_DUMMY) + LONGSIZE)	/* 74 */
+#define GDB_FR_FRP			((GDB_FR_EPC) + LONGSIZE)	/* 72 */
+#define GDB_FR_CP0_INDEX	((GDB_FR_FRP) + LONGSIZE)	/* 74 */
+
+#define GDB_FR_CP0_RANDOM	((GDB_FR_CP0_INDEX) + LONGSIZE)	/* 75 */
+#define GDB_FR_CP0_ENTRYLO0	((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */
+#define GDB_FR_CP0_ENTRYLO1	((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */
+#define GDB_FR_CP0_CONTEXT	((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */
+#define GDB_FR_CP0_PAGEMASK	((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */
+#define GDB_FR_CP0_WIRED	((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */
+#define GDB_FR_CP0_REG7		((GDB_FR_CP0_WIRED) + LONGSIZE)	/* 81 */
+#define GDB_FR_CP0_REG8		((GDB_FR_CP0_REG7) + LONGSIZE)	/* 82 */
+#define GDB_FR_CP0_REG9		((GDB_FR_CP0_REG8) + LONGSIZE)	/* 83 */
+#define GDB_FR_CP0_ENTRYHI	((GDB_FR_CP0_REG9) + LONGSIZE)	/* 84 */
+#define GDB_FR_CP0_REG11	((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */
+#define GDB_FR_CP0_REG12	((GDB_FR_CP0_REG11) + LONGSIZE)	/* 86 */
+#define GDB_FR_CP0_REG13	((GDB_FR_CP0_REG12) + LONGSIZE)	/* 87 */
+#define GDB_FR_CP0_REG14	((GDB_FR_CP0_REG13) + LONGSIZE)	/* 88 */
+#define GDB_FR_CP0_PRID		((GDB_FR_CP0_REG14) + LONGSIZE)	/* 89 */
+
+#define GDB_FR_SIZE			((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
+
+/*
+ * This is the same as above, but for the high-level
+ * part of the INT stub.
+ */
+typedef struct pt_regs_s
+{
+	/* Saved main processor registers. */
+	rt_base_t regs[32];
+	/* Saved special registers. */
+	rt_base_t cp0_status;
+	rt_base_t hi;
+	rt_base_t lo;
+	rt_base_t cp0_badvaddr;
+	rt_base_t cp0_cause;
+	rt_base_t cp0_epc;
+} pt_regs_t;
+
+typedef void (* exception_func_t)(pt_regs_t *regs);
+
+extern exception_func_t sys_exception_handlers[];
+exception_func_t rt_set_except_vector(int n, exception_func_t func);
+void install_default_execpt_handle(void);
+
+#endif /* end of __EXCEPTION_H__ */

bsp/x1000/cpu/common/mips.h

+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016-09-07     Urey         first version
+ */
+
+#ifndef _COMMON_MIPS_H_
+#define _COMMON_MIPS_H_
+
+#include "mips_cfg.h"
+
+#include "mips_types.h"
+#include "mips_asm.h"
+#include "mips_def.h"
+#include "mips_regs.h"
+#include "mips_addrspace.h"
+#include "mips_cache.h"
+#include "mips_context.h"
+#include "mips_excpt.h"
+
+#endif /* _COMMON_MIPS_H_ */

bsp/x1000/cpu/common/mips.inc

+/*
+ * File      : mips.inc
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2010, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-05-17     sangwei      first version
+ */
+#ifndef __MIPS_INC__
+#define __MIPS_INC__
+
+#define zero    $0		/* wired zero */
+// #define at      $1
+#define v0      $2		/* return value */
+#define v1      $3
+#define a0      $4		/* argument registers */
+#define a1      $5
+#define a2      $6
+#define a3      $7
+#define t0      $8		/* caller saved */
+#define t1      $9
+#define t2      $10
+#define t3      $11
+#define t4      $12
+#define t5      $13
+#define t6      $14
+#define t7      $15
+#define s0      $16		/* callee saved */
+#define s1      $17
+#define s2      $18
+#define s3      $19
+#define s4      $20
+#define s5      $21
+#define s6      $22
+#define s7      $23
+#define t8      $24		/* caller saved */
+#define t9      $25
+#define jp      $25     /* PIC jump register */
+#define k0      $26     /* kernel scratch */
+#define k1      $27
+#define gp      $28     /* global pointer */
+#define sp      $29     /* stack pointer */
+#define fp      $30     /* frame pointer */
+#define s8		$30		/* same like fp! */
+#define ra      $31     /* return address */
+
+#endif /* end of __MIPS_INC__   */

bsp/x1000/cpu/common/mips_addrspace.h

+/*
+ * File      : mips_addrspace.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016912     Urey         the first version
+ */
+
+#ifndef _MIPS_ADDRSPACE_H_
+#define _MIPS_ADDRSPACE_H_
+
+
+/*
+ *  Configure language
+ */
+#ifdef __ASSEMBLY__
+#define _ATYPE_
+#define _ATYPE32_
+#define _ATYPE64_
+#define _CONST64_(x)	x
+#else
+#define _ATYPE_		__PTRDIFF_TYPE__
+#define _ATYPE32_	int
+#define _ATYPE64_	__s64
+#ifdef CONFIG_64BIT
+#define _CONST64_(x)	x ## L
+#else
+#define _CONST64_(x)	x ## LL
+#endif
+#endif
+
+/*
+ *  32-bit MIPS address spaces
+ */
+#ifdef __ASSEMBLY__
+#define _ACAST32_
+#define _ACAST64_
+#else
+#define _ACAST32_		(_ATYPE_)(_ATYPE32_)	/* widen if necessary */
+#define _ACAST64_		(_ATYPE64_)		/* do _not_ narrow */
+#endif
+
+/*
+ * Returns the kernel segment base of a given address
+ */
+#define KSEGX(a)		((_ACAST32_ (a)) & 0xe0000000)
+
+/*
+ * Returns the physical address of a CKSEGx / XKPHYS address
+ */
+#define CPHYSADDR(a)		((_ACAST32_(a)) & 0x1fffffff)
+#define XPHYSADDR(a)		((_ACAST64_(a)) &			\
+				 _CONST64_(0x000000ffffffffff))
+
+#ifdef CONFIG_64BIT
+
+/*
+ * Memory segments (64bit kernel mode addresses)
+ * The compatibility segments use the full 64-bit sign extended value.  Note
+ * the R8000 doesn't have them so don't reference these in generic MIPS code.
+ */
+#define XKUSEG			_CONST64_(0x0000000000000000)
+#define XKSSEG			_CONST64_(0x4000000000000000)
+#define XKPHYS			_CONST64_(0x8000000000000000)
+#define XKSEG			_CONST64_(0xc000000000000000)
+#define CKSEG0			_CONST64_(0xffffffff80000000)
+#define CKSEG1			_CONST64_(0xffffffffa0000000)
+#define CKSSEG			_CONST64_(0xffffffffc0000000)
+#define CKSEG3			_CONST64_(0xffffffffe0000000)
+
+#define CKSEG0ADDR(a)		(CPHYSADDR(a) | CKSEG0)
+#define CKSEG1ADDR(a)		(CPHYSADDR(a) | CKSEG1)
+#define CKSEG2ADDR(a)		(CPHYSADDR(a) | CKSEG2)
+#define CKSEG3ADDR(a)		(CPHYSADDR(a) | CKSEG3)
+
+#else
+
+#define CKSEG0ADDR(a)		(CPHYSADDR(a) | KSEG0BASE)
+#define CKSEG1ADDR(a)		(CPHYSADDR(a) | KSEG1BASE)
+#define CKSEG2ADDR(a)		(CPHYSADDR(a) | KSEG2BASE)
+#define CKSEG3ADDR(a)		(CPHYSADDR(a) | KSEG3BASE)
+
+/*
+ * Map an address to a certain kernel segment
+ */
+#define KSEG0ADDR(a)		(CPHYSADDR(a) | KSEG0BASE)
+#define KSEG1ADDR(a)		(CPHYSADDR(a) | KSEG1BASE)
+#define KSEG2ADDR(a)		(CPHYSADDR(a) | KSEG2BASE)
+#define KSEG3ADDR(a)		(CPHYSADDR(a) | KSEG3BASE)
+
+/*
+ * Memory segments (32bit kernel mode addresses)
+ * These are the traditional names used in the 32-bit universe.
+ */
+//#define KUSEGBASE			0x00000000
+//#define KSEG0BASE			0x80000000
+//#define KSEG1BASE			0xa0000000
+//#define KSEG2BASE			0xc0000000
+//#define KSEG3BASE			0xe0000000
+
+#define CKUSEG			0x00000000
+#define CKSEG0			0x80000000
+#define CKSEG1			0xa0000000
+#define CKSEG2			0xc0000000
+#define CKSEG3			0xe0000000
+
+#endif
+
+/*
+ * Cache modes for XKPHYS address conversion macros
+ */
+#define K_CALG_COH_EXCL1_NOL2	0
+#define K_CALG_COH_SHRL1_NOL2	1
+#define K_CALG_UNCACHED		2
+#define K_CALG_NONCOHERENT	3
+#define K_CALG_COH_EXCL		4
+#define K_CALG_COH_SHAREABLE	5
+#define K_CALG_NOTUSED		6
+#define K_CALG_UNCACHED_ACCEL	7
+
+/*
+ * 64-bit address conversions
+ */
+#define PHYS_TO_XKSEG_UNCACHED(p)	PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
+#define PHYS_TO_XKSEG_CACHED(p)		PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
+#define XKPHYS_TO_PHYS(p)		((p) & TO_PHYS_MASK)
+#define PHYS_TO_XKPHYS(cm, a)		(_CONST64_(0x8000000000000000) | \
+					 (_CONST64_(cm) << 59) | (a))
+
+/*
+ * Returns the uncached address of a sdram address
+ */
+#ifndef __ASSEMBLY__
+#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229)
+/* We use a 36 bit physical address map here and
+   cannot access physical memory directly from core */
+#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
+#else	/* !CONFIG_SOC_AU1X00 */
+#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
+#endif	/* CONFIG_SOC_AU1X00 */
+#endif	/* __ASSEMBLY__ */
+
+/*
+ * The ultimate limited of the 64-bit MIPS architecture:  2 bits for selecting
+ * the region, 3 bits for the CCA mode.  This leaves 59 bits of which the
+ * R8000 implements most with its 48-bit physical address space.
+ */
+#define TO_PHYS_MASK	_CONST64_(0x07ffffffffffffff)	/* 2^^59 - 1 */
+
+#ifndef CONFIG_CPU_R8000
+
+/*
+ * The R8000 doesn't have the 32-bit compat spaces so we don't define them
+ * in order to catch bugs in the source code.
+ */
+
+#define COMPAT_K1BASE32		_CONST64_(0xffffffffa0000000)
+#define PHYS_TO_COMPATK1(x)	((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
+
+#endif
+
+#define KDM_TO_PHYS(x)		(_ACAST64_ (x) & TO_PHYS_MASK)
+#define PHYS_TO_K0(x)		(_ACAST64_ (x) | CAC_BASE)
+
+
+#ifndef __ASSEMBLY__
+/*
+ * Change virtual addresses to physical addresses and vv.
+ * These are trivial on the 1:1 Linux/MIPS mapping
+ */
+static inline phys_addr_t virt_to_phys(volatile void * address)
+{
+#ifndef CONFIG_64BIT
+	return CPHYSADDR(address);
+#else
+	return XPHYSADDR(address);
+#endif
+}
+
+static inline void * phys_to_virt(unsigned long address)
+{
+#ifndef CONFIG_64BIT
+	return (void *)KSEG0ADDR(address);
+#else
+	return (void *)CKSEG0ADDR(address);
+#endif
+}
+#endif
+
+
+#endif /* _MIPS_ADDRSPACE_H_ */

bsp/x1000/cpu/common/mips_asm.h

+/*
+ * File      : mips_asm.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 201697     Urey         the first version
+ */
+
+#ifndef _MIPS_ASM_H_
+#define _MIPS_ASM_H_
+
+
+/* ********************************************************************* */
+/* Interface macro & data definition */
+
+#ifdef __ASSEMBLY__
+
+/******** ASSEMBLER SPECIFIC DEFINITIONS ********/
+
+#ifdef  __ghs__
+#define ALIGN(x) .##align (1 << (x))
+#else
+#define ALIGN(x) .##align (x)
+#endif
+
+#ifdef __ghs__
+#define SET_MIPS3()
+#define SET_MIPS0()
+#define SET_PUSH()
+#define SET_POP()
+#else
+#define SET_MIPS3() .##set mips3
+#define SET_MIPS0() .##set mips0
+#define SET_PUSH()  .##set push
+#define SET_POP()   .##set pop
+#endif
+
+/*  Different assemblers have different requirements for how to
+ *  indicate that the next section is bss :
+ *
+ *  Some use :   .bss
+ *  Others use : .section bss
+ *
+ *  We select which to use based on _BSS_OLD_, which may be defined
+ *  in makefile.
+ */
+#ifdef _BSS_OLD_
+#define BSS	.##section bss
+#else
+#define BSS	.##bss
+#endif
+
+#define LEAF(name)\
+  		.##text;\
+  		.##globl	name;\
+  		.##ent	name;\
+name:
+
+
+#define SLEAF(name)\
+  		.##text;\
+  		.##ent	name;\
+name:
+
+
+#ifdef __ghs__
+#define END(name)\
+  		.##end	name
+#else
+#define END(name)\
+  		.##size name,.-name;\
+  		.##end	name
+#endif
+
+
+#define EXTERN(name)
+
+#else
+
+#define U64 unsigned long long
+#define U32 unsigned int
+#define U16 unsigned short
+#define U8  unsigned char
+#define S64 signed long long
+#define S32 int
+#define S16 short int
+#define S8  signed char
+//#define bool U8
+
+#ifndef _SIZE_T_
+#define _SIZE_T_
+#ifdef __ghs__
+   typedef unsigned int size_t;
+#else
+   typedef unsigned long size_t;
+#endif
+#endif
+
+/* Sets the result on bPort */
+#define BIT_SET(bPort,bBitMask)        (bPort |= bBitMask)
+#define BIT_CLR(bPort,bBitMask)        (bPort &= ~bBitMask)
+
+/* Returns the result */
+#define GET_BIT_SET(bPort,bBitMask)    (bPort | bBitMask)
+#define GET_BIT_CLR(bPort,bBitMask)    (bPort & ~bBitMask)
+
+/* Returns 0 if the condition is False & a non-zero value if it is True */
+#define TEST_BIT_SET(bPort,bBitMask)   (bPort & bBitMask)
+#define TEST_BIT_CLR(bPort,bBitMask)   ((~bPort) & bBitMask)
+
+/* Split union definitions */
+typedef union tunSU16
+{
+        U16 hwHW;
+        struct tst2U8
+        {
+                U8 bB0;
+                U8 bB1;
+        }st2U8;
+}tunSU16;
+
+typedef union tunSU32
+{
+        U32 wW;
+        struct tst2U16
+        {
+                U16 hwHW0;
+                U16 hwHW1;
+        }st2U16;
+        struct tst4U8
+        {
+                U8 bB0;
+                U8 bB1;
+                U8 bB2;
+                U8 bB3;
+        }st4U8;
+}tunSU32;
+
+#endif /* #ifdef __ASSEMBLY__ */
+
+
+/******** DEFINITIONS FOR BOTH ASSEMBLER AND C ********/
+
+
+#define  NO_ERR             0x00000000     /* operation completed successfully */
+#define  ERR                0xffffffff     /* operation completed not successfully */
+
+#define False 0
+#define True !False
+
+#ifndef NULL
+#define NULL		      	((void *)0)
+#endif//NULL
+
+#ifndef MIN
+#define MIN(x,y)           ((x) < (y) ? (x) : (y))
+#endif//MIN
+
+#ifndef MAX
+#define MAX(x,y)      		((x) > (y) ? (x) : (y))
+#endif//MAX
+
+#define MAXUINT(w)	(\
+		((w) == sizeof(U8))  ? 0xFFU :\
+		((w) == sizeof(U16)) ? 0xFFFFU :\
+		((w) == sizeof(U32)) ? 0xFFFFFFFFU : 0\
+		        )
+
+#define MAXINT(w)	(\
+		((w) == sizeof(S8))  ? 0x7F :\
+		((w) == sizeof(S16)) ? 0x7FFF :\
+		((w) == sizeof(S32)) ? 0x7FFFFFFF : 0\
+		        )
+
+#define MSK(n)			  ((1 << (n)) - 1)
+
+#define KUSEG_MSK		  0x80000000
+#define KSEG_MSK		  0xE0000000
+
+#define KUSEGBASE		  0x00000000
+#define KSEG0BASE		  0x80000000
+#define KSEG1BASE		  0xA0000000
+#define KSSEGBASE		  0xC0000000
+#define KSEG3BASE		  0xE0000000
+
+/*  Below macros perform the following functions :
+ *
+ *  KSEG0    : Converts KSEG0/1 or physical addr (below 0.5GB) to KSEG0.
+ *  KSEG1    : Converts KSEG0/1 or physical addr (below 0.5GB) to KSEG1.
+ *  PHYS     : Converts KSEG0/1 or physical addr (below 0.5GB) to physical address.
+ *  KSSEG    : Not relevant for converting, but used for determining range.
+ *  KSEG3    : Not relevant for converting, but used for determining range.
+ *  KUSEG    : Not relevant for converting, but used for determining range.
+ *  KSEG0A   : Same as KSEG0 but operates on register rather than constant.
+ *  KSEG1A   : Same as KSEG1 but operates on register rather than constant.
+ *  PHYSA    : Same as PHYS  but operates on register rather than constant.
+ *  CACHED   : Alias for KSEG0 macro .
+ *	       (Note that KSEG0 cache attribute is determined by K0
+ *	       field of Config register, but this is typically cached).
+ *  UNCACHED : Alias for KSEG1 macro .
+ */
+#ifdef __ASSEMBLY__
+#define KSEG0(addr)     (((addr) & ~KSEG_MSK)  | KSEG0BASE)
+#define KSEG1(addr)     (((addr) & ~KSEG_MSK)  | KSEG1BASE)
+#define KSSEG(addr)     (((addr) & ~KSEG_MSK)  | KSSEGBASE)
+#define KSEG3(addr)     (((addr) & ~KSEG_MSK)  | KSEG3BASE)
+#define KUSEG(addr)     (((addr) & ~KUSEG_MSK) | KUSEGBASE)
+#define PHYS(addr)      ( (addr) & ~KSEG_MSK)
+#define KSEG0A(reg) 	and reg, ~KSEG_MSK; or reg, KSEG0BASE
+#define KSEG1A(reg) 	and reg, ~KSEG_MSK; or reg, KSEG1BASE
+#define PHYSA(reg)	and reg, ~KSEG_MSK
+#else
+#define KSEG0(addr)     (((U32)(addr) & ~KSEG_MSK)  | KSEG0BASE)
+#define KSEG1(addr)     (((U32)(addr) & ~KSEG_MSK)  | KSEG1BASE)
+#define KSSEG(addr)	(((U32)(addr) & ~KSEG_MSK)  | KSSEGBASE)
+#define KSEG3(addr)	(((U32)(addr) & ~KSEG_MSK)  | KSEG3BASE)
+#define KUSEG(addr)	(((U32)(addr) & ~KUSEG_MSK) | KUSEGBASE)
+#define PHYS(addr) 	((U32)(addr)  & ~KSEG_MSK)
+#endif
+
+#define CACHED(addr)	KSEG0(addr)
+#define UNCACHED(addr)	KSEG1(addr)
+
+
+#ifdef __ASSEMBLY__
+/* Macroes to access variables at constant addresses
+ * Compensates for signed 16 bit displacement
+ * Typical use:	li	a0, HIKSEG1(ATLAS_ASCIIWORD)
+ *		sw	v1, LO_OFFS(ATLAS_ASCIIWORD)(a0)
+ */
+#define HIKSEG0(addr)	((KSEG0(addr) + 0x8000) & 0xffff0000)
+#define HIKSEG1(addr)	((KSEG1(addr) + 0x8000) & 0xffff0000)
+#define HI_PART(addr)	(((addr) + 0x8000) & 0xffff0000)
+#define LO_OFFS(addr)	((addr) & 0xffff)
+#endif
+
+
+/* Most/Least significant 32 bit from 64 bit double word */
+#define HI32(data64)		  ((U32)(data64 >> 32))
+#define LO32(data64)		  ((U32)(data64 & 0xFFFFFFFF))
+
+#if ((!defined(__ASSEMBLY__)) && (!defined(__LANGUAGE_ASSEMBLY)))
+#define REG8( addr )		  (*(volatile U8 *) (addr))
+#define REG16( addr )		  (*(volatile U16 *)(addr))
+#define REG32( addr )		  (*(volatile U32 *)(addr))
+#define REG64( addr )		  (*(volatile U64 *)(addr))
+#endif
+
+/* Register field mapping */
+#define REGFIELD(reg, rfld)	  (((reg) & rfld##_MSK) >> rfld##_SHF)
+
+/* absolute register address, access 					*/
+#define	REGA(addr)		  REG32(addr)
+
+/* physical register address, access: base address + offsett		*/
+#define	REGP(base,phys)	REG32( (U32)(base) + (phys) )
+
+/* relative register address, access: base address + offsett		*/
+#define REG(base,offs)  REG32( (U32)(base) + offs##_##OFS )
+
+/* relative register address, access: base address + offsett		*/
+#define REG_8(base,offs)  REG8( (U32)(base) + offs##_##OFS )
+
+/* relative register address, access: base address + offsett		*/
+#define REG_16(base,offs)  REG16( (U32)(base) + offs##_##OFS )
+
+/* relative register address, access: base address + offsett		*/
+#define REG_64(base,offs)  REG64( (U32)(base) + offs##_##OFS )
+
+/**************************************
+ * Macroes not used by YAMON any more
+ * (kept for backwards compatibility)
+ */
+/* register read field							*/
+#define	REGARD(addr,fld)	((REGA(addr) & addr##_##fld##_##MSK) 	\
+			 >> addr##_##fld##_##SHF)
+
+/* register write numeric field value					*/
+#define	REGAWRI(addr,fld,intval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\
+				 | ((intval) << addr##_##fld##_##SHF))
+
+/* register write enumerated field value				*/
+#define	REGAWRE(addr,fld,enumval) ((REGA(addr) & ~(addr##_##fld##_##MSK))\
+			| ((addr##_##fld##_##enumval) << addr##_##fld##_##SHF))
+
+
+/* Examples:
+ *
+ *	exccode = REGARD(CPU_CAUSE,EXC);
+ *
+ *	REGA(SDR_CONTROL) = REGAWRI(OSG_CONTROL,TMO,17)
+ *			 | REGAWRE(OSG_CONTROL,DTYPE,PC1);
+ */
+
+
+/* register read field							*/
+#define	REGRD(base,offs,fld) ((REG(base,offs) & offs##_##fld##_##MSK) 	\
+			 >> offs##_##fld##_##SHF)
+
+/* register write numeric field value					*/
+#define	REGWRI(base,offs,fld,intval)((REG(base,offs)& ~(offs##_##fld##_##MSK))\
+                                 | (((intval) << offs##_##fld##_##SHF) & offs##_##fld##_##MSK))
+
+/* register write enumerated field value				*/
+#define	REGWRE(base,offs,fld,enumval)((REG(base,offs) & ~(offs##_##fld##_##MSK))\
+				| ((offs##_##fld##_##enumval) << offs##_##fld##_##SHF))
+
+
+/* physical register read field							*/
+#define	REGPRD(base,phys,fld) ((REGP(base,phys) & phys##_##fld##_##MSK) 	\
+			 >> phys##_##fld##_##SHF)
+
+/* physical register write numeric field value					*/
+#define	REGPWRI(base,phys,fld,intval)((REGP(base,phys)& ~(phys##_##fld##_##MSK))\
+				 | ((intval) << phys##_##fld##_##SHF))
+
+/* physical register write enumerated field value				*/
+#define	REGPWRE(base,phys,fld,enumval)((REGP(base,phys) & ~(phys##_##fld##_##MSK))\
+				| ((phys##_##fld##_##enumval) << phys##_##fld##_##SHF))
+/*
+ * End of macroes not used by YAMON any more
+ *********************************************/
+
+/* Endian related macros */
+
+#define SWAP_BYTEADDR32( addr )   ( (addr) ^ 0x3 )
+#define SWAP_U16ADDR32( addr ) ( (addr) ^ 0x2 )
+
+/* Set byte address to little endian format */
+#ifdef EL
+#define SWAP_BYTEADDR_EL(addr) 	  addr
+#else
+#define SWAP_BYTEADDR_EL(addr)    SWAP_BYTEADDR32( addr )
+#endif
+
+/* Set byte address to big endian format */
+#ifdef EB
+#define SWAP_BYTEADDR_EB(addr) 	  addr
+#else
+#define SWAP_BYTEADDR_EB(addr)    SWAP_BYTEADDR32( addr )
+#endif
+
+/* Set U16 address to little endian format */
+#ifdef EL
+#define SWAP_U16ADDR_EL(addr)  addr
+#else
+#define SWAP_U16ADDR_EL(addr)  SWAP_U16ADDR32( addr )
+#endif
+
+/* Set U16 address to big endian format */
+#ifdef EB
+#define SWAP_U16ADDR_EB(addr)  addr
+#else
+#define SWAP_U16ADDR_EB(addr)  SWAP_U16ADDR32( addr )
+#endif
+
+#ifdef EL
+#define REGW32LE(addr, data)      REG32(addr) = (data)
+#define REGR32LE(addr, data)      (data)      = REG32(addr)
+#else
+#define REGW32LE(addr, data)      REG32(addr) = SWAPEND32(data)
+#define REGR32LE(addr, data)      (data)      = REG32(addr), (data) = SWAPEND32(data)
+#endif
+
+/* Set of 'LE'-macros, convert by BE: */
+#ifdef EL
+#define CPU_TO_LE32( value ) (value)
+#define LE32_TO_CPU( value ) (value)
+
+#define CPU_TO_LE16( value ) (value)
+#define LE16_TO_CPU( value ) (value)
+#else
+#define CPU_TO_LE32( value ) ( (                ((U32)value)  << 24) |   \
+                               ((0x0000FF00UL & ((U32)value)) <<  8) |   \
+                               ((0x00FF0000UL & ((U32)value)) >>  8) |   \
+                               (                ((U32)value)  >> 24)   )
+#define LE32_TO_CPU( value ) CPU_TO_LE32( value )
+
+#define CPU_TO_LE16( value ) ( ((U16)(((U16)value)  << 8)) |   \
+                               ((U16)(((U16)value)  >> 8))   )
+#define LE16_TO_CPU( value ) CPU_TO_LE16( value )
+#endif
+
+/* Set of 'BE'-macros, convert by LE: */
+#ifdef EB
+#define CPU_TO_BE32( value ) (value)
+#define BE32_TO_CPU( value ) (value)
+
+#define CPU_TO_BE16( value ) (value)
+#define BE16_TO_CPU( value ) (value)
+#else
+#define CPU_TO_BE32( value ) ( (                ((U32)value)  << 24) |   \
+                               ((0x0000FF00UL & ((U32)value)) <<  8) |   \
+                               ((0x00FF0000UL & ((U32)value)) >>  8) |   \
+                               (                ((U32)value)  >> 24)   )
+#define BE32_TO_CPU( value ) CPU_TO_BE32( value )
+
+#define CPU_TO_BE16( value ) ( ((U16)(((U16)value)  << 8)) |   \
+                               ((U16)(((U16)value)  >> 8))   )
+#define BE16_TO_CPU( value ) CPU_TO_BE16( value )
+#endif
+
+
+/* Control characters */
+#define CTRL_A          ('A'-0x40)
+#define CTRL_B          ('B'-0x40)
+#define CTRL_C          ('C'-0x40)
+#define CTRL_D          ('D'-0x40)
+#define CTRL_E          ('E'-0x40)
+#define CTRL_F          ('F'-0x40)
+#define CTRL_H          ('H'-0x40)
+#define CTRL_K          ('K'-0x40)
+#define CTRL_N          ('N'-0x40)
+#define CTRL_P          ('P'-0x40)
+#define CTRL_U          ('U'-0x40)
+#define BACKSPACE       0x08
+#define DEL             0x7F
+#define TAB             0x09
+#define CR              0x0D /* Enter Key */
+#define LF              0x0A
+#define ESC             0x1B
+#define SP              0x20
+#define CSI             0x9B
+
+
+/* DEF2STR(x) converts #define symbol to string */
+#define DEF2STR1(x) #x
+#define DEF2STR(x)  DEF2STR1(x)
+
+
+#endif /* _MIPS_ASM_H_ */

bsp/x1000/cpu/common/mips_cache.c

+/*
+ * File      : mips_cache.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 201697     Urey         the first version
+ */
+
+#include <rtthread.h>
+#include "mips.h"
+
+extern void cache_init(rt_ubase_t cache_size, rt_ubase_t cache_line_size);
+void r4k_cache_init(void)
+{
+//	cache_init(dcache_size, cpu_dcache_line_size);
+}
+
+void r4k_cache_flush_all(void)
+{
+    blast_dcache16();
+    blast_icache16();
+}
+
+
+void r4k_icache_flush_all(void)
+{
+    blast_icache16();
+}
+
+void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size)
+{
+	rt_ubase_t end, a;
+
+    if (size > g_mips_core.icache_size)
+    {
+        blast_icache16();
+    }
+    else
+    {
+    	rt_ubase_t ic_lsize = g_mips_core.icache_line_size;
+
+        a = addr & ~(ic_lsize - 1);
+        end = ((addr + size) - 1) & ~(ic_lsize - 1);
+        while (1)
+        {
+            flush_icache_line(a);
+            if (a == end)
+                break;
+            a += ic_lsize;
+        }
+    }
+}
+
+void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size)
+{
+	rt_ubase_t end, a;
+	rt_ubase_t ic_lsize = g_mips_core.icache_line_size;
+
+    a = addr & ~(ic_lsize - 1);
+    end = ((addr + size) - 1) & ~(ic_lsize - 1);
+    while (1)
+    {
+        lock_icache_line(a);
+        if (a == end)
+            break;
+        a += ic_lsize;
+    }
+}
+
+void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size)
+{
+	rt_ubase_t end, a;
+    rt_ubase_t dc_lsize = g_mips_core.dcache_line_size;
+
+    a = addr & ~(dc_lsize - 1);
+    end = ((addr + size) - 1) & ~(dc_lsize - 1);
+    while (1)
+    {
+        invalidate_dcache_line(a);
+        if (a == end)
+            break;
+        a += dc_lsize;
+    }
+}
+
+void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size)
+{
+	rt_ubase_t end, a;
+
+    if (size >= g_mips_core.dcache_size)
+    {
+        blast_dcache16();
+    }
+    else
+    {
+    	rt_ubase_t dc_lsize = g_mips_core.dcache_line_size;
+
+        a = addr & ~(dc_lsize - 1);
+        end = ((addr + size) - 1) & ~(dc_lsize - 1);
+        while (1)
+        {
+            flush_dcache_line(a);
+            if (a == end)
+                break;
+            a += dc_lsize;
+        }
+    }
+}
+
+#define dma_cache_wback_inv(start,size) \
+    do { (void) (start); (void) (size); } while (0)
+#define dma_cache_wback(start,size) \
+    do { (void) (start); (void) (size); } while (0)
+#define dma_cache_inv(start,size)   \
+    do { (void) (start); (void) (size); } while (0)
+
+
+void r4k_dma_cache_sync(rt_ubase_t addr, rt_size_t size, enum dma_data_direction direction)
+{
+    switch (direction)
+    {
+        case DMA_TO_DEVICE:
+            r4k_dcache_wback_inv(addr, size);
+        break;
+
+        case DMA_FROM_DEVICE:
+            r4k_dcache_wback_inv(addr, size);
+        break;
+
+        case DMA_BIDIRECTIONAL:
+            dma_cache_wback_inv(addr, size);
+        break;
+        default:
+            RT_ASSERT(0) ;
+    }
+}
+

bsp/x1000/cpu/common/mips_cache.h

+/*
+ * File      : mips_cache.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2016910     Urey         the first version
+ */
+
+#ifndef _MIPS_CACHE_H_
+#define _MIPS_CACHE_H_
+
+#ifndef __ASSEMBLER__
+#include <rtdef.h>
+#include <mips_cfg.h>
+
+/*
+ * Cache Operations available on all MIPS processors with R4000-style caches
+ */
+#define INDEX_INVALIDATE_I      0x00
+#define INDEX_WRITEBACK_INV_D   0x01
+#define INDEX_LOAD_TAG_I        0x04
+#define INDEX_LOAD_TAG_D        0x05
+#define INDEX_STORE_TAG_I       0x08
+#define INDEX_STORE_TAG_D       0x09
+#if defined(CONFIG_CPU_LOONGSON2)
+#define HIT_INVALIDATE_I        0x00
+#else
+#define HIT_INVALIDATE_I        0x10
+#endif
+#define HIT_INVALIDATE_D        0x11
+#define HIT_WRITEBACK_INV_D     0x15
+
+/*
+ *The lock state is cleared by executing an Index
+Invalidate, Index Writeback Invalidate, Hit
+Invalidate, or Hit Writeback Invalidate
+operation to the locked line, or via an Index
+Store Tag operation with the lock bit reset in
+the TagLo register.
+ */
+#define FETCH_AND_LOCK_I        0x1c
+#define FETCH_AND_LOCK_D        0x1d
+
+
+enum dma_data_direction
+{
+    DMA_BIDIRECTIONAL = 0,
+    DMA_TO_DEVICE = 1,
+    DMA_FROM_DEVICE = 2,
+    DMA_NONE = 3,
+};
+
+/*
+ * R4000-specific cacheops
+ */
+#define CREATE_DIRTY_EXCL_D     0x0d
+#define FILL                    0x14
+#define HIT_WRITEBACK_I         0x18
+#define HIT_WRITEBACK_D         0x19
+
+/*
+ * R4000SC and R4400SC-specific cacheops
+ */
+#define INDEX_INVALIDATE_SI     0x02
+#define INDEX_WRITEBACK_INV_SD  0x03
+#define INDEX_LOAD_TAG_SI       0x06
+#define INDEX_LOAD_TAG_SD       0x07
+#define INDEX_STORE_TAG_SI      0x0A
+#define INDEX_STORE_TAG_SD      0x0B
+#define CREATE_DIRTY_EXCL_SD    0x0f
+#define HIT_INVALIDATE_SI       0x12
+#define HIT_INVALIDATE_SD       0x13
+#define HIT_WRITEBACK_INV_SD    0x17
+#define HIT_WRITEBACK_SD        0x1b
+#define HIT_SET_VIRTUAL_SI      0x1e
+#define HIT_SET_VIRTUAL_SD      0x1f
+
+/*
+ * R5000-specific cacheops
+ */
+#define R5K_PAGE_INVALIDATE_S   0x17
+
+/*
+ * RM7000-specific cacheops
+ */
+#define PAGE_INVALIDATE_T       0x16
+
+/*
+ * R10000-specific cacheops
+ *
+ * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
+ * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
+ */
+#define INDEX_WRITEBACK_INV_S   0x03
+#define INDEX_LOAD_TAG_S        0x07
+#define INDEX_STORE_TAG_S       0x0B
+#define HIT_INVALIDATE_S        0x13
+#define CACHE_BARRIER           0x14
+#define HIT_WRITEBACK_INV_S     0x17
+#define INDEX_LOAD_DATA_I       0x18
+#define INDEX_LOAD_DATA_D       0x19
+#define INDEX_LOAD_DATA_S       0x1b
+#define INDEX_STORE_DATA_I      0x1c
+#define INDEX_STORE_DATA_D      0x1d
+#define INDEX_STORE_DATA_S      0x1f
+
+#define cache_op(op, addr)		    \
+    __asm__ __volatile__(        \
+        ".set   push\n"             \
+        ".set   noreorder\n"        \
+        ".set   mips3\n"            \
+        "cache  %0, %1\n"           \
+        ".set   pop\n"              \
+        :                           \
+        : "i" (op), "R" (*(unsigned char *)(addr)))
+
+#define cache16_unroll32(base, op)					\
+	__asm__ __volatile__(						\
+	"	.set noreorder					\n"	\
+	"	.set mips3					\n"	\
+	"	cache %1, 0x000(%0); cache %1, 0x010(%0)	\n"	\
+	"	cache %1, 0x020(%0); cache %1, 0x030(%0)	\n"	\
+	"	cache %1, 0x040(%0); cache %1, 0x050(%0)	\n"	\
+	"	cache %1, 0x060(%0); cache %1, 0x070(%0)	\n"	\
+	"	cache %1, 0x080(%0); cache %1, 0x090(%0)	\n"	\
+	"	cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)	\n"	\
+	"	cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)	\n"	\
+	"	cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)	\n"	\
+	"	cache %1, 0x100(%0); cache %1, 0x110(%0)	\n"	\
+	"	cache %1, 0x120(%0); cache %1, 0x130(%0)	\n"	\
+	"	cache %1, 0x140(%0); cache %1, 0x150(%0)	\n"	\
+	"	cache %1, 0x160(%0); cache %1, 0x170(%0)	\n"	\
+	"	cache %1, 0x180(%0); cache %1, 0x190(%0)	\n"	\
+	"	cache %1, 0x1a0(%0); cache %1, 0x1b0(%0)	\n"	\
+	"	cache %1, 0x1c0(%0); cache %1, 0x1d0(%0)	\n"	\
+	"	cache %1, 0x1e0(%0); cache %1, 0x1f0(%0)	\n"	\
+	"	.set mips0					\n"	\
+	"	.set reorder					\n"	\
+		:							\
+		: "r" (base),						\
+		  "i" (op));
+
+
+static inline void flush_icache_line_indexed(rt_ubase_t addr)
+{
+	cache_op(INDEX_INVALIDATE_I, addr);
+}
+
+static inline void flush_dcache_line_indexed(rt_ubase_t addr)
+{
+	cache_op(INDEX_WRITEBACK_INV_D, addr);
+}
+
+static inline void flush_icache_line(rt_ubase_t addr)
+{
+	cache_op(HIT_INVALIDATE_I, addr);
+}
+
+static inline void lock_icache_line(rt_ubase_t addr)
+{
+	cache_op(FETCH_AND_LOCK_I, addr);
+}
+
+static inline void lock_dcache_line(rt_ubase_t addr)
+{
+	cache_op(FETCH_AND_LOCK_D, addr);
+}
+
+static inline void flush_dcache_line(rt_ubase_t addr)
+{
+	cache_op(HIT_WRITEBACK_INV_D, addr);
+}
+
+static inline void invalidate_dcache_line(rt_ubase_t addr)
+{
+	cache_op(HIT_INVALIDATE_D, addr);
+}
+static inline void blast_dcache16(void)
+{
+	rt_ubase_t start = KSEG0BASE;
+	rt_ubase_t end = start + g_mips_core.dcache_size;
+	rt_ubase_t addr;
+
+	for (addr = start; addr < end; addr += g_mips_core.dcache_line_size)
+		cache16_unroll32(addr, INDEX_WRITEBACK_INV_D);
+}
+
+static inline void inv_dcache16(void)
+{
+	rt_ubase_t start = KSEG0BASE;
+	rt_ubase_t end = start + g_mips_core.dcache_size;
+	rt_ubase_t addr;
+
+	for (addr = start; addr < end; addr += g_mips_core.dcache_line_size)
+		cache16_unroll32(addr, HIT_INVALIDATE_D);
+}
+
+static inline void blast_icache16(void)
+{
+	rt_ubase_t start = KSEG0BASE;
+	rt_ubase_t end = start + g_mips_core.icache_size;
+	rt_ubase_t addr;
+
+	for (addr = start; addr < end; addr += g_mips_core.icache_line_size)
+		cache16_unroll32(addr, INDEX_INVALIDATE_I);
+}
+
+void r4k_cache_init(void);
+void r4k_cache_flush_all(void);
+void r4k_icache_flush_all(void);
+void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size);
+void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size);
+void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size);
+void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size);
+void r4k_dma_cache_sync(rt_ubase_t addr, rt_size_t size, enum dma_data_direction direction);
+#endif
+
+#endif /* _MIPS_CACHE_H_ */

libcpu/mips/xburst/cpu.c → bsp/x1000/cpu/common/mips_cfg.h

 /*
- * File      : cpu.c
- * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
+ * File      : mips_cfg.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,58 +19,30 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2010-07-09     Bernard      first version
- * 2010-09-11     Bernard      add CPU reset implementation
+ * 2016Äê9ÔÂ10ÈÕ     Urey         the first version
  */
-#include <rtthread.h>
-#include <board.h>
 
-/**
- * @addtogroup Ingenic
- */
-/*@{*/
+#ifndef _MIPS_CFG_H_
+#define _MIPS_CFG_H_
 
-/**
- * this function will reset CPU
- *
- */
-void rt_hw_cpu_reset()
+#ifndef __ASSEMBLY__
+#include <stdint.h>
+typedef struct mips32_core_cfg
 {
-    /* open the watch-dog */
-    REG_WDT_TCSR  = WDT_TCSR_EXT_EN;
-    REG_WDT_TCSR |= WDT_TCSR_PRESCALE_1024;
-    REG_WDT_TDR   = 0x03;
-    REG_WDT_TCNT  = 0x00;
-    REG_WDT_TCER |= WDT_TCER_TCEN;
+    uint16_t icache_line_size;
+//    uint16_t icache_lines_per_way;
+//    uint16_t icache_ways;
+    uint16_t icache_size;
+    uint16_t dcache_line_size;
+//    uint16_t dcache_lines_per_way;
+//    uint16_t dcache_ways;
+    uint16_t dcache_size;
 
-    rt_kprintf("reboot system...\n");
-    while (1);
-}
+    uint16_t max_tlb_entries;	/* number of tlb entry */
+} mips32_core_cfg_t;
 
-/**
- * this function will shutdown CPU
- *
- */
-void rt_hw_cpu_shutdown()
-{
-    rt_kprintf("shutdown...\n");
+extern mips32_core_cfg_t g_mips_core;
 
-    while (1);
-}
-
-/**
- * This function finds the first bit set (beginning with the least significant bit)
- * in value and return the index of that bit.
- *
- * Bits are numbered starting at 1 (the least significant bit).  A return value of
- * zero from any of these functions means that the argument was zero.
- *
- * @return return the index of the first bit set. If value is 0, then this function
- * shall return 0.
- */
-int __rt_ffs(int value)
-{
-    return __builtin_ffs(value);
-}
+#endif /* __ASSEMBLY__ */
 
-/*@}*/
+#endif /* _MIPS_CFG_H_ */

bsp/x1000/cpu/common/mips_context.h

+/*
+ * File      : mips_context_asm.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 201697     Urey         the first version
+ */
+
+#ifndef _MIPS_CONTEXT_ASM_H_
+#define _MIPS_CONTEXT_ASM_H_
+
+#define CONTEXT_SIZE	( STK_CTX_SIZE + FPU_ADJ )
+#ifdef __mips_hard_float
+#define FPU_ADJ			(32 * 4 + 8)		/* FP0-FP31 + CP1_STATUS */
+#define FPU_CTX			( CONTEXT_SIZE - FPU_ADJ )
+#else
+#define FPU_ADJ			0
+#endif
+
+
+
+#ifdef __ASSEMBLY__
+
+#ifdef __mips_hard_float
+.global _fpctx_save
+.global _fpctx_load
+#endif
+
+.macro SAVE_CONTEXT
+	.set    push
+	.set    noat
+	.set    noreorder
+	.set    volatile
+
+	//save SP
+	move	k1, 	sp
+	move	k0, 	sp
+	subu 	sp, 	k1, 	CONTEXT_SIZE
+	sw		k0, 	(29 * 4)(sp)
+
+	//save REG
+	sw		$0, 	( 0 * 4)(sp)
+	sw		$1, 	( 1 * 4)(sp)
+	sw		$2, 	( 2 * 4)(sp)
+	sw		$3, 	( 3 * 4)(sp)
+	sw		$4, 	( 4 * 4)(sp)
+	sw		$5, 	( 5 * 4)(sp)
+	sw		$6, 	( 6 * 4)(sp)
+	sw		$7, 	( 7 * 4)(sp)
+	sw		$8,     ( 8 * 4)(sp)
+	sw		$9,     ( 9 * 4)(sp)
+	sw		$10,    (10 * 4)(sp)
+	sw		$11,    (11 * 4)(sp)
+	sw		$12,    (12 * 4)(sp)
+	sw		$13,    (13 * 4)(sp)
+	sw		$14,    (14 * 4)(sp)
+	sw		$15,    (15 * 4)(sp)
+	sw		$16,    (16 * 4)(sp)
+	sw		$17,    (17 * 4)(sp)
+	sw		$18,    (18 * 4)(sp)
+	sw		$19,    (19 * 4)(sp)
+	sw		$20,    (20 * 4)(sp)
+	sw		$21,    (21 * 4)(sp)
+	sw		$22,    (22 * 4)(sp)
+	sw		$23,    (23 * 4)(sp)
+	sw		$24,    (24 * 4)(sp)
+	sw		$25, 	(25 * 4)(sp)
+	/* K0 K1 */
+	sw		$28, 	(28 * 4)(sp)
+	/* SP */
+	sw		$30,    (30 * 4)(sp)
+	sw		$31, 	(31 * 4)(sp)
+
+	/* STATUS CAUSE EPC.... */
+	mfc0	$2, 	CP0_STATUS
+	sw		$2, 	STK_OFFSET_SR(sp)
+
+	mfc0	$2, 	CP0_CAUSE
+	sw		$2, 	STK_OFFSET_CAUSE(sp)
+
+	mfc0	$2, 	CP0_BADVADDR
+	sw		$2, 	STK_OFFSET_BADVADDR(sp)
+
+	MFC0	$2, 	CP0_EPC
+	sw		$2, 	STK_OFFSET_EPC(sp)
+
+	mfhi	$2
+	sw		$2,     STK_OFFSET_HI(sp)
+
+	mflo	$2
+	sw		$2,     STK_OFFSET_LO(sp)
+#ifdef __mips_hard_float
+	add		a0,		sp,STK_CTX_SIZE
+
+    mfc0 	t0, 	CP0_STATUS
+    .set	push
+    .set	at
+    or      t0,   	M_StatusCU1
+    .set 	push
+    mtc0 	t0, 	CP0_STATUS
+
+    cfc1 	t0,  	CP1_STATUS
+    sw      t0   ,  0x00(a0)
+	swc1    $f0,(0x04 *  1)(a0)
+	swc1    $f1,(0x04 *  2)(a0)
+	swc1    $f2,(0x04 *  3)(a0)
+	swc1    $f3,(0x04 *  4)(a0)
+	swc1    $f4,(0x04 *  5)(a0)
+	swc1    $f5,(0x04 *  6)(a0)
+	swc1    $f6,(0x04 *  7)(a0)
+	swc1    $f7,(0x04 *  8)(a0)
+	swc1    $f8,(0x04 *  9)(a0)
+	swc1    $f9,(0x04 * 10)(a0)
+	swc1   $f10,(0x04 * 11)(a0)
+	swc1   $f11,(0x04 * 12)(a0)
+	swc1   $f12,(0x04 * 13)(a0)
+	swc1   $f13,(0x04 * 14)(a0)
+	swc1   $f14,(0x04 * 15)(a0)
+	swc1   $f15,(0x04 * 16)(a0)
+	swc1   $f16,(0x04 * 17)(a0)
+	swc1   $f17,(0x04 * 18)(a0)
+	swc1   $f18,(0x04 * 19)(a0)
+	swc1   $f19,(0x04 * 20)(a0)
+	swc1   $f20,(0x04 * 21)(a0)
+	swc1   $f21,(0x04 * 22)(a0)
+	swc1   $f22,(0x04 * 23)(a0)
+	swc1   $f23,(0x04 * 24)(a0)
+	swc1   $f24,(0x04 * 25)(a0)
+	swc1   $f25,(0x04 * 26)(a0)
+	swc1   $f26,(0x04 * 27)(a0)
+	swc1   $f27,(0x04 * 28)(a0)
+	swc1   $f28,(0x04 * 29)(a0)
+	swc1   $f29,(0x04 * 30)(a0)
+	swc1   $f30,(0x04 * 31)(a0)
+	swc1   $f31,(0x04 * 32)(a0)
+
+	nop
+#endif
+
+	//restore a0
+	lw		a0,		(REG_A0 * 4)(sp)
+
+	.set	pop
+.endm
+
+
+.macro RESTORE_CONTEXT
+	.set    push
+	.set    noat
+	.set    noreorder
+	.set    volatile
+
+#ifdef __mips_hard_float
+	add		a0,	sp,STK_CTX_SIZE
+
+    mfc0 	t0, CP0_STATUS
+    .set	push
+    .set	at
+    or      t0, M_StatusCU1
+    .set	noat
+    mtc0	t0, CP0_STATUS
+
+    lw      t0   ,   0x00(a0)
+	lwc1    $f0,(0x04 *  1)(a0)
+	lwc1    $f1,(0x04 *  2)(a0)
+	lwc1    $f2,(0x04 *  3)(a0)
+	lwc1    $f3,(0x04 *  4)(a0)
+	lwc1    $f4,(0x04 *  5)(a0)
+	lwc1    $f5,(0x04 *  6)(a0)
+	lwc1    $f6,(0x04 *  7)(a0)
+	lwc1    $f7,(0x04 *  8)(a0)
+	lwc1    $f8,(0x04 *  9)(a0)
+	lwc1    $f9,(0x04 * 10)(a0)
+	lwc1   $f10,(0x04 * 11)(a0)
+	lwc1   $f11,(0x04 * 12)(a0)
+	lwc1   $f12,(0x04 * 13)(a0)
+	lwc1   $f13,(0x04 * 14)(a0)
+	lwc1   $f14,(0x04 * 15)(a0)
+	lwc1   $f15,(0x04 * 16)(a0)
+	lwc1   $f16,(0x04 * 17)(a0)
+	lwc1   $f17,(0x04 * 18)(a0)
+	lwc1   $f18,(0x04 * 19)(a0)
+	lwc1   $f19,(0x04 * 20)(a0)
+	lwc1   $f20,(0x04 * 21)(a0)
+	lwc1   $f21,(0x04 * 22)(a0)
+	lwc1   $f22,(0x04 * 23)(a0)
+	lwc1   $f23,(0x04 * 24)(a0)
+	lwc1   $f24,(0x04 * 25)(a0)
+	lwc1   $f25,(0x04 * 26)(a0)
+	lwc1   $f26,(0x04 * 27)(a0)
+	lwc1   $f27,(0x04 * 28)(a0)
+	lwc1   $f28,(0x04 * 29)(a0)
+	lwc1   $f29,(0x04 * 30)(a0)
+	lwc1   $f30,(0x04 * 31)(a0)
+	lwc1   $f31,(0x04 * 32)(a0)
+    ctc1 	t0,     CP1_STATUS                                            ;/*  restore fpp status reg      */
+
+	nop
+#endif
+
+	/* ͨüĴ */
+	/* ZERO */
+	lw		$1,  	( 1 * 4)(sp)
+	/* V0   */
+	lw		$3,  	( 3 * 4)(sp)
+	lw		$4,  	( 4 * 4)(sp)
+	lw		$5,  	( 5 * 4)(sp)
+	lw		$6,  	( 6 * 4)(sp)
+	lw		$7,  	( 7 * 4)(sp)
+	lw		$8, 	( 8 * 4)(sp)
+	lw		$9, 	( 9 * 4)(sp)
+	lw		$10,    (10 * 4)(sp)
+	lw		$11,    (11 * 4)(sp)
+	lw		$12,    (12 * 4)(sp)
+	lw		$13,    (13 * 4)(sp)
+	lw		$14,    (14 * 4)(sp)
+	lw		$15,    (15 * 4)(sp)
+	lw		$16,    (16 * 4)(sp)
+	lw		$17,    (17 * 4)(sp)
+	lw		$18,    (18 * 4)(sp)
+	lw		$19,    (19 * 4)(sp)
+	lw		$20,    (20 * 4)(sp)
+	lw		$21,    (21 * 4)(sp)
+	lw		$22,    (22 * 4)(sp)
+	lw		$23, 	(23 * 4)(sp)
+	lw		$24, 	(24 * 4)(sp)
+	lw		$25, 	(25 * 4)(sp)
+	lw		$26, 	(26 * 4)(sp)
+	lw		$27, 	(27 * 4)(sp)
+	lw		$28, 	(28 * 4)(sp)
+	/* SP */
+	lw		$30, 	(30 * 4)(sp)
+	lw		$31, 	(31 * 4)(sp)
+
+
+	/* STATUS CAUSE EPC.... */
+	lw		$2,    STK_OFFSET_HI(sp)
+	mthi	$2
+	lw		$2, 	STK_OFFSET_LO(sp)
+	mtlo	$2
+
+	lw		$2, 	STK_OFFSET_SR(sp)
+	mtc0	$2, 	CP0_STATUS
+
+	lw		$2, 	STK_OFFSET_BADVADDR(sp)
+	mtc0	$2, 	CP0_BADVADDR
+
+	lw		$2, 	STK_OFFSET_CAUSE(sp)
+	mtc0	$2, 	CP0_CAUSE
+
+	lw		$2, 	STK_OFFSET_EPC(sp)
+	MTC0	$2, 	CP0_EPC
+
+	//restore $2
+	lw		$2,  	( 2 * 4)(sp)
+	//restore sp
+	lw		$29, 	(29 * 4)(sp)
+
+	eret
+	nop
+    .set    pop
+.endm
+#endif
+#endif /* _MIPS_CONTEXT_ASM_H_ */

libcpu/mips/xburst/stack.h → bsp/x1000/cpu/common/mips_excpt.h

 /*
- * File      : stack.h
- * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
+ * File      : mips_excpt.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,11 +19,21 @@
  *
  * Change Logs:
  * Date           Author       Notes
-*/
+ * 2016Äê9ÔÂ7ÈÕ     Urey         the first version
+ */
 
-#ifndef __STACK_H__
-#define __STACK_H__
+#ifndef _MIPS_EXCPT_H_
+#define _MIPS_EXCPT_H_
 
-#define SYSTEM_STACK          0x80003fe8		/* the kernel system stack address */
+#include "mips_regs.h"
 
-#endif
+#ifndef __ASSEMBLY__
+typedef void (* exception_func_t)(mips_reg_ctx *regs);
+
+//extern exception_func_t mips_exception_handlers[];
+
+int rt_hw_exception_init(void);
+exception_func_t rt_set_except_vector(int n, exception_func_t func);
+void install_default_execpt_handle(void);
+#endif /* __ASSEMBLY__ */
+#endif /* _MIPS_EXCPT_H_ */

libcpu/mips/xburst/exception.c → bsp/x1000/cpu/common/mips_types.h

 /*
- * File      : exception.c
- * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
+ * File      : mips_types.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
  *
  *  This program is free software; you can redistribute it and/or modify
  *  it under the terms of the GNU General Public License as published by
@@ -18,64 +19,100 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2010-05-17     swkyer       first version
+ * 201697     Urey         the first version
  */
-#include <rtthread.h>
-#include <rthw.h>
-#include "../common/exception.h"
-#include "../common/mipsregs.h"
 
-/**
- * @addtogroup Ingenic
- */
-/*@{*/
+#ifndef _MIPS_TYPES_H_
+#define _MIPS_TYPES_H_
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
 
-/**
- * exception handle table
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
  */
-exception_func_t sys_exception_handlers[33];
 
-/**
- * setup the exception handle
+typedef __signed__ char     __s8;
+typedef unsigned char       __u8;
+
+typedef __signed__ short    __s16;
+typedef unsigned short      __u16;
+
+typedef __signed__ int      __s32;
+typedef unsigned int        __u32;
+
+#if (_MIPS_SZLONG == 64)
+
+typedef __signed__ long     __s64;
+typedef unsigned long       __u64;
+
+#else
+
+#if defined(__GNUC__)
+__extension__ typedef __signed__ long long __s64;
+__extension__ typedef unsigned long long __u64;
+#endif
+
+#endif
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
  */
-exception_func_t rt_set_except_vector(int n, exception_func_t func)
-{
-    exception_func_t old_handler = sys_exception_handlers[n];
 
-    if ((n == 0) || (n > 32) || (!func))
-    {
-        return 0;
-    }
+#define BITS_PER_LONG _MIPS_SZLONG
+
+
+typedef __signed char s8;
+typedef unsigned char u8;
+
+typedef __signed short s16;
+typedef unsigned short u16;
+
+typedef __signed int s32;
+typedef unsigned int u32;
+
+#if (_MIPS_SZLONG == 64)
 
-    sys_exception_handlers[n] = func;
+typedef __signed__ long s64;
+typedef unsigned long u64;
 
-    return old_handler;
-}
+#else
 
-void tlb_refill_handler(void)
-{
-    rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
-    rt_hw_cpu_shutdown();
-}
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long s64;
+typedef unsigned long long u64;
+#endif
 
-void cache_error_handler(void)
-{
-    rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
-    rt_hw_cpu_shutdown();
-}
+#endif
 
-static void unhandled_exception_handle(pt_regs_t *regs)
-{
-    rt_kprintf("exception happens, epc: 0x%08x\n", regs->cp0_epc);
-}
+#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \
+    || defined(CONFIG_64BIT)
+typedef u64 dma_addr_t;
 
-void install_default_execpt_handle(void)
-{
-    rt_int32_t i;
+typedef u64 phys_addr_t;
+typedef u64 phys_size_t;
+
+#else
+typedef u32 dma_addr_t;
+
+typedef u32 phys_addr_t;
+typedef u32 phys_size_t;
+
+#endif
+typedef u64 dma64_addr_t;
+
+/*
+ * Don't use phys_t.  You've been warned.
+ */
+#ifdef CONFIG_64BIT_PHYS_ADDR
+typedef unsigned long long phys_t;
+#else
+typedef unsigned long phys_t;
+#endif
 
-    for (i=0; i<33; i++)
-        sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
-}
+#endif /* __ASSEMBLY__ */
 
-/*@}*/
 
+#endif /* _MIPS_TYPES_H_ */

bsp/x1000/cpu/common/mipscfg.h

+/*
+ * File      : mipscfg.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2010, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-05-27     swkyer       first version
+ */
+#ifndef __MIPSCFG_H__
+#define __MIPSCFG_H__
+
+
+typedef struct mips32_core_cfg
+{
+    rt_uint16_t icache_line_size;
+    rt_uint16_t icache_lines_per_way;
+    rt_uint16_t icache_ways;
+    rt_uint16_t dcache_line_size;
+    rt_uint16_t dcache_lines_per_way;
+    rt_uint16_t dcache_ways;
+
+    rt_uint16_t max_tlb_entries;	/* number of tlb entry */
+} mips32_core_cfg_t;
+
+extern mips32_core_cfg_t g_mips_core;
+
+#endif /* end of __MIPSCFG_H__ */

bsp/x1000/cpu/common/stackframe.h

+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
+ * Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2007  Maciej W. Rozycki
+ */
+#ifndef __STACKFRAME_H__
+#define __STACKFRAME_H__
+
+#include "asm.h"
+#include "mipsregs.h"
+
+/*
+ * Stack layout for the INT exception handler
+ * Derived from the stack layout described in asm-mips/stackframe.h
+ *
+ * The first PTRSIZE*6 bytes are argument save space for C subroutines.
+ */
+
+//#define PT_R0		(PTRSIZE*6)			/* 0 */
+#define PT_R0		(0)						/* 0 */
+#define PT_R1		((PT_R0) + LONGSIZE)	/* 1 */
+#define PT_R2		((PT_R1) + LONGSIZE)	/* 2 */
+#define PT_R3		((PT_R2) + LONGSIZE)	/* 3 */
+#define PT_R4		((PT_R3) + LONGSIZE)	/* 4 */
+#define PT_R5		((PT_R4) + LONGSIZE)	/* 5 */
+#define PT_R6		((PT_R5) + LONGSIZE)	/* 6 */
+#define PT_R7		((PT_R6) + LONGSIZE)	/* 7 */
+#define PT_R8		((PT_R7) + LONGSIZE)	/* 8 */
+#define PT_R9		((PT_R8) + LONGSIZE)	/* 9 */
+#define PT_R10		((PT_R9) + LONGSIZE)	/* 10 */
+#define PT_R11		((PT_R10) + LONGSIZE)	/* 11 */
+#define PT_R12		((PT_R11) + LONGSIZE)	/* 12 */
+#define PT_R13		((PT_R12) + LONGSIZE)	/* 13 */
+#define PT_R14		((PT_R13) + LONGSIZE)	/* 14 */
+#define PT_R15		((PT_R14) + LONGSIZE)	/* 15 */
+#define PT_R16		((PT_R15) + LONGSIZE)	/* 16 */
+#define PT_R17		((PT_R16) + LONGSIZE)	/* 17 */
+#define PT_R18		((PT_R17) + LONGSIZE)	/* 18 */
+#define PT_R19		((PT_R18) + LONGSIZE)	/* 19 */
+#define PT_R20		((PT_R19) + LONGSIZE)	/* 20 */
+#define PT_R21		((PT_R20) + LONGSIZE)	/* 21 */
+#define PT_R22		((PT_R21) + LONGSIZE)	/* 22 */
+#define PT_R23		((PT_R22) + LONGSIZE)	/* 23 */
+#define PT_R24		((PT_R23) + LONGSIZE)	/* 24 */
+#define PT_R25		((PT_R24) + LONGSIZE)	/* 25 */
+#define PT_R26		((PT_R25) + LONGSIZE)	/* 26 */
+#define PT_R27		((PT_R26) + LONGSIZE)	/* 27 */
+#define PT_R28		((PT_R27) + LONGSIZE)	/* 28 */
+#define PT_R29		((PT_R28) + LONGSIZE)	/* 29 */
+#define PT_R30		((PT_R29) + LONGSIZE)	/* 30 */
+#define PT_R31		((PT_R30) + LONGSIZE)	/* 31 */
+
+/*
+ * Saved special registers
+ */
+#define PT_STATUS	((PT_R31) + LONGSIZE)	/* 32 */
+#define PT_HI		((PT_STATUS) + LONGSIZE)	/* 33 */
+#define PT_LO		((PT_HI) + LONGSIZE)	/* 34 */
+#define PT_BADVADDR	((PT_LO) + LONGSIZE)	/* 35 */
+#define PT_CAUSE	((PT_BADVADDR) + LONGSIZE)	/* 36 */
+#define PT_EPC		((PT_CAUSE) + LONGSIZE)	/* 37 */
+
+#define PT_SIZE		((((PT_EPC) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
+
+
+		.macro	SAVE_AT
+		.set	push
+		.set	noat
+		LONG_S	$1, PT_R1(sp)
+		.set	pop
+		.endm
+
+		.macro	SAVE_TEMP
+		mfhi	v1
+		LONG_S	$8, PT_R8(sp)
+		LONG_S	$9, PT_R9(sp)
+		LONG_S	v1, PT_HI(sp)
+		mflo	v1
+		LONG_S	$10, PT_R10(sp)
+		LONG_S	$11, PT_R11(sp)
+		LONG_S	v1,  PT_LO(sp)
+		LONG_S	$12, PT_R12(sp)
+		LONG_S	$13, PT_R13(sp)
+		LONG_S	$14, PT_R14(sp)
+		LONG_S	$15, PT_R15(sp)
+		LONG_S	$24, PT_R24(sp)
+		.endm
+
+		.macro	SAVE_STATIC
+		LONG_S	$16, PT_R16(sp)
+		LONG_S	$17, PT_R17(sp)
+		LONG_S	$18, PT_R18(sp)
+		LONG_S	$19, PT_R19(sp)
+		LONG_S	$20, PT_R20(sp)
+		LONG_S	$21, PT_R21(sp)
+		LONG_S	$22, PT_R22(sp)
+		LONG_S	$23, PT_R23(sp)
+		LONG_S	$30, PT_R30(sp)
+		.endm
+
+		.macro	get_saved_sp
+		nop
+		.endm
+
+		.macro	SAVE_SOME
+		.set	push
+		.set	noat
+		.set	reorder
+        move	k1, sp
+8:		move	k0, sp
+		PTR_SUBU sp, k1, PT_SIZE
+		LONG_S	k0, PT_R29(sp)
+		LONG_S	$3, PT_R3(sp)
+		LONG_S	$0, PT_R0(sp)
+		mfc0	v1, CP0_STATUS
+		LONG_S	$2, PT_R2(sp)
+		LONG_S	v1, PT_STATUS(sp)
+		LONG_S	$4, PT_R4(sp)
+		mfc0	v1, CP0_CAUSE
+		LONG_S	$5, PT_R5(sp)
+		LONG_S	v1, PT_CAUSE(sp)
+		LONG_S	$6, PT_R6(sp)
+		MFC0	v1, CP0_EPC
+		LONG_S	$7, PT_R7(sp)
+		LONG_S	v1, PT_EPC(sp)
+		LONG_S	$25, PT_R25(sp)
+		LONG_S	$28, PT_R28(sp)
+		LONG_S	$31, PT_R31(sp)
+		.set	pop
+		.endm
+
+		.macro	SAVE_ALL
+		SAVE_SOME
+		SAVE_AT
+		SAVE_TEMP
+		SAVE_STATIC
+		.endm
+
+		.macro	RESTORE_AT
+		.set	push
+		.set	noat
+		LONG_L	$1,  PT_R1(sp)
+		.set	pop
+		.endm
+
+		.macro	RESTORE_TEMP
+		LONG_L	$24, PT_LO(sp)
+		LONG_L	$8, PT_R8(sp)
+		LONG_L	$9, PT_R9(sp)
+		mtlo	$24
+		LONG_L	$24, PT_HI(sp)
+		LONG_L	$10, PT_R10(sp)
+		LONG_L	$11, PT_R11(sp)
+		mthi	$24
+		LONG_L	$12, PT_R12(sp)
+		LONG_L	$13, PT_R13(sp)
+		LONG_L	$14, PT_R14(sp)
+		LONG_L	$15, PT_R15(sp)
+		LONG_L	$24, PT_R24(sp)
+		.endm
+
+		.macro	RESTORE_STATIC
+		LONG_L	$16, PT_R16(sp)
+		LONG_L	$17, PT_R17(sp)
+		LONG_L	$18, PT_R18(sp)
+		LONG_L	$19, PT_R19(sp)
+		LONG_L	$20, PT_R20(sp)
+		LONG_L	$21, PT_R21(sp)
+		LONG_L	$22, PT_R22(sp)
+		LONG_L	$23, PT_R23(sp)
+		LONG_L	$30, PT_R30(sp)
+		.endm
+
+		.macro	RESTORE_SOME
+		.set	push
+		.set	reorder
+		.set	noat
+		LONG_L	v0, PT_STATUS(sp)
+		mtc0	v0, CP0_STATUS
+		LONG_L	v1, PT_EPC(sp)
+		MTC0	v1, CP0_EPC
+		LONG_L	$31, PT_R31(sp)
+		LONG_L	$28, PT_R28(sp)
+		LONG_L	$25, PT_R25(sp)
+		LONG_L	$7,  PT_R7(sp)
+		LONG_L	$6,  PT_R6(sp)
+		LONG_L	$5,  PT_R5(sp)
+		LONG_L	$4,  PT_R4(sp)
+		LONG_L	$3,  PT_R3(sp)
+		LONG_L	$2,  PT_R2(sp)
+		.set	pop
+		.endm
+
+		.macro	RESTORE_SP_AND_RET
+		LONG_L	sp, PT_R29(sp)
+		.set	mips3
+		eret
+		.set	mips0
+		.endm
+
+
+		.macro	RESTORE_SP
+		LONG_L	sp, PT_R29(sp)
+		.endm
+
+		.macro	RESTORE_ALL
+		RESTORE_TEMP
+		RESTORE_STATIC
+		RESTORE_AT
+		RESTORE_SOME
+		RESTORE_SP
+		.endm
+
+		.macro	RESTORE_ALL_AND_RET
+		RESTORE_TEMP
+		RESTORE_STATIC
+		RESTORE_AT
+		RESTORE_SOME
+		RESTORE_SP_AND_RET
+		.endm
+
+#endif /* end of __STACKFRAME_H__ */
+

libcpu/mips/xburst/SConscript → bsp/x1000/cpu/x1000/SConscript

@@ -2,10 +2,13 @@
 
 from building import *
 
-cwd = GetCurrentDir()
-src = Glob('*.c') + Glob('*.S')
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
 CPPPATH = [cwd]
+ASFLAGS = ''
 
-group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH)
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
 
 Return('group')

bsp/x1000/rtconfig.py

@@ -10,7 +10,7 @@ if os.getenv('RTT_CC'):
 
 if  CROSS_TOOL == 'gcc':
     PLATFORM    = 'gcc'
-    EXEC_PATH   = r'E:\work\env\tools\gnu_gcc\mips_gcc\mips-2016.05\bin'
+    EXEC_PATH   = r'/opt/mips-2016.05/bin/'
 else:
     print('Please make sure your toolchains is GNU GCC!')
     exit(0)

libcpu/mips/xburst/cache.c

-/*
- * File      : cache.c
- * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
-*/
-
-#include "../xburst/cache.h"
-
-#include <board.h>
-
-#define CACHE_SIZE              16*1024
-#define CACHE_LINE_SIZE         32
-#define KSEG0                   0x80000000
-
-#define K0_TO_K1()              \
-do {                        \
-    unsigned long __k0_addr;        \
-                        \
-    __asm__ __volatile__(           \
-    "la %0, 1f\n\t"             \
-    "or %0, %0, %1\n\t"         \
-    "jr %0\n\t"             \
-    "nop\n\t"               \
-    "1: nop\n"              \
-    : "=&r"(__k0_addr)          \
-    : "r" (0x20000000) );           \
-} while(0)
-
-#define K1_TO_K0()              \
-do {                        \
-    unsigned long __k0_addr;        \
-    __asm__ __volatile__(           \
-    "nop;nop;nop;nop;nop;nop;nop\n\t"   \
-    "la %0, 1f\n\t"             \
-    "jr %0\n\t"             \
-    "nop\n\t"               \
-    "1: nop\n"              \
-    : "=&r" (__k0_addr));           \
-} while (0)
-
-#define INVALIDATE_BTB()            \
-do {                        \
-    unsigned long tmp;          \
-    __asm__ __volatile__(           \
-    ".set mips32\n\t"           \
-    "mfc0 %0, $16, 7\n\t"           \
-    "nop\n\t"               \
-    "ori %0, 2\n\t"             \
-    "mtc0 %0, $16, 7\n\t"           \
-    "nop\n\t"               \
-    ".set mips2\n\t"            \
-    : "=&r" (tmp));             \
-} while (0)
-
-#define SYNC_WB() __asm__ __volatile__ ("sync")
-
-#define cache_op(op,addr)                       \
-    __asm__ __volatile__(                       \
-    "   .set    noreorder       \n"         \
-    "   .set    mips32\n\t      \n"         \
-    "   cache   %0, %1          \n"         \
-    "   .set    mips0           \n"         \
-    "   .set    reorder"                    \
-    :                                       \
-    : "i" (op), "m" (*(unsigned char *)(addr)))
-
-void __icache_invalidate_all(void)
-{
-    unsigned int i;
-
-    K0_TO_K1();
-
-    asm volatile (".set noreorder\n"
-              ".set mips32\n\t"
-              "mtc0\t$0,$28\n\t"
-              "mtc0\t$0,$29\n"
-              ".set mips0\n"
-              ".set reorder\n");
-    for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
-        cache_op(Index_Store_Tag_I, i);
-
-    K1_TO_K0();
-
-    INVALIDATE_BTB();
-}
-
-void __dcache_writeback_all(void)
-{
-    unsigned int i;
-
-    for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
-        cache_op(Index_Writeback_Inv_D, i);
-
-    SYNC_WB();
-}
-
-void rt_hw_cache_init(void)
-{
-    __dcache_writeback_all();
-    __icache_invalidate_all();
-}
-

libcpu/mips/xburst/cache.h

-/*
- * File      : cache.h
- * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
-*/
-
-#ifndef __CACHE_H__
-#define __CACHE_H__
-
-/*
- * Cache Operations
- */
-#define Index_Invalidate_I          0x00
-#define Index_Writeback_Inv_D    0x01
-#define Index_Invalidate_SI         0x02
-#define Index_Writeback_Inv_SD  0x03
-#define Index_Load_Tag_I        0x04
-#define Index_Load_Tag_D        0x05
-#define Index_Load_Tag_SI       0x06
-#define Index_Load_Tag_SD       0x07
-#define Index_Store_Tag_I       0x08
-#define Index_Store_Tag_D       0x09
-#define Index_Store_Tag_SI      0x0A
-#define Index_Store_Tag_SD      0x0B
-#define Create_Dirty_Excl_D     0x0d
-#define Create_Dirty_Excl_SD        0x0f
-#define Hit_Invalidate_I            0x10
-#define Hit_Invalidate_D            0x11
-#define Hit_Invalidate_SI           0x12
-#define Hit_Invalidate_SD           0x13
-#define Fill                        0x14
-#define Hit_Writeback_Inv_D     0x15
-/* 0x16 is unused */
-#define Hit_Writeback_Inv_SD        0x17
-#define Hit_Writeback_I         0x18
-#define Hit_Writeback_D         0x19
-/* 0x1a is unused */
-#define Hit_Writeback_SD            0x1b
-/* 0x1c is unused */
-/* 0x1e is unused */
-#define Hit_Set_Virtual_SI      0x1e
-#define Hit_Set_Virtual_SD      0x1f
-
-void rt_hw_cache_init(void);
-
-#endif

libcpu/mips/xburst/cache_gcc.S

-/*
- * Copyright (c) 2006-2019, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2019-07-19     Zhou Yanjie  clean up code
- */
-
-#ifndef __ASSEMBLY__
-#define __ASSEMBLY__
-#endif
-
-#include "../common/mips_def.h"
-#include "../common/mipsregs.h"
-#include "../common/stackframe.h"
-
-    .text
-    .set noreorder
-
-    .globl  cache_init
-    .ent    cache_init
-cache_init:
-    .set    noreorder
-    mtc0    zero, CP0_TAGLO
-    move    t0, a0                  // cache total size
-    move    t1, a1                  // cache line size
-    li      t2, 0x80000000
-    addu    t3, t0, t2
-
-_cache_init_loop:
-    cache   8, 0(t2)                // icache_index_store_tag
-    cache   9, 0(t2)                // dcache_index_store_tag
-    addu    t2, t1
-    bne     t2, t3, _cache_init_loop
-    nop
-
-    mfc0    t0, CP0_CONFIG
-    li      t1, 0x7
-    not     t1
-    and     t0, t0, t1
-    or      t0, 0x3                 // cacheable, noncoherent, write-back, write allocate
-    mtc0    t0, CP0_CONFIG
-
-    jr      ra
-    nop
-
-    .set    reorder
-    .end    cache_init

libcpu/mips/xburst/stack.c

-/*
- * File      : stack.c
- * COPYRIGHT (C) 2008 - 2016, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-07-07     Bernard      porting to Ingenic CPU
- */
-#include <rtthread.h>
-
-/**
- * @addtogroup Ingenic
- */
-/*@{*/
-
-extern rt_uint32_t cp0_get_cause(void);
-extern rt_uint32_t cp0_get_status(void);
-extern rt_uint32_t cp0_get_hi(void);
-extern rt_uint32_t cp0_get_lo(void);
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
-{
-    rt_uint32_t *stk;
-    static rt_uint32_t g_sr = 0;
-
-    if (g_sr == 0)
-    {
-        g_sr = cp0_get_status();
-        g_sr &= 0xfffffffe;
-        g_sr |= 0x0403;
-    }
-
-    /** Start at stack top */
-    stk = (rt_uint32_t *)stack_addr;
-    *(stk)   = (rt_uint32_t) tentry;        /* pc: Entry Point */
-    *(--stk) = (rt_uint32_t) 0xeeee;        /* c0_cause */
-    *(--stk) = (rt_uint32_t) 0xffff;        /* c0_badvaddr */
-    *(--stk) = (rt_uint32_t) cp0_get_lo();  /* lo */
-    *(--stk) = (rt_uint32_t) cp0_get_hi();  /* hi */
-    *(--stk) = (rt_uint32_t) g_sr;          /* C0_SR: HW2 = En, IE = En */
-    *(--stk) = (rt_uint32_t) texit;         /* ra */
-    *(--stk) = (rt_uint32_t) 0x0000001e;    /* s8 */
-    *(--stk) = (rt_uint32_t) stack_addr;    /* sp */
-    *(--stk) = (rt_uint32_t) 0x0000001c;    /* gp */
-    *(--stk) = (rt_uint32_t) 0x0000001b;    /* k1 */
-    *(--stk) = (rt_uint32_t) 0x0000001a;    /* k0 */
-    *(--stk) = (rt_uint32_t) 0x00000019;    /* t9 */
-    *(--stk) = (rt_uint32_t) 0x00000018;    /* t8 */
-    *(--stk) = (rt_uint32_t) 0x00000017;    /* s7 */
-    *(--stk) = (rt_uint32_t) 0x00000016;    /* s6 */
-    *(--stk) = (rt_uint32_t) 0x00000015;    /* s5 */
-    *(--stk) = (rt_uint32_t) 0x00000014;    /* s4 */
-    *(--stk) = (rt_uint32_t) 0x00000013;    /* s3 */
-    *(--stk) = (rt_uint32_t) 0x00000012;    /* s2 */
-    *(--stk) = (rt_uint32_t) 0x00000011;    /* s1 */
-    *(--stk) = (rt_uint32_t) 0x00000010;    /* s0 */
-    *(--stk) = (rt_uint32_t) 0x0000000f;    /* t7 */
-    *(--stk) = (rt_uint32_t) 0x0000000e;    /* t6 */
-    *(--stk) = (rt_uint32_t) 0x0000000d;    /* t5 */
-    *(--stk) = (rt_uint32_t) 0x0000000c;    /* t4 */
-    *(--stk) = (rt_uint32_t) 0x0000000b;    /* t3 */
-    *(--stk) = (rt_uint32_t) 0x0000000a;    /* t2 */
-    *(--stk) = (rt_uint32_t) 0x00000009;    /* t1 */
-    *(--stk) = (rt_uint32_t) 0x00000008;    /* t0 */
-    *(--stk) = (rt_uint32_t) 0x00000007;    /* a3 */
-    *(--stk) = (rt_uint32_t) 0x00000006;    /* a2 */
-    *(--stk) = (rt_uint32_t) 0x00000005;    /* a1 */
-    *(--stk) = (rt_uint32_t) parameter;     /* a0 */
-    *(--stk) = (rt_uint32_t) 0x00000003;    /* v1 */
-    *(--stk) = (rt_uint32_t) 0x00000002;    /* v0 */
-    *(--stk) = (rt_uint32_t) 0x00000001;    /* at */
-    *(--stk) = (rt_uint32_t) 0x00000000;    /* zero */
-
-    /* return task's current stack address */
-    return (rt_uint8_t *)stk;
-}
-
-/*@}*/