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提交 5d166c38 编写于 作者: xuzhuoyi96's avatar xuzhuoyi96
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[bsp][gd32e230k-start] Add GD32E230K-START BSP port

上级 459ddc3b
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bsp/gd32e230k-start/.config 0 → 100644
浏览文件 @ 5d166c38
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_DEBUG_INIT=0
CONFIG_RT_DEBUG_THREAD=0
CONFIG_RT_USING_HOOK=y
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_MEMHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
# CONFIG_RT_USING_MODULE is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
# CONFIG_FINSH_USING_MSH_ONLY is not set
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=2
CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
CONFIG_DFS_FD_MAX=4
CONFIG_RT_USING_DFS_ELMFAT=y
#
# elm-chan's FatFs, Generic FAT Filesystem Module
#
CONFIG_RT_DFS_ELM_CODE_PAGE=437
CONFIG_RT_DFS_ELM_WORD_ACCESS=y
CONFIG_RT_DFS_ELM_USE_LFN_0=y
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_3 is not set
CONFIG_RT_DFS_ELM_USE_LFN=0
CONFIG_RT_DFS_ELM_MAX_LFN=255
CONFIG_RT_DFS_ELM_DRIVES=2
CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=4096
# CONFIG_RT_DFS_ELM_USE_ERASE is not set
CONFIG_RT_DFS_ELM_REENTRANT=y
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_NET is not set
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_UFFS is not set
# CONFIG_RT_USING_DFS_JFFS2 is not set
# CONFIG_RT_USING_DFS_NFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_SERIAL_USING_DMA=y
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
CONFIG_RT_USING_I2C=y
# CONFIG_RT_USING_I2C_BITOPS is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_SPI_MSD is not set
CONFIG_RT_USING_SFUD=y
# CONFIG_RT_SFUD_USING_SFDP is not set
CONFIG_RT_SFUD_USING_FLASH_INFO_TABLE=y
# CONFIG_RT_SFUD_DEBUG is not set
# CONFIG_RT_USING_W25QXX is not set
# CONFIG_RT_USING_GD is not set
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_POSIX is not set
# CONFIG_HAVE_SYS_SIGNALS is not set
#
# Network stack
#
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
# CONFIG_RT_USING_LWIP141 is not set
# CONFIG_RT_USING_LWIP202 is not set
#
# Modbus master and slave stack
#
# CONFIG_RT_USING_MODBUS is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_LOGTRACE is not set
# CONFIG_RT_USING_RYM is not set
#
# RT-Thread online packages
#
#
# system packages
#
#
# RT-Thread GUI Engine
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
#
# IoT - internet of things
#
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_ONENET is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
#
# language packages
#
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_IPERF is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_SAMPLES is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
#
# example package: hello
#
# CONFIG_PKG_USING_HELLO is not set
CONFIG_RT_USING_USART0=y
CONFIG_RT_USING_USART1=y
# CONFIG_RT_USING_USART2 is not set
# CONFIG_RT_USING_UART3 is not set
# CONFIG_RT_USING_UART4 is not set
CONFIG_RT_USING_SPI0=y
CONFIG_RT_USING_SPI1=y
# CONFIG_RT_USING_SPI2 is not set
CONFIG_RT_USING_I2C0=y
# CONFIG_RT_USING_I2C1 is not set
bsp/gd32e230k-start/Kconfig 0 → 100644
浏览文件 @ 5d166c38
mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
config RT_USING_USART0
bool "Using USART0"
select RT_USING_SERIAL
default y
config RT_USING_USART1
bool "Using USART1"
select RT_USING_SERIAL
default n
config RT_USING_USART2
bool "Using USART2"
select RT_USING_SERIAL
default n
config RT_USING_UART3
bool "Using UART3"
select RT_USING_SERIAL
default n
config RT_USING_UART4
bool "Using UART4"
select RT_USING_SERIAL
default n
config RT_USING_SPI0
bool "Using SPI0"
select RT_USING_SPI
default y
config RT_USING_SPI1
bool "Using SPI1"
select RT_USING_SPI
default n
config RT_USING_SPI2
bool "Using SPI2"
select RT_USING_SPI
default n
config RT_USING_I2C0
bool "Using I2C0"
select RT_USING_I2C
default n
config RT_USING_I2C1
bool "Using I2C1"
select RT_USING_I2C
default n
bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Include/gd32e230.h 0 → 100644
浏览文件 @ 5d166c38
/*!
\file gd32e230.h
\brief general definitions for GD32E230
\version 2018-06-19, V1.0.0, firmware for GD32E230
*/
/*
Copyright (c) 2018, GigaDevice Semiconductor Inc.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E230_H
#define GD32E230_H
#ifdef __cplusplus
extern "C" {
#endif
/* define GD32E230 */
#if !defined (GD32E230)
#define GD32E230
#endif /* define GD32E230 */
#if !defined (GD32E230)
#error "Please select the target GD32E230 device used in your application (in gd32e230.h file)"
#endif /* undefine GD32E230 tip */
/* define value of high speed crystal oscillator (HXTAL) in Hz */
#if !defined (HXTAL_VALUE)
#define HXTAL_VALUE ((uint32_t)8000000)
#endif /* high speed crystal oscillator value */
/* define startup timeout value of high speed crystal oscillator (HXTAL) */
#if !defined (HXTAL_STARTUP_TIMEOUT)
#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0800)
#endif /* high speed crystal oscillator startup timeout */
/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
#if !defined (IRC8M_VALUE)
#define IRC8M_VALUE ((uint32_t)8000000)
#endif /* internal 8MHz RC oscillator value */
/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
#if !defined (IRC8M_STARTUP_TIMEOUT)
#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500)
#endif /* internal 8MHz RC oscillator startup timeout */
/* define value of internal RC oscillator for ADC in Hz */
#if !defined (IRC28M_VALUE)
#define IRC28M_VALUE ((uint32_t)28000000)
#endif /* IRC28M_VALUE */
#if !defined (IRC48M_VALUE)
#define IRC48M_VALUE ((uint32_t)48000000)
#endif /* IRC48M_VALUE */
/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
#if !defined (IRC40K_VALUE)
#define IRC40K_VALUE ((uint32_t)40000)
#endif /* internal 40KHz RC oscillator value */
/* define value of low speed crystal oscillator (LXTAL)in Hz */
#if !defined (LXTAL_VALUE)
#define LXTAL_VALUE ((uint32_t)32768)
#endif /* low speed crystal oscillator value */
/* GD32E1x0 firmware library version number V1.0 */
#define __GD32E230_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __GD32E230_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
#define __GD32E230_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __GD32E230_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __GD32E230_STDPERIPH_VERSION ((__GD32E230_STDPERIPH_VERSION_MAIN << 24)\
|(__GD32E230_STDPERIPH_VERSION_SUB1 << 16)\
|(__GD32E230_STDPERIPH_VERSION_SUB2 << 8)\
|(__GD32E230_STDPERIPH_VERSION_RC))
/* configuration of the Cortex-M23 processor and core peripherals */
#define __CM23_REV 0x0100U /*!< Core revision r1p0 */
#define __SAUREGION_PRESENT 0U /*!< SAU regions are not present */
#define __MPU_PRESENT 0U /*!< MPU is present */
#define __VTOR_PRESENT 1U /*!< VTOR is present */
#define __NVIC_PRIO_BITS 2U /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
/* define interrupt number */
typedef enum IRQn
{
/* Cortex-M23 processor exceptions numbers */
NonMaskableInt_IRQn = -14, /*!< non maskable interrupt */
HardFault_IRQn = -13, /*!< hardfault interrupt */
SVCall_IRQn = -5, /*!< sv call interrupt */
PendSV_IRQn = -2, /*!< pend sv interrupt */
SysTick_IRQn = -1, /*!< system tick interrupt */
/* interruput numbers */
WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */
LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
RTC_IRQn = 2, /*!< RTC through EXTI line interrupt */
FMC_IRQn = 3, /*!< FMC interrupt */
RCU_IRQn = 4, /*!< RCU interrupt */
EXTI0_1_IRQn = 5, /*!< EXTI line 0 and 1 interrupts */
EXTI2_3_IRQn = 6, /*!< EXTI line 2 and 3 interrupts */
EXTI4_15_IRQn = 7, /*!< EXTI line 4 to 15 interrupts */
DMA_Channel0_IRQn = 9, /*!< DMA channel 0 interrupt */
DMA_Channel1_2_IRQn = 10, /*!< DMA channel 1 and channel 2 interrupts */
DMA_Channel3_4_IRQn = 11, /*!< DMA channel 3 and channel 4 interrupts */
ADC_CMP_IRQn = 12, /*!< ADC, CMP interrupts */
TIMER0_BRK_UP_TRG_COM_IRQn = 13, /*!< TIMER0 break, update, trigger and commutation interrupts */
TIMER0_Channel_IRQn = 14, /*!< TIMER0 channel capture compare interrupts */
TIMER2_IRQn = 16, /*!< TIMER2 interrupt */
TIMER5_IRQn = 17, /*!< TIMER5 interrupt */
TIMER13_IRQn = 19, /*!< TIMER13 interrupt */
TIMER14_IRQn = 20, /*!< TIMER14 interrupt */
TIMER15_IRQn = 21, /*!< TIMER15 interrupt */
TIMER16_IRQn = 22, /*!< TIMER16 interrupt */
I2C0_EV_IRQn = 23, /*!< I2C0 event interrupt */
I2C1_EV_IRQn = 24, /*!< I2C1 event interrupt */
SPI0_IRQn = 25, /*!< SPI0 interrupt */
SPI1_IRQn = 26, /*!< SPI1 interrupt */
USART0_IRQn = 27, /*!< USART0 interrupt */
USART1_IRQn = 28, /*!< USART1 interrupt */
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
} IRQn_Type;
/* includes */
#include "core_cm23.h"
#include "system_gd32e230.h"
#include <stdint.h>
/* enum definitions */
typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
typedef enum {RESET = 0, SET = !RESET} FlagStatus;
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
/* bit operations */
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
/* main flash and SRAM memory map */
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address */
/* SRAM and peripheral base bit-band region */
#define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM bit-band base address */
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< peripheral bit-band base address */
/* peripheral memory map */
#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */
#define AHB2_BUS_BASE ((uint32_t)0x48000000U) /*!< ahb2 base address */
/* advanced peripheral bus 1 memory map */
#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
/* advanced peripheral bus 2 memory map */
#define SYSCFG_BASE (APB2_BUS_BASE + 0x00000000U) /*!< SYSCFG base address */
#define CMP_BASE (APB2_BUS_BASE + 0x0000001CU) /*!< CMP base address */
#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
/* advanced high performance bus 1 memory map */
#define DMA_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address */
#define DMA_CHANNEL_BASE (DMA_BASE + 0x00000008U) /*!< DMA channel base address */
#define RCU_BASE (AHB1_BUS_BASE + 0x00001000U) /*!< RCU base address */
#define FMC_BASE (AHB1_BUS_BASE + 0x00002000U) /*!< FMC base address */
#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */
/* advanced high performance bus 2 memory map */
#define GPIO_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< GPIO base address */
/* option byte and debug memory map */
#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */
#define DBG_BASE ((uint32_t)0x40015800U) /*!< DBG base address */
#include "gd32e230_libopt.h"
#ifdef __cplusplus
}
#endif
#endif /* GD32E230_H */
bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Include/system_gd32e230.h 0 → 100644
浏览文件 @ 5d166c38
/*!
\file system_gd32e230.h
\brief CMSIS Cortex-M23 Device Peripheral Access Layer Header File for
GD32E230 Device Series
*/
/* Copyright (c) 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
#ifndef SYSTEM_GD32E230_H
#define SYSTEM_GD32E230_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
/* system clock frequency (core clock) */
extern uint32_t SystemCoreClock;
/* function declarations */
/* initialize the system and update the SystemCoreClock variable */
extern void SystemInit (void);
/* update the SystemCoreClock with current core clock retrieved from cpu registers */
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_GD32E230_H */
bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/ARM/startup_gd32e230.s 0 → 100644
浏览文件 @ 5d166c38
;/*!
; \file startup_gd32e230.s
; \brief start up file
;
; \version 2018-6-19, V1.0.0, firmware for GD32E230
;*/
;
;/*
; Copyright (c) 2018, GigaDevice Semiconductor Inc.
;
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without modification,
;are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
; 3. Neither the name of the copyright holder nor the names of its contributors
; may be used to endorse or promote products derived from this software without
; specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
;OF SUCH DAMAGE.
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000400
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; /* reset Vector Mapped to at Address 0 */
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; /* external interrupts handler */
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
DCD RTC_IRQHandler ; 18:RTC through EXTI Line
DCD FMC_IRQHandler ; 19:FMC
DCD RCU_IRQHandler ; 20:RCU
DCD EXTI0_1_IRQHandler ; 21:EXTI Line 0 and EXTI Line 1
DCD EXTI2_3_IRQHandler ; 22:EXTI Line 2 and EXTI Line 3
DCD EXTI4_15_IRQHandler ; 23:EXTI Line 4 to EXTI Line 15
DCD 0 ; Reserved
DCD DMA_Channel0_IRQHandler ; 25:DMA Channel 0
DCD DMA_Channel1_2_IRQHandler ; 26:DMA Channel 1 and DMA Channel 2
DCD DMA_Channel3_4_IRQHandler ; 27:DMA Channel 3 and DMA Channel 4
DCD ADC_CMP_IRQHandler ; 28:ADC and Comparator
DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; 29:TIMER0 Break,Update,Trigger and Commutation
DCD TIMER0_Channel_IRQHandler ; 30:TIMER0 Channel Capture Compare
DCD 0 ; Reserved
DCD TIMER2_IRQHandler ; 32:TIMER2
DCD TIMER5_IRQHandler ; 33:TIMER5
DCD 0 ; Reserved
DCD TIMER13_IRQHandler ; 35:TIMER13
DCD TIMER14_IRQHandler ; 36:TIMER14
DCD TIMER15_IRQHandler ; 37:TIMER15
DCD TIMER16_IRQHandler ; 38:TIMER16
DCD I2C0_EV_IRQHandler ; 39:I2C0 Event
DCD I2C1_EV_IRQHandler ; 40:I2C1 Event
DCD SPI0_IRQHandler ; 41:SPI0
DCD SPI1_IRQHandler ; 42:SPI1
DCD USART0_IRQHandler ; 43:USART0
DCD USART1_IRQHandler ; 44:USART1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
DCD 0 ; Reserved
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
;/* reset Handler */
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
;/* dummy Exception Handlers */
NMI_Handler\
PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler\
PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler\
PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler\
PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
; /* external interrupts handler */
EXPORT WWDGT_IRQHandler [WEAK]
EXPORT LVD_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FMC_IRQHandler [WEAK]
EXPORT RCU_IRQHandler [WEAK]
EXPORT EXTI0_1_IRQHandler [WEAK]
EXPORT EXTI2_3_IRQHandler [WEAK]
EXPORT EXTI4_15_IRQHandler [WEAK]
EXPORT DMA_Channel0_IRQHandler [WEAK]
EXPORT DMA_Channel1_2_IRQHandler [WEAK]
EXPORT DMA_Channel3_4_IRQHandler [WEAK]
EXPORT ADC_CMP_IRQHandler [WEAK]
EXPORT TIMER0_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TIMER0_Channel_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER5_IRQHandler [WEAK]
EXPORT TIMER13_IRQHandler [WEAK]
EXPORT TIMER14_IRQHandler [WEAK]
EXPORT TIMER15_IRQHandler [WEAK]
EXPORT TIMER16_IRQHandler [WEAK]
EXPORT I2C0_EV_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT SPI0_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART0_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT I2C0_ER_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
;/* external interrupts handler */
WWDGT_IRQHandler
LVD_IRQHandler
RTC_IRQHandler
FMC_IRQHandler
RCU_IRQHandler
EXTI0_1_IRQHandler
EXTI2_3_IRQHandler
EXTI4_15_IRQHandler
DMA_Channel0_IRQHandler
DMA_Channel1_2_IRQHandler
DMA_Channel3_4_IRQHandler
ADC_CMP_IRQHandler
TIMER0_BRK_UP_TRG_COM_IRQHandler
TIMER0_Channel_IRQHandler
TIMER2_IRQHandler
TIMER5_IRQHandler
TIMER13_IRQHandler
TIMER14_IRQHandler
TIMER15_IRQHandler
TIMER16_IRQHandler
I2C0_EV_IRQHandler
I2C1_EV_IRQHandler
SPI0_IRQHandler
SPI1_IRQHandler
USART0_IRQHandler
USART1_IRQHandler
I2C0_ER_IRQHandler
I2C1_ER_IRQHandler
B .
ENDP
ALIGN
; user Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END
bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/IAR/startup_gd32e230.s 0 → 100644
浏览文件 @ 5d166c38
;/*!
; \file startup_gd32e230.s
; \brief start up file
;
; \version 2018-06-19, V1.0.0, firmware for GD32E230
;*/
;
;/*
; Copyright (c) 2018, GigaDevice Semiconductor Inc.
;
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without modification,
;are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice, this
; list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
; 3. Neither the name of the copyright holder nor the names of its contributors
; may be used to endorse or promote products derived from this software without
; specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
;OF SUCH DAMAGE.
;*/
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK) ; top of stack
DCD Reset_Handler ; Vector Number 1,Reset Handler
DCD NMI_Handler ; Vector Number 2,NMI Handler
DCD HardFault_Handler ; Vector Number 3,Hard Fault Handler
DCD MemManage_Handler ; Vector Number 4,MPU Fault Handler
DCD BusFault_Handler ; Vector Number 5,Bus Fault Handler
DCD UsageFault_Handler ; Vector Number 6,Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; Vector Number 11,SVCall Handler
DCD DebugMon_Handler ; Vector Number 12,Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; Vector Number 14,PendSV Handler
DCD SysTick_Handler ; Vector Number 15,SysTick Handler
; External Interrupts
DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
DCD RTC_IRQHandler ; 18:RTC through EXTI Line
DCD FMC_IRQHandler ; 19:FMC
DCD RCU_IRQHandler ; 20:RCU
DCD EXTI0_1_IRQHandler ; 21:EXTI Line 0 and EXTI Line 1
DCD EXTI2_3_IRQHandler ; 22:EXTI Line 2 and EXTI Line 3
DCD EXTI4_15_IRQHandler ; 23:EXTI Line 4 to EXTI Line 15
DCD 0 ; Reserved
DCD DMA_Channel0_IRQHandler ; 25:DMA Channel 0
DCD DMA_Channel1_2_IRQHandler ; 26:DMA Channel 1 and DMA Channel 2
DCD DMA_Channel3_4_IRQHandler ; 27:DMA Channel 3 and DMA Channel 4
DCD ADC_CMP_IRQHandler ; 28:ADC and Comparator
DCD TIMER0_BRK_UP_TRG_COM_IRQHandler ; 29:TIMER0 Break,Update,Trigger and Commutation
DCD TIMER0_Channel_IRQHandler ; 30:TIMER0 Channel Capture Compare
DCD 0 ; Reserved
DCD TIMER2_IRQHandler ; 32:TIMER2
DCD TIMER5_IRQHandler ; 33:TIMER5
DCD 0 ; Reserved
DCD TIMER13_IRQHandler ; 35:TIMER13
DCD TIMER14_IRQHandler ; 36:TIMER14
DCD TIMER15_IRQHandler ; 37:TIMER15
DCD TIMER16_IRQHandler ; 38:TIMER16
DCD I2C0_EV_IRQHandler ; 39:I2C0 Event
DCD I2C1_EV_IRQHandler ; 40:I2C1 Event
DCD SPI0_IRQHandler ; 41:SPI0
DCD SPI1_IRQHandler ; 42:SPI1
DCD USART0_IRQHandler ; 43:USART0
DCD USART1_IRQHandler ; 44:USART1
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
DCD 0 ; Reserved
DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDGT_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDGT_IRQHandler
B WWDGT_IRQHandler
PUBWEAK LVD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
LVD_IRQHandler
B LVD_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FMC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FMC_IRQHandler
B FMC_IRQHandler
PUBWEAK RCU_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCU_IRQHandler
B RCU_IRQHandler
PUBWEAK EXTI0_1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_1_IRQHandler
B EXTI0_1_IRQHandler
PUBWEAK EXTI2_3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_3_IRQHandler
B EXTI2_3_IRQHandler
PUBWEAK EXTI4_15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_15_IRQHandler
B EXTI4_15_IRQHandler
PUBWEAK DMA_Channel0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA_Channel0_IRQHandler
B DMA_Channel0_IRQHandler
PUBWEAK DMA_Channel1_2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA_Channel1_2_IRQHandler
B DMA_Channel1_2_IRQHandler
PUBWEAK DMA_Channel3_4_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA_Channel3_4_IRQHandler
B DMA_Channel3_4_IRQHandler
PUBWEAK ADC_CMP_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC_CMP_IRQHandler
B ADC_CMP_IRQHandler
PUBWEAK TIMER0_BRK_UP_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER0_BRK_UP_TRG_COM_IRQHandler
B TIMER0_BRK_UP_TRG_COM_IRQHandler
PUBWEAK TIMER0_Channel_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER0_Channel_IRQHandler
B TIMER0_Channel_IRQHandler
PUBWEAK TIMER2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER2_IRQHandler
B TIMER2_IRQHandler
PUBWEAK TIMER5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER5_IRQHandler
B TIMER5_IRQHandler
PUBWEAK TIMER13_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER13_IRQHandler
B TIMER13_IRQHandler
PUBWEAK TIMER14_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER14_IRQHandler
B TIMER14_IRQHandler
PUBWEAK TIMER15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER15_IRQHandler
B TIMER15_IRQHandler
PUBWEAK TIMER16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIMER16_IRQHandler
B TIMER16_IRQHandler
PUBWEAK I2C0_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C0_EV_IRQHandler
B I2C0_EV_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK SPI0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI0_IRQHandler
B SPI0_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK USART0_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART0_IRQHandler
B USART0_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK I2C0_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C0_ER_IRQHandler
B I2C0_ER_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
END
\ No newline at end of file
bsp/gd32e230k-start/Libraries/CMSIS/GD/GD32E230/Source/system_gd32e230.c 0 → 100644
浏览文件 @ 5d166c38
/*!
\file system_gd32e230.c
\brief CMSIS Cortex-M23 Device Peripheral Access Layer Source File for
GD32E1x0 Device Series
*/
/* Copyright (c) 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
#include "gd32e230.h"
/* system frequency define */
#define __IRC8M (IRC8M_VALUE) /* internal 8 MHz RC oscillator frequency */
#define __HXTAL (HXTAL_VALUE) /* high speed crystal oscillator frequency */
#define __SYS_OSC_CLK (__IRC8M) /* main oscillator frequency */
#define VECT_TAB_OFFSET (uint32_t)0x00 /* vector table base offset */
/* select a system clock by uncommenting the following line */
//#define __SYSTEM_CLOCK_8M_HXTAL (__HXTAL)
//#define __SYSTEM_CLOCK_8M_IRC8M (__IRC8M)
#define __SYSTEM_CLOCK_72M_PLL_HXTAL (uint32_t)(72000000)
//#define __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2 (uint32_t)(72000000)
#define SEL_IRC8M 0x00
#define SEL_HXTAL 0x01
#define SEL_PLL 0x02
/* set the system clock frequency and declare the system clock configuration function */
#ifdef __SYSTEM_CLOCK_8M_HXTAL
uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_HXTAL;
static void system_clock_8m_hxtal(void);
#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_HXTAL;
static void system_clock_72m_hxtal(void);
#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
uint32_t SystemCoreClock = __SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2;
static void system_clock_72m_irc8m(void);
#else
uint32_t SystemCoreClock = __SYSTEM_CLOCK_8M_IRC8M;
static void system_clock_8m_irc8m(void);
#endif /* __SYSTEM_CLOCK_8M_HXTAL */
/* configure the system clock */
static void system_clock_config(void);
/*!
\brief setup the microcontroller system, initialize the system
\param[in] none
\param[out] none
\retval none
*/
void SystemInit (void)
{
/* enable IRC8M */
RCU_CTL0 |= RCU_CTL0_IRC8MEN;
while(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
}
/* reset RCU */
RCU_CFG0 &= ~(RCU_CFG0_SCS | RCU_CFG0_AHBPSC | RCU_CFG0_APB1PSC | RCU_CFG0_APB2PSC |\
RCU_CFG0_ADCPSC | RCU_CFG0_CKOUTSEL | RCU_CFG0_CKOUTDIV | RCU_CFG0_PLLDV);
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLMF4 | RCU_CFG0_PLLDV);
RCU_CTL0 &= ~(RCU_CTL0_HXTALEN | RCU_CTL0_CKMEN | RCU_CTL0_PLLEN | RCU_CTL0_HXTALBPS);
RCU_CFG1 &= ~(RCU_CFG1_PREDV);
RCU_CFG2 &= ~(RCU_CFG2_USART0SEL | RCU_CFG2_ADCSEL);
RCU_CFG2 &= ~RCU_CFG2_IRC28MDIV;
RCU_CFG2 &= ~RCU_CFG2_ADCPSC2;
RCU_CTL1 &= ~RCU_CTL1_IRC28MEN;
RCU_INT = 0x00000000U;
/* configure system clock */
system_clock_config();
#ifdef VECT_TAB_SRAM
nvic_vector_table_set(NVIC_VECTTAB_RAM,VECT_TAB_OFFSET);
#else
nvic_vector_table_set(NVIC_VECTTAB_FLASH,VECT_TAB_OFFSET);
#endif
}
/*!
\brief configure the system clock
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_config(void)
{
#ifdef __SYSTEM_CLOCK_8M_HXTAL
system_clock_8m_hxtal();
#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
system_clock_72m_hxtal();
#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
system_clock_72m_irc8m();
#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC48M_DIV2)
system_clock_72m_irc48m();
#else
system_clock_8m_irc8m();
#endif /* __SYSTEM_CLOCK_8M_HXTAL */
}
#ifdef __SYSTEM_CLOCK_8M_HXTAL
/*!
\brief configure the system clock to 8M by HXTAL
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_8m_hxtal(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
/* enable HXTAL */
RCU_CTL0 |= RCU_CTL0_HXTALEN;
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
do{
timeout++;
stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
}
while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
while(1){
}
}
/* HXTAL is stable */
/* AHB = SYSCLK */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
/* APB2 = AHB */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
/* select HXTAL as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_HXTAL;
/* wait until HXTAL is selected as system clock */
while(0U == (RCU_CFG0 & RCU_SCSS_HXTAL)){
}
}
#elif defined (__SYSTEM_CLOCK_72M_PLL_HXTAL)
/*!
\brief configure the system clock to 72M by PLL which selects HXTAL as its clock source
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_72m_hxtal(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
/* enable HXTAL */
RCU_CTL0 |= RCU_CTL0_HXTALEN;
/* wait until HXTAL is stable or the startup time is longer than HXTAL_STARTUP_TIMEOUT */
do{
timeout++;
stab_flag = (RCU_CTL0 & RCU_CTL0_HXTALSTB);
}
while((0U == stab_flag) && (HXTAL_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL0 & RCU_CTL0_HXTALSTB)){
while(1){
}
}
FMC_WS &= ~FMC_WS_WSCNT;
FMC_WS |= WS_WSCNT_2;
/* HXTAL is stable */
/* AHB = SYSCLK */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
/* APB2 = AHB */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
/* PLL = HXTAL * 9 = 72 MHz */
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF | RCU_CFG0_PLLDV);
RCU_CFG0 |= (RCU_PLLSRC_HXTAL | RCU_PLL_MUL9);
/* enable PLL */
RCU_CTL0 |= RCU_CTL0_PLLEN;
/* wait until PLL is stable */
while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
}
/* select PLL as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
/* wait until PLL is selected as system clock */
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
}
}
#elif defined (__SYSTEM_CLOCK_72M_PLL_IRC8M_DIV2)
/*!
\brief configure the system clock to 72M by PLL which selects IRC8M/2 as its clock source
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_72m_irc8m(void)
{
uint32_t timeout = 0U;
uint32_t stab_flag = 0U;
/* enable IRC8M */
RCU_CTL0 |= RCU_CTL0_IRC8MEN;
/* wait until IRC8M is stable or the startup time is longer than IRC8M_STARTUP_TIMEOUT */
do{
timeout++;
stab_flag = (RCU_CTL0 & RCU_CTL0_IRC8MSTB);
}
while((0U == stab_flag) && (IRC8M_STARTUP_TIMEOUT != timeout));
/* if fail */
if(0U == (RCU_CTL0 & RCU_CTL0_IRC8MSTB)){
while(1){
}
}
FMC_WS &= ~FMC_WS_WSCNT;
FMC_WS |= WS_WSCNT_2;
/* AHB = SYSCLK */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
/* APB2 = AHB */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
/* PLL = (IRC8M/2) * 18 = 72 MHz */
RCU_CFG0 &= ~(RCU_CFG0_PLLSEL | RCU_CFG0_PLLMF);
RCU_CFG0 |= (RCU_PLLSRC_IRC8M_DIV2 | RCU_PLL_MUL18);
/* enable PLL */
RCU_CTL0 |= RCU_CTL0_PLLEN;
/* wait until PLL is stable */
while(0U == (RCU_CTL0 & RCU_CTL0_PLLSTB)){
}
/* select PLL as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_PLL;
/* wait until PLL is selected as system clock */
while(0U == (RCU_CFG0 & RCU_SCSS_PLL)){
}
}
#else
/*!
\brief configure the system clock to 8M by IRC8M
\param[in] none
\param[out] none
\retval none
*/
static void system_clock_8m_irc8m(void)
{
/* AHB = SYSCLK */
RCU_CFG0 |= RCU_AHB_CKSYS_DIV1;
/* APB2 = AHB */
RCU_CFG0 |= RCU_APB2_CKAHB_DIV1;
/* APB1 = AHB */
RCU_CFG0 |= RCU_APB1_CKAHB_DIV1;
/* select IRC8M as system clock */
RCU_CFG0 &= ~RCU_CFG0_SCS;
RCU_CFG0 |= RCU_CKSYSSRC_IRC8M;
/* wait until IRC8M is selected as system clock */
while(0U != (RCU_CFG0 & RCU_SCSS_IRC8M)){
}
}
#endif /* __SYSTEM_CLOCK_8M_HXTAL */
/*!
\brief update the SystemCoreClock with current core clock retrieved from cpu registers
\param[in] none
\param[out] none
\retval none
*/
void SystemCoreClockUpdate (void)
{
uint32_t sws = 0U;
uint32_t pllmf = 0U, pllmf4 = 0U, pllsel = 0U, prediv = 0U, idx = 0U, clk_exp = 0U;
/* exponent of AHB clock divider */
const uint8_t ahb_exp[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
sws = GET_BITS(RCU_CFG0, 2, 3);
switch(sws){
/* IRC8M is selected as CK_SYS */
case SEL_IRC8M:
SystemCoreClock = IRC8M_VALUE;
break;
/* HXTAL is selected as CK_SYS */
case SEL_HXTAL:
SystemCoreClock = HXTAL_VALUE;
break;
/* PLL is selected as CK_SYS */
case SEL_PLL:
/* get the value of PLLMF[3:0] */
pllmf = GET_BITS(RCU_CFG0, 18, 21);
pllmf4 = GET_BITS(RCU_CFG0, 27, 27);
/* high 16 bits */
if(1U == pllmf4){
pllmf += 17U;
}else if(15U == pllmf){
pllmf = 16U;
}else{
pllmf += 2U;
}
/* PLL clock source selection, HXTAL or IRC8M/2 */
pllsel = GET_BITS(RCU_CFG0, 16, 16);
if(0U != pllsel){
prediv = (GET_BITS(RCU_CFG1, 0, 3) + 1U);
SystemCoreClock = (HXTAL_VALUE / prediv) * pllmf;
}else{
SystemCoreClock = (IRC8M_VALUE >> 1) * pllmf;
}
break;
/* IRC8M is selected as CK_SYS */
default:
SystemCoreClock = IRC8M_VALUE;
break;
}
/* calculate AHB clock frequency */
idx = GET_BITS(RCU_CFG0, 4, 7);
clk_exp = ahb_exp[idx];
SystemCoreClock >>= clk_exp;
}
bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_cmp.h 0 → 100644
浏览文件 @ 5d166c38
/*!
\file gd32e230_cmp.h
\brief definitions for the CMP
\version 2018-06-19, V1.0.0, firmware for GD32E230
*/
/*
Copyright (c) 2018, GigaDevice Semiconductor Inc.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E230_CMP_H
#define GD32E230_CMP_H
#include "gd32e230.h"
/* CMP definitions */
#define CMP CMP_BASE /*!< CMP base address */
/* registers definitions */
#define CMP_CS REG32((CMP) + 0x00U) /*!< CMP control and status register */
/* CMP_CS bits definitions */
#define CMP_CS_CMPEN BIT(0) /*!< CMP enable */
#define CMP_CS_CMPSW BIT(1) /*!< CMP switch */
#define CMP_CS_CMPM BITS(2,3) /*!< CMP mode */
#define CMP_CS_CMPMSEL BITS(4,6) /*!< COMP_M input selection */
#define CMP_CS_CMPOSEL BITS(8,10) /*!< CMP output selection */
#define CMP_CS_CMPPL BIT(11) /*!< polarity of CMP output */
#define CMP_CS_CMPHST BITS(12,13) /*!< CMP hysteresis */
#define CMP_CS_CMPO BIT(14) /*!< CMP output */
#define CMP_CS_CMPLK BIT(15) /*!< CMP lock */
/* consts definitions */
/* operating mode */
typedef enum{
CMP_HIGHSPEED = 0, /*!< high speed mode */
CMP_MIDDLESPEED, /*!< medium speed mode */
CMP_LOWSPEED, /*!< low speed mode */
CMP_VERYLOWSPEED /*!< very-low speed mode */
}operating_mode_enum;
/* inverting input */
typedef enum{
CMP_1_4VREFINT = 0, /*!< VREFINT /4 input */
CMP_1_2VREFINT, /*!< VREFINT /2 input */
CMP_3_4VREFINT, /*!< VREFINT *3/4 input */
CMP_VREFINT, /*!< VREFINT input */
CMP_PA4, /*!< PA4 input */
CMP_PA5, /*!< PA5 input */
CMP_PA0, /*!< PA0 input */
CMP_PA2 /*!< PA2 input */
}inverting_input_enum;
/* hysteresis */
typedef enum{
CMP_HYSTERESIS_NO = 0, /*!< output no hysteresis */
CMP_HYSTERESIS_LOW, /*!< output low hysteresis */
CMP_HYSTERESIS_MIDDLE, /*!< output middle hysteresis */
CMP_HYSTERESIS_HIGH /*!< output high hysteresis */
}cmp_hysteresis_enum;
/* output */
typedef enum{
CMP_OUTPUT_NONE = 0x0U, /*!< output no selection */
CMP_OUTPUT_TIMER0BKIN = 0x1U, /*!< TIMER 0 break input */
CMP_OUTPUT_TIMER0IC0 = 0x2U, /*!< TIMER 0 channel0 input capture */
CMP_OUTPUT_TIMER0OCPRECLR = 0x3U, /*!< TIMER 0 OCPRE_CLR input */
CMP_OUTPUT_TIMER2IC0 = 0x06U, /*!< TIMER 2 channel0 input capture */
CMP_OUTPUT_TIMER2OCPRECLR = 0x7U /*!< TIMER 2 OCPRE_CLR input */
}cmp_output_enum;
/* CMP mode */
#define CS_CMPM(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
#define CS_CMPM_HIGHSPEED CS_CMPM(0) /*!< CMP mode high speed */
#define CS_CMPM_MIDDLESPEED CS_CMPM(1) /*!< CMP mode middle speed */
#define CS_CMPM_LOWSPEED CS_CMPM(2) /*!< CMP mode low speed */
#define CS_CMPM_VERYLOWSPEED CS_CMPM(3) /*!< CMP mode very low speed */
/* comparator inverting input */
#define CS_CMPMSEL(regval) (BITS(4,6) & ((uint32_t)(regval) << 4))
#define CS_CMPMSEL_1_4VREFINT CS_CMPMSEL(0) /*!< CMP inverting input 1/4 Vrefint */
#define CS_CMPMSEL_1_2VREFINT CS_CMPMSEL(1) /*!< CMP inverting input 1/2 Vrefint */
#define CS_CMPMSEL_3_4VREFINT CS_CMPMSEL(2) /*!< CMP inverting input 3/4 Vrefint */
#define CS_CMPMSEL_VREFINT CS_CMPMSEL(3) /*!< CMP inverting input Vrefint */
#define CS_CMPMSEL_PA4 CS_CMPMSEL(4) /*!< CMP inverting input PA4*/
#define CS_CMPMSEL_PA5 CS_CMPMSEL(5) /*!< CMP inverting input PA5*/
#define CS_CMPMSEL_PA0 CS_CMPMSEL(6) /*!< CMP inverting input PA0*/
#define CS_CMPMSEL_PA2 CS_CMPMSEL(7) /*!< CMP inverting input PA2*/
/* CMP output */
#define CS_CMPOSEL(regval) (BITS(8,10) & ((uint32_t)(regval) << 8))
#define CS_CMPOSEL_OUTPUT_NONE CS_CMPOSEL(0) /*!< CMP output none */
#define CS_CMPOSEL_OUTPUT_TIMER0BKIN CS_CMPOSEL(1) /*!< CMP output TIMER 0 break input */
#define CS_CMPOSEL_OUTPUT_TIMER0IC0 CS_CMPOSEL(2) /*!< CMP output TIMER 0 channel 0 input capture */
#define CS_CMPOSEL_OUTPUT_TIMER0OCPRECLR CS_CMPOSEL(3) /*!< CMP output TIMER 0 ocpreclear input */
#define CS_CMPOSEL_OUTPUT_TIMER2IC0 CS_CMPOSEL(6) /*!< CMP output TIMER 2 channle 0 input capture */
#define CS_CMPOSEL_OUTPUT_TIMER2OCPRECLR CS_CMPOSEL(7) /*!< CMP output TIMER 2 ocpreclear input */
/* CMP hysteresis */
#define CS_CMPHST(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
#define CS_CMPHST_HYSTERESIS_NO CS_CMPHST(0) /*!< CMP output no hysteresis */
#define CS_CMPHST_HYSTERESIS_LOW CS_CMPHST(1) /*!< CMP output low hysteresis */
#define CS_CMPHST_HYSTERESIS_MIDDLE CS_CMPHST(2) /*!< CMP output middle hysteresis */
#define CS_CMPHST_HYSTERESIS_HIGH CS_CMPHST(3) /*!< CMP output high hysteresis */
/* CMP output level */
#define CMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001) /*!< comparator output high */
#define CMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000) /*!< comparator output low */
/* output polarity of comparator */
#define CMP_OUTPUT_POLARITY_INVERTED ((uint32_t)0x00000001) /*!< output is inverted */
#define CMP_OUTPUT_POLARITY_NOINVERTED ((uint32_t)0x00000000) /*!< output is not inverted */
/* function declarations */
/* initialization functions */
/* CMP deinit */
void cmp_deinit(void);
/* CMP mode init */
void cmp_mode_init(operating_mode_enum operating_mode, inverting_input_enum inverting_input, cmp_hysteresis_enum output_hysteresis);
/* CMP output init */
void cmp_output_init(cmp_output_enum output_slection, uint32_t output_polarity);
/* enable CMP */
void cmp_enable(void);
/* disable CMP */
void cmp_disable(void);
/* enable CMP switch */
void cmp_switch_enable(void);
/* disable CMP switch */
void cmp_switch_disable(void);
/* get output level */
uint32_t cmp_output_level_get(void);
/* lock the CMP */
void cmp_lock_enable(void);
#endif /* GD32E230_CMP_H */
bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_crc.h 0 → 100644
浏览文件 @ 5d166c38
/*!
\file gd32e230_crc.h
\brief definitions for the CRC
\version 2018-06-19, V1.0.0, firmware for GD32E230
*/
/*
Copyright (c) 2018, GigaDevice Semiconductor Inc.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E230_CRC_H
#define GD32E230_CRC_H
#include "gd32e230.h"
/* CRC definitions */
#define CRC CRC_BASE
/* registers definitions */
#define CRC_DATA REG32((CRC) + 0x00U) /*!< CRC data register */
#define CRC_FDATA REG32((CRC) + 0x04U) /*!< CRC free data register */
#define CRC_CTL REG32((CRC) + 0x08U) /*!< CRC control register */
#define CRC_IDATA REG32((CRC) + 0x10U) /*!< CRC initialization data register */
#define CRC_POLY REG32((CRC) + 0x14U) /*!< CRC polynomial register */
/* bits definitions */
/* CRC_DATA */
#define CRC_DATA_DATA BITS(0,31) /*!< CRC data bits */
/* CRC_FDATA */
#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */
/* CRC_CTL */
#define CRC_CTL_RST BIT(0) /*!< CRC reset bit */
#define CRC_CTL_PS BITS(3,4) /*!< size of polynomial function bits */
#define CRC_CTL_REV_I BITS(5,6) /*!< input data reverse function bits */
#define CRC_CTL_REV_O BIT(7) /*!< output data reverse function bit */
/* CRC_INIT */
#define CRC_IDATA_IDATA BITS(0,31) /*!< CRC initialization data bits */
/* CRC_POLY */
#define CRC_POLY_POLY BITS(0,31) /*!< CRC polynomial value bits */
/* constants definitions */
/* size of polynomial function */
#define CTL_PS(regval) (BITS(3, 4) & ((regval) << 3))
#define CRC_CTL_PS_32 CTL_PS(0) /*!< 32-bit polynomial for CRC calculation */
#define CRC_CTL_PS_16 CTL_PS(1) /*!< 16-bit polynomial for CRC calculation */
#define CRC_CTL_PS_8 CTL_PS(2) /*!< 8-bit polynomial for CRC calculation */
#define CRC_CTL_PS_7 CTL_PS(3) /*!< 7-bit polynomial for CRC calculation */
/* input data reverse function */
#define CTL_REV_I(regval) (BITS(5, 6) & ((regval) << 5))
#define CRC_INPUT_DATA_NOT CTL_REV_I(0) /*!< input data not reverse */
#define CRC_INPUT_DATA_BYTE CTL_REV_I(1) /*!< input data reversed by byte type */
#define CRC_INPUT_DATA_HALFWORD CTL_REV_I(2) /*!< input data reversed by half-word type */
#define CRC_INPUT_DATA_WORD CTL_REV_I(3) /*!< input data reversed by word type */
/* function declarations */
/* deinit CRC calculation unit */
void crc_deinit(void);
/* enable the reverse operation of output data */
void crc_reverse_output_data_enable(void);
/* disable the reverse operation of output data */
void crc_reverse_output_data_disable(void);
/* reset data register to the value of initializaiton data register */
void crc_data_register_reset(void);
/* read the data register */
uint32_t crc_data_register_read(void);
/* read the free data register */
uint8_t crc_free_data_register_read(void);
/* write the free data register */
void crc_free_data_register_write(uint8_t free_data);
/* write the initial value register */
void crc_init_data_register_write(uint32_t init_data);
/* configure the CRC input data function */
void crc_input_data_reverse_config(uint32_t data_reverse);
/* configure the CRC size of polynomial function */
void crc_polynomial_size_set(uint32_t poly_size);
/* configure the CRC polynomial value function */
void crc_polynomial_set(uint32_t poly);
/* CRC calculate a 32-bit data */
uint32_t crc_single_data_calculate(uint32_t sdata);
/* CRC calculate a 32-bit data array */
uint32_t crc_block_data_calculate(uint32_t array[], uint32_t size);
#endif /* GD32E230_CRC_H */
bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_dbg.h 0 → 100644
浏览文件 @ 5d166c38
/*!
\file gd32e230_dbg.h
\brief definitions for the DBG
\version 2018-06-19, V1.0.0, firmware for GD32E230
*/
/*
Copyright (c) 2018, GigaDevice Semiconductor Inc.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E230_DBG_H
#define GD32E230_DBG_H
#include "gd32e230.h"
/* DBG definitions */
#define DBG DBG_BASE
/* registers definitions */
#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */
#define DBG_CTL0 REG32(DBG + 0x04U) /*!< DBG control register 0 */
#define DBG_CTL1 REG32(DBG + 0x08U) /*!< DBG control register 1 */
/* bits definitions */
/* DBG_ID */
#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
/* DBG_CTL0 */
#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
#define DBG_CTL0_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */
#define DBG_CTL0_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */
#define DBG_CTL0_TIMER0_HOLD BIT(10) /*!< TIMER0 counter kept when core is halted */
#define DBG_CTL0_TIMER2_HOLD BIT(12) /*!< TIMER2 counter kept when core is halted */
#define DBG_CTL0_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */
#define DBG_CTL0_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */
#define DBG_CTL0_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */
#define DBG_CTL0_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */
/* DBG_CTL1 */
#define DBG_CTL1_RTC_HOLD BIT(10) /*!< hold RTC calendar and wakeup counter when core is halted */
#define DBG_CTL1_TIMER14_HOLD BIT(16) /*!< hold TIMER14 counter when core is halted */
#define DBG_CTL1_TIMER15_HOLD BIT(17) /*!< hold TIMER15 counter when core is halted */
#define DBG_CTL1_TIMER16_HOLD BIT(18) /*!< hold TIMER16 counter when core is halted */
/* constants definitions */
#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */
/* define the peripheral debug hold bit position and its register index offset */
#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos))
#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6)))
#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
/* register index */
enum dbg_reg_idx
{
DBG_IDX_CTL0 = 0x04U,
DBG_IDX_CTL1 = 0x08U,
};
/* peripherals hold bit */
typedef enum
{
DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 8U), /*!< FWDGT hold bit */
DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 9U), /*!< WWDGT hold bit */
DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 10U), /*!< TIMER0 hold bit */
DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 12U), /*!< TIMER2 hold bit */
DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 19U), /*!< TIMER5 hold bit */
DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 27U), /*!< TIMER13 hold bit */
DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 16U), /*!< TIMER14 hold bit */
DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 17U), /*!< TIMER15 hold bit */
DBG_TIMER16_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 18U), /*!< TIMER16 hold bit */
DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 15U), /*!< I2C0 hold bit */
DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 16U), /*!< I2C1 hold bit */
DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< RTC hold bit */
}dbg_periph_enum;
/* function declarations */
/* deinitialize the DBG */
void dbg_deinit(void);
/* read DBG_ID code register */
uint32_t dbg_id_get(void);
/* enable low power behavior when the MCU is in debug mode */
void dbg_low_power_enable(uint32_t dbg_low_power);
/* disable low power behavior when the MCU is in debug mode */
void dbg_low_power_disable(uint32_t dbg_low_power);
/* enable peripheral behavior when the MCU is in debug mode */
void dbg_periph_enable(dbg_periph_enum dbg_periph);
/* disable peripheral behavior when the MCU is in debug mode */
void dbg_periph_disable(dbg_periph_enum dbg_periph);
#endif /* GD32E230_DBG_H */
bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_dma.h 0 → 100644
浏览文件 @ 5d166c38
/*!
\file gd32e230_dma.h
\brief definitions for the DMA
\version 2018-06-19, V1.0.0, firmware for GD32E230
*/
/*
Copyright (c) 2018, GigaDevice Semiconductor Inc.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E230_DMA_H
#define GD32E230_DMA_H
#include "gd32e230.h"
/* DMA definitions */
#define DMA DMA_BASE /*!< DMA base address */
/* registers definitions */
#define DMA_INTF REG32(DMA + 0x00U) /*!< DMA interrupt flag register */
#define DMA_INTC REG32(DMA + 0x04U) /*!< DMA interrupt flag clear register */
#define DMA_CH0CTL REG32(DMA + 0x08U) /*!< DMA channel 0 control register */
#define DMA_CH0CNT REG32(DMA + 0x0CU) /*!< DMA channel 0 counter register */
#define DMA_CH0PADDR REG32(DMA + 0x10U) /*!< DMA channel 0 peripheral base address register */
#define DMA_CH0MADDR REG32(DMA + 0x14U) /*!< DMA channel 0 memory base address register */
#define DMA_CH1CTL REG32(DMA + 0x1CU) /*!< DMA channel 1 control register */
#define DMA_CH1CNT REG32(DMA + 0x20U) /*!< DMA channel 1 counter register */
#define DMA_CH1PADDR REG32(DMA + 0x24U) /*!< DMA channel 1 peripheral base address register */
#define DMA_CH1MADDR REG32(DMA + 0x28U) /*!< DMA channel 1 memory base address register */
#define DMA_CH2CTL REG32(DMA + 0x30U) /*!< DMA channel 2 control register */
#define DMA_CH2CNT REG32(DMA + 0x34U) /*!< DMA channel 2 counter register */
#define DMA_CH2PADDR REG32(DMA + 0x38U) /*!< DMA channel 2 peripheral base address register */
#define DMA_CH2MADDR REG32(DMA + 0x3CU) /*!< DMA channel 2 memory base address register */
#define DMA_CH3CTL REG32(DMA + 0x44U) /*!< DMA channel 3 control register */
#define DMA_CH3CNT REG32(DMA + 0x48U) /*!< DMA channel 3 counter register */
#define DMA_CH3PADDR REG32(DMA + 0x4CU) /*!< DMA channel 3 peripheral base address register */
#define DMA_CH3MADDR REG32(DMA + 0x50U) /*!< DMA channel 3 memory base address register */
#define DMA_CH4CTL REG32(DMA + 0x58U) /*!< DMA channel 4 control register */
#define DMA_CH4CNT REG32(DMA + 0x5CU) /*!< DMA channel 4 counter register */
#define DMA_CH4PADDR REG32(DMA + 0x60U) /*!< DMA channel 4 peripheral base address register */
#define DMA_CH4MADDR REG32(DMA + 0x64U) /*!< DMA channel 4 memory base address register */
/* bits definitions */
/* DMA_INTF */
#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */
#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */
#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */
#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */
/* DMA_INTC */
#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */
#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */
#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */
#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */
/* DMA_CHxCTL,x=0..4 */
#define DMA_CHXCTL_CHEN BIT(0) /*!< channel x enable */
#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel x transfer complete interrupt */
#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel x transfer half complete interrupt */
#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel x error interrupt */
#define DMA_CHXCTL_DIR BIT(4) /*!< direction of the data transfer on the channel */
#define DMA_CHXCTL_CMEN BIT(5) /*!< circulation mode */
#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */
#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */
#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data size of peripheral */
#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data size of memory */
#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level of channelx */
#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */
/* DMA_CHxCNT,x=0..4 */
#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */
/* DMA_CHxPADDR,x=0..4 */
#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */
/* DMA_CHxMADDR,x=0..4 */
#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */
/* constants definitions */
/* DMA channel select */
typedef enum
{
DMA_CH0 = 0, /*!< DMA Channel0 */
DMA_CH1, /*!< DMA Channel1 */
DMA_CH2, /*!< DMA Channel2 */
DMA_CH3, /*!< DMA Channel3 */
DMA_CH4, /*!< DMA Channel4 */
} dma_channel_enum;
/* DMA initialize struct */
typedef struct
{
uint32_t periph_addr; /*!< peripheral base address */
uint32_t periph_width; /*!< transfer data size of peripheral */
uint32_t memory_addr; /*!< memory base address */
uint32_t memory_width; /*!< transfer data size of memory */
uint32_t number; /*!< channel transfer number */
uint32_t priority; /*!< channel priority level */
uint8_t periph_inc; /*!< peripheral increasing mode */
uint8_t memory_inc; /*!< memory increasing mode */
uint8_t direction; /*!< channel data transfer direction */
} dma_parameter_struct;
/* DMA reset value */
#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */
#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */
#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */
#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */
#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \
DMA_INTF_HTFIF | DMA_INTF_ERRIF)
#define DMA_FLAG_ADD(flag,shift) ((flag) << ((uint32_t)(shift) * 4U)) /*!< DMA channel flag shift */
/* DMA_CHCTL base address */
#define DMA_CHXCTL_BASE (DMA + 0x08U) /*!< the base address of DMA channel CHXCTL register */
#define DMA_CHXCNT_BASE (DMA + 0x0CU) /*!< the base address of DMA channel CHXCNT register */
#define DMA_CHXPADDR_BASE (DMA + 0x10U) /*!< the base address of DMA channel CHXPADDR register */
#define DMA_CHXMADDR_BASE (DMA + 0x14U) /*!< the base address of DMA channel CHXMADDR register */
/* DMA channel shift bit */
#define DMA_CHCTL(channel) REG32(DMA_CHXCTL_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */
#define DMA_CHCNT(channel) REG32(DMA_CHXCNT_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */
#define DMA_CHPADDR(channel) REG32(DMA_CHXPADDR_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */
#define DMA_CHMADDR(channel) REG32(DMA_CHXMADDR_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */
/* DMA_INTF register */
/* interrupt flag bits */
#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */
#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */
#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */
/* flag bits */
#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */
#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */
#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */
/* DMA_CHxCTL register */
/* interrupt enable bits */
#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */
#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */
#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */
/* transfer direction */
#define DMA_PERIPHERAL_TO_MEMORY ((uint32_t)0x00000000U) /*!< read from peripheral and write to memory */
#define DMA_MEMORY_TO_PERIPHERAL ((uint32_t)0x00000001U) /*!< read from memory and write to peripheral */
/* peripheral increasing mode */
#define DMA_PERIPH_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of peripheral is fixed address mode */
#define DMA_PERIPH_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of peripheral is increasing address mode */
/* memory increasing mode */
#define DMA_MEMORY_INCREASE_DISABLE ((uint32_t)0x00000000U) /*!< next address of memory is fixed address mode */
#define DMA_MEMORY_INCREASE_ENABLE ((uint32_t)0x00000001U) /*!< next address of memory is increasing address mode */
/* transfer data size of peripheral */
#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8)) /*!< transfer data size of peripheral */
#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */
#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */
#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */
/* transfer data size of memory */
#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10)) /*!< transfer data size of memory */
#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */
#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */
#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */
/* channel priority level */
#define CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12)) /*!< DMA channel priority level */
#define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */
#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */
#define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */
#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */
/* DMA_CHxCNT register */
/* transfer counter */
#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT
/* function declarations */
/* deinitialize DMA a channel registers */
void dma_deinit(dma_channel_enum channelx);
/* initialize the parameters of DMA struct with the default values */
void dma_struct_para_init(dma_parameter_struct* init_struct);
/* initialize DMA channel */
void dma_init(dma_channel_enum channelx, dma_parameter_struct* init_struct);
/* enable DMA circulation mode */
void dma_circulation_enable(dma_channel_enum channelx);
/* disable DMA circulation mode */
void dma_circulation_disable(dma_channel_enum channelx);
/* enable memory to memory mode */
void dma_memory_to_memory_enable(dma_channel_enum channelx);
/* disable memory to memory mode */
void dma_memory_to_memory_disable(dma_channel_enum channelx);
/* enable DMA channel */
void dma_channel_enable(dma_channel_enum channelx);
/* disable DMA channel */
void dma_channel_disable(dma_channel_enum channelx);
/* set DMA peripheral base address */
void dma_periph_address_config(dma_channel_enum channelx, uint32_t address);
/* set DMA memory base address */
void dma_memory_address_config(dma_channel_enum channelx, uint32_t address);
/* set the number of remaining data to be transferred by the DMA */
void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number);
/* get the number of remaining data to be transferred by the DMA */
uint32_t dma_transfer_number_get(dma_channel_enum channelx);
/* configure priority level of DMA channel */
void dma_priority_config(dma_channel_enum channelx, uint32_t priority);
/* configure transfer data size of memory */
void dma_memory_width_config (dma_channel_enum channelx, uint32_t mwidth);
/* configure transfer data size of peripheral */
void dma_periph_width_config (dma_channel_enum channelx, uint32_t pwidth);
/* enable next address increasement algorithm of memory */
void dma_memory_increase_enable(dma_channel_enum channelx);
/* disable next address increasement algorithm of memory */
void dma_memory_increase_disable(dma_channel_enum channelx);
/* enable next address increasement algorithm of peripheral */
void dma_periph_increase_enable(dma_channel_enum channelx);
/* disable next address increasement algorithm of peripheral */
void dma_periph_increase_disable(dma_channel_enum channelx);
/* configure the direction of data transfer on the channel */
void dma_transfer_direction_config(dma_channel_enum channelx, uint32_t direction);
/* check DMA flag is set or not */
FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag);
/* clear DMA a channel flag */
void dma_flag_clear(dma_channel_enum channelx, uint32_t flag);
/* check DMA flag and interrupt enable bit is set or not */
FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag);
/* clear DMA a channel flag */
void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag);
/* enable DMA interrupt */
void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source);
/* disable DMA interrupt */
void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source);
#endif /* GD32E230_DMA_H */
bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_fmc.h 0 → 100644
浏览文件 @ 5d166c38
/*!
\file gd32e230_fmc.h
\brief definitions for the FMC
\version 2018-06-19, V1.0.0, firmware for GD32E230
*/
/*
Copyright (c) 2018, GigaDevice Semiconductor Inc.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E230_FMC_H
#define GD32E230_FMC_H
#include "gd32e230.h"
/* FMC and option byte definition */
#define FMC FMC_BASE /*!< FMC register base address */
#define OB OB_BASE /*!< option byte base address */
/* registers definitions */
#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */
#define FMC_KEY REG32((FMC) + 0x04U) /*!< FMC unlock key register */
#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */
#define FMC_STAT REG32((FMC) + 0x0CU) /*!< FMC status register */
#define FMC_CTL REG32((FMC) + 0x10U) /*!< FMC control register */
#define FMC_ADDR REG32((FMC) + 0x14U) /*!< FMC address register */
#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */
#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC write protection register */
#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */
#define OB_SPC_USER REG32((OB) + 0x00U) /*!< option byte security protection value and user value */
#define OB_DATA REG32((OB) + 0x04U) /*!< option byte data value*/
#define OB_WP REG32((OB) + 0x08U) /*!< option byte write protection */
/* bits definitions */
/* FMC_WS */
#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */
#define FMC_WS_PFEN BIT(4) /*!< pre-fetch enable */
#define FMC_WS_PGW BIT(15) /*!< program width to flash memory */
/* FMC_KEY */
#define FMC_KEY_KEY BITS(0,31) /*!< FMC main flash unlock key bits */
/* FMC_OBKEY */
#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */
/* FMC_STAT */
#define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */
#define FMC_STAT_PGERR BIT(2) /*!< flash program error flag bit */
#define FMC_STAT_PGAERR BIT(3) /*!< program alignment error flag bit */
#define FMC_STAT_WPERR BIT(4) /*!< flash write protection error flag bit */
#define FMC_STAT_ENDF BIT(5) /*!< end of operation flag bit */
/* FMC_CTL */
#define FMC_CTL_PG BIT(0) /*!< main flash program command bit */
#define FMC_CTL_PER BIT(1) /*!< main flash page erase bit */
#define FMC_CTL_MER BIT(2) /*!< main flash mass erase bit */
#define FMC_CTL_OBPG BIT(4) /*!< option bytes program command bit */
#define FMC_CTL_OBER BIT(5) /*!< option bytes erase command bit */
#define FMC_CTL_START BIT(6) /*!< send erase command to FMC bit */
#define FMC_CTL_LK BIT(7) /*!< flash lock bit */
#define FMC_CTL_OBWEN BIT(9) /*!< option bytes erase/program enable bit */
#define FMC_CTL_ERRIE BIT(10) /*!< error interrupt enable bit */
#define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable bit */
#define FMC_CTL_OBRLD BIT(13) /*!< option bytes reload bit */
/* FMC_ADDR */
#define FMC_ADDR_ADDR BITS(0,31) /*!< flash command address bits */
/* FMC_OBSTAT */
#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit */
#define FMC_OBSTAT_PLEVEL_BIT0 BIT(1) /*!< protection level bit 0 */
#define FMC_OBSTAT_PLEVEL_BIT1 BIT(2) /*!< protection level bit 1 */
#define FMC_OBSTAT_USER BITS(8,15) /*!< option bytes user bits */
#define FMC_OBSTAT_DATA BITS(16,31) /*!< option byte data bits */
/* FMC_WP */
#define FMC_WP_WP BITS(0,15) /*!< store WP[15:0] of option byte block after system reset */
/* FMC_PID */
#define FMC_PID_PID BITS(0,31) /*!< product ID bits */
/* constants definitions */
/* fmc state */
typedef enum
{
FMC_READY, /*!< the operation has been completed */
FMC_BUSY, /*!< the operation is in progress */
FMC_PGERR, /*!< program error */
FMC_PGAERR, /*!< program alignment error */
FMC_WPERR, /*!< erase/program protection error */
FMC_TOERR, /*!< timeout error */
FMC_OB_HSPC /*!< option byte security protection code high */
}fmc_state_enum;
/* unlock key */
#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */
#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */
/* wait state counter value */
#define WS_WSCNT_0 ((uint8_t)0x00U) /*!< 0 wait state added */
#define WS_WSCNT_1 ((uint8_t)0x01U) /*!< 1 wait state added */
#define WS_WSCNT_2 ((uint8_t)0x02U) /*!< 2 wait state added */
/* read protect configure */
#define FMC_NSPC ((uint16_t)0x5AA5U) /*!< no security protection */
#define FMC_LSPC ((uint16_t)0x44BBU) /*!< low security protection, any value except 0xA5 or 0xCC */
#define FMC_HSPC ((uint16_t)0x33CCU) /*!< high security protection */
#define LOW_16BITS_MASK ((uint32_t)0x0000FFFFU) /*!< low 16 bits mask */
#define HIGH_16BITS_MASK ((uint32_t)0xFFFF0000U) /*!< high 16 bits mask */
/* option byte address */
#define OB_SPC_USER_ADDRESS ((uint32_t)0x1FFFF800U) /*!< address of option byte security protection and user */
#define OB_DATA_ADDRESS ((uint32_t)0x1FFFF804U) /*!< address of option byte data */
#define OB_WP_ADDRESS ((uint32_t)0x1FFFF808U) /*!< address of option byte write protection */
/* option byte write protection */
#define OB_LWP ((uint32_t)0x000000FFU) /*!< write protection low bits */
#define OB_HWP ((uint32_t)0x0000FF00U) /*!< write protection high bits */
/* option byte software/hardware free watchdog timer */
#define OB_FWDGT_HW ((uint8_t)(~BIT(0))) /*!< hardware free watchdog timer */
#define OB_FWDGT_SW ((uint8_t)BIT(0)) /*!< software free watchdog timer */
/* option byte reset or not entering deep sleep mode */
#define OB_DEEPSLEEP_RST ((uint8_t)(~BIT(1))) /*!< generate a reset instead of entering deepsleep mode */
#define OB_DEEPSLEEP_NRST ((uint8_t)BIT(1)) /*!< no reset when entering deepsleep mode */
/* option byte reset or not entering standby mode */
#define OB_STDBY_RST ((uint8_t)(~BIT(2))) /*!< generate a reset instead of entering standby mode */
#define OB_STDBY_NRST ((uint8_t)BIT(2)) /*!< no reset when entering deepsleep mode */
/* option byte OB_BOOT1_n set */
#define OB_BOOT1_SET_1 ((uint8_t)(~BIT(4))) /*!< BOOT1 bit is 1 */
#define OB_BOOT1_SET_0 ((uint8_t)BIT(4)) /*!< BOOT1 bit is 0 */
/* option byte VDDA monitor enable/disable */
#define OB_VDDA_DISABLE ((uint8_t)(~BIT(5))) /*!< disable VDDA monitor */
#define OB_VDDA_ENABLE ((uint8_t)BIT(5)) /*!< enable VDDA monitor */
/* option byte SRAM parity enable/disable */
#define OB_SRAM_PARITY_ENABLE ((uint8_t)(~BIT(6))) /*!< enable SRAM parity check */
#define OB_SRAM_PARITY_DISABLE ((uint8_t)BIT(6)) /*!< disable SRAM parity check */
/* option byte security protection level in FMC_OBSTAT register */
#define OB_OBSTAT_PLEVEL_NO ((uint8_t)0x00U) /*!< no security protection */
#define OB_OBSTAT_PLEVEL_LOW ((uint8_t)0x01U) /*!< low security protection */
#define OB_OBSTAT_PLEVEL_HIGH ((uint8_t)0x03U) /*!< high security protection */
/* option byte user mask */
#define OB_USER_MASK ((uint8_t)0x88U) /*!< OB_USER reserved bit mask */
/* option byte data address */
#define OB_DATA_ADDR0 ((uint32_t)0x1FFFF804U) /*!< option byte data address 0 */
#define OB_DATA_ADDR1 ((uint32_t)0x1FFFF806U) /*!< option byte data address 1 */
/* FMC flags */
#define FMC_FLAG_BUSY FMC_STAT_BUSY /*!< FMC busy flag */
#define FMC_FLAG_PGERR FMC_STAT_PGERR /*!< FMC programming error flag */
#define FMC_FLAG_PGAERR FMC_STAT_PGAERR /*!< FMC program alignment error flag */
#define FMC_FLAG_WPERR FMC_STAT_WPERR /*!< FMC write protection error flag */
#define FMC_FLAG_END FMC_STAT_ENDF /*!< FMC end of programming flag */
/* FMC interrupt flags */
#define FMC_INT_FLAG_PGERR FMC_STAT_PGERR /*!< FMC programming error flag */
#define FMC_INT_FLAG_PGAERR FMC_STAT_PGAERR /*!< FMC program alignment error flag */
#define FMC_INT_FLAG_WPERR FMC_STAT_WPERR /*!< FMC write protection error flag */
#define FMC_INT_FLAG_END FMC_STAT_ENDF /*!< FMC end of programming flag */
/* FMC interrupt enable */
#define FMC_INTEN_END FMC_CTL_ENDIE /*!< enable FMC end of operation interrupt */
#define FMC_INTEN_ERR FMC_CTL_ERRIE /*!< enable FMC error interrupt */
/* FMC time out */
#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< count to judge of FMC timeout */
/* function declarations */
/* FMC main memory programming functions */
/* unlock the main FMC operation */
void fmc_unlock(void);
/* lock the main FMC operation */
void fmc_lock(void);
/* set the wait state counter value */
void fmc_wscnt_set(uint8_t wscnt);
/* pre-fetch enable */
void fmc_prefetch_enable(void);
/* pre-fetch disable */
void fmc_prefetch_disable(void);
/* FMC erase page */
fmc_state_enum fmc_page_erase(uint32_t page_address);
/* FMC erase whole chip */
fmc_state_enum fmc_mass_erase(void);
/* FMC program a double word at the corresponding address */
fmc_state_enum fmc_doubleword_program(uint32_t address, uint64_t data);
/* FMC program a word at the corresponding address */
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
/* FMC option bytes programming functions */
/* unlock the option byte operation */
void ob_unlock(void);
/* lock the option byte operation */
void ob_lock(void);
/* reload the option byte and generate a system reset */
void ob_reset(void);
/* get option byte value */
uint32_t option_byte_value_get(uint32_t addr);
/* erase option byte */
fmc_state_enum ob_erase(void);
/* enable option byte write protection (OB_WP) */
fmc_state_enum ob_write_protection_enable(uint16_t ob_wp);
/* configure read out protect */
fmc_state_enum ob_security_protection_config(uint16_t ob_spc);
/* write the FMC option byte user */
fmc_state_enum ob_user_write(uint8_t ob_user);
/* write the FMC option byte data */
fmc_state_enum ob_data_program(uint16_t data);
/* get the FMC option byte OB_USER */
uint8_t ob_user_get(void);
/* get the FMC option byte OB_DATA */
uint16_t ob_data_get(void);
/* get the FMC option byte write protection */
uint16_t ob_write_protection_get(void);
/* get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register */
uint32_t ob_obstat_plevel_get(void);
/* FMC interrupts and flags management functions */
/* enable FMC interrupt */
void fmc_interrupt_enable(uint32_t interrupt);
/* disable FMC interrupt */
void fmc_interrupt_disable(uint32_t interrupt);
/* get flag set or reset */
FlagStatus fmc_flag_get(uint32_t flag);
/* clear the FMC pending flag */
void fmc_flag_clear(uint32_t flag);
/* get intrrupt flag set or reset */
FlagStatus fmc_interrupt_flag_get(uint32_t int_flag);
/* clear the FMC interrupt pending flag by writing 1 */
void fmc_interrupt_flag_clear(uint32_t int_flag);
/* return the FMC state */
fmc_state_enum fmc_state_get(void);
/* check FMC ready or not */
fmc_state_enum fmc_ready_wait(uint32_t timeout);
#endif /* GD32E230_FMC_H */
bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_fwdgt.h 0 → 100644
浏览文件 @ 5d166c38
/*!
\file gd32e230_fwdgt.h
\brief definitions for the FWDGT
\version 2018-06-19, V1.0.0, firmware for GD32E230
*/
/*
Copyright (c) 2018, GigaDevice Semiconductor Inc.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E230_FWDGT_H
#define GD32E230_FWDGT_H
#include "gd32e230.h"
/* FWDGT definitions */
#define FWDGT FWDGT_BASE
/* registers definitions */
#define FWDGT_CTL REG32((FWDGT) + 0x00000000U) /*!< FWDGT control register */
#define FWDGT_PSC REG32((FWDGT) + 0x00000004U) /*!< FWDGT prescaler register */
#define FWDGT_RLD REG32((FWDGT) + 0x00000008U) /*!< FWDGT reload register */
#define FWDGT_STAT REG32((FWDGT) + 0x0000000CU) /*!< FWDGT status register */
#define FWDGT_WND REG32((FWDGT) + 0x00000010U) /*!< FWDGT window register */
/* bits definitions */
/* FWDGT_CTL */
#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */
/* FWDGT_PSC */
#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */
/* FWDGT_RLD */
#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */
/* FWDGT_STAT */
#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */
#define FWDGT_STAT_WUD BIT(2) /*!< FWDGT counter window value update */
/* FWDGT_WND */
#define FWDGT_WND_WND BITS(0,11) /*!< FWDGT counter window value */
/* constants definitions */
/* FWDGT_PSC register value */
#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U))
#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */
#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */
#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */
#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */
#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */
/* control value */
#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x00005555U) /*!< FWDGT_CTL bits write access enable value */
#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x00000000U) /*!< FWDGT_CTL bits write access disable value */
#define FWDGT_KEY_RELOAD ((uint16_t)0x0000AAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */
#define FWDGT_KEY_ENABLE ((uint16_t)0x0000CCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */
/* FWDGT timeout value */
#define FWDGT_WND_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_WND register write operation state flag timeout */
#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
/* FWDGT flag definitions */
#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< a write operation to FWDGT_PSC register is on going */
#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< a write operation to FWDGT_RLD register is on going */
#define FWDGT_FLAG_WUD FWDGT_STAT_WUD /*!< a write operation to FWDGT_WND register is on going */
/* function declarations */
/* enable write access to FWDGT_PSC and FWDGT_RLD */
void fwdgt_write_enable(void);
/* disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND */
void fwdgt_write_disable(void);
/* start the free watchdog timer counter */
void fwdgt_enable(void);
/* configure the free watchdog timer counter prescaler value */
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value);
/* configure the free watchdog timer counter reload value */
ErrStatus fwdgt_reload_value_config(uint16_t reload_value);
/* configure the free watchdog timer counter window value */
ErrStatus fwdgt_window_value_config(uint16_t window_value);
/* reload the counter of FWDGT */
void fwdgt_counter_reload(void);
/* configure counter reload value, and prescaler divider value */
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
/* get flag state of FWDGT */
FlagStatus fwdgt_flag_get(uint16_t flag);
#endif /* GD32E230_FWDGT_H */
bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_misc.h 0 → 100644
浏览文件 @ 5d166c38
/*!
\file gd32e230_misc.h
\brief definitions for the MISC
\version 2018-06-19, V1.0.0, firmware for GD32E230
*/
/*
Copyright (c) 2018, GigaDevice Semiconductor Inc.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E230_MISC_H
#define GD32E230_MISC_H
#include "gd32e230.h"
/* constants definitions */
/* set the RAM and FLASH base address */
#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */
#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */
/* set the NVIC vector table offset mask */
#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) /*!< NVIC vector table offset mask */
/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) /*!< NVIC VECTKEY mask */
/* choose the method to enter or exit the lowpower mode */
#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */
#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */
#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */
#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT /*!< low power mode by exiting from ISR */
#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP /*!< DEEPSLEEP mode or SLEEP mode */
#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND /*!< wakeup by all interrupt */
/* choose the systick clock source */
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */
/* function declarations */
/* enable NVIC request */
void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_priority);
/* disable NVIC request */
void nvic_irq_disable(uint8_t nvic_irq);
/* initiates a system reset request to reset the MCU */
void nvic_system_reset(void);
/* set the NVIC vector table base address */
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
/* set the state of the low power mode */
void system_lowpower_set(uint8_t lowpower_mode);
/* reset the state of the low power mode */
void system_lowpower_reset(uint8_t lowpower_mode);
/* set the systick clock source */
void systick_clksource_set(uint32_t systick_clksource);
#endif /* GD32E230_MISC_H */
bsp/gd32e230k-start/Libraries/GD32E230_standard_peripheral/Include/gd32e230_pmu.h 0 → 100644
浏览文件 @ 5d166c38
/*!
\file gd32e230_pmu.h
\brief definitions for the PMU
\version 2018-06-19, V1.0.0, firmware for GD32E230
*/
/*
Copyright (c) 2018, GigaDevice Semiconductor Inc.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/
#ifndef GD32E230_PMU_H
#define GD32E230_PMU_H
#include "gd32e230.h"
/* PMU definitions */
#define PMU PMU_BASE /*!< PMU base address */
/* registers definitions */
#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */
#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */
/* bits definitions */
/* PMU_CTL */
#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */
#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */
#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */
#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */
#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */
#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */
#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */
#define PMU_CTL_LDOVS_0 BIT(14) /*!< LDO output voltage select */
#define PMU_CTL_LDOVS_1 BIT(15) /*!< LDO output voltage select */
#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */
/* PMU_CS */
#define PMU_CS_WUF BIT(0) /*!< wakeup flag */
#define PMU_CS_STBF BIT(1) /*!< standby flag */
#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */
#define PMU_CS_WUPEN0 BIT(8) /*!< wakeup pin enable */
#define PMU_CS_WUPEN1 BIT(9) /*!< wakeup pin enable */
#define PMU_CS_WUPEN5 BIT(13) /*!< wakeup pin enable */
#define PMU_CS_WUPEN6 BIT(14) /*!< wakeup pin enable */
/* constants definitions */
/* PMU low voltage detector threshold definitions */
#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5))
#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */
#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */
#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */
#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */
#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */
#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */
#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */
#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */
/* PMU LDO output voltage select definitions */
#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14))
#define PMU_LDOVS_HIGH CTL_LDOVS(1) /*!< LDO output voltage high mode */
#define PMU_LDOVS_LOW CTL_LDOVS(2) /*!< LDO output voltage low mode */
/* PMU ldo definitions */
#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO operates normally when PMU enter deepsleep mode */
#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */
/* PMU flag definitions */
#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */
#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */
#define PMU_FLAG_LVD PMU_CS_LVDF /*!< LVD flag status */
/* PMU WKUP pin definitions */
#define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0 /*!< WKUP Pin 0 (PA0) enable */
#define PMU_WAKEUP_PIN1 PMU_CS_WUPEN1 /*!< WKUP Pin 1 (PC13) enable */
#define PMU_WAKEUP_PIN5 PMU_CS_WUPEN5 /*!< WKUP Pin 5 (PB5) enable */
#define PMU_WAKEUP_PIN6 PMU_CS_WUPEN6 /*!< WKUP Pin 6 (PB15) enable */
/* PMU flag reset definitions */
#define PMU_FLAG_RESET_WAKEUP PMU_CTL_WURST /*!< wakeup flag reset */
#define PMU_FLAG_RESET_STANDBY PMU_CTL_STBRST /*!< standby flag reset */
/* PMU command constants definitions */
#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */
#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */
/* function declarations */
/* reset PMU registers */
void pmu_deinit(void);
/* select low voltage detector threshold */
void pmu_lvd_select(uint32_t lvdt_n);
/* select LDO output voltage */
void pmu_ldo_output_select(uint32_t ldo_output);
/* disable PMU lvd */
void pmu_lvd_disable(void);
/* set PMU mode */
/* PMU work in sleep mode */
void pmu_to_sleepmode(uint8_t sleepmodecmd);
/* PMU work in deepsleep mode */
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd);
/* PMU work in standby mode */
void pmu_to_standbymode(uint8_t standbymodecmd);
/* enable PMU wakeup pin */
void pmu_wakeup_pin_enable(uint32_t wakeup_pin);
/* disable PMU wakeup pin */
void pmu_wakeup_pin_disable(uint32_t wakeup_pin);
/* backup related functions */
/* enable backup domain write */
void pmu_backup_write_enable(void);
/* disable backup domain write */
void pmu_backup_write_disable(void);
/* flag functions */
/* clear flag bit */
void pmu_flag_clear(uint32_t flag_clear);
/* get flag state */
FlagStatus pmu_flag_get(uint32_t flag);
#endif /* GD32E230_PMU_H */
bsp/gd32e230k-start/Libraries/SConscript 0 → 100644
浏览文件 @ 5d166c38
import rtconfig
from building import *
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Glob('GD32F30x_standard_peripheral/Source/*.c')
src += [cwd + '/CMSIS/GD/GD32F30x/Source/system_gd32f30x.c']
#add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
src += [cwd + '/CMSIS/GD/GD32F30x/Source/GCC/startup_gd32f30x_hd.s']
elif rtconfig.CROSS_TOOL == 'keil':
src += [cwd + '/CMSIS/GD/GD32F30x/Source/ARM/startup_gd32f30x_hd.s']
elif rtconfig.CROSS_TOOL == 'iar':
src += [cwd + '/CMSIS/GD/GD32F30x/Source/IAR/startup_gd32f30x_hd.s']
path = [
cwd + '/CMSIS/GD/GD32F30x/Include',
cwd + '/CMSIS',
cwd + '/GD32F30x_standard_peripheral/Include',]
if GetDepend(['RT_USING_BSP_USB']):
path += [cwd + '/GD32F30x_usb_driver/Include']
src += [cwd + '/GD32F30x_usb_driver/Source']
CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'GD32F30X_HD']
group = DefineGroup('GD32_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')
bsp/gd32e230k-start/SConscript 0 → 100644
浏览文件 @ 5d166c38
# for module compiling
import os
Import('RTT_ROOT')
cwd = str(Dir('#'))
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')
bsp/gd32e230k-start/SConstruct 0 → 100644
浏览文件 @ 5d166c38
此差异已折叠。
bsp/gd32e230k-start/applications/SConscript 0 → 100644
浏览文件 @ 5d166c38
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'applications')
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/gd32e230k-start/applications/main.c 0 → 100644
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bsp/gd32e230k-start/drivers/gd32e230_libopt.h 0 → 100644
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bsp/gd32e230k-start/gd32_rom.icf 0 → 100644
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bsp/gd32e230k-start/gd32_rom.ld 0 → 100644
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libcpu/arm/cortex-m23/context_gcc.S 0 → 100644
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