Fixes the following checkpatch errors:

ERROR: do not use assignment in if condition
Signed-off-by: NRan Sun <sunran001@208suo.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

ERROR: that open brace { should be on the previous line
Signed-off-by: NRan Sun <sunran001@208suo.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

ERROR: that open brace { should be on the previous line
Signed-off-by: NRan Sun <sunran001@208suo.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

ERROR: else should follow close brace '}'

ERROR: space required after that ',' (ctx:VxV)
Signed-off-by: NRan Sun <sunran001@208suo.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

On GFX v9.4.3, compute queue MQD is populated using the values in HQD
persistent state register. Hence don't clear the values on module
unload, instead restore it to the default reset value so that MQD is
initialized correctly during next module load. In particular, preload
flag needs to be set on compute queue MQD, otherwise it could cause
uninitialized values being used at device reset state resulting in EDC.
Signed-off-by: NLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: NAsad Kamal <asad.kamal@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

ERROR: space required after that ';' (ctx:BxV)
Signed-off-by: NRan Sun <sunran001@208suo.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

ERROR: open brace '{' following struct go on the same line
Signed-off-by: NRan Sun <sunran001@208suo.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

To acquire the voltage and current info from gpu_metrics interface,
but gpu_metrics_v2_3 doesn't contain them, and to be backward compatible,
add new gpu_metrics_v2_4 structure.
Reviewed-by: NMario Limonciello <mario.limonciello@amd.com>
Acked-by: NEvan Quan <evan.quan@amd.com>
Signed-off-by: NWenyou Yang <WenYou.Yang@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[why]
User mode driver need to check the sdma ucode version to
see whether the sdma engine supports a new type of PM4 packet.
In SRIOV, sdma is loaded by the host. And, there is no way
to check the sdma ucode version of CHIP_NAVI12 and
CHIP_SIENNA_CICHLID of the host in the guest machine.

[how]
Load the sdma ucode for CHIP_NAVI12 and CHIP_SIENNA_CICHLID
in the guest machine.
Signed-off-by: NYuanShang <YuanShang.Mao@amd.com>
Reviewed-By: NHorace Chen <horace.chen@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

For a constant format without additional arguments, use seq_puts()
instead of seq_printf(). Also, it fixes the following warning.

WARNING: Prefer seq_puts to seq_printf

And other style fixes:

WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
WARNING: Block comments should align the * on each line

Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: NSrinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fixes the following:

WARNING: min() should probably be min_t(size_t, size, sizeof(ip))
+               ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));

And other style fixes:

WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
WARNING: Missing a blank line after declarations

Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: NSrinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Expressions under 'else' branch under case 'CHIP_SIENNA_CICHLID' in
function 'is_fru_eeprom_supported' are executed whenever the expression
in 'if' is False. Otherwise, return from case occurs. Therefore, there
is no need in 'else', and it has been removed.

Fixes the following:

WARNING: else is not generally useful after a break or return
+                               return false;
+                       } else {

Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: NSrinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: NGuchun Chen <guchun.chen@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

drm/amd/display: Remove else after return in 'dm_vblank_get_counter' & 'amdgpu_dm_backlight_get_level'

Expressions under 'else' branch in function 'dm_vblank_get_counter' &
'amdgpu_dm_backlight_get_level' are executed whenever the expression in
'if' is False. Otherwise, return from function occurs. Therefore, there is
no need in 'else', and it has been removed.

Fixes the following:

WARNING: else is not generally useful after a break or return
+               return 0;
+       else {

WARNING: else is not generally useful after a break or return
+               return convert_brightness_to_user(&caps, avg);
+       } else {

Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: NSrinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: NRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Return -ENOMEM, when there is no sufficient dynamically allocated memory

Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: NSrinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Only disable RAS by default for aqua vanjaram on APU platform.
Signed-off-by: NStanley.Yang <Stanley.Yang@amd.com>
Reviewed-by: NTao Zhou <tao.zhou1@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

In case that the GET_INST() is used for looping, only loops for the
times of actual num of xcc, otherwise GET_INST() will return the invalid
index, a.k.a -1

And also remove the redundant mask checking in case of GET_INST()
Signed-off-by: NShiwu Zhang <shiwu.zhang@amd.com>
Reviewed-by: NLe Ma <le.ma@amd.com>
Reviewed-by: NLijo Lazar <lijo.lazar@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This allows tools to distinguish between VRAM and visible VRAM.

Use the opportunity to fix locking before accessing bo.

v2: squash in unused variable fix
Reviewed-by: NChristian König <christian.koenig@amd.com>
Signed-off-by: NPierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Set dynamic_svm_range_dump macro to avoid iterating over SVM lists
from svm_range_debug_dump when dynamic debug is disabled. Otherwise,
it could drop performance, specially with big number of SVM ranges.
Make sure both svm_range_set_attr and svm_range_debug_dump functions
are dynamically enabled to print svm_range_debug_dump debug traces.
Signed-off-by: NAlex Sierra <alex.sierra@amd.com>
Tested-by: NAlex Sierra <alex.sierra@amd.com>
Signed-off-by: NPhilip Yang <Philip.Yang@amd.com>
Reviewed-by: NFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fix two occurrences of the checkpatch.pl error:
ERROR: "foo * bar" should be "foo *bar"
Signed-off-by: NRan Sun <sunran001@208suo.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

ERROR: open brace '{' following struct go on the same line
Signed-off-by: NRan Sun <sunran001@208suo.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

ERROR: open brace '{' following struct go on the same line
Signed-off-by: NRan Sun <sunran001@208suo.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fix the checkpatch error as open brace '{' following struct should
go on the same line.
Signed-off-by: NRan Sun <sunran001@208suo.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This error path needs to unlock the "aconnector->handle_mst_msg_ready"
mutex before returning.

Fixes: bb4fa525 ("drm/amd/display: Add polling method to handle MST reply packet")
Signed-off-by: NDan Carpenter <dan.carpenter@linaro.org>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This version brings along following fixes:
- Fix underflow issue on 175hz timing
- Add interface to modify DMUB panel power options
- Remove check for default eDP panel_mode
- Add new sequence for 4-lane HBR3 on vendor specific retimers
- Update DPG test pattern programming
- Correct unit conversion for vstartup
- Exit idle optimizations before attempt to access PHY
- Refactor recout calculation with a more generic formula
- Read down-spread percentage from lut to adjust dprefclk.
- Don't apply FIFO resync W/A if rdivider = 0
- Prevent invalid pipe connections
- Rearrange dmub_cmd defs order
- Add VESA SCR case for default aux backlight
- Guard DCN31 PHYD32CLK logic against chip family
- Correct grammar mistakes
Acked-by: NAlex Hung <alex.hung@amd.com>
Signed-off-by: NAric Cyr <aric.cyr@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Screen underflows happen on 175hz timing for 3 plane overlay case.

[How]
Based on dst y prefetch value clamp to equ or oto for bandwidth
calculation.
Reviewed-by: NDillon Varone <dillon.varone@amd.com>
Acked-by: NAlex Hung <alex.hung@amd.com>
Signed-off-by: NLeo Ma <hanghong.ma@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
This option can vary depending on the panel and may be required to be
called during sink detection phase before transmitter control.

[How]
Allow modify the bit depending on the eDP panel connected with a new
interface.
Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NAlex Hung <alex.hung@amd.com>
Signed-off-by: NPaul Hsieh <paul.hsieh@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

 - Rearranged defs order
Acked-by: NAlex Hung <alex.hung@amd.com>
Signed-off-by: NAnthony Koo <anthony.koo@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
DPCD read is skipped first time after driver initialization.
Reviewed-by: NCharlene Liu <charlene.liu@amd.com>
Acked-by: NAlex Hung <alex.hung@amd.com>
Signed-off-by: NTaimur Hassan <syed.hassan@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Fixes the following to align to linux coding style:

WARNING: braces {} are not necessary for any arm of this statement
WARNING: Missing a blank line after declarations
ERROR: space prohibited before that close parenthesis ')'
WARNING: unnecessary whitespace before a quoted newline
WARNING: %LX is non-standard C, use %llX

Cc: Christian König <christian.koenig@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: NSrinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
In some vendor specific retimer setups for downstream 4-lane HBR3
configuration, the sink will show severe corruption (horizontal shifting)
and intermittent blanking.

[How]
Add new retimer programming sequence before clock recovery when 4 lanes
are active.
Reviewed-by: NMichael Strauss <michael.strauss@amd.com>
Acked-by: NAlex Hung <alex.hung@amd.com>
Signed-off-by: NOvidiu Bunea <ovidiu.bunea@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Last ODM slice could be slightly larger than other slice because it can be
including the residual.

[How]
Update DPG pattern programming sequence to use a different width for
last odm slice.
Reviewed-by: NChris Park <chris.park@amd.com>
Acked-by: NAlex Hung <alex.hung@amd.com>
Signed-off-by: NWenjing Liu <wenjing.liu@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
vstartup is calculated to be a large number. It works because
it is within vertical blank, but it reduces region of blank that
can be used for power gating.

[How]
Calculation needs to convert micro seconds to number of
vertical lines.
Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NAlex Hung <alex.hung@amd.com>
Signed-off-by: NReza Amini <reza.amini@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why & How]
DMUB may hang when powering down pixel clocks due to no dprefclk.

It is fixed by exiting idle optimization before the attempt to access PHY.
Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NAlex Hung <alex.hung@amd.com>
Signed-off-by: NLeo Chen <sancchen@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Current recout calculation has a few assumptions and implementation
for MPO + ODM combine calculation is very specific. The equation has
too many cases without enough comments to document the detail.

[How]
The change remove the following assumptions:
1. When MPO is enabled, we only allow ODM Combine 2:1
2. ODM Combine always has even segment width.
3. Secondary MPO plane's pipe_ctx copies pre_odm_pipe from
its top pipe.

The change applies a generic formula with more details in comment to
document this solution so it is eaiser to learn and debug later.
Reviewed-by: NDmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Acked-by: NAlex Hung <alex.hung@amd.com>
Signed-off-by: NWenjing Liu <wenjing.liu@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Why]
Panels show corruption with high refresh rate timings when
ss is enabled.

[How]
Read down-spread percentage from lut to adjust dprefclk.
Reviewed-by: NNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: NAlex Hung <alex.hung@amd.com>
Signed-off-by: NMartin Tsai <martin.tsai@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Description]
It is not valid to set the WDIVIDER value to 0, so do not
re-write to DISPCLK_WDIVIDER if the current value is 0
(i.e., it is at it's initial value and we have not made any
requests to change DISPCLK yet).
Reviewed-by: NSaaem Rizvi <syedsaaem.rizvi@amd.com>
Acked-by: NAlex Hung <alex.hung@amd.com>
Signed-off-by: NAlvin Lee <alvin.lee2@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[Description]
 - Prevent ODM pipe connections between pipes that are not part
   of the same plane when adding a plane to context
 - Re-attach child pipes of ODM slice about to be disconnected
   to prevent any lost pipes with invalid tops/bottoms
 - We cannot split if head_pipe is not in ODM. Preventing this
   avoids creating an invalid context with an invalid pipe.
Reviewed-by: NAlvin Lee <alvin.lee2@amd.com>
Acked-by: NAlex Hung <alex.hung@amd.com>
Signed-off-by: NEthan Bitnun <ethan.bitnun@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

Not all rings have scheduler associated. Only update scheduler data for
rings with scheduler. It could result in out of bound access as total
rings are more than those associated with particular IPs.
Signed-off-by: NLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: NJames Zhu <James.Zhu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

This patch will enable VCN FW workaround using
DRM KEY INJECT WORKAROUND method,
which is helping in fixing the secure playback.
Signed-off-by: Nsguttula <Suresh.Guttula@amd.com>
Reviewed-by: NLeo Liu <leo.liiu@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>

[How & Why]
When determining default aux backlight level, read from
DPCD address 0x734 for VESA SCR on OLED.
Reviewed-by: NFelipe Clark <felipe.clark@amd.com>
Acked-by: NAlex Hung <alex.hung@amd.com>
Signed-off-by: NIswara Nagulendran <iswara.nagulendran@amd.com>
Tested-by: NDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>