drm/i915: Don't rely that 2 VDSC engines are always enough for pixel rate
We are currently having FIFO underruns happening for kms_dsc test case, problem is that, we check if curreny cdclk is >= pixel rate only if there is a single VDSC engine enabled(i.e dsc_split=false) however if we happen to have 2 VDSC engines enabled, we just kinda rely that this would be automatically enough. However pixel rate can be even >= than VDSC clock(cdclk) * 2, so in that case even with 2 VDSC engines enabled, we still need to tweak it up. So lets compare pixel rate with cdclk * VDSC engine count and check if it still requires bumping up. Previously we had to bump up CDCLK many times for similar reasons. v2: - Use new intel_dsc_get_num_vdsc_instances to determine number of VDSC engines, instead of slice count(Ankit Nautiyal) v3: - s/u8/int/ (Jani Nikula) v4: - Remove slice count mentions(Ankit Nautiyal) - Use DIV_ROUND_UP in order to make sure that resulting CDCLK would be always >= than required, after division(Ankit Nautiyal) Signed-off-by: NStanislav Lisovskiy <stanislav.lisovskiy@intel.com> Reviewed-by: NAnkit Nautiyal <ankit.k.nautiyal@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230704131758.14024-3-stanislav.lisovskiy@intel.com
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