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提交 e4892b95 编写于 作者: I iysheng
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[bsp][gd32103c-eval] Port rtc, adc, wdt, hwtimer drivers to new gd32 

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上级 382e19cc
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Showing with 192 addition and 41843 deletion
bsp/gd32/gd32103c-eval/board/Kconfig
浏览文件 @ e4892b95
......@@ -74,12 +74,66 @@ menu "On-chip Peripheral Drivers"
range 1 216
default 25
endif
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
config BSP_USING_RTC
bool "Enable Internal RTC"
select RT_USING_RTC
default n
menuconfig BSP_USING_HWTIMER
bool "Enable hwtimer"
default n
select RT_USING_HWTIMER
if BSP_USING_HWTIMER
config BSP_USING_HWTIMER0
bool "using hwtimer0"
default n
config BSP_USING_HWTIMER1
bool "using hwtimer1"
default n
config BSP_USING_HWTIMER2
bool "using hwtimer2"
default n
config BSP_USING_HWTIMER3
bool "using hwtimer3"
default n
config BSP_USING_HWTIMER4
bool "using hwtimer4"
default n
config BSP_USING_HWTIMER5
bool "using hwtimer5"
default n
config BSP_USING_HWTIMER6
bool "using hwtimer6"
default n
config BSP_USING_HWTIMER7
bool "using hwtimer7"
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC0
bool "using adc0"
default n
config BSP_USING_ADC1
bool "using adc1"
default n
endif
source "../libraries/gd32_drivers/Kconfig"
endmenu
menu "Board extended module Drivers"
endmenu
endmenu
bsp/gd32/libraries/GD32F10x_Firmware_Library/SConscript
浏览文件 @ e4892b95
......@@ -40,6 +40,7 @@ if GetDepend(['RT_USING_HWTIMER']):
if GetDepend(['RT_USING_RTC']):
src += ['GD32F10x_standard_peripheral/Source/gd32f10x_rtc.c']
src += ['GD32F10x_standard_peripheral/Source/gd32f10x_pmu.c']
if GetDepend(['RT_USING_WDT']):
src += ['GD32F10x_standard_peripheral/Source/gd32f10x_wwdgt.c']
......
bsp/gd32/libraries/gd32_drivers/SConscript
浏览文件 @ e4892b95
......@@ -27,9 +27,21 @@ if GetDepend('RT_USING_SPI'):
# add spi flash drivers.
if GetDepend('RT_USING_SFUD'):
src += ['drv_spi_flash.c', 'drv_spi.c']
src += ['drv_spi_flash.c', 'drv_spi.c']
path = [cwd]
if GetDepend('RT_USING_WDT'):
src += ['drv_wdt.c']
if GetDepend('RT_USING_RTC'):
src += ['drv_rtc.c']
if GetDepend('RT_USING_HWTIMER'):
src += ['drv_hwtimer.c']
if GetDepend('RT_USING_ADC'):
src += ['drv_adc.c']
path = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
......
bsp/gd32103c-eval/drivers/drv_adc.c → bsp/gd32/libraries/gd32_drivers/drv_adc.c
浏览文件 @ e4892b95
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-03 iysheng first version
* 2021-02-25 iysheng first version
*/
#include <board.h>
#include <drivers/drv_comm.h>
#include <drivers/adc.h>
#define DBG_TAG "drv.adc"
......@@ -39,7 +38,7 @@ static gd32_adc_device g_gd32_devs[] = {
GET_PIN(B, 0), GET_PIN(B, 1), GET_PIN(C, 0), GET_PIN(C, 1),
GET_PIN(C, 2), GET_PIN(C, 3), GET_PIN(C, 4), GET_PIN(C, 5),
},
ADC0,
(void *)ADC0,
},
#endif
......@@ -53,7 +52,7 @@ static gd32_adc_device g_gd32_devs[] = {
GET_PIN(B, 0), GET_PIN(B, 1), GET_PIN(C, 0), GET_PIN(C, 1),
GET_PIN(C, 2), GET_PIN(C, 3), GET_PIN(C, 4), GET_PIN(C, 5),
},
ADC1,
(void *)ADC1,
},
#endif
};
......@@ -61,53 +60,41 @@ static gd32_adc_device g_gd32_devs[] = {
/*
* static void init_pin4adc
*
* 初始化指定的管腳爲 analog 模式
* @ rt_uint32_t pin: pin information
* return: N/A
*/
static void init_pin4adc(rt_base_t pin)
{
GPIO_InitPara GPIO_InitStruct = {0};
GPIO_InitStruct.GPIO_Pin = PIN_GDPIN(pin);
GPIO_InitStruct.GPIO_Speed = GPIO_SPEED_50MHZ;
GPIO_InitStruct.GPIO_Mode = GPIO_MODE_AIN;
GPIO_Init(PIN_GDPORT(pin), &GPIO_InitStruct);
gpio_init(PIN_GDPORT(pin), GPIO_MODE_AIN, GPIO_OSPEED_50MHZ, PIN_GDPIN(pin));
}
static rt_err_t gd32_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
{
ADC_TypeDef *ADCx;
ADC_InitPara ADC_InitParaStruct = {0};
uint32_t adc_periph;
gd32_adc_device * gd32_adc = (gd32_adc_device *)device;
if (channel >= MAX_EXTERN_ADC_CHANNEL)
{
LOG_E("invalid channel");
return -E2BIG;
return -RT_EINVAL;
}
ADCx = (ADC_TypeDef *)(device->parent.user_data);
adc_periph = (uint32_t )(device->parent.user_data);
if (enabled == ENABLE)
{
init_pin4adc(gd32_adc->adc_pins[channel]);
ADC_InitParaStruct.ADC_Trig_External = ADC_EXTERNAL_TRIGGER_MODE_NONE;
/* Fix the channel number to fit the firmware library */
ADC_InitParaStruct.ADC_Channel_Number = 1 + channel;
ADC_InitParaStruct.ADC_Data_Align = ADC_DATAALIGN_RIGHT;
ADC_InitParaStruct.ADC_Mode_Scan = DISABLE;
ADC_InitParaStruct.ADC_Mode = ADC_MODE_INDEPENDENT;
ADC_InitParaStruct.ADC_Mode_Continuous = ENABLE;
ADC_Init(ADCx, &ADC_InitParaStruct);
ADC_RegularChannel_Config(ADCx, channel, 1, ADC_SAMPLETIME_13POINT5);
ADC_Enable(ADCx, ENABLE);
ADC_SoftwareStartConv_Enable(ADCx, ENABLE);
adc_deinit(adc_periph);
adc_channel_length_config(adc_periph, ADC_REGULAR_CHANNEL, 1);
adc_data_alignment_config(adc_periph, ADC_DATAALIGN_RIGHT);
adc_external_trigger_source_config(adc_periph, ADC_REGULAR_CHANNEL, ADC0_1_2_EXTTRIG_INSERTED_NONE);
adc_external_trigger_config(adc_periph, ADC_REGULAR_CHANNEL, ENABLE);
adc_regular_channel_config(adc_periph, 0, channel, ADC_SAMPLETIME_13POINT5);
adc_enable(adc_periph);
}
else
{
ADC_Enable(ADCx, DISABLE);
adc_disable(adc_periph);
}
return 0;
......@@ -115,16 +102,17 @@ static rt_err_t gd32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann
static rt_err_t gd32_adc_convert(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
{
ADC_TypeDef *ADCx;
uint32_t adc_periph;
if (!value)
{
LOG_E("invalid param");
return -EINVAL;
return -RT_EINVAL;
}
ADCx = (ADC_TypeDef *)(device->parent.user_data);
*value = ADC_GetConversionValue(ADCx);
adc_periph = (uint32_t )(device->parent.user_data);
adc_software_trigger_enable(adc_periph, ADC_REGULAR_CHANNEL);
*value = adc_regular_data_read(adc_periph);
return 0;
}
......@@ -148,11 +136,11 @@ static int rt_hw_adc_init(void)
rcu_periph_clock_enable(RCU_ADC1);
#endif
for (; i < ARRAY_SIZE(g_gd32_devs); i++)
for (; i < sizeof(g_gd32_devs) / sizeof(g_gd32_devs[0]); i++)
{
ret = rt_hw_adc_register(&g_gd32_devs[i].adc_dev, \
(const char *)g_gd32_devs[i].name, \
&g_gd32_adc_ops, g_gd32_devs[i].private_data);
&g_gd32_adc_ops, (void *)g_gd32_devs[i].private_data);
if (ret != RT_EOK)
{
/* TODO err handler */
......
bsp/gd32/libraries/gd32_drivers/drv_gpio.h
浏览文件 @ e4892b95
......@@ -38,7 +38,7 @@ extern "C" {
EXTI_SOURCE_PIN##pin}
#else
#define GD32_PIN(index, port, pin) {index, RCU_GPIO##port, \
GPIO##port, GPIO_PIN_##pin, \
GPIO##port, GPIO_PIN_##pin, \
GPIO_PORT_SOURCE_GPIO##port, \
GPIO_PIN_SOURCE_##pin}
......@@ -48,6 +48,12 @@ extern "C" {
#define GET_PIN(PORTx,PIN) (rt_base_t)((16 * ( ((rt_base_t)__GD32_PORT(PORTx) - (rt_base_t)GPIO_BASE)/(0x0400UL) )) + PIN)
#define PIN_PORT(pin) ((uint8_t)(((pin) >> 4) & 0xFu))
#define PIN_NO(pin) ((uint8_t)((pin) & 0xFu))
#define PIN_GDPORT(pin) (GPIO_BASE + (0x400u * PIN_PORT(pin)))
#define PIN_GDPIN(pin) ((uint16_t)(1u << PIN_NO(pin)))
struct pin_index
{
rt_int16_t index;
......
bsp/gd32103c-eval/drivers/drv_hwtimer.c → bsp/gd32/libraries/gd32_drivers/drv_hwtimer.c
浏览文件 @ e4892b95
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-28 iysheng first version
* 2021-02-25 iysheng first version
*/
#include <board.h>
#include <drivers/drv_comm.h>
#include <drivers/drv_hwtimer.h>
#include <rtdevice.h>
#include <drivers/hwtimer.h>
#ifdef BSP_USING_HWTIMER
typedef struct {
uint32_t reg_base;
IRQn_Type irqn;
rcu_periph_enum rcu;
} gd32_hwtimer_data;
typedef struct {
char dev_name[RT_NAME_MAX];
const gd32_hwtimer_data hw_data;
rt_hwtimer_t hwtimer_dev;
const struct rt_hwtimer_info hwtimer_info;
} gd32_hwtimer_device;
enum timer_index_E {
#ifdef BSP_USING_HWTIMER0
TIM0_INDEX,
......@@ -67,49 +80,48 @@ enum timer_index_E {
* @param freq of the timer clock
* @retval None
*/
static void __set_timerx_freq(TIMER_TypeDef *timerx, uint32_t freq)
static void __set_timerx_freq(uint32_t timerx, uint32_t freq)
{
RCC_ClocksPara RCC_Clocks = {0};
uint32_t ap1freq, ap2freq;
uint16_t prescaler;
uint32_t temp;
RCC_GetClocksFreq(&RCC_Clocks);
if (timerx == TIMER0 || timerx == TIMER7 || timerx == TIMER8 \
|| timerx == TIMER9 || timerx == TIMER10)
{
temp = RCC->GCFGR & RCC_GCFGR_APB2PS;
ap2freq = rcu_clock_freq_get(CK_APB2);
temp = RCU_CFG0 & RCU_CFG0_APB2PSC;
temp >>= 11;
/* whether should frequency doubling */
temp = (temp < 4) ? 0 : 1;
prescaler = (RCC_Clocks.APB2_Frequency << temp) / freq - 1;
prescaler = (ap2freq << temp) / freq - 1;
}
else
{
temp = RCC->GCFGR & RCC_GCFGR_APB1PS;
ap1freq = rcu_clock_freq_get(CK_APB1);
temp = RCU_CFG0 & RCU_CFG0_APB1PSC;
temp >>= 8;
/* whether should frequency doubling */
temp = (temp < 4) ? 0 : 1;
prescaler = (RCC_Clocks.APB1_Frequency << temp) / freq - 1;
prescaler = (ap1freq << temp) / freq - 1;
}
TIMER_PrescalerConfig(timerx, prescaler, TIMER_PSC_RELOAD_NOW);
timer_prescaler_config(timerx, prescaler, TIMER_PSC_RELOAD_NOW);
}
static void gd32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
{
TIMER_TypeDef * timer_base = timer->parent.user_data;
TIMER_BaseInitPara TIMER_Init;
RT_ASSERT(timer_base);
uint32_t timer_base = (uint32_t)timer->parent.user_data;
timer_parameter_struct initpara;
if (state)
{
TIMER_InternalClockConfig(timer_base);
TIMER_BaseStructInit(&TIMER_Init);
TIMER_Init.TIMER_Period = timer->info->maxcnt;
TIMER_BaseInit(timer_base, &TIMER_Init);
timer_internal_clock_config(timer_base);
timer_struct_para_init(&initpara);
initpara.period = timer->info->maxcnt;
timer_init(timer_base, &initpara);
__set_timerx_freq(timer_base, timer->info->maxfreq);
}
}
......@@ -117,37 +129,37 @@ static void gd32_hwtimer_init(struct rt_hwtimer_device *timer, rt_uint32_t state
static rt_err_t gd32_hwtimer_start(struct rt_hwtimer_device *timer, \
rt_uint32_t cnt, rt_hwtimer_mode_t mode)
{
TIMER_TypeDef * timer_base = timer->parent.user_data;
uint32_t timer_base = (uint32_t)timer->parent.user_data;
if (mode == HWTIMER_MODE_ONESHOT)
{
TIMER_SinglePulseMode(timer_base, TIMER_SP_MODE_SINGLE);
timer_single_pulse_mode_config(timer_base, TIMER_SP_MODE_SINGLE);
}
else if (mode == HWTIMER_MODE_PERIOD)
{
TIMER_SinglePulseMode(timer_base, TIMER_SP_MODE_REPETITIVE);
timer_single_pulse_mode_config(timer_base, TIMER_SP_MODE_REPETITIVE);
}
TIMER_SetCounter(timer_base, 0);
TIMER_SetAutoreload(timer_base, cnt - 1);
TIMER_Enable(timer_base, ENABLE);
timer_counter_value_config(timer_base, 0);
timer_autoreload_value_config(timer_base, cnt - 1);
timer_enable(timer_base);
return 0;
}
static void gd32_hwtimer_stop(struct rt_hwtimer_device *timer)
{
TIMER_TypeDef * timer_base = timer->parent.user_data;
uint32_t timer_base = (uint32_t)timer->parent.user_data;
TIMER_Enable(timer_base, DISABLE);
timer_disable(timer_base);
}
static rt_uint32_t gd32_hwtimer_count_get(struct rt_hwtimer_device *timer)
{
TIMER_TypeDef * timer_base = timer->parent.user_data;
uint32_t timer_base = (uint32_t)timer->parent.user_data;
rt_uint32_t count;
count = TIMER_GetCounter(timer_base);
count = timer_counter_read(timer_base);
return count;
}
......@@ -163,11 +175,11 @@ static rt_err_t gd32_hwtimer_control(struct rt_hwtimer_device *timer, rt_uint32_
{
case HWTIMER_CTRL_FREQ_SET:
freq = *(rt_uint32_t *)args;
__set_timerx_freq(timer->parent.user_data, freq);
__set_timerx_freq((uint32_t)timer->parent.user_data, freq);
break;
default:
rt_kprintf("invalid cmd:%x\n", cmd);
ret = -EINVAL;
ret = -RT_EINVAL;
break;
}
......@@ -428,8 +440,8 @@ void TIMER0_UP_IRQHandler(void)
{
rt_interrupt_enter();
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM0_INDEX].hwtimer_dev);
TIMER_ClearIntBitState(g_gd32_hwtimer[TIM0_INDEX].hwtimer_dev.parent.user_data, \
TIMER_INT_UPDATE);
timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM0_INDEX].hwtimer_dev.parent.user_data, \
TIMER_INT_UP);
rt_interrupt_leave();
}
#endif
......@@ -439,8 +451,8 @@ void TIMER1_IRQHandler(void)
{
rt_interrupt_enter();
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM1_INDEX].hwtimer_dev);
TIMER_ClearIntBitState(g_gd32_hwtimer[TIM1_INDEX].hwtimer_dev.parent.user_data, \
TIMER_INT_UPDATE);
timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM1_INDEX].hwtimer_dev.parent.user_data, \
TIMER_INT_UP);
rt_interrupt_leave();
}
#endif
......@@ -450,8 +462,8 @@ void TIMER2_IRQHandler(void)
{
rt_interrupt_enter();
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM2_INDEX].hwtimer_dev);
TIMER_ClearIntBitState(g_gd32_hwtimer[TIM2_INDEX].hwtimer_dev.parent.user_data, \
TIMER_INT_UPDATE);
timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM2_INDEX].hwtimer_dev.parent.user_data, \
TIMER_INT_UP);
rt_interrupt_leave();
}
#endif
......@@ -461,8 +473,8 @@ void TIMER3_IRQHandler(void)
{
rt_interrupt_enter();
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM3_INDEX].hwtimer_dev);
TIMER_ClearIntBitState(g_gd32_hwtimer[TIM3_INDEX].hwtimer_dev.parent.user_data, \
TIMER_INT_UPDATE);
timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM3_INDEX].hwtimer_dev.parent.user_data, \
TIMER_INT_UP);
rt_interrupt_leave();
}
#endif
......@@ -472,8 +484,8 @@ void TIMER4_IRQHandler(void)
{
rt_interrupt_enter();
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM4_INDEX].hwtimer_dev);
TIMER_ClearIntBitState(g_gd32_hwtimer[TIM4_INDEX].hwtimer_dev.parent.user_data, \
TIMER_INT_UPDATE);
timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM4_INDEX].hwtimer_dev.parent.user_data, \
TIMER_INT_UP);
rt_interrupt_leave();
}
#endif
......@@ -483,8 +495,8 @@ void TIMER5_IRQHandler(void)
{
rt_interrupt_enter();
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM5_INDEX].hwtimer_dev);
TIMER_ClearIntBitState(g_gd32_hwtimer[TIM5_INDEX].hwtimer_dev.parent.user_data, \
TIMER_INT_UPDATE);
timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM5_INDEX].hwtimer_dev.parent.user_data, \
TIMER_INT_UP);
rt_interrupt_leave();
}
#endif
......@@ -494,8 +506,8 @@ void TIMER6_IRQHandler(void)
{
rt_interrupt_enter();
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM6_INDEX].hwtimer_dev);
TIMER_ClearIntBitState(g_gd32_hwtimer[TIM6_INDEX].hwtimer_dev.parent.user_data, \
TIMER_INT_UPDATE);
timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM6_INDEX].hwtimer_dev.parent.user_data, \
TIMER_INT_UP);
rt_interrupt_leave();
}
#endif
......@@ -505,8 +517,8 @@ void TIMER7_UP_IRQHandler(void)
{
rt_interrupt_enter();
rt_device_hwtimer_isr(&g_gd32_hwtimer[TIM7_INDEX].hwtimer_dev);
TIMER_ClearIntBitState(g_gd32_hwtimer[TIM7_INDEX].hwtimer_dev.parent.user_data, \
TIMER_INT_UPDATE);
timer_flag_clear((uint32_t)g_gd32_hwtimer[TIM7_INDEX].hwtimer_dev.parent.user_data, \
TIMER_INT_UP);
rt_interrupt_leave();
}
#endif
......@@ -515,7 +527,7 @@ static int rt_hwtimer_init(void)
{
int ret = 0, i = 0;
for (; i < ARRAY_SIZE(g_gd32_hwtimer); i++)
for (; i < sizeof(g_gd32_hwtimer) / sizeof(g_gd32_hwtimer[0]); i++)
{
g_gd32_hwtimer[i].hwtimer_dev.ops = &g_gd32_hwtimer_ops;
g_gd32_hwtimer[i].hwtimer_dev.info = &g_gd32_hwtimer[i].hwtimer_info;
......@@ -523,9 +535,9 @@ static int rt_hwtimer_init(void)
rcu_periph_clock_enable(g_gd32_hwtimer[i].hw_data.rcu);
NVIC_SetPriority(g_gd32_hwtimer[i].hw_data.irqn, 0);
NVIC_EnableIRQ(g_gd32_hwtimer[i].hw_data.irqn);
TIMER_INTConfig(g_gd32_hwtimer[i].hw_data.reg_base, TIMER_INT_UPDATE, ENABLE);
timer_interrupt_enable(g_gd32_hwtimer[i].hw_data.reg_base, TIMER_INT_UP);
ret = rt_device_hwtimer_register(&g_gd32_hwtimer[i].hwtimer_dev, \
g_gd32_hwtimer[i].dev_name, g_gd32_hwtimer[i].hw_data.reg_base);
g_gd32_hwtimer[i].dev_name, (void *)g_gd32_hwtimer[i].hw_data.reg_base);
if (RT_EOK != ret)
{
rt_kprintf("failed register %s, err=%d\n", g_gd32_hwtimer[i].dev_name, \
......
bsp/gd32103c-eval/drivers/drv_rtc.c → bsp/gd32/libraries/gd32_drivers/drv_rtc.c
浏览文件 @ e4892b95
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-02-20 iysheng first version
* 2022-01-25 iysheng first version
*/
#include <board.h>
#include <sys/time.h>
#include <drivers/drv_comm.h>
#define DBG_TAG "drv.rtc"
#define DBG_LVL DBG_INFO
......@@ -29,7 +28,7 @@ static time_t get_rtc_timestamp(void)
{
time_t rtc_counter;
rtc_counter = (time_t)RTC_GetCounter();
rtc_counter = (time_t)rtc_counter_get();
return rtc_counter;
}
......@@ -41,15 +40,15 @@ static rt_err_t set_rtc_timestamp(time_t time_stamp)
rtc_counter = (uint32_t)time_stamp;
/* wait until LWOFF bit in RTC_CTL to 1 */
RTC_WaitLWOFF();
rtc_lwoff_wait();
/* enter configure mode */
RTC_EnterConfigMode();
rtc_configuration_mode_enter();
/* write data to rtc register */
RTC_SetCounter(rtc_counter);
rtc_counter_set(rtc_counter);
/* exit configure mode */
RTC_ExitConfigMode();
rtc_configuration_mode_exit();
/* wait until LWOFF bit in RTC_CTL to 1 */
RTC_WaitLWOFF();
rtc_lwoff_wait();
return RT_EOK;
}
......@@ -94,7 +93,7 @@ static int rt_hw_rtc_init(void)
time_t rtc_counter;
rcu_periph_clock_enable(RCU_PMU);
PWR_BackupAccess_Enable(ENABLE);
pmu_backup_write_enable();
rcu_periph_clock_enable(RCU_BKPI);
rtc_counter = get_rtc_timestamp();
......
bsp/gd32103c-eval/drivers/drv_iwdt.c → bsp/gd32/libraries/gd32_drivers/drv_wdt.c
浏览文件 @ e4892b95
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
* Copyright (c) 2006-2022, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-03-03 iysheng first version
* 2022-01-25 iysheng first version
*/
#include <board.h>
......@@ -25,13 +25,13 @@ typedef struct {
static gd32_wdt_device_t g_wdt_dev;
static rt_err_t gd32_iwdt_init(rt_watchdog_t *wdt)
static rt_err_t gd32_wdt_init(rt_watchdog_t *wdt)
{
rcu_osci_on(RCU_IRC40K);
if (ERROR == rcu_osci_stab_wait(RCU_IRC40K))
{
LOG_E("failed init IRC40K clock for free watchdog.");
return -EINVAL;
return -RT_EINVAL;
}
g_wdt_dev.min_threshold_s = 1;
......@@ -39,22 +39,21 @@ static rt_err_t gd32_iwdt_init(rt_watchdog_t *wdt)
LOG_I("threshold section [%u, %d]", \
g_wdt_dev.min_threshold_s, g_wdt_dev.max_threshold_s);
IWDG_Write_Enable(IWDG_WRITEACCESS_ENABLE);
IWDG_SetPrescaler(IWDG_PRESCALER_256);
IWDG_SetReloadValue(0xfff);
IWDG_Write_Enable(IWDG_WRITEACCESS_DISABLE);
fwdgt_write_enable();
fwdgt_config(0xfff, FWDGT_PSC_DIV256);
fwdgt_enable();
return 0;
}
static rt_err_t gd32_iwdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
static rt_err_t gd32_wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
{
rt_uint32_t param;
switch (cmd)
{
case RT_DEVICE_CTRL_WDT_KEEPALIVE:
IWDG_ReloadCounter();
fwdgt_counter_reload();
break;
case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
param = *(rt_uint32_t *) arg;
......@@ -62,21 +61,21 @@ static rt_err_t gd32_iwdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
(param < g_wdt_dev.min_threshold_s))
{
LOG_E("invalid param@%u.", param);
return -E2BIG;
return -RT_EINVAL;
}
else
{
g_wdt_dev.current_threshold_s = param;
}
IWDG_Write_Enable(IWDG_WRITEACCESS_ENABLE);
IWDG_SetReloadValue(param * 40000 >> 8);
IWDG_Write_Enable(IWDG_WRITEACCESS_DISABLE);
fwdgt_write_enable();
fwdgt_config(param * 40000 >> 8, FWDGT_PSC_DIV256);
fwdgt_write_disable();
break;
case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
*(rt_uint32_t *)arg = g_wdt_dev.current_threshold_s;
break;
case RT_DEVICE_CTRL_WDT_START:
IWDG_Enable();
fwdgt_enable();
break;
default:
LOG_W("This command is not supported.");
......@@ -87,17 +86,17 @@ static rt_err_t gd32_iwdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
}
static struct rt_watchdog_ops g_wdt_ops = {
gd32_iwdt_init,
gd32_iwdt_control,
gd32_wdt_init,
gd32_wdt_control,
};
static int rt_hw_iwdt_init(void)
static int rt_hw_wdt_init(void)
{
rt_err_t ret;
g_wdt_dev.wdt.ops = &g_wdt_ops;
/* register watchdog device */
if (rt_hw_watchdog_register(&g_wdt_dev.wdt, "iwdt", \
if (rt_hw_watchdog_register(&g_wdt_dev.wdt, "wdt", \
RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
{
LOG_E("wdt device register failed.");
......@@ -107,5 +106,5 @@ static int rt_hw_iwdt_init(void)
return ret;
}
INIT_BOARD_EXPORT(rt_hw_iwdt_init);
INIT_PREV_EXPORT(rt_hw_wdt_init);
#endif
bsp/gd32103c-eval/.config 已删除 100644 → 0
浏览文件 @ 382e19cc
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_BIG_ENDIAN is not set
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_HOOK_USING_FUNC_PTR=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
#
# kservice optimization
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_TINY_FFS is not set
# CONFIG_RT_PRINTF_LONGLONG is not set
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMHEAP is not set
CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
# CONFIG_RT_USING_SLAB_AS_HEAP is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
# CONFIG_RT_USING_HEAP_ISR is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_VER_NUM=0x40100
# CONFIG_RT_USING_CPU_FFS is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
# CONFIG_RT_USING_LEGACY is not set
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_RT_USING_MSH=y
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_CMD_SIZE=80
CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_POSIX=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=2
CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB is not set
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
# CONFIG_RT_USING_MODULE is not set
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# POSIX (Portable Operating System Interface) layer
#
# CONFIG_RT_USING_POSIX_FS is not set
# CONFIG_RT_USING_POSIX_DELAY is not set
# CONFIG_RT_USING_POSIX_CLOCK is not set
# CONFIG_RT_USING_PTHREADS is not set
#
# Interprocess Communication (IPC)
#
# CONFIG_RT_USING_POSIX_PIPE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
#
# Socket is in the 'Network' category
#
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_RT_LINK is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
# CONFIG_PKG_USING_ZB_COORDINATOR is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_EZ_IOT_OS is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
# CONFIG_PKG_USING_RAPIDJSON is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_AGILE_MODBUS is not set
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
# CONFIG_PKG_USING_LORA_PKT_FWD is not set
# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
# CONFIG_PKG_USING_HM is not set
# CONFIG_PKG_USING_SMALL_MODBUS is not set
# CONFIG_PKG_USING_NET_SERVER is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_LIBSODIUM is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
#
# CONFIG_PKG_USING_LUATOS_SOC is not set
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
# CONFIG_PKG_USING_PIKASCRIPT is not set
#
# multimedia packages
#
#
# LVGL: powerful and easy-to-use embedded GUI library
#
# CONFIG_PKG_USING_LVGL is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
#
# u8g2: a monochrome graphic library
#
# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_PDFGEN is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
# CONFIG_PKG_USING_NUEMWIN is not set
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
# CONFIG_PKG_USING_UGUI is not set
#
# PainterEngine: A cross-platform graphics application framework written in C language
#
# CONFIG_PKG_USING_PAINTERENGINE is not set
# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_TERMBOX is not set
# CONFIG_PKG_USING_VT100 is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_MEMORYPERF is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
# CONFIG_PKG_USING_KDB is not set
# CONFIG_PKG_USING_WAMR is not set
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
# CONFIG_PKG_USING_LWLOG is not set
# CONFIG_PKG_USING_ANV_TRACE is not set
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
# CONFIG_PKG_USING_ANV_BENCH is not set
# CONFIG_PKG_USING_DEVMEM is not set
# CONFIG_PKG_USING_REGEX is not set
# CONFIG_PKG_USING_MEM_SANDBOX is not set
# CONFIG_PKG_USING_SOLAR_TERMS is not set
# CONFIG_PKG_USING_GAN_ZHI is not set
# CONFIG_PKG_USING_FDT is not set
#
# system packages
#
#
# enhanced kernel services
#
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
#
# POSIX extension functions
#
# CONFIG_PKG_USING_POSIX_GETLINE is not set
# CONFIG_PKG_USING_POSIX_WCWIDTH is not set
# CONFIG_PKG_USING_POSIX_ITOA is not set
#
# acceleration: Assembly language or algorithmic acceleration packages
#
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
#
# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
#
# CONFIG_PKG_USING_CMSIS_5 is not set
# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
# CONFIG_PKG_USING_UC_CRC is not set
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_RT_USING_ARDUINO is not set
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
# CONFIG_PKG_USING_DFS_UFFS is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
# CONFIG_PKG_USING_ARM_2D is not set
# CONFIG_PKG_USING_MCUBOOT is not set
# CONFIG_PKG_USING_TINYUSB is not set
# CONFIG_PKG_USING_USB_STACK is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
# CONFIG_PKG_USING_TMC51XX is not set
# CONFIG_PKG_USING_TCA9534 is not set
# CONFIG_PKG_USING_KOBUKI is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_MICRO_ROS is not set
# CONFIG_PKG_USING_MCP23008 is not set
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
# CONFIG_PKG_USING_BL_MCU_SDK is not set
# CONFIG_PKG_USING_SOFT_SERIAL is not set
# CONFIG_PKG_USING_MB85RS16 is not set
# CONFIG_PKG_USING_CW2015 is not set
#
# AI packages
#
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# miscellaneous packages
#
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# entertainment: terminal games and other interesting software packages
#
# CONFIG_PKG_USING_CMATRIX is not set
# CONFIG_PKG_USING_SL is not set
# CONFIG_PKG_USING_CAL is not set
# CONFIG_PKG_USING_ACLOCK is not set
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_MINIZIP is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_DESIGN_PATTERN is not set
CONFIG_SOC_SERIES_GD32F1=y
CONFIG_SOC_GD32103C=y
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART0=y
# CONFIG_BSP_USING_UART1 is not set
# CONFIG_BSP_USING_UART2 is not set
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_UART4 is not set
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_HWTIMER is not set
# CONFIG_BSP_USING_WDT is not set
# CONFIG_BSP_USING_RTC is not set
bsp/gd32103c-eval/Kconfig 已删除 100644 → 0
浏览文件 @ 382e19cc
mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
# you can change the RTT_ROOT default: "rt-thread"
# example : default "F:/git_repositories/rt-thread"
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
config SOC_SERIES_GD32F1
bool
default y
config SOC_GD32103C
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
select SOC_SERIES_GD32F1
default y
menu "On-chip Peripheral Drivers"
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART0
bool "using uart0"
default n
config BSP_USING_UART1
bool "using uart1"
default n
config BSP_USING_UART2
bool "using uart2"
default y
config BSP_USING_UART3
bool "using uart3"
default n
config BSP_USING_UART4
bool "using uart4"
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC0
bool "using adc0"
default n
config BSP_USING_ADC1
bool "using adc1"
default n
endif
menuconfig BSP_USING_HWTIMER
bool "Enable hwtimer"
default n
select RT_USING_HWTIMER
if BSP_USING_HWTIMER
config BSP_USING_HWTIMER0
bool "using hwtimer0"
default n
config BSP_USING_HWTIMER1
bool "using hwtimer1"
default n
config BSP_USING_HWTIMER2
bool "using hwtimer2"
default n
config BSP_USING_HWTIMER3
bool "using hwtimer3"
default n
config BSP_USING_HWTIMER4
bool "using hwtimer4"
default n
config BSP_USING_HWTIMER5
bool "using hwtimer5"
default n
config BSP_USING_HWTIMER6
bool "using hwtimer6"
default n
config BSP_USING_HWTIMER7
bool "using hwtimer7"
default n
endif
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
config BSP_USING_RTC
bool "using internal rtc"
default n
select RT_USING_RTC
endmenu
bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/gd32f10x_conf.h 已删除 100644 → 0
浏览文件 @ 382e19cc
/**
******************************************************************************
* @brief Configuration file.
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __GD32F10X_CONF_H
#define __GD32F10X_CONF_H
/* Includes ------------------------------------------------------------------*/
/* Comment the line below to disable peripheral header file inclusion */
#include "gd32f10x_adc.h"
#include "gd32f10x_bkp.h"
#include "gd32f10x_can.h"
#include "gd32f10x_crc.h"
#include "gd32f10x_dac.h"
#include "gd32f10x_dma.h"
#include "gd32f10x_eth.h"
#include "gd32f10x_exmc.h"
#include "gd32f10x_exti.h"
#include "gd32f10x_fmc.h"
#include "gd32f10x_gpio.h"
#include "gd32f10x_i2c.h"
#include "gd32f10x_iwdg.h"
#include "gd32f10x_mcudbg.h"
#include "gd32f10x_misc.h"
#include "gd32f10x_pwr.h"
#include "gd32f10x_rcc.h"
#include "gd32f10x_rcu.h"
#include "gd32f10x_rtc.h"
#include "gd32f10x_sdio.h"
#include "gd32f10x_spi.h"
#include "gd32f10x_timer.h"
#include "gd32f10x_usart.h"
#include "gd32f10x_wwdg.h"
#endif /* __GD32F10X_CONF_H */
bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Include/system_gd32f10x.h 已删除 100644 → 0
浏览文件 @ 382e19cc
/**
******************************************************************************
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup GD32F10x_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_GD32F10X_H
#define __SYSTEM_GD32F10X_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup GD32F10x_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup GD32F10x_System_Exported_types
* @{
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* @}
*/
/** @addtogroup GD32F10x_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_GD32F10X_H */
/**
* @}
*/
/**
* @}
*/
bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Source/GCC/isr_tab.s 已删除 100644 → 0
浏览文件 @ 382e19cc
/*
* File : isr_tab.s
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2021, RT-Thread Development Team
*
* Change Logs:
* Date Author Notes
* 2021-01-02 iysheng first implementation
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_isr_vectors
.section .isr_vector,"a",%progbits
.type g_isr_vectors, STT_OBJECT
.weak Reset_Handler
g_isr_vectors:
.word _estack /* Top of Stack */
.word Reset_Handler /* Reset Handler */
.word NMI_Handler /* NMI Handler */
.word HardFault_Handler /* Hard Fault Handler */
.word MemManage_Handler /* MPU Fault Handler */
.word BusFault_Handler /* Bus Fault Handler */
.word UsageFault_Handler /* Usage Fault Handler */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word SVC_Handler /* SVCall Handler */
.word DebugMon_Handler /* Debug Monitor Handler */
.word 0 /* Reserved */
.word PendSV_Handler /* PendSV Handler */
.word SysTick_Handler /* SysTick Handler */
/* external interrupts handler */
.word WWDGT_IRQHandler /* 16:Window Watchdog Timer */
.word LVD_IRQHandler /* 17:LVD through EXTI Line detect */
.word TAMPER_IRQHandler /* 18:Tamper through EXTI Line detect */
.word RTC_IRQHandler /* 19:RTC through EXTI Line */
.word FMC_IRQHandler /* 20:FMC */
.word RCU_CTC_IRQHandler /* 21:RCU and CTC */
.word EXTI0_IRQHandler /* 22:EXTI Line 0 */
.word EXTI1_IRQHandler /* 23:EXTI Line 1 */
.word EXTI2_IRQHandler /* 24:EXTI Line 2 */
.word EXTI3_IRQHandler /* 25:EXTI Line 3 */
.word EXTI4_IRQHandler /* 26:EXTI Line 4 */
.word DMA0_Channel0_IRQHandler /* 27:DMA0 Channel0 */
.word DMA0_Channel1_IRQHandler /* 28:DMA0 Channel1 */
.word DMA0_Channel2_IRQHandler /* 29:DMA0 Channel2 */
.word DMA0_Channel3_IRQHandler /* 30:DMA0 Channel3 */
.word DMA0_Channel4_IRQHandler /* 31:DMA0 Channel4 */
.word DMA0_Channel5_IRQHandler /* 32:DMA0 Channel5 */
.word DMA0_Channel6_IRQHandler /* 33:DMA0 Channel6 */
.word ADC0_1_IRQHandler /* 34:ADC0 and ADC1 */
.word USBD_HP_CAN0_TX_IRQHandler /* 35:USBD HP and CAN0 TX */
.word USBD_LP_CAN0_RX0_IRQHandler /* 36:USBD LP and CAN0 RX0 */
.word CAN0_RX1_IRQHandler /* 37:CAN0 RX1 */
.word CAN0_EWMC_IRQHandler /* 38:CAN0 EWMC */
.word EXTI5_9_IRQHandler /* 39:EXTI5 to EXTI9 */
.word TIMER0_BRK_IRQHandler /* 40:TIMER0 Break */
.word TIMER0_UP_IRQHandler /* 41:TIMER0 Update */
.word TIMER0_TRG_CMT_IRQHandler /* 42:TIMER0 Trigger and Commutation */
.word TIMER0_Channel_IRQHandler /* 43:TIMER0 Channel Capture Compare */
.word TIMER1_IRQHandler /* 44:TIMER1 */
.word TIMER2_IRQHandler /* 45:TIMER2 */
.word TIMER3_IRQHandler /* 46:TIMER3 */
.word I2C0_EV_IRQHandler /* 47:I2C0 Event */
.word I2C0_ER_IRQHandler /* 48:I2C0 Error */
.word I2C1_EV_IRQHandler /* 49:I2C1 Event */
.word I2C1_ER_IRQHandler /* 50:I2C1 Error */
.word SPI0_IRQHandler /* 51:SPI0 */
.word SPI1_IRQHandler /* 52:SPI1 */
.word USART0_IRQHandler /* 53:USART0 */
.word USART1_IRQHandler /* 54:USART1 */
.word USART2_IRQHandler /* 55:USART2 */
.word EXTI10_15_IRQHandler /* 56:EXTI10 to EXTI15 */
.word RTC_Alarm_IRQHandler /* 57:RTC Alarm */
.word USBD_WKUP_IRQHandler /* 58:USBD Wakeup */
.word TIMER7_BRK_IRQHandler /* 59:TIMER7 Break */
.word TIMER7_UP_IRQHandler /* 60:TIMER7 Update */
.word TIMER7_TRG_CMT_IRQHandler /* 61:TIMER7 Trigger and Commutation */
.word TIMER7_Channel_IRQHandler /* 62:TIMER7 Channel Capture Compare */
.word ADC2_IRQHandler /* 63:ADC2 */
.word EXMC_IRQHandler /* 64:EXMC */
.word SDIO_IRQHandler /* 65:SDIO */
.word TIMER4_IRQHandler /* 66:TIMER4 */
.word SPI2_IRQHandler /* 67:SPI2 */
.word UART3_IRQHandler /* 68:UART3 */
.word UART4_IRQHandler /* 69:UART4 */
.word TIMER5_IRQHandler /* 70:TIMER5 */
.word TIMER6_IRQHandler /* 71:TIMER6 */
.word DMA1_Channel0_IRQHandler /* 72:DMA1 Channel0 */
.word DMA1_Channel1_IRQHandler /* 73:DMA1 Channel1 */
.word DMA1_Channel2_IRQHandler /* 74:DMA1 Channel2 */
.word DMA1_Channel3_4_IRQHandler /* 75:DMA1 Channel3 and Channel4 */
/* Exception Handlers */
.weak NMI_Handler
.type NMI_Handler, STT_FUNC
NMI_Handler:
b .
.weak MemManage_Handler
.type MemManage_Handler, STT_FUNC
MemManage_Handler:
b .
.weak BusFault_Handler
.type BusFault_Handler, STT_FUNC
BusFault_Handler:
b .
.weak UsageFault_Handler
.type UsageFault_Handler, STT_FUNC
UsageFault_Handler:
b .
.weak SVC_Handler
.type SVC_Handler, STT_FUNC
SVC_Handler:
b .
.weak DebugMon_Handler
.type DebugMon_Handler, STT_FUNC
DebugMon_Handler:
b .
.weak PendSV_Handler
.type PendSV_Handler, STT_FUNC
PendSV_Handler:
b .
.weak SysTick_Handler
.type SysTick_Handler, STT_FUNC
SysTick_Handler:
b .
.global default_irq_handler
.section .text.default_irq_handler,"ax",%progbits
.type default_irq_handler, STT_FUNC
default_irq_handler:
b .
.macro IRQ handler
.weak \handler
.set \handler, default_irq_handler
.endm
/* IQR Handler */
IRQ WWDGT_IRQHandler
IRQ LVD_IRQHandler
IRQ TAMPER_IRQHandler
IRQ RTC_IRQHandler
IRQ FMC_IRQHandler
IRQ RCU_CTC_IRQHandler
IRQ EXTI0_IRQHandler
IRQ EXTI1_IRQHandler
IRQ EXTI2_IRQHandler
IRQ EXTI3_IRQHandler
IRQ EXTI4_IRQHandler
IRQ DMA0_Channel0_IRQHandler
IRQ DMA0_Channel1_IRQHandler
IRQ DMA0_Channel2_IRQHandler
IRQ DMA0_Channel3_IRQHandler
IRQ DMA0_Channel4_IRQHandler
IRQ DMA0_Channel5_IRQHandler
IRQ DMA0_Channel6_IRQHandler
IRQ ADC0_1_IRQHandler
IRQ USBD_HP_CAN0_TX_IRQHandler
IRQ USBD_LP_CAN0_RX0_IRQHandler
IRQ CAN0_RX1_IRQHandler
IRQ CAN0_EWMC_IRQHandler
IRQ EXTI5_9_IRQHandler
IRQ TIMER0_BRK_IRQHandler
IRQ TIMER0_UP_IRQHandler
IRQ TIMER0_TRG_CMT_IRQHandler
IRQ TIMER0_Channel_IRQHandler
IRQ TIMER1_IRQHandler
IRQ TIMER2_IRQHandler
IRQ TIMER3_IRQHandler
IRQ I2C0_EV_IRQHandler
IRQ I2C0_ER_IRQHandler
IRQ I2C1_EV_IRQHandler
IRQ I2C1_ER_IRQHandler
IRQ SPI0_IRQHandler
IRQ SPI1_IRQHandler
IRQ USART0_IRQHandler
IRQ USART1_IRQHandler
IRQ USART2_IRQHandler
IRQ EXTI10_15_IRQHandler
IRQ RTC_Alarm_IRQHandler
IRQ USBD_WKUP_IRQHandler
IRQ TIMER7_BRK_IRQHandler
IRQ TIMER7_UP_IRQHandler
IRQ TIMER7_TRG_CMT_IRQHandler
IRQ TIMER7_Channel_IRQHandler
IRQ ADC2_IRQHandler
IRQ EXMC_IRQHandler
IRQ SDIO_IRQHandler
IRQ TIMER4_IRQHandler
IRQ SPI2_IRQHandler
IRQ UART3_IRQHandler
IRQ UART4_IRQHandler
IRQ TIMER5_IRQHandler
IRQ TIMER6_IRQHandler
IRQ DMA1_Channel0_IRQHandler
IRQ DMA1_Channel1_IRQHandler
IRQ DMA1_Channel2_IRQHandler
IRQ DMA1_Channel3_4_IRQHandler
bsp/gd32103c-eval/Libraries/CMSIS/GD/GD32F1xx/Source/GCC/startup_gd32.s 已删除 100644 → 0
浏览文件 @ 382e19cc
/*
* File : startup_gd32f10x_hd.s
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2021, RT-Thread Development Team
*
* Change Logs:
* Date Author Notes
* 2021-01-02 iysheng first implementation
*/
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global Reset_Handler
.section .text.Reset_Handler
.type Reset_Handler, STT_FUNC
Reset_Handler:
ldr r1, =_sidata
ldr r2, =_sdata
ldr r3, =_edata
subs r3, r2
ble fill_bss_start
loop_copy_data:
subs r3, #4
ldr r0, [r1,r3]
str r0, [r2,r3]
bgt loop_copy_data
fill_bss_start:
ldr r1, =__bss_start
ldr r2, =__bss_end
movs r0, 0
subs r2, r1
ble startup_enter
loop_fill_bss:
subs r2, #4
str r0, [r1, r2]
bgt loop_fill_bss
startup_enter:
bl SystemInit
bl entry
bsp/gd32103c-eval/Libraries/CMSIS/core_cm3.c 已删除 100644 → 0
浏览文件 @ 382e19cc
/**************************************************************************//**
* @file core_cm3.c
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
* @version V1.30
* @date 30. October 2009
*
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/* ################### Compiler specific Intrinsics ########################### */
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
__ASM uint32_t __get_PSP(void)
{
mrs r0, psp
bx lr
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
__ASM void __set_PSP(uint32_t topOfProcStack)
{
msr psp, r0
bx lr
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
__ASM uint32_t __get_MSP(void)
{
mrs r0, msp
bx lr
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
__ASM void __set_MSP(uint32_t mainStackPointer)
{
msr msp, r0
bx lr
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
__ASM uint32_t __REV16(uint16_t value)
{
rev16 r0, r0
bx lr
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
__ASM int32_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#if (__ARMCC_VERSION < 400000)
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
__ASM void __CLREX(void)
{
clrex
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
__ASM uint32_t __get_BASEPRI(void)
{
mrs r0, basepri
bx lr
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
__ASM void __set_BASEPRI(uint32_t basePri)
{
msr basepri, r0
bx lr
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
__ASM uint32_t __get_PRIMASK(void)
{
mrs r0, primask
bx lr
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
__ASM void __set_PRIMASK(uint32_t priMask)
{
msr primask, r0
bx lr
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
__ASM uint32_t __get_FAULTMASK(void)
{
mrs r0, faultmask
bx lr
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
__ASM void __set_FAULTMASK(uint32_t faultMask)
{
msr faultmask, r0
bx lr
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
__ASM uint32_t __get_CONTROL(void)
{
mrs r0, control
bx lr
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
__ASM void __set_CONTROL(uint32_t control)
{
msr control, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#pragma diag_suppress=Pe940
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void)
{
__ASM("mrs r0, psp");
__ASM("bx lr");
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack)
{
__ASM("msr psp, r0");
__ASM("bx lr");
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void)
{
__ASM("mrs r0, msp");
__ASM("bx lr");
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack)
{
__ASM("msr msp, r0");
__ASM("bx lr");
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
__ASM("rev16 r0, r0");
__ASM("bx lr");
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
__ASM("rbit r0, r0");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit values)
*/
uint8_t __LDREXB(uint8_t *addr)
{
__ASM("ldrexb r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
__ASM("ldrexh r0, [r0]");
__ASM("bx lr");
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
__ASM("ldrex r0, [r0]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
__ASM("strexb r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
__ASM("strexh r0, r0, [r1]");
__ASM("bx lr");
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
__ASM("strex r0, r0, [r1]");
__ASM("bx lr");
}
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
uint32_t __get_PSP(void) __attribute__((naked));
uint32_t __get_PSP(void)
{
uint32_t result = 0;
__ASM volatile("MRS %0, psp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r"(result));
return (result);
}
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
void __set_PSP(uint32_t topOfProcStack) __attribute__((naked));
void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile("MSR psp, %0\n\t"
"BX lr \n\t" : : "r"(topOfProcStack));
}
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
uint32_t __get_MSP(void) __attribute__((naked));
uint32_t __get_MSP(void)
{
uint32_t result = 0;
__ASM volatile("MRS %0, msp\n\t"
"MOV r0, %0 \n\t"
"BX lr \n\t" : "=r"(result));
return (result);
}
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
void __set_MSP(uint32_t topOfMainStack) __attribute__((naked));
void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile("MSR msp, %0\n\t"
"BX lr \n\t" : : "r"(topOfMainStack));
}
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
uint32_t __get_BASEPRI(void)
{
uint32_t result = 0;
__ASM volatile("MRS %0, basepri_max" : "=r"(result));
return (result);
}
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
void __set_BASEPRI(uint32_t value)
{
__ASM volatile("MSR basepri, %0" : : "r"(value));
}
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
uint32_t __get_PRIMASK(void)
{
uint32_t result = 0;
__ASM volatile("MRS %0, primask" : "=r"(result));
return (result);
}
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile("MSR primask, %0" : : "r"(priMask));
}
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
uint32_t __get_FAULTMASK(void)
{
uint32_t result = 0;
__ASM volatile("MRS %0, faultmask" : "=r"(result));
return (result);
}
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile("MSR faultmask, %0" : : "r"(faultMask));
}
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
uint32_t __get_CONTROL(void)
{
uint32_t result = 0;
__ASM volatile("MRS %0, control" : "=r"(result));
return (result);
}
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
void __set_CONTROL(uint32_t control)
{
__ASM volatile("MSR control, %0" : : "r"(control));
}
/**
* @brief Reverse byte order in integer value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
uint32_t __REV(uint32_t value)
{
uint32_t result = 0;
__ASM volatile("rev %0, %1" : "=r"(result) : "r"(value));
return (result);
}
/**
* @brief Reverse byte order in unsigned short value
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
uint32_t __REV16(uint16_t value)
{
uint32_t result = 0;
__ASM volatile("rev16 %0, %1" : "=r"(result) : "r"(value));
return (result);
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
int32_t __REVSH(int16_t value)
{
uint32_t result = 0;
__ASM volatile("revsh %0, %1" : "=r"(result) : "r"(value));
return (result);
}
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
uint32_t __RBIT(uint32_t value)
{
uint32_t result = 0;
__ASM volatile("rbit %0, %1" : "=r"(result) : "r"(value));
return (result);
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit value
*/
uint8_t __LDREXB(uint8_t *addr)
{
uint8_t result = 0;
__ASM volatile("ldrexb %0, [%1]" : "=r"(result) : "r"(addr));
return (result);
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
uint16_t __LDREXH(uint16_t *addr)
{
uint16_t result = 0;
__ASM volatile("ldrexh %0, [%1]" : "=r"(result) : "r"(addr));
return (result);
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
uint32_t __LDREXW(uint32_t *addr)
{
uint32_t result = 0;
__ASM volatile("ldrex %0, [%1]" : "=r"(result) : "r"(addr));
return (result);
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result = 0;
__ASM volatile("strexb %0, %2, [%1]" : "=r"(result) : "r"(addr), "r"(value));
return (result);
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
uint32_t result = 0;
__ASM volatile("strexh %0, %2, [%1]" : "=r"(result) : "r"(addr), "r"(value));
return (result);
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
uint32_t result = 0;
__ASM volatile("strex %0, %2, [%1]" : "=r"(result) : "r"(addr), "r"(value));
return (result);
}
#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
bsp/gd32103c-eval/Libraries/CMSIS/core_cm3.h 已删除 100644 → 0
浏览文件 @ 382e19cc
此差异已折叠。
bsp/gd32103c-eval/Libraries/CMSIS/core_cmFunc.h 已删除 100644 → 0
浏览文件 @ 382e19cc
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.01
* @date 06. March 2012
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return (__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return (__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return (__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return (__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return (__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return (__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return (__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return (__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return (__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return (__regfpscr);
#else
return (0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile("cpsie i");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile("cpsid i");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile("MRS %0, control" : "=r"(result));
return (result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile("MSR control, %0" : : "r"(control));
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile("MRS %0, ipsr" : "=r"(result));
return (result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile("MRS %0, apsr" : "=r"(result));
return (result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile("MRS %0, xpsr" : "=r"(result));
return (result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile("MRS %0, psp\n" : "=r"(result));
return (result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile("MSR psp, %0\n" : : "r"(topOfProcStack));
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile("MRS %0, msp\n" : "=r"(result));
return (result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile("MSR msp, %0\n" : : "r"(topOfMainStack));
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile("MRS %0, primask" : "=r"(result));
return (result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile("MSR primask, %0" : : "r"(priMask));
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile("cpsie f");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile("cpsid f");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile("MRS %0, basepri_max" : "=r"(result));
return (result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile("MSR basepri, %0" : : "r"(value));
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile("MRS %0, faultmask" : "=r"(result));
return (result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile("MSR faultmask, %0" : : "r"(faultMask));
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
__ASM volatile("VMRS %0, fpscr" : "=r"(result));
return (result);
#else
return (0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
__ASM volatile("VMSR fpscr, %0" : : "r"(fpscr));
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */
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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.01
* @date 06. March 2012
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
{
__ASM volatile("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
{
__ASM volatile("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
{
__ASM volatile("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
{
__ASM volatile("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
{
__ASM volatile("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
{
__ASM volatile("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
{
__ASM volatile("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
uint32_t result;
__ASM volatile("rev %0, %1" : "=r"(result) : "r"(value));
return (result);
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile("rev16 %0, %1" : "=r"(result) : "r"(value));
return (result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
uint32_t result;
__ASM volatile("revsh %0, %1" : "=r"(result) : "r"(value));
return (result);
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
__ASM volatile("ror %0, %0, %1" : "+r"(op1) : "r"(op2));
return (op1);
}
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile("rbit %0, %1" : "=r"(result) : "r"(value));
return (result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint8_t result;
__ASM volatile("ldrexb %0, [%1]" : "=r"(result) : "r"(addr));
return (result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint16_t result;
__ASM volatile("ldrexh %0, [%1]" : "=r"(result) : "r"(addr));
return (result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile("ldrex %0, [%1]" : "=r"(result) : "r"(addr));
return (result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile("strexb %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value));
return (result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile("strexh %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value));
return (result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile("strex %0, %2, [%1]" : "=&r"(result) : "r"(addr), "r"(value));
return (result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile("clrex");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__((always_inline)) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint8_t result;
__ASM volatile("clz %0, %1" : "=r"(result) : "r"(value));
return (result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */
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import rtconfig
from building import *
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Glob('GD32F1xx_standard_peripheral/Source/*.c')
src += [cwd + '/CMSIS/GD/GD32F1xx/Source/system_gd32f1xx.c']
#add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
src += [cwd + '/CMSIS/GD/GD32F1xx/Source/GCC/startup_gd32.s']
src += [cwd + '/CMSIS/GD/GD32F1xx/Source/GCC/isr_tab.s']
path = [
cwd + '/CMSIS/GD/GD32F1xx/Include',
cwd + '/CMSIS',
cwd + '/GD32F1xx_standard_peripheral/Include',]
CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'GD32F1XX']
group = DefineGroup('GD32_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')
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