update bsp lpc2478.

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1853 bbd45198-f89e-11dd-88c7-29a3b14d5316

bsp/lpc2478/SConscript

-import rtconfig
+# for module compiling
+import os
 Import('RTT_ROOT')
-from building import *
 
-src_bsp   = ['application.c', 'startup.c', 'board.c']
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
 
-src = File(src_bsp)
-CPPPATH = [RTT_ROOT + '/bsp/lpc2478']
-group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH)
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
 
-Return('group')
+Return('objs')

bsp/lpc2478/SConstruct

@@ -6,7 +6,7 @@ RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
 sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
 from building import *
 
-TARGET = 'rtthread-lpc.' + rtconfig.TARGET_EXT
+TARGET = 'rtthread-lpc24xx.' + rtconfig.TARGET_EXT
 
 env = Environment(tools = ['mingw'],
 	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
@@ -19,7 +19,7 @@ Export('RTT_ROOT')
 Export('rtconfig')
 
 # prepare building environment
-objs = PrepareBuilding(env, RTT_ROOT)
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
 
 # build program 
 env.Program(TARGET, objs)

bsp/lpc2478/applications/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/lpc2478/drivers/SConscript

+import copy
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+
+# remove no need file.
+if GetDepend('RT_USING_LWIP') == False:
+    src_need_remove = ['dm9000.c'] # need remove file list.
+    SrcRemove(src, src_need_remove)
+
+if GetDepend('RT_USING_DFS') == False:
+    src_need_remove = ['sd.c'] # need remove file list.
+    SrcRemove(src, src_need_remove)
+
+CPPPATH = [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/lpc2478/board.h → bsp/lpc2478/drivers/board.h

@@ -15,6 +15,10 @@
 #ifndef __BOARD_H__
 #define __BOARD_H__
 
+/* RT_USING_UART */
+#define RT_USING_UART1
+#define RT_USING_UART2
+#define RT_UART_RX_BUFFER_SIZE	64
 void rt_hw_board_init(void);
 void rt_hw_led_set(rt_uint32_t led);
 void rt_hw_led_flash(void);

bsp/lpc2478/drivers/serial.c

+/*
+ * File      : serial.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-08-23     Bernard      first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "LPC24xx.h"
+#include "board.h"
+
+/* serial hardware register */
+#define REG8(d)			(*((volatile unsigned char *)(d)))
+#define REG32(d)		(*((volatile unsigned long *)(d)))
+
+#define UART_RBR(base)  REG8(base + 0x00)
+#define UART_THR(base)  REG8(base + 0x00)
+#define UART_IER(base)  REG32(base + 0x04)
+#define UART_IIR(base)  REG32(base + 0x08)
+#define UART_FCR(base)  REG8(base + 0x08)
+#define UART_LCR(base)  REG8(base + 0x0C)
+#define UART_MCR(base)  REG8(base + 0x10)
+#define UART_LSR(base)  REG8(base + 0x14)
+#define UART_MSR(base)  REG8(base + 0x18)
+#define UART_SCR(base)  REG8(base + 0x1C)
+#define UART_DLL(base)  REG8(base + 0x00)
+#define UART_DLM(base)  REG8(base + 0x04)
+#define UART_ACR(base)  REG32(base + 0x20)
+#define UART_FDR(base)  REG32(base + 0x28)
+#define UART_TER(base)  REG8(base + 0x30)
+
+/* LPC serial device */
+struct rt_lpcserial
+{
+	/* inherit from device */
+	struct rt_device parent;
+
+	rt_uint32_t hw_base;
+	rt_uint32_t irqno;
+	rt_uint32_t baudrate;
+
+	/* reception field */
+	rt_uint16_t save_index, read_index;
+	rt_uint8_t  rx_buffer[RT_UART_RX_BUFFER_SIZE];
+};
+
+#ifdef RT_USING_UART1
+struct rt_lpcserial serial1;
+#endif
+#ifdef RT_USING_UART2
+struct rt_lpcserial serial2;
+#endif
+
+void rt_hw_serial_init(void);
+
+#define U0PINS  	0x00000005
+
+void rt_hw_uart_isr(struct rt_lpcserial* lpc_serial)
+{
+	UNUSED rt_uint32_t iir;
+
+	RT_ASSERT(lpc_serial != RT_NULL)
+		
+	if (UART_LSR(lpc_serial->hw_base) & 0x01)
+	{
+		rt_base_t level;
+
+		while (UART_LSR(lpc_serial->hw_base) & 0x01)
+		{
+			/* disable interrupt */
+			level = rt_hw_interrupt_disable();
+
+			/* read character */
+			lpc_serial->rx_buffer[lpc_serial->save_index] = 
+				UART_RBR(lpc_serial->hw_base);
+			lpc_serial->save_index ++;
+			if (lpc_serial->save_index >= RT_UART_RX_BUFFER_SIZE)
+				lpc_serial->save_index = 0;
+			
+			/* if the next position is read index, discard this 'read char' */
+			if (lpc_serial->save_index == lpc_serial->read_index)
+			{
+				lpc_serial->read_index ++;
+				if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
+					lpc_serial->read_index = 0;
+			}
+
+			/* enable interrupt */
+			rt_hw_interrupt_enable(level);
+		}
+
+		/* invoke callback */
+		if(lpc_serial->parent.rx_indicate != RT_NULL)
+		{
+		  lpc_serial->parent.rx_indicate(&lpc_serial->parent, 1);
+		}
+	}
+
+	/* clear interrupt source */
+	iir = UART_IIR(lpc_serial->hw_base);
+
+	/* acknowledge Interrupt */
+	VICVectAddr = 0;
+}
+
+#ifdef RT_USING_UART1
+void rt_hw_uart_isr_1(int irqno)
+{
+	/* get lpc serial device */
+	rt_hw_uart_isr(&serial1);
+}	
+#endif
+
+#ifdef RT_USING_UART2
+void rt_hw_uart_isr_2(int irqno)
+{
+	/* get lpc serial device */
+	rt_hw_uart_isr(&serial2);
+}	
+#endif
+
+/**
+ * @addtogroup LPC214x
+ */
+/*@{*/
+
+static rt_err_t rt_serial_init (rt_device_t dev)
+{
+	return RT_EOK;
+}
+
+static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
+{
+	struct rt_lpcserial* lpc_serial;
+	lpc_serial = (struct rt_lpcserial*) dev;
+	
+	RT_ASSERT(lpc_serial != RT_NULL);
+	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+	{
+	    /* init UART rx interrupt */
+    	UART_IER(lpc_serial->hw_base) = 0x01;
+
+		/* install ISR */
+		if (lpc_serial->irqno == UART0_INT)
+		{
+#ifdef RT_USING_UART1
+		    rt_hw_interrupt_install(lpc_serial->irqno, rt_hw_uart_isr_1, RT_NULL);
+#endif
+		}
+		else
+		{
+#ifdef RT_USING_UART2
+		    rt_hw_interrupt_install(lpc_serial->irqno, rt_hw_uart_isr_2, RT_NULL);
+#endif
+		}
+
+	    rt_hw_interrupt_umask(lpc_serial->irqno);
+	}
+
+	return RT_EOK;
+}
+
+static rt_err_t rt_serial_close(rt_device_t dev)
+{
+	struct rt_lpcserial* lpc_serial;
+	lpc_serial = (struct rt_lpcserial*) dev;
+	
+	RT_ASSERT(lpc_serial != RT_NULL);
+
+	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+	{
+		/* disable UART rx interrupt */
+		UART_IER(lpc_serial->hw_base) = 0x00;
+	}
+
+	return RT_EOK;
+}
+
+static rt_err_t rt_serial_control(rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+	return RT_EOK;
+}
+
+static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+	rt_uint8_t* ptr;
+	struct rt_lpcserial *lpc_serial = (struct rt_lpcserial*)dev;
+	RT_ASSERT(lpc_serial != RT_NULL);
+
+	/* point to buffer */
+	ptr = (rt_uint8_t*) buffer;
+
+	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+	{
+		while (size)
+		{
+			/* interrupt receive */
+			rt_base_t level;
+
+			/* disable interrupt */
+			level = rt_hw_interrupt_disable();
+			if (lpc_serial->read_index != lpc_serial->save_index)
+			{
+				*ptr = lpc_serial->rx_buffer[lpc_serial->read_index];
+
+				lpc_serial->read_index ++;
+				if (lpc_serial->read_index >= RT_UART_RX_BUFFER_SIZE)
+					lpc_serial->read_index = 0;
+			}
+			else
+			{
+				/* no data in rx buffer */
+
+				/* enable interrupt */
+				rt_hw_interrupt_enable(level);
+				break;
+			}
+
+			/* enable interrupt */
+			rt_hw_interrupt_enable(level);
+
+			ptr ++; size --;
+		}
+
+		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+	}
+	else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
+	{
+		/* not support right now */
+		RT_ASSERT(0);
+	}
+
+	/* polling mode */
+	while (size && (UART_LSR(lpc_serial->hw_base) & 0x01))
+	{
+		/* Read Character */
+		*ptr = UART_RBR(lpc_serial->hw_base);
+		
+		ptr  ++;
+		size --;
+	}
+
+	return (rt_size_t)ptr - (rt_size_t)buffer;
+}
+
+static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+	struct rt_lpcserial* lpc_serial;
+	char *ptr;
+
+	lpc_serial = (struct rt_lpcserial*) dev;
+	if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+	{
+		/* not support */
+		RT_ASSERT(0);
+	}
+	else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
+	{
+		/* not support */
+		RT_ASSERT(0);
+	}
+
+	/* polling write */
+	ptr = (char *)buffer;
+	
+	if (dev->flag & RT_DEVICE_FLAG_STREAM)
+	{
+		/* stream mode */
+		while (size)
+		{
+			if (*ptr == '\n')
+			{
+				while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
+				UART_THR(lpc_serial->hw_base) = '\r';
+			}
+
+			while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
+			UART_THR(lpc_serial->hw_base) = *ptr;
+			
+			ptr ++;
+			size --;
+		}
+	}
+	else
+	{
+		while (size)
+		{
+			while (!(UART_LSR(lpc_serial->hw_base) & 0x20));
+			UART_THR(lpc_serial->hw_base) = *ptr;
+			
+			ptr ++;
+			size --;
+		}
+	}
+	
+	return (rt_size_t) ptr - (rt_size_t) buffer;
+}
+
+void rt_hw_serial_init(void)
+{
+	struct rt_lpcserial* lpc_serial;
+	
+#ifdef RT_USING_UART1
+	lpc_serial = &serial1;
+	
+	lpc_serial->parent.type = RT_Device_Class_Char;
+	
+	lpc_serial->hw_base = 0xE000C000;
+	lpc_serial->baudrate = 115200;
+	lpc_serial->irqno = UART0_INT;
+	
+	rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
+	lpc_serial->read_index = lpc_serial->save_index = 0;
+
+	/* Enable UART0 RxD and TxD pins */
+  	PINSEL0 |= 0x50;
+
+	/* 8 bits, no Parity, 1 Stop bit */
+	UART_LCR(lpc_serial->hw_base) = 0x83;
+	
+	/* Setup Baudrate */
+	UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
+	UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
+
+	/* DLAB = 0 */
+	UART_LCR(lpc_serial->hw_base) = 0x03;
+
+	lpc_serial->parent.type     = RT_Device_Class_Char;
+	lpc_serial->parent.init 	= rt_serial_init;
+	lpc_serial->parent.open 	= rt_serial_open;
+	lpc_serial->parent.close    = rt_serial_close;
+	lpc_serial->parent.read 	= rt_serial_read;
+	lpc_serial->parent.write    = rt_serial_write;
+	lpc_serial->parent.control  = rt_serial_control;
+	lpc_serial->parent.user_data  = RT_NULL;
+
+	rt_device_register(&lpc_serial->parent, 
+		"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM);
+#endif
+
+#ifdef RT_USING_UART2
+	lpc_serial = &serial2;
+	
+	lpc_serial->parent.type = RT_Device_Class_Char;
+
+	lpc_serial->hw_base = 0xE0010000;
+	lpc_serial->baudrate = 115200;
+	lpc_serial->irqno = UART1_INT;
+
+	rt_memset(lpc_serial->rx_buffer, 0, sizeof(lpc_serial->rx_buffer));
+	lpc_serial->read_index = lpc_serial->save_index = 0;
+
+	/* Enable UART1 RxD and TxD pins */
+  	PINSEL0 |= 0x05 << 16;
+
+	/* 8 bits, no Parity, 1 Stop bit */
+	UART_LCR(lpc_serial->hw_base) = 0x83;
+	
+	/* Setup Baudrate */
+	UART_DLL(lpc_serial->hw_base) = (PCLK/16/lpc_serial->baudrate) & 0xFF;
+	UART_DLM(lpc_serial->hw_base) = ((PCLK/16/lpc_serial->baudrate) >> 8) & 0xFF;
+
+	/* DLAB = 0 */
+	UART_LCR(lpc_serial->hw_base) = 0x03;
+
+	lpc_serial->parent.type     = RT_Device_Class_Char;
+	lpc_serial->parent.init 	= rt_serial_init;
+	lpc_serial->parent.open 	= rt_serial_open;
+	lpc_serial->parent.close    = rt_serial_close;
+	lpc_serial->parent.read 	= rt_serial_read;
+	lpc_serial->parent.write    = rt_serial_write;
+	lpc_serial->parent.control  = rt_serial_control;
+	lpc_serial->parent.user_data  = RT_NULL;
+
+	rt_device_register(&lpc_serial->parent, 
+		"uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
+#endif
+}
+
+/*@}*/

bsp/lpc2478/project.Uv2

@@ -3,52 +3,50 @@
 
 Target (RT-Thread LPC2478), 0x0004 // Tools: 'ARM-ADS'
 
-Group (Startup)
+Group (Applications)
+Group (Drivers)
 Group (Kernel)
 Group (LPC24XX)
 Group (finsh)
 
-File 1,1,<.\application.c><application.c>
-File 1,1,<.\startup.c><startup.c>
-File 1,1,<.\board.c><board.c>
-File 2,1,<..\..\src\clock.c><clock.c>
-File 2,1,<..\..\src\device.c><device.c>
-File 2,1,<..\..\src\idle.c><idle.c>
-File 2,1,<..\..\src\ipc.c><ipc.c>
-File 2,1,<..\..\src\irq.c><irq.c>
-File 2,1,<..\..\src\kservice.c><kservice.c>
-File 2,1,<..\..\src\mem.c><mem.c>
-File 2,1,<..\..\src\mempool.c><mempool.c>
-File 2,1,<..\..\src\module.c><module.c>
-File 2,1,<..\..\src\object.c><object.c>
-File 2,1,<..\..\src\rtm.c><rtm.c>
-File 2,1,<..\..\src\scheduler.c><scheduler.c>
-File 2,1,<..\..\src\slab.c><slab.c>
-File 2,1,<..\..\src\thread.c><thread.c>
-File 2,1,<..\..\src\timer.c><timer.c>
-File 3,1,<..\..\libcpu\arm\lpc24xx\cpu.c><cpu.c>
-File 3,1,<..\..\libcpu\arm\lpc24xx\interrupt.c><interrupt.c>
-File 3,1,<..\..\libcpu\arm\lpc24xx\serial.c><serial.c>
-File 3,1,<..\..\libcpu\arm\lpc24xx\stack.c><stack.c>
-File 3,1,<..\..\libcpu\arm\lpc24xx\trap.c><trap.c>
-File 3,2,<..\..\libcpu\arm\lpc24xx\context_rvds.S><context_rvds.S>
-File 3,2,<..\..\libcpu\arm\lpc24xx\start_rvds.S><start_rvds.S>
-File 3,1,<..\..\libcpu\arm\common\backtrace.c><backtrace.c>
-File 3,1,<..\..\libcpu\arm\common\div0.c><div0.c>
-File 3,1,<..\..\libcpu\arm\common\showmem.c><showmem.c>
-File 4,1,<..\..\components\finsh\cmd.c><cmd.c>
-File 4,1,<..\..\components\finsh\finsh_compiler.c><finsh_compiler.c>
-File 4,1,<..\..\components\finsh\finsh_error.c><finsh_error.c>
-File 4,1,<..\..\components\finsh\finsh_heap.c><finsh_heap.c>
-File 4,1,<..\..\components\finsh\finsh_init.c><finsh_init.c>
-File 4,1,<..\..\components\finsh\finsh_node.c><finsh_node.c>
-File 4,1,<..\..\components\finsh\finsh_ops.c><finsh_ops.c>
-File 4,1,<..\..\components\finsh\finsh_parser.c><finsh_parser.c>
-File 4,1,<..\..\components\finsh\finsh_token.c><finsh_token.c>
-File 4,1,<..\..\components\finsh\finsh_var.c><finsh_var.c>
-File 4,1,<..\..\components\finsh\finsh_vm.c><finsh_vm.c>
-File 4,1,<..\..\components\finsh\shell.c><shell.c>
-File 4,1,<..\..\components\finsh\symbol.c><symbol.c>
+File 1,1,<applications\application.c><application.c>
+File 1,1,<applications\startup.c><startup.c>
+File 2,1,<drivers\board.c><board.c>
+File 2,1,<drivers\serial.c><serial.c>
+File 3,1,<..\..\src\device.c><device.c>
+File 3,1,<..\..\src\thread.c><thread.c>
+File 3,1,<..\..\src\scheduler.c><scheduler.c>
+File 3,1,<..\..\src\timer.c><timer.c>
+File 3,1,<..\..\src\irq.c><irq.c>
+File 3,1,<..\..\src\kservice.c><kservice.c>
+File 3,1,<..\..\src\clock.c><clock.c>
+File 3,1,<..\..\src\object.c><object.c>
+File 3,1,<..\..\src\mempool.c><mempool.c>
+File 3,1,<..\..\src\ipc.c><ipc.c>
+File 3,1,<..\..\src\idle.c><idle.c>
+File 3,1,<..\..\src\mem.c><mem.c>
+File 4,1,<..\..\libcpu\arm\lpc24xx\cpu.c><cpu.c>
+File 4,1,<..\..\libcpu\arm\lpc24xx\interrupt.c><interrupt.c>
+File 4,1,<..\..\libcpu\arm\lpc24xx\stack.c><stack.c>
+File 4,1,<..\..\libcpu\arm\lpc24xx\trap.c><trap.c>
+File 4,2,<..\..\libcpu\arm\lpc24xx\context_rvds.S><context_rvds.S>
+File 4,2,<..\..\libcpu\arm\lpc24xx\start_rvds.S><start_rvds.S>
+File 4,1,<..\..\libcpu\arm\common\backtrace.c><backtrace.c>
+File 4,1,<..\..\libcpu\arm\common\div0.c><div0.c>
+File 4,1,<..\..\libcpu\arm\common\showmem.c><showmem.c>
+File 5,1,<..\..\components\finsh\cmd.c><cmd.c>
+File 5,1,<..\..\components\finsh\finsh_compiler.c><finsh_compiler.c>
+File 5,1,<..\..\components\finsh\finsh_error.c><finsh_error.c>
+File 5,1,<..\..\components\finsh\finsh_heap.c><finsh_heap.c>
+File 5,1,<..\..\components\finsh\finsh_init.c><finsh_init.c>
+File 5,1,<..\..\components\finsh\finsh_node.c><finsh_node.c>
+File 5,1,<..\..\components\finsh\finsh_ops.c><finsh_ops.c>
+File 5,1,<..\..\components\finsh\finsh_parser.c><finsh_parser.c>
+File 5,1,<..\..\components\finsh\finsh_token.c><finsh_token.c>
+File 5,1,<..\..\components\finsh\finsh_var.c><finsh_var.c>
+File 5,1,<..\..\components\finsh\finsh_vm.c><finsh_vm.c>
+File 5,1,<..\..\components\finsh\shell.c><shell.c>
+File 5,1,<..\..\components\finsh\symbol.c><symbol.c>
 
 
 Options 1,0,0  // Target 'RT-Thread LPC2478'
@@ -109,7 +107,7 @@ Options 1,0,0  // Target 'RT-Thread LPC2478'
  ADSCMISC ()
  ADSCDEFN ()
  ADSCUDEF ()
- ADSCINCD (..\..\include;..\..\libcpu\arm\common;..\..\components\finsh;..\..\libcpu\arm\lpc24xx;.)
+ ADSCINCD (..\..\include;drivers;.;applications;..\..\libcpu\arm\common;..\..\components\finsh;..\..\libcpu\arm\lpc24xx)
  ADSASFLG { 1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
  ADSAMISC ()
  ADSADEFN ()
@@ -130,11 +128,11 @@ Options 1,0,0  // Target 'RT-Thread LPC2478'
  ADSLDSC ()
  ADSLDIB ()
  ADSLDIC ()
- ADSLDMC ( --keep __fsym_* --keep __vsym_*)
+ ADSLDMC ( --keep __fsym_* --keep __vsym_* )
  ADSLDIF ()
  ADSLDDW ()
   OPTDL (SARM.DLL)(-cLPC24xx)(DARMP.DLL)(-pLPC2478)(SARM.DLL)()(TARMP.DLL)(-pLPC2478)
-  OPTDBG 48125,7,()()()()()()()()()() (Segger\JL2CM3.dll)()()()
+  OPTDBG 48126,7,()()()()()()()()()() (Segger\JL2CM3.dll)()()()
  FLASH1 { 9,0,0,0,1,0,0,0,0,16,0,0,0,0,0,0,0,0,0,0 }
  FLASH2 (BIN\UL2ARM.DLL)
  FLASH3 ("LPC210x_ISP.EXE" ("#H" ^X $D COM1: 38400 1))

bsp/lpc2478/rtconfig.h

@@ -63,8 +63,6 @@
 /* SECTION: Device System */
 /* Using Device System*/
 #define RT_USING_DEVICE
-#define RT_USING_UART1
-#define RT_UART_RX_BUFFER_SIZE	64
 
 /* SECTION: Console options */
 #define RT_USING_CONSOLE

bsp/lpc2478/rtconfig.py

 # toolchains options
 ARCH='arm'
 CPU='lpc24xx'
-CROSS_TOOL='gcc'
+CROSS_TOOL='keil'
 
 if  CROSS_TOOL == 'gcc':
 	PLATFORM 	= 'gcc'
@@ -9,12 +9,16 @@ if  CROSS_TOOL == 'gcc':
 elif CROSS_TOOL == 'keil':
 	PLATFORM 	= 'armcc'
 	EXEC_PATH 	= 'E:/Keil'
+elif CROSS_TOOL == 'iar':
+	PLATFORM 	= 'iar'
+	EXEC_PATH 	= 'E:/Program Files/IAR Systems/Embedded Workbench 6.0/arm/bin'
 BUILD = 'debug'
 
 if PLATFORM == 'gcc':
     # toolchains
     PREFIX = 'arm-none-eabi-'
     CC = PREFIX + 'gcc'
+    CXX = PREFIX + 'g++'
     AS = PREFIX + 'gcc'
     AR = PREFIX + 'ar'
     LINK = PREFIX + 'gcc'
@@ -23,8 +27,8 @@ if PLATFORM == 'gcc':
     OBJDUMP = PREFIX + 'objdump'
     OBJCPY = PREFIX + 'objcopy'
 
-    DEVICE = ' -mcpu=arm7tdmi'
-    CFLAGS = DEVICE
+    DEVICE = ' -mcpu=arm7tdmi-s'
+    CFLAGS = DEVICE + ' -DRT_USING_MINILIBC'
     AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
     LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-lpc2478.map,-cref,-u,Reset_Handler -T lpc2478_rom.lds'
 
@@ -42,6 +46,7 @@ if PLATFORM == 'gcc':
 elif PLATFORM == 'armcc':
     # toolchains
     CC = 'armcc'
+    CXX = 'armcc'    
     AS = 'armasm'
     AR = 'armar'
     LINK = 'armlink'