[bsp/ra6m4-iot] add ra6m4-iot BSP

bsp/renesas/ra6m4-iot/.gitignore

+/RTE
+/Listings
+/Objects
+ra_cfg.txt
+

bsp/renesas/ra6m4-iot/.ignore_format.yml

+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- ra
+- ra_gen
+- ra_cfg

bsp/renesas/ra6m4-iot/.settings/standalone.prefs

+#Fri Jan 07 11:55:32 CST 2022
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
+com.renesas.cdt.ddsc.packs.componentfiles/RECH\#\#BSP\#\#Board\#\#RA6M4_IoT\#\#\#\#3.5.0/all=3595564841,ra/board/ra6m4_iot/board_keys.c|1504341481,ra/board/ra6m4_iot/SEGGER_RTT_Conf.h|310556077,ra/board/ra6m4_iot/board_init.c|1596843605,ra/board/ra6m4_iot/board_keys.h|431480014,ra/board/ra6m4_iot/board_leds.h|443795680,ra/board/ra6m4_iot/board_leds.c|736642717,ra/board/ra6m4_iot/SEGGER_RTT.h|2021830415,ra/board/ra6m4_iot/board_ethernet_phy.h|311023834,ra/board/ra6m4_iot/board.h|2513852369,ra/board/ra6m4_iot/board_init.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|1728953905,ra/fsp/inc/fsp_features.h|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|546480625,ra/fsp/inc/fsp_common_api.h|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|1939984091,ra/fsp/inc/api/r_ioport_api.h|3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|3297195641,ra/fsp/inc/fsp_version.h|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|2425160085,ra/fsp/inc/api/bsp_api.h|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|2208590403,ra/fsp/inc/instances/r_ioport.h|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#device\#\#\#\#3.5.0/all=2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#device\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=PinConfiguration
+com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#device\#\#R7FA6M4AF3CFP\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#fsp\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#fsp\#\#\#\#3.5.0/all=1009023542,ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h|3301568719,ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h|2347061782,ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/all=2208590403,ra/fsp/inc/instances/r_ioport.h|1939984091,ra/fsp/inc/api/r_ioport_api.h|3254285722,ra/fsp/src/r_ioport/r_ioport.c
+com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.2044193823=false
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c|1889256766,ra/fsp/inc/instances/r_sci_uart.h|3916852077,ra/fsp/inc/api/r_uart_api.h|1610456547,ra/fsp/inc/api/r_transfer_api.h
+com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/libraries=
+com.renesas.cdt.ddsc.packs.componentfiles/RECH\#\#BSP\#\#Board\#\#RA6M4_IoT\#\#\#\#3.5.0/libraries=

bsp/renesas/ra6m4-iot/Kconfig

+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+    
+# you can change the RTT_ROOT default "../.." to your rtthread_root,
+# example : default "F:/git_repositories/rt-thread"
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+    
+config ENV_DIR
+    string
+    option env="ENV_ROOT"
+    default "/"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "$BSP_DIR/drivers/Kconfig"
+
+config SOC_FAMILY_RENESAS
+    bool
+    default y
+
+config SOC_SERIES_R7FA6M4AF
+    bool
+    select ARCH_ARM_CORTEX_M4
+    select SOC_FAMILY_RENESAS
+    default y
\ No newline at end of file

bsp/renesas/ra6m4-iot/R7FA6M4AF3CFP.pincfg

+<?xml version="1.0" encoding="utf-8"?>
+<v1:pinSettings xmlns:v1="http://www.tasking.com/schema/pinsettings/v1.1">
+  <v1:pinMappingsRef version="2.05" file="" />
+  <v1:deviceSetting id="renesas.ra6m4_fp" pattern="R7FA6M4****FP">
+    <v1:packageSetting id="renesas.100lqfp" />
+  </v1:deviceSetting>
+  <v1:configSetting configurationId="debug0.mode" altId="debug0.mode.jtag" />
+  <v1:configSetting configurationId="p108.gpio_mode" altId="p108.gpio_mode.gpio_mode_peripheral" />
+  <v1:configSetting configurationId="p108" altId="p108.debug0.tms">
+    <v1:connectionSetting altId="debug0.tms.p108" />
+  </v1:configSetting>
+  <v1:configSetting configurationId="debug0.tms" altId="debug0.tms.p108">
+    <v1:connectionSetting altId="p108.debug0.tms" />
+  </v1:configSetting>
+  <v1:configSetting configurationId="p109.gpio_mode" altId="p109.gpio_mode.gpio_mode_peripheral" />
+  <v1:configSetting configurationId="p109" altId="p109.debug0.tdo">
+    <v1:connectionSetting altId="debug0.tdo.p109" />
+  </v1:configSetting>
+  <v1:configSetting configurationId="debug0.tdo" altId="debug0.tdo.p109">
+    <v1:connectionSetting altId="p109.debug0.tdo" />
+  </v1:configSetting>
+  <v1:configSetting configurationId="p110.gpio_mode" altId="p110.gpio_mode.gpio_mode_peripheral" />
+  <v1:configSetting configurationId="p110" altId="p110.debug0.tdi">
+    <v1:connectionSetting altId="debug0.tdi.p110" />
+  </v1:configSetting>
+  <v1:configSetting configurationId="debug0.tdi" altId="debug0.tdi.p110">
+    <v1:connectionSetting altId="p110.debug0.tdi" />
+  </v1:configSetting>
+  <v1:configSetting configurationId="p300.gpio_mode" altId="p300.gpio_mode.gpio_mode_peripheral" />
+  <v1:configSetting configurationId="p300" altId="p300.debug0.tck">
+    <v1:connectionSetting altId="debug0.tck.p300" />
+  </v1:configSetting>
+  <v1:configSetting configurationId="debug0.tck" altId="debug0.tck.p300">
+    <v1:connectionSetting altId="p300.debug0.tck" />
+  </v1:configSetting>
+</v1:pinSettings>
\ No newline at end of file

bsp/renesas/ra6m4-iot/README.md

+# 瑞萨 IOT-RA6M4 开发板 BSP 说明
+
+## 简介
+
+本文档为瑞萨 IOT-RA6M4 开发板提供的 BSP (板级支持包) 说明。通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
+
+主要内容如下：
+
+- 开发板介绍
+- BSP 快速上手指南
+
+## 开发板介绍
+
+基于瑞萨 RA6M4 MCU 开发的 IOT-RA6M4 MCU 评估板，通过灵活配置软件包和 IDE，可帮助用户对 RA6M4 MCU 群组的特性轻松进行评估，并对嵌入系统应用程序进行开发。
+
+该开发板常用 **板载资源** 如下：
+
+- MCU：R7FA6M4AF3CFP，200MHz，Arm Cortex®-M33 内核，1MB 代码闪存, 256kB SRAM
+- 调试接口：板载 J-Link 接口
+- 扩展接口：两个 PMOD 连接器
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **片上外设** | **支持情况** | **备注** |
+| :----------------: | :----------------: | :------------- |
+| UART               | 支持               | UART6 为默认日志输出端口 |
+| GPIO               | 支持               |                |
+| IIC                | 支持               | 软件           |
+| WDT                | 支持               |                |
+| RTC                | 支持               |                |
+| ADC                | 支持               |                |
+| DAC                | 支持               |                |
+| SPI                | 支持               |                |
+| FLASH              | 支持               |                |
+| PWM                | 支持               |                |
+| CAN                | 支持               |                |
+| 持续更新中...      |                    |                |
+| **外接外设** | **支持情况** | **备注** |
+| WiFi 模块     | 支持        |  [RW007 WiFi 网络模块](https://github.com/RT-Thread-packages/rw007)  |
+| 温湿度传感器   | 支持       |  [HS300x 温湿度模块](https://github.com/Guozhanxin/hs300x) |
+| 室内空气质量传感器 | 支持 | [zmod4410 室内空气质量模块](https://github.com/ShermanShao/zmod4410) |
+
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+  本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+- 进阶使用
+
+  本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+### 快速上手
+
+本 BSP 目前仅提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+**硬件连接**
+
+使用 USB 数据线连接开发板到 PC，使用 J-link 接口下载和 DEBUG 程序。使用 USB 转串口工具连接 UART6：P305(TXD)、P304(RXD)。
+
+**编译下载**
+
+- 编译：双击 project.uvprojx 文件，打开 MDK5 工程，编译程序。
+
+> 注意：此工程需要使用 J-Flash Lite 工具烧录程序。建议使用 V7.50 及以上版本烧录工程。[J-Link 下载链接](https://www.segger.com/downloads/jlink/)
+
+- 下载：打开 J-Flash lite 工具，选择芯片型号 R7FA6M4AF，点击 OK 进入工具。选择 BSP 目录下 MDK 编译出的 /object/ra6m4.hex 文件，点击 Program Device 按钮开始烧录。具体操作过程可参考下图步骤：
+
+![image-20211011181555421](docs/picture/jflash1.png)
+
+![image-20211011182047981](docs/picture/jflash2.png)
+
+![image-20211011182434519](docs/picture/jflash.png)
+
+![image-20211011182949604](docs/picture/jflash3.png)
+
+**查看运行结果**
+
+下载程序成功之后，系统会自动运行并打印系统信息。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息。输入 help 命令可查看系统中支持的命令。
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.4 build Oct 11 2021
+ 2006 - 2021 Copyright by rt-thread team
+
+Hello RT-Thread!
+msh >
+msh >help
+RT-Thread shell commands:
+reboot           - Reboot System
+help             - RT - Thread shell help.
+ps               - List threads in the system.
+free             - Show the memory usage in the system.
+hello            - say hello world
+clear            - clear the terminal screen
+version          - show RT - Thread version information
+list_thread      - list thread
+list_sem         - list semaphore in system
+list_event       - list event in system
+list_mutex       - list mutex in system
+list_mailbox     - list mail box in system
+list_msgqueue    - list message queue in system
+list_timer       - list timer in system
+list_device      - list device in system
+list             - list all commands in system
+
+msh > 
+```
+
+**应用入口函数**
+
+应用层的入口函数在 **bsp\renesas\ra6m4-iot\src\hal_emtry.c** 中 的 `void hal_entry(void)` 。用户编写的源文件可直接放在 src 目录下。
+
+```c
+void hal_entry(void)
+{
+    rt_kprintf("\nHello RT-Thread!\n");
+
+    while (1)
+    {
+        rt_pin_write(LED3_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED3_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+}
+```
+
+### 进阶使用
+
+**资料及文档**
+
+- 开发板用户手册: \docs\开发板手册.docx
+- [瑞萨RA MCU 基础知识](https://www2.renesas.cn/cn/zh/document/gde/1520091)
+- [RA6 MCU 快速设计指南](https://www2.renesas.cn/cn/zh/document/apn/ra6-quick-design-guide)
+- [RA6M4_datasheet](https://www2.renesas.cn/cn/zh/document/dst/ra6m4-group-datasheet)
+- [RA6M4 Group User’s Manual: Hardware](https://www2.renesas.cn/cn/zh/document/man/ra6m4-group-user-s-manual-hardware)
+
+**FSP 配置**
+
+需要修改瑞萨的 BSP 外设配置或添加新的外设端口，需要用到瑞萨的 [FSP](https://www2.renesas.cn/jp/zh/software-tool/flexible-software-package-fsp#document) 配置工具。请务必按照如下步骤完成配置。配置中有任何问题可到[RT-Thread 社区论坛](https://club.rt-thread.org/)中提问。
+
+1. [下载灵活配置软件包 (FSP) | Renesas](https://www.renesas.com/cn/zh/software-tool/flexible-software-package-fsp)，请使用 FSP 3.5.0 版本
+2. 下载安装完成后，需要添加 IOT-RA6M4 开发板的官方板级支持包
+> 在 docs 目录下找到 **IOT-RA6M4 板级支持包:** Xiaoxiongpai_BSP_FSP3.5.0.rar
+3. 如何将 **”IOT-RA6M4 板级支持包“**添加到 FSP 中，请参考文档[如何导入板级支持包](https://www2.renesas.cn/document/ppt/1527171?language=zh&r=1527191)
+4. 请查看文档：[使用瑞萨 FSP 配置工具](./docs/使用瑞萨FSP配置工具.md)。在 MDK 中通过添加自定义命名来打开当前工程的 FSP 配置。
+
+**ENV 配置**
+
+- 如何使用 ENV 工具：[RT-Thread env 工具用户手册](https://www.rt-thread.org/document/site/#/development-tools/env/env)
+
+此 BSP 默认只开启了 UART6 的功能，如果需使用更多高级功能例如组件、软件包等，需要利用 ENV 工具进行配置。
+
+步骤如下：
+1. 在 bsp 下打开 env 工具。
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+3. 输入`pkgs --update`命令更新软件包。
+4. 输入`scons --target=mdk5` 命令重新生成工程。
+
+
+## FAQ
+
+### 使用 MDK 的 DEBUG 时如果遇到提示  “Error: Flash Download failed Cortex-M33” 怎么办？
+
+可按照下图操作，修改 Utilities 中的选项：
+
+![image-20211214102231248](docs/picture/readme_faq1.png)
+
+## 联系人信息
+
+在使用过程中若您有任何的想法和建议，建议您通过以下方式来联系到我们  [RT-Thread 社区论坛](https://club.rt-thread.org/)
+
+## 贡献代码
+
+如果您对 IOT-RA6M4 感兴趣，并且有一些好玩的项目愿意与大家分享的话欢迎给我们贡献代码，您可以参考 [如何向 RT-Thread 代码贡献](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/development-guide/github/github)。

bsp/renesas/ra6m4-iot/RTE/_Target_1/RTE_Components.h

+
+/*
+ * Auto generated Run-Time-Environment Configuration File
+ *      *** Do not modify ! ***
+ *
+ * Project: 'project' 
+ * Target:  'Target 1' 
+ */
+
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+
+
+#endif /* RTE_COMPONENTS_H */

bsp/renesas/ra6m4-iot/SConscript

+# for module compiling
+import os
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = []
+CPPPATH = []
+list = os.listdir(cwd)
+
+if rtconfig.CROSS_TOOL == 'iar':
+    print("\nThe current project does not support iar build\n")
+    Return('group')
+elif rtconfig.CROSS_TOOL == 'gcc':
+    CPPPATH = [cwd]
+    src = Glob('./src/*.c')
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        group = group + SConscript(os.path.join(d, 'SConscript'))
+
+Return('group')

bsp/renesas/ra6m4-iot/SConstruct

+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/renesas/ra6m4-iot/buildinfo.gpdsc

+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance">
+  <vendor>Renesas</vendor>
+  <name>Project Content</name>
+  <description>Project content managed by the Renesas Smart Configurator</description>
+  <url/>
+  <releases>
+    <release version="1.0.0"/>
+  </releases>
+  <generators>
+    <generator id="Renesas RA Smart Configurator">
+      <project_files>
+        <file category="include" name="src/"/>
+        <file category="source" name="src/hal_entry.c"/>
+      </project_files>
+    </generator>
+  </generators>
+  <components generator="Renesas RA Smart Configurator">
+    <component Cclass="Flex Software" Cgroup="Components" Csub="ra">
+      <files>
+        <file category="include" name="ra/arm/CMSIS_5/CMSIS/Core/Include/"/>
+        <file category="include" name="ra/fsp/inc/"/>
+        <file category="include" name="ra/fsp/inc/api/"/>
+        <file category="include" name="ra/fsp/inc/instances/"/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h" path=""/>
+        <file category="header" name="ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h" path=""/>
+        <file category="other" name="ra/arm/CMSIS_5/LICENSE.txt"/>
+        <file category="header" name="ra/board/ra6m4_iot/board.h" path=""/>
+        <file category="header" name="ra/board/ra6m4_iot/board_ethernet_phy.h" path=""/>
+        <file category="source" name="ra/board/ra6m4_iot/board_init.c"/>
+        <file category="header" name="ra/board/ra6m4_iot/board_init.h" path=""/>
+        <file category="source" name="ra/board/ra6m4_iot/board_keys.c"/>
+        <file category="header" name="ra/board/ra6m4_iot/board_keys.h" path=""/>
+        <file category="source" name="ra/board/ra6m4_iot/board_leds.c"/>
+        <file category="header" name="ra/board/ra6m4_iot/board_leds.h" path=""/>
+        <file category="header" name="ra/board/ra6m4_iot/SEGGER_RTT.h" path=""/>
+        <file category="header" name="ra/board/ra6m4_iot/SEGGER_RTT_Conf.h" path=""/>
+        <file category="header" name="ra/fsp/inc/api/bsp_api.h" path=""/>
+        <file category="header" name="ra/fsp/inc/api/r_ioport_api.h" path=""/>
+        <file category="header" name="ra/fsp/inc/api/r_transfer_api.h" path=""/>
+        <file category="header" name="ra/fsp/inc/api/r_uart_api.h" path=""/>
+        <file category="header" name="ra/fsp/inc/fsp_common_api.h" path=""/>
+        <file category="header" name="ra/fsp/inc/fsp_features.h" path=""/>
+        <file category="header" name="ra/fsp/inc/fsp_version.h" path=""/>
+        <file category="header" name="ra/fsp/inc/instances/r_ioport.h" path=""/>
+        <file category="header" name="ra/fsp/inc/instances/r_sci_uart.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c"/>
+        <file category="source" name="ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_clocks.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_common.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_common.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_delay.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_delay.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_group_irq.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_guard.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_guard.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_io.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_io.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_irq.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_irq.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_module_stop.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_register_protection.h" path=""/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c"/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_sbrk.c"/>
+        <file category="source" name="ra/fsp/src/bsp/mcu/all/bsp_security.c"/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_security.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/all/bsp_tfu.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h" path=""/>
+        <file category="header" name="ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h" path=""/>
+        <file category="source" name="ra/fsp/src/r_ioport/r_ioport.c"/>
+        <file category="source" name="ra/fsp/src/r_sci_uart/r_sci_uart.c"/>
+      </files>
+    </component>
+    <component Cclass="Flex Software" Cgroup="Build Configuration">
+      <files>
+        <file category="include" name="ra_cfg/fsp_cfg/"/>
+        <file category="include" name="ra_cfg/fsp_cfg/bsp/"/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/board_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/r_ioport_cfg.h" path=""/>
+        <file category="header" name="ra_cfg/fsp_cfg/r_sci_uart_cfg.h" path=""/>
+      </files>
+    </component>
+    <component Cclass="Flex Software" Cgroup="Generated Data">
+      <files>
+        <file category="include" name="ra_gen/"/>
+        <file category="header" name="ra_gen/bsp_clock_cfg.h" path=""/>
+        <file category="source" name="ra_gen/common_data.c"/>
+        <file category="header" name="ra_gen/common_data.h" path=""/>
+        <file category="source" name="ra_gen/hal_data.c"/>
+        <file category="header" name="ra_gen/hal_data.h" path=""/>
+        <file category="source" name="ra_gen/main.c"/>
+        <file category="source" name="ra_gen/pin_data.c"/>
+        <file category="source" name="ra_gen/vector_data.c"/>
+        <file category="header" name="ra_gen/vector_data.h" path=""/>
+      </files>
+    </component>
+    <component Cclass="Flex Software" Cgroup="Linker Script">
+      <files>
+        <file category="linkerScript" name="script/fsp.scat"/>
+        <file category="other" name="script/ac6/fsp_keep.via"/>
+      </files>
+    </component>
+  </components>
+</package>

bsp/renesas/ra6m4-iot/docs/使用瑞萨FSP配置工具.md

+## 在 MDK 中使用 FSP
+
+###  添加RA Smart Config
+
+1. 打开 MDK，选择 “Tools -> Customize Tools Menu…”
+2. 点击 “new” 图标，添加一条自定义命令: RA Smart Configurator
+3. Command 输入工具的安装路径， 点击“**…**”找到安装路径下的“rasc.exe”文件并选中 (rasc 安装目录下)
+4. Initial Folder 输入参数: $P
+5. Arguments 输入参数: --device $D --compiler ARMv6 configuration.xml
+6. 点击 OK 保存命令
+
+![img](picture/customize.png)
+
+7. 点击添加的命令 “Tools -> RA smart Configurator”，**打开配置工具**：RA Smart Config
+
+![image.png](picture/openrasc.png)
+
+###  添加 Device Partition Manager，添加步骤同上。
+
+1. 输入命令名称:`Device Partition Manager`
+2. Command: 在安装路径选中`rasc.exe`
+3. Initial Folder :`$P`
+4. Arguments:`-application com.renesas.cdt.ddsc.dpm.ui.dpmapplication configuration.xml "SL%L"`
+
+> PS：以上相关操作也可以在 FSP 的说明文档中找到。
+>
+> 文档路径（本地）：在 FSP 的安装目录下  .\fsp_documentation\v3.5.0\fsp_user_manual_v3.5.0\index.html
+>
+> 文档路径（官网）：https://www2.renesas.cn/jp/zh/software-tool/flexible-software-package-fsp#document
+
+###  FSP 版本选择
+
+此 BSP 已更新 **FSP 3.5.0** 版本的支持，请使用 **FSP 3.5.0** 版本进行配置修改。下文中部分操作截图使用的是 FSP 3.1.0 版本，仅供参考。
+
+**使用 RASC 前请务必检查 FSP version 、Board、Device 配置项是否正确。**
+
+![fsp_version](picture/fsp_version.png)
+
+## 更新工程配置
+
+使用 FSP 配置完成后如果有新的文件添加进工程中，不会马上添加进去。需要先编译一次，如果弹出如下提醒，选择 “是” 然后再次编译即可。
+
+![img](picture/import_changes.png)
+
+## 如何使用 RASC 添加外设
+
+**注意：文档中的外设添加步骤均为单独配置的说明，排版顺序不代表外设添加顺序，如遇到引脚冲突请查阅开发板及芯片手册的相关章节。**
+
+### UART
+
+如何添加一个 UART 端口外设配置？
+
+1. 选择 Stacks 配置页，点击 New Stack 找到 UART。
+
+![image.png](picture/rascuart.png)
+
+2. 配置 UART 参数，因为需要适配 RT-Thread 驱动中使用的命名，所以需要修改命名，设置**name** 、**channel**  、**callback** 是一致的标号。![image.png](picture/rascuart1.png)
+
+###  GPIO 中断
+
+如何添加一个 IO 中断？
+
+1. 选择引脚编号，进入配置，比如选择 P105 做为中断引脚。可先找到引脚查看可配置成的 IRQx 通道号。
+
+![image-20211103200949759](picture/p105.png)
+
+2. 打开 ICU 中断通道 IRQ00
+
+![image-20211103200813467](picture/irq0.png)
+
+3. 创建 stack 并进入配置。因为需要适配 RT-Thread 驱动中使用的命名，所以需要修改命名，设置**name** 、**channel**  、**callback** 是一致的标号。选择你希望的触发方式，最后保存配置，生成配置代码。
+
+![](picture/1635929089445.png)
+
+![image-20211103201047103](picture/irq1.png)
+
+4. 测试中断是否成功开启
+
+   ```c
+   #define IRQ_TEST_PIN	"p105"
+   void irq_callback_test(void *args)
+   {
+       rt_kprintf("\n IRQ00 triggered \n");
+   }
+
+   void icu_sample(void)
+   {
+       /* init */
+       rt_uint32_t pin = rt_pin_get(IRQ_TEST_PIN);
+       rt_kprintf("\n pin number : 0x%04X \n", pin);
+       rt_err_t err = rt_pin_attach_irq(pin, PIN_IRQ_MODE_RISING, irq_callback_test, RT_NULL);
+       if(RT_EOK != err)
+       {
+           rt_kprintf("\n attach irq failed. \n");
+       }
+       err = rt_pin_irq_enable(pin, PIN_IRQ_ENABLE);
+       if(RT_EOK != err)
+       {
+           rt_kprintf("\n enable irq failed. \n");
+       }
+   }
+   MSH_CMD_EXPORT(icu_sample, icu sample);
+   ```
+
+### WDT
+
+1. 创建 WDT
+
+![image-20211019152302939](picture/wdt.png)
+
+2. 配置 WDT，需要注意在 RT-Thread 中只使用了一个 WDT 设备，所以没有对其进行编号，如果是新创建的 WDT 设备需要注意 name 字段，在驱动中默认使用的是`g_wdt` 。
+
+![image-20211019152407572](picture/wdt_config.png)
+
+3. 如何在 ENV 中打开 WDT 以及[WDT 接口使用说明](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/watchdog/watchdog)
+
+![image-20211027183406251](picture/wdt_env.png)
+
+### RTC
+
+1. 添加 RTC 设备
+
+![image-20211019152536749](picture/rtc.png)
+
+2. 配置 RTC，需要注意在 RT-Thread 中只是用了一个 RTC 设备，所以没有对其进行编号，如果是新创建的 RTC 设备需要注意 name 字段，在驱动中默认使用的是`g_rtc` 。修改 Callback 为 rtc_callback
+
+![image-20211019152627412](picture/rtc_config.png)
+
+3. 如何在 ENV 中打开 RTC 以及[ RTC 接口使用说明](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/rtc/rtc)
+
+![image-20211027181550233](picture/rtc_env.png)
+
+### Flash
+
+1. 创建 Flash
+
+![image-20211026105031200](picture/add_flash.png)
+
+2. 配置 Flash，需要注意在 RT-Thread 中只使用了一个 flash 设备，所以没有对其进行编号，如果是新创建的 flash 设备需要注意 name 字段，在驱动中默认使用的是`g_flash` 。
+
+![image-20211026105628706](picture/config_flash.png)
+
+3. 如何在 ENV 中打开 Flash
+
+![image-20211026123252310](picture/flash_menuconfig.png)
+
+### SPI
+
+1. 添加一个 SPI 外设端口
+
+![image-20211027180820968](picture/spi_add.png)
+
+2. 配置 channel、name、Clock Phase、Clock Polarity、Callback、 SPI Mode 等参数，波特率在代码中可通过 API 修改，这里可以设置一个默认值。
+
+![img](picture/spi.png)
+
+3. 在 Pins 中打开 SPI0 ，配置端口引脚。**注意：请勿在此处配置 SSLx 片选引脚，片选引脚的控制在驱动程序中由软件控制。**
+
+![image-20211209162334093](picture/spi_pin.png)
+
+
+4. 如何在 ENV 中打开 SPI 以及 [SPI 接口使用说明](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/spi/spi)
+
+   ![image-20211027181444023](picture/spi_env.png)
+
+### ADC/DAC
+
+创建 ADC/DAC
+
+![img](picture/adc_dac.png)
+
+- **ADC**
+
+1. 配置 name、unit、mode，选择扫描的通道编号
+
+![img](picture/adc_config.png)
+
+2. 配置扫描通道对应的引脚
+
+![img](picture/adc_config1.png)
+
+3. 在 menuconfig 中打开对应的通道
+
+- **DAC**
+
+1. 需要先关闭 P014 的默认 mode
+
+![img](picture/dac_config0.png)
+
+2. 开启 DAC0 通道
+
+![img](picture/dac_config1.png)
+
+3. 修改通道号为 0，与 DAC0 对应
+
+![img](picture/dac_config2.png)
+
+4. 在 menuconfig 中打开对应的通道
+
+### 通用 PWM 定时器（GPT）
+
+GPT 定时器在该芯片中可作为通用定时器，也可以用于产生 PWM 信号。在将其用于产生 PWM 信号时，GPT 定时器提供了 gpt0 - gpt9 总共 10 个通道，每个通道可以设定两个输出端口。当前版本的 PWM 驱动将每个通道都看做一个单独的 PWM 设备，每个设备都只有一个通道。用户可以选择开启一个通道的任意一个输出端口，或将两个端口均开启，但在同时开启两个端口的情况下，它们输出的波形将完全一致。
+
+1. 添加 GPT 设备
+
+   ![img](./picture/add_gpt1.png)
+2. 配置通道
+
+   ![img](./picture/add_gpt2.png)
+
+   对 GPT 较为关键的配置如图所示，具体解释如下：
+
+   1. 将``Common`` ->``Pin Output Support`` 设置为 Enable ，以开启 PWM 波形的输出。
+   2. 指定 GPT 通道，并根据通道数指定 GPT 的名称，例如此处指定 GPT 通道 3 ，所以 GPT 的名称必须为``g_timer3``。并且将定时器模式设置为 PWM ，并指定每个 PWM 周期的计数值。
+   3. 设定 PWM 通道默认输出的占空比，这里为 50% 。
+   4. 设定 GPT 通道下两个输出端口的使能状态。
+   5. 此处设置 GPT 通道下两个输出端口各自对应的引脚。
+3. 配置输出引脚
+
+   ![img](./picture/add_gpt3.png)
+
+   在完成上一步对 GPT 定时器的设置后，根据图示找到对应 GPT 通道输出引脚设置的界面（这里是 GPT3），将图中标号 **1** 处设置为 ``GTIOCA or GTIOCB`` ，并根据需要在图中标号 **2** 处设置 GPT 通道下两个输出端口各自对应的输出引脚。
+
+   4. 在 menuconfig 中打开对应的通道，[RT-Thread 的 pwm 框架介绍](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/pwm/pwm)
+
+   ![image-20211103202216381](picture/pwm_env.png)
+
+### SDHI
+
+1. 添加sdhi驱动
+
+![添加sdhi驱动](picture/sdhi_config.png)
+
+2. 添加DMAC
+
+   ![添加DMAC](picture/dmac_config.png)
+
+3. 设置DMAC中断
+
+   ![设置DMAC中断](picture/dmac_int.png)
+
+4. 设置SDHI中断和引脚
+
+   ![设置SDHI](picture/sdhi_config1.png)
+
+5. 在ENV中打开SDHI
+
+   ![打开SDHI](picture/sdhi_env.png)
+   
+6. 在ENV中配置DFS，添加文件系统，如FatFS
+
+   ![配置DFS](picture/sdhi_dfs.png)
+
+7. 在命令行中，使用 `mkfs sd0 -t elm` 格式化sd卡
+
+8. 在命令行中，使用 `mount sd0 / elm` 将sd0挂载到 `/`
+
+9. 参考RT-Thread DFS使用手册[虚拟文件系统 (rt-thread.org)](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/filesystem/filesystem)
+
+### CAN
+
+1. 添加CAN
+
+![image-20211102145023112](picture/can.png)
+
+2. 配置Callback为 `can0_callback` 或 `can1_callback`
+
+![image-20211102145227603](picture/can_callback.png)
+
+3. 配置其他选项，并生成代码。
+
+4. 使用ENV使能CAN。[CAN设备使用说明](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/can/can)
+
+![image-20211102145613309](picture/can_menuconfig.png)
+
+
+### 使用 WiFi 模块 [RW007 ](https://github.com/RT-Thread-packages/rw007) 
+
+1. 软件包配置中找到 RW007，并修改为下图配置
+
+![image-20211108142805319](picture/rw007_pkg.png)
+
+2. menuconfig 中打开驱动的 RW007 配置，默认使用了 SPI1 端口。所以需要打开 SPI1 总线。
+
+![image-20211108142453678](picture/rw007_spi.png)
+
+![image-20211213212034701](picture/drv_rw007.png)
+
+3. 在设备驱动框架中打开 [WLAN 框架](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/wlan/wlan)，
+
+![image-20211108143027485](picture/rw007_wlan.png)
+
+在网络配置中打开 NETDEV 组件：
+
+![image-20211108143712513](picture/rw007_netdev.png)
+
+在 kernel 中打开 mempool 配置：
+
+![image-20211209161902884](picture/rw007_mempool.png)
+
+4. FSP 中打开添加 SPI 外设端口，[如何添加SPI](#SPI)。下图以 SPI1 端口为例的配置如下：
+
+![image-20211108183631379](picture/rw007_spicfg.png)
+
+5. RW007 有一个从机控制的 INT 引脚，需要占用一个 IRQ 通道，下图以 P506 为例的配置如下：
+
+![image-20211108183724282](picture/rw007_int.png)
+
+6. RW007 的 RESET 控制引脚修改默认配置，这里在 RASC 中 mode 设为关闭，交由 RW007 中进行控制。
+
+![image-20211213144108558](picture/rw007_reset.png)
+
+7. 配置完成，检查 MDK 工程中是否加入了必要的文件
+
+![image-20211109102232233](picture/rw007_mdk.png)
+
+8. 编译下载，验证结果。
+
+系统启动会自动获取 RW007 的信息，输入`wifi scan` 命令扫描环境中的 WiFi 信号。[更多 WiFi 命令](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/wlan/wlan?id=finsh-%e5%91%bd%e4%bb%a4)
+
+![image-20211109103856130](picture/rw007_test.png)
+
+使用 `WiFi join` 命令连接 WiFi 热点 ：
+
+![image-20211109104735733](picture/rw007_wifijoin.png)
+
+使用 `ping rt-thread.com` 测试网络连接：
+
+![image-20211109104700939](picture/rw007_ping.png)
\ No newline at end of file

bsp/renesas/ra6m4-iot/drivers/Kconfig

+menu "Hardware Drivers Config"
+
+    config SOC_SERIES_R7FA6M4AF
+        bool
+        select RT_USING_COMPONENTS_INIT
+        select RT_USING_USER_MAIN
+        default y
+
+    menu "Onboard Peripheral Drivers"
+
+    endmenu
+
+    menu "On-chip Peripheral Drivers"
+
+        config BSP_USING_GPIO
+            bool "Enable GPIO"
+            select RT_USING_PIN
+            default y
+
+        config BSP_USING_ONCHIP_FLASH
+            bool "Enable Onchip FLASH"
+            default n
+
+        config BSP_USING_WDT
+            bool "Enable Watchdog Timer"
+            select RT_USING_WDT
+            default n
+
+        menuconfig BSP_USING_UART
+            bool "Enable UART"
+            default y
+            select RT_USING_SERIAL
+            select RT_USING_SERIAL_V2
+            if BSP_USING_UART
+                menuconfig BSP_USING_UART6
+                    bool "Enable UART6 (Console)"
+                    default y
+                    if BSP_USING_UART6
+                        config BSP_UART6_RX_USING_DMA
+                            bool "Enable UART6 RX DMA"
+                            depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART6_TX_USING_DMA
+                            bool "Enable UART6 TX DMA"
+                            depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART6_RX_BUFSIZE
+                            int "Set UART6 RX buffer size"
+                            range 64 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 256
+
+                        config BSP_UART6_TX_BUFSIZE
+                            int "Set UART6 TX buffer size"
+                            range 0 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 0
+                    endif
+                menuconfig BSP_USING_UART7
+                    bool "Enable UART7 (Console)"
+                    default n
+                    if BSP_USING_UART7
+                        config BSP_UART7_RX_USING_DMA
+                            bool "Enable UART7 RX DMA"
+                            depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART7_TX_USING_DMA
+                            bool "Enable UART7 TX DMA"
+                            depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA
+                            default n
+
+                        config BSP_UART7_RX_BUFSIZE
+                            int "Set UART7 RX buffer size"
+                            range 64 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 256
+
+                        config BSP_UART7_TX_BUFSIZE
+                            int "Set UART7 TX buffer size"
+                            range 0 65535
+                            depends on RT_USING_SERIAL_V2
+                            default 0
+                    endif
+            endif
+
+        menuconfig BSP_USING_I2C
+            bool "Enable I2C BUS"
+            default n
+            select RT_USING_I2C
+            select RT_USING_I2C_BITOPS
+            select RT_USING_PIN
+            if BSP_USING_I2C
+                menuconfig BSP_USING_I2C1
+                    bool "Enable I2C1 BUS (software simulation)"
+                    default y
+                    if BSP_USING_I2C1
+                        config BSP_I2C1_SCL_PIN
+                            hex "i2c1 scl pin number"
+                            range 0x0000 0x0B0F
+                            default 0x0512
+                        config BSP_I2C1_SDA_PIN
+                            hex "I2C1 sda pin number"
+                            range 0x0000 0x0B0F
+                            default 0x0511
+                    endif
+            endif
+
+        menuconfig BSP_USING_ONCHIP_RTC
+            bool "Enable RTC"
+            select RT_USING_RTC
+            default n
+            if BSP_USING_ONCHIP_RTC
+            endif
+
+        menuconfig BSP_USING_SPI
+            bool "Enable SPI BUS"
+            default n
+            select RT_USING_SPI
+            if BSP_USING_SPI
+                config BSP_SPI_USING_DTC_DMA
+                    bool "Enable SPI DTC transfers data without using the CPU."
+                    default n
+
+                config BSP_USING_SPI0
+                    bool "Enable SPI0 BUS"
+                    default n
+        
+                config BSP_USING_SPI1
+                    bool "Enable SPI1 BUS"
+                    default n
+            endif
+
+        menuconfig BSP_USING_ADC
+            bool "Enable ADC"
+            default n
+            select RT_USING_ADC
+            if BSP_USING_ADC
+                config BSP_USING_ADC0
+                    bool "Enable ADC0"
+                    default n
+
+                config BSP_USING_ADC1
+                    bool "Enable ADC1"
+                    default n
+            endif
+
+        menuconfig BSP_USING_DAC
+            bool "Enable DAC"
+            default n
+            select RT_USING_DAC
+            if BSP_USING_DAC
+                config BSP_USING_DAC0
+                    bool "Enable DAC0"
+                    default n
+
+                config BSP_USING_DAC1
+                    bool "Enable DAC1"
+                    default n
+            endif
+
+        menuconfig BSP_USING_PWM
+            bool "Enable PWM"
+            default n
+            select RT_USING_PWM
+            if BSP_USING_PWM
+                config BSP_USING_PWM0
+                    bool "Enable GPT0 (32-Bits) output PWM"
+                    default n
+                
+                config BSP_USING_PWM1
+                    bool "Enable GPT1 (32-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM2
+                    bool "Enable GPT2 (32-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM3
+                    bool "Enable GPT3 (32-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM4
+                    bool "Enable GPT4 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM5
+                    bool "Enable GPT5 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM6
+                    bool "Enable GPT6 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM7
+                    bool "Enable GPT7 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM8
+                    bool "Enable GPT8 (16-Bits) output PWM"
+                    default n
+
+                config BSP_USING_PWM9
+                    bool "Enable GPT9 (16-Bits) output PWM"
+                    default n
+            endif
+
+        menuconfig BSP_USING_SDHI
+            bool "Enable SDHI"
+            default n
+            select RT_USING_SDIO
+            select RT_USING_DFS
+            select RT_LIBC_USING_FILEIO
+            select RT_USING_POSIX
+            if BSP_USING_SDHI
+                config SDHI_USING_1_BIT
+                    bool "Use 1-bit Mode(4-bit when disable)"
+                    default y
+            endif
+
+        menuconfig BSP_USING_CAN
+            bool "Enable CAN"
+            default n
+            select RT_USING_CAN
+            if BSP_USING_CAN
+                config BSP_USING_CAN0
+                    bool "Enable CAN0"
+                    default n
+
+                config BSP_USING_CAN1
+                    bool "Enable CAN1"
+                    default n
+            endif
+
+    endmenu
+
+    menu "Board extended module Drivers"
+
+        menuconfig BSP_USING_RW007
+            bool "Enable RW007"
+            default n
+            select PKG_USING_RW007
+            select BSP_USING_SPI
+
+        if BSP_USING_RW007
+            config RA_RW007_SPI_BUS_NAME
+                string "RW007 BUS NAME"
+                default "spi1"
+
+            config RA_RW007_CS_PIN
+                hex "(HEX)CS pin index"
+                default 0x040D
+
+            config RA_RW007_BOOT0_PIN
+                hex "(HEX)BOOT0 pin index (same as spi clk pin)"
+                default 0x040C
+
+            config RA_RW007_BOOT1_PIN
+                hex "(HEX)BOOT1 pin index (same as spi cs pin)"
+                default 0x040D
+
+            config RA_RW007_INT_BUSY_PIN
+                hex "(HEX)INT/BUSY pin index"
+                default 0x0506
+
+            config RA_RW007_RST_PIN
+                hex "(HEX)RESET pin index"
+                default 0x040F
+        endif
+
+    endmenu
+endmenu

bsp/renesas/ra6m4-iot/drivers/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+    drv_common.c
+""")
+
+if GetDepend(['BSP_USING_UART']):
+    if GetDepend(['RT_USING_SERIAL_V2']):
+        src += ['drv_usart_v2.c']
+    else:
+        print("\nThe current project does not support serial-v1\n")
+        Return('group')
+
+if GetDepend(['BSP_USING_GPIO']):
+    src += ['drv_gpio.c']
+
+if GetDepend(['BSP_USING_WDT']):
+    src += ['drv_wdt.c']
+
+if GetDepend(['BSP_USING_ONCHIP_RTC']):
+    src += ['drv_rtc.c']
+
+if GetDepend(['BSP_USING_I2C', 'RT_USING_I2C_BITOPS']):
+    if GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'):
+        src += ['drv_soft_i2c.c']
+
+if GetDepend(['BSP_USING_SPI']):
+    src += ['drv_spi.c']
+
+if GetDepend(['BSP_USING_ADC']):
+    src += ['drv_adc.c']
+
+if GetDepend(['BSP_USING_DAC']):
+    src += ['drv_dac.c']
+
+if GetDepend(['BSP_USING_ONCHIP_FLASH']):
+    src += ['drv_flash.c']
+
+if GetDepend(['BSP_USING_PWM']):
+    src += ['drv_pwm.c']
+
+if GetDepend(['BSP_USING_CAN']):
+    src += ['drv_can.c']
+
+if GetDepend(['BSP_USING_SDHI']):
+    src += ['drv_sdhi.c']
+
+path =  [cwd]
+path += [cwd + '/config']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/renesas/ra6m4-iot/drivers/board.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-10-10      Sherman      first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RA_SRAM_SIZE           256
+#define RA_SRAM_END            (0x20000000 + RA_SRAM_SIZE * 1024)
+
+#ifdef __ARMCC_VERSION
+extern int Image$$RAM_END$$ZI$$Base;
+#define HEAP_BEGIN  ((void *)&Image$$RAM_END$$ZI$$Base)
+#elif __ICCARM__
+#pragma section="CSTACK"
+#define HEAP_BEGIN      (__segment_end("CSTACK"))
+#else
+extern int __RAM_segment_used_end__;
+#define HEAP_BEGIN      (&__RAM_segment_used_end__)
+#endif
+
+#define HEAP_END        RA_SRAM_END
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/renesas/ra6m4-iot/drivers/config/drv_config.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-07-29     KyleChan          first version
+ */
+
+#ifndef __DRV_CONFIG_H__
+#define __DRV_CONFIG_H__
+
+#include "board.h"
+#include <rtthread.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef SOC_SERIES_R7FA6M4AF
+#include "ra6m4/uart_config.h"
+
+#ifdef BSP_USING_ADC
+#include "ra6m4/adc_config.h"
+#endif
+
+#ifdef BSP_USING_DAC
+#include "ra6m4/dac_config.h"
+#endif
+
+#ifdef BSP_USING_PWM
+#include "ra6m4/pwm_config.h"
+#endif
+
+#ifdef BSP_USING_CAN
+#include "ra6m4/can_config.h"
+#endif
+
+#endif/* SOC_SERIES_R7FA6M4AF */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif/* __DRV_CONFIG_H__ */

bsp/renesas/ra6m4-iot/drivers/config/ra6m4/adc_config.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-19     Mr.Tiger     first version
+ */
+
+#ifndef __ADC_CONFIG_H__
+#define __ADC_CONFIG_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "hal_data.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_ADC0) || defined(BSP_USING_ADC1)
+struct ra_adc_map
+{
+    char name;
+    const adc_cfg_t *g_cfg;
+    const adc_instance_ctrl_t *g_ctrl;
+    const adc_channel_cfg_t   *g_channel_cfg;
+};
+
+struct ra_dev
+{
+    rt_adc_device_t     ra_adc_device_t;
+    struct ra_adc_map  *ra_adc_dev;
+};
+#endif
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+

bsp/renesas/ra6m4-iot/drivers/config/ra6m4/can_config.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-10-29     mazhiyuan         first version
+ */
+
+#ifndef __CAN_CONFIG_H__
+#define __CAN_CONFIG_H__
+
+#include <rtthread.h>
+#include "hal_data.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_CAN0)
+#ifndef CAN0_CONFIG
+#define CAN0_CONFIG                                                 \
+    {                                                               \
+        .name = "can0",                                            \
+        .num_of_mailboxs = CAN_NO_OF_MAILBOXES_g_can0,             \
+        .p_api_ctrl = &g_can0_ctrl,                                \
+        .p_cfg = &g_can0_cfg,                                      \
+    }
+#endif /* CAN0_CONFIG */
+#endif /* BSP_USING_CAN0 */
+
+#if defined(BSP_USING_CAN1)
+#ifndef CAN1_CONFIG
+#define CAN1_CONFIG                                                 \
+    {                                                               \
+        .name = "can1",                                            \
+        .num_of_mailboxs = CAN_NO_OF_MAILBOXES_g_can1,             \
+        .p_api_ctrl = &g_can1_ctrl,                                \
+        .p_cfg = &g_can1_cfg,                                      \
+    }
+#endif /* CAN1_CONFIG */
+#endif /* BSP_USING_CAN1 */
+
+#ifdef __cplusplus
+}
+#endif
+#endif

bsp/renesas/ra6m4-iot/drivers/config/ra6m4/dac_config.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-19     Mr.Tiger     first version
+ */
+
+#ifndef __DAC_CONFIG_H__
+#define __DAC_CONFIG_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "hal_data.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef BSP_USING_DAC
+struct ra_dac_map
+{
+    char name;
+    const struct st_dac_cfg *g_cfg;
+    const struct st_dac_instance_ctrl *g_ctrl;
+};
+
+struct ra_dac_dev
+{
+    rt_dac_device_t       ra_dac_device_t;
+    struct ra_dac_map    *ra_dac_map_dev;
+};
+#endif
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+

bsp/renesas/ra6m4-iot/drivers/config/ra6m4/pwm_config.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-10-26     KevinXu           first version
+ */
+#ifndef __PWM_CONFIG_H__
+#define __PWM_CONFIG_H__
+
+#include <rtthread.h>
+#include <drv_config.h>
+#include "hal_data.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum
+{
+#ifdef BSP_USING_PWM0
+    BSP_PWM0_INDEX,
+#endif
+#ifdef BSP_USING_PWM1
+    BSP_PWM1_INDEX,
+#endif
+#ifdef BSP_USING_PWM2
+    BSP_PWM2_INDEX,
+#endif
+#ifdef BSP_USING_PWM3
+    BSP_PWM3_INDEX,
+#endif
+#ifdef BSP_USING_PWM4
+    BSP_PWM4_INDEX,
+#endif
+#ifdef BSP_USING_PWM5
+    BSP_PWM5_INDEX,
+#endif
+#ifdef BSP_USING_PWM6
+    BSP_PWM6_INDEX,
+#endif
+#ifdef BSP_USING_PWM7
+    BSP_PWM7_INDEX,
+#endif
+#ifdef BSP_USING_PWM8
+    BSP_PWM8_INDEX,
+#endif
+#ifdef BSP_USING_PWM9
+    BSP_PWM9_INDEX,
+#endif
+    BSP_PWMS_NUM
+};
+
+#define PWM_DRV_INITIALIZER(num)        \
+    {                                   \
+        .name = "pwm"#num ,             \
+        .g_cfg = &g_timer##num##_cfg,   \
+        .g_ctrl = &g_timer##num##_ctrl, \
+        .g_timer = &g_timer##num,       \
+    }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __PWM_CONFIG_H__ */

bsp/renesas/ra6m4-iot/drivers/config/ra6m4/uart_config.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-07-29     KyleChan          first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+#include "hal_data.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(BSP_USING_UART6)
+#ifndef UART6_CONFIG
+#define UART6_CONFIG                                                \
+    {                                                               \
+        .name = "uart6",                                            \
+        .p_api_ctrl = &g_uart6_ctrl,                                \
+        .p_cfg = &g_uart6_cfg,                                      \
+    }
+#endif /* UART6_CONFIG */
+#endif /* BSP_USING_UART6 */
+
+#if defined(BSP_USING_UART7)
+#ifndef UART7_CONFIG
+#define UART7_CONFIG                                                \
+    {                                                               \
+        .name = "uart7",                                            \
+        .p_api_ctrl = &g_uart7_ctrl,                                \
+        .p_cfg = &g_uart7_cfg,                                      \
+    }
+#endif /* UART7_CONFIG */
+#endif /* BSP_USING_UART7 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/renesas/ra6m4-iot/drivers/drv_adc.c

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-19     Mr.Tiger     first version
+ */
+
+#include "drv_config.h"
+#ifdef RT_USING_ADC
+
+// #define DRV_DEBUG
+#define DBG_TAG              "drv.adc"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+#include <rtdbg.h>
+
+struct ra_adc_map ra_adc[] =
+{
+#if defined(BSP_USING_ADC0)
+    {'0', &g_adc0_cfg, &g_adc0_ctrl, &g_adc0_channel_cfg},
+#endif
+
+#if defined(BSP_USING_ADC1)
+    {'1', &g_adc1_cfg, &g_adc1_ctrl, &g_adc1_channel_cfg},
+#endif
+};
+
+#if defined(BSP_USING_ADC0)
+struct rt_adc_device adc0_device;
+struct ra_dev _ra_adc0_device = {.ra_adc_device_t = &adc0_device, .ra_adc_dev = &ra_adc[0]};
+#endif
+
+#if defined(BSP_USING_ADC1)
+struct rt_adc_device adc1_device;
+struct ra_dev _ra_adc1_device = {.ra_adc_device_t = &adc1_device, .ra_adc_dev = &ra_adc[1]};
+#endif
+
+static rt_err_t ra_adc_enabled(struct rt_adc_device *device, rt_uint32_t channel, rt_bool_t enabled)
+{
+    RT_ASSERT(device != RT_NULL);
+    struct ra_adc_map *adc = (struct ra_adc_map *)device->parent.user_data;
+    /**< start adc*/
+    if (enabled)
+    {
+        if (FSP_SUCCESS != R_ADC_ScanStart((adc_ctrl_t *)adc->g_ctrl))
+        {
+            LOG_E("start adc%c failed.", adc->name);
+            return -RT_ERROR;
+        }
+    }
+    else
+    {
+        /**< stop adc*/
+        if (FSP_SUCCESS != R_ADC_ScanStop((adc_ctrl_t *)adc->g_ctrl))
+        {
+            LOG_E("stop adc%c failed.", adc->name);
+            return -RT_ERROR;
+        }
+    }
+    return RT_EOK;
+}
+
+rt_err_t ra_adc_close(struct rt_adc_device *device)
+{
+    RT_ASSERT(device != RT_NULL);
+    struct ra_adc_map *adc = (struct ra_adc_map *)(struct ra_adc_map *)device->parent.user_data;
+    if (FSP_SUCCESS != R_ADC_Close((adc_ctrl_t *)adc->g_ctrl))
+    {
+        LOG_E("close adc%c failed.", adc->name);
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+static rt_err_t ra_get_adc_value(struct rt_adc_device *device, rt_uint32_t channel, rt_uint32_t *value)
+{
+    RT_ASSERT(device != RT_NULL);
+    struct ra_adc_map *adc = (struct ra_adc_map *)device->parent.user_data;
+    if (RT_EOK != R_ADC_Read32((adc_ctrl_t *)adc->g_ctrl, channel, value))
+    {
+        LOG_E("get adc value failed.\n");
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+static const struct rt_adc_ops ra_adc_ops =
+{
+    .enabled = ra_adc_enabled,
+    .convert = ra_get_adc_value,
+};
+
+static int ra_adc_init(void)
+{
+#if defined(BSP_USING_ADC0)
+    R_ADC_Open((adc_ctrl_t *)_ra_adc0_device.ra_adc_dev->g_ctrl,
+               (adc_cfg_t const * const)_ra_adc0_device.ra_adc_dev->g_cfg);
+
+    R_ADC_ScanCfg((adc_ctrl_t *)_ra_adc0_device.ra_adc_dev->g_ctrl,
+                  (adc_cfg_t const * const)_ra_adc0_device.ra_adc_dev->g_channel_cfg);
+
+    if (RT_EOK != rt_hw_adc_register(_ra_adc0_device.ra_adc_device_t, "adc0", &ra_adc_ops, (void *)_ra_adc0_device.ra_adc_dev))
+    {
+        LOG_E("adc0 register failed");
+        return -RT_ERROR;
+    }
+#endif
+
+#if defined(BSP_USING_ADC1)
+    R_ADC_Open((adc_ctrl_t *)_ra_adc1_device.ra_adc_dev->g_ctrl,
+               (adc_cfg_t const * const)_ra_adc1_device.ra_adc_dev->g_cfg);
+
+    R_ADC_ScanCfg((adc_ctrl_t *)_ra_adc1_device.ra_adc_dev->g_ctrl,
+                  (adc_cfg_t const * const)_ra_adc1_device.ra_adc_dev->g_channel_cfg);
+
+    if (RT_EOK != rt_hw_adc_register(_ra_adc1_device.ra_adc_device_t, "adc1", &ra_adc_ops, (void *)_ra_adc1_device.ra_adc_dev))
+    {
+        LOG_E("adc1 register failed");
+        return -RT_ERROR;
+    }
+#endif
+
+    return RT_EOK;
+}
+INIT_BOARD_EXPORT(ra_adc_init);
+#endif

bsp/renesas/ra6m4-iot/drivers/drv_can.c

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-10-29     mazhiyuan         first version
+ */
+
+#include "drv_can.h"
+
+static struct ra_can_config can_config[] =
+{
+#ifdef BSP_USING_CAN0
+    CAN0_CONFIG,
+#endif
+
+#ifdef BSP_USING_CAN1
+    CAN1_CONFIG
+#endif
+};
+
+enum
+{
+#ifdef BSP_USING_CAN0
+    CAN0_INDEX,
+#endif
+
+#ifdef BSP_USING_CAN1
+    CAN1_INDEX,
+#endif
+};
+
+static struct ra_can can_obj[sizeof(can_config) / sizeof(can_config[0])] = {0};
+
+static const struct ra_baud_rate_tab can_baud_rate_tab[] =
+{
+    {CAN1MBaud, 3, 6, 3, 1 + 4},
+    {CAN800kBaud, 4, 15, 5, 1 + 2},
+    {CAN500kBaud, 4, 14, 5, 1 + 4},
+    {CAN250kBaud, 4, 14, 5, 1 + 9},
+    {CAN125kBaud, 4, 14, 5, 1 + 19},
+    {CAN100kBaud, 4, 14, 5, 1 + 24},
+    {CAN50kBaud, 4, 14, 5, 1 + 49},
+    {CAN20kBaud, 4, 14, 5, 1 + 124},
+    {CAN10kBaud, 4, 14, 5, 1 + 249}
+};
+
+static rt_uint32_t get_can_baud_index(rt_uint32_t baud)
+{
+    rt_uint32_t len, index;
+
+    len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]);
+    for (index = 0; index < len; index++)
+    {
+        if (can_baud_rate_tab[index].baud_rate == baud)
+            return index;
+    }
+
+    return 0; /* default baud is CAN1MBaud */
+}
+
+static void ra_can_get_config(void)
+{
+    struct can_configure config = CANDEFAULTCONFIG;
+#ifdef BSP_USING_CAN0
+    can_obj[CAN0_INDEX].can_dev.config = config;
+    can_obj[CAN0_INDEX].can_dev.config.msgboxsz = CAN_NO_OF_MAILBOXES_g_can0;
+    can_obj[CAN0_INDEX].can_dev.config.sndboxnumber = 1;
+    can_obj[CAN0_INDEX].can_dev.config.ticks = 50;
+#endif
+#ifdef BSP_USING_CAN1
+    can_obj[CAN1_INDEX].can_dev.config = config;
+    can_obj[CAN1_INDEX].can_dev.config.msgboxsz = CAN_NO_OF_MAILBOXES_g_can1;
+    can_obj[CAN1_INDEX].can_dev.config.sndboxnumber = 1;
+    can_obj[CAN1_INDEX].can_dev.config.ticks = 50;
+#endif
+}
+rt_err_t ra_can_configure(struct rt_can_device *can_dev, struct can_configure *cfg)
+{
+    struct ra_can *can;
+    RT_ASSERT(can_dev != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    fsp_err_t err = FSP_SUCCESS;
+
+    can = rt_container_of(can_dev, struct ra_can, can_dev);
+    RT_ASSERT(can != RT_NULL);
+    err = R_CAN_Open(can->config->p_api_ctrl, can->config->p_cfg);
+    if (FSP_SUCCESS != err)
+    {
+        return RT_ERROR;
+    }
+    return RT_EOK;
+}
+rt_err_t ra_can_control(struct rt_can_device *can_dev, int cmd, void *arg)
+{
+    struct ra_can *can;
+    can_info_t can_info;
+    rt_uint32_t argval;
+    RT_ASSERT(can_dev != RT_NULL);
+    can = rt_container_of(can_dev, struct ra_can, can_dev);
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        R_BSP_IrqStatusClear((IRQn_Type)arg);
+        break;
+    case RT_CAN_CMD_SET_BAUD:
+        argval = (rt_uint32_t) arg;
+        if (argval != CAN1MBaud &&
+                argval != CAN800kBaud &&
+                argval != CAN500kBaud &&
+                argval != CAN250kBaud &&
+                argval != CAN125kBaud &&
+                argval != CAN100kBaud &&
+                argval != CAN50kBaud  &&
+                argval != CAN20kBaud  &&
+                argval != CAN10kBaud)
+        {
+            return -RT_ERROR;
+        }
+        if (argval != can->can_dev.config.baud_rate)
+        {
+            can->can_dev.config.baud_rate = argval;
+            uint32_t index = get_can_baud_index(argval);
+            can->config->p_cfg->p_bit_timing->baud_rate_prescaler = can_baud_rate_tab[index].prescaler;
+            can->config->p_cfg->p_bit_timing->synchronization_jump_width = can_baud_rate_tab[index].sjw;
+            can->config->p_cfg->p_bit_timing->time_segment_1 = can_baud_rate_tab[index].ts1;
+            can->config->p_cfg->p_bit_timing->time_segment_2 = can_baud_rate_tab[index].ts2;
+            return ra_can_configure(&can->can_dev, &can->can_dev.config);
+        }
+        break;
+    case RT_CAN_CMD_SET_MODE:
+        argval = (rt_uint32_t) arg;
+        if (argval != RT_CAN_MODE_NORMAL &&
+                argval != RT_CAN_MODE_LISEN &&
+                argval != RT_CAN_MODE_LOOPBACK)
+        {
+            return -RT_ERROR;
+        }
+        if (argval != can->can_dev.config.mode)
+        {
+            can_test_mode_t mode_to_set;
+            can->can_dev.config.mode = argval;
+            switch (argval)
+            {
+            case RT_CAN_MODE_NORMAL:
+                mode_to_set = CAN_TEST_MODE_DISABLED;
+            case RT_CAN_MODE_LISEN:
+                mode_to_set = CAN_TEST_MODE_LISTEN;
+            case RT_CAN_MODE_LOOPBACK:
+                mode_to_set = CAN_TEST_MODE_LOOPBACK_INTERNAL;
+            }
+            R_CAN_ModeTransition(can->config->p_api_ctrl, ((can_instance_ctrl_t *)(can->config->p_api_ctrl))->operation_mode, mode_to_set);
+        }
+        break;
+    case RT_CAN_CMD_GET_STATUS:
+        R_CAN_InfoGet(can->config->p_api_ctrl, &can_info);
+        can->can_dev.status.rcverrcnt = can_info.error_count_receive;
+        can->can_dev.status.snderrcnt = can_info.error_count_transmit;
+        can->can_dev.status.errcode = can_info.error_code;
+        rt_memcpy(arg, &can->can_dev.status, sizeof(can->can_dev.status));
+        break;
+    default:
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+int ra_can_sendmsg(struct rt_can_device *can_dev, const void *buf, rt_uint32_t boxno)
+{
+    struct ra_can *can;
+    can_frame_t g_can_tx_frame;
+    struct rt_can_msg *msg_rt = (struct rt_can_msg *)buf;
+    RT_ASSERT(can_dev != RT_NULL);
+    RT_ASSERT(buf != RT_NULL);
+
+    g_can_tx_frame.id = msg_rt->id;
+    g_can_tx_frame.id_mode = msg_rt->ide;
+    g_can_tx_frame.type = msg_rt->rtr;
+    g_can_tx_frame.data_length_code = msg_rt->len;
+    g_can_tx_frame.options = 0;
+    memcpy(g_can_tx_frame.data, msg_rt->data, 8);
+    can = rt_container_of(can_dev, struct ra_can, can_dev);
+    RT_ASSERT(boxno < can->config->num_of_mailboxs);
+
+    if (R_CAN_Write(can->config->p_api_ctrl, boxno, &g_can_tx_frame) != FSP_SUCCESS)
+    {
+        rt_exit_critical();
+        return RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+int ra_can_recvmsg(struct rt_can_device *can_dev, void *buf, rt_uint32_t boxno)
+{
+    struct rt_can_msg *msg_rt = (struct rt_can_msg *)buf;
+    can_frame_t *msg_ra;
+    struct ra_can *can;
+
+    RT_ASSERT(can_dev != RT_NULL);
+    RT_ASSERT(buf != RT_NULL);
+    can = rt_container_of(can_dev, struct ra_can, can_dev);
+    RT_ASSERT(boxno < can->config->num_of_mailboxs);
+    if (can->callback_args->mailbox != boxno)
+        return 0;
+    msg_ra = can->callback_args->p_frame;
+
+    msg_rt->id = msg_ra->id;
+    msg_rt->ide = msg_ra->id_mode;
+    msg_rt->rtr = msg_ra->type;
+    msg_rt->rsv = RT_NULL;
+    msg_rt->len = msg_ra->data_length_code;
+    msg_rt->priv = boxno;
+    msg_rt->hdr = RT_NULL;
+    memcpy(msg_rt->data, msg_ra->data, msg_ra->data_length_code);
+    return sizeof(struct rt_can_msg);
+}
+const struct rt_can_ops ra_can_ops =
+{
+    .configure = ra_can_configure,
+    .control = ra_can_control,
+    .sendmsg = ra_can_sendmsg,
+    .recvmsg = ra_can_recvmsg
+};
+
+#ifdef BSP_USING_CAN0
+void can0_callback(can_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    switch (p_args->event)
+    {
+    case CAN_EVENT_TX_COMPLETE:
+        rt_hw_can_isr(&can_obj[CAN0_INDEX].can_dev, RT_CAN_EVENT_TX_DONE | p_args->mailbox << 8);
+        break;
+    case CAN_EVENT_RX_COMPLETE:
+        can_obj[CAN0_INDEX].callback_args = p_args;
+        if (p_args->event == CAN_EVENT_RX_COMPLETE)
+            rt_hw_can_isr(&can_obj[CAN0_INDEX].can_dev, RT_CAN_EVENT_RX_IND | p_args->mailbox << 8);
+        break;
+    case CAN_EVENT_TX_ABORTED:
+        rt_hw_can_isr(&can_obj[CAN0_INDEX].can_dev, RT_CAN_EVENT_TX_FAIL | p_args->mailbox << 8);
+        break;
+    case CAN_EVENT_MAILBOX_MESSAGE_LOST:    //overwrite/overrun error event
+    case CAN_EVENT_BUS_RECOVERY:            //Bus recovery error event
+    case CAN_EVENT_ERR_BUS_OFF:             //error Bus Off event
+    case CAN_EVENT_ERR_PASSIVE:             //error passive event
+    case CAN_EVENT_ERR_WARNING:             //error warning event
+    case CAN_EVENT_ERR_BUS_LOCK:            //error bus lock
+    case CAN_EVENT_ERR_CHANNEL:             //error channel
+    case CAN_EVENT_ERR_GLOBAL:              //error global
+    {
+        break;
+    }
+    }
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef BSP_USING_CAN1
+void can1_callback(can_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    switch (p_args->event)
+    {
+    case CAN_EVENT_TX_COMPLETE:
+        rt_hw_can_isr(&can_obj[CAN1_INDEX].can_dev, RT_CAN_EVENT_TX_DONE | p_args->mailbox << 8);
+        break;
+    case CAN_EVENT_RX_COMPLETE:
+        can_obj[CAN1_INDEX].callback_args = p_args;
+        if (p_args->event == CAN_EVENT_RX_COMPLETE)
+            rt_hw_can_isr(&can_obj[CAN1_INDEX].can_dev, RT_CAN_EVENT_RX_IND | p_args->mailbox << 8);
+        break;
+    case CAN_EVENT_TX_ABORTED:
+        rt_hw_can_isr(&can_obj[CAN1_INDEX].can_dev, RT_CAN_EVENT_TX_FAIL | p_args->mailbox << 8);
+        break;
+    case CAN_EVENT_MAILBOX_MESSAGE_LOST:    //overwrite/overrun error event
+    case CAN_EVENT_BUS_RECOVERY:            //Bus recovery error event
+    case CAN_EVENT_ERR_BUS_OFF:             //error Bus Off event
+    case CAN_EVENT_ERR_PASSIVE:             //error passive event
+    case CAN_EVENT_ERR_WARNING:             //error warning event
+    case CAN_EVENT_ERR_BUS_LOCK:            //error bus lock
+    case CAN_EVENT_ERR_CHANNEL:             //error channel
+    case CAN_EVENT_ERR_GLOBAL:              //error global
+    {
+        break;
+    }
+    }
+    rt_interrupt_leave();
+}
+#endif
+
+int rt_hw_can_init(void)
+{
+    rt_err_t result = 0;
+    rt_size_t obj_num = sizeof(can_obj) / sizeof(struct ra_can);
+    ra_can_get_config();
+    for (int i = 0; i < obj_num; i++)
+    {
+        /* init CAN object */
+        can_obj[i].config = &can_config[i];
+        can_obj[i].can_dev.ops = &ra_can_ops;
+        /* register CAN device */
+        result = rt_hw_can_register(&can_obj[i].can_dev, can_obj[i].config->name, can_obj[i].can_dev.ops, RT_NULL);
+        RT_ASSERT(result == RT_EOK);
+    }
+
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_can_init);

bsp/renesas/ra6m4-iot/drivers/drv_can.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-10-29     mazhiyuan         first version
+ */
+
+#ifndef __DRV_CAN_H__
+#define __DRV_CAN_H__
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rthw.h>
+#include <drv_common.h>
+#include <drv_config.h>
+#include <hal_data.h>
+
+/* renesas config class */
+struct ra_can_config
+{
+    const char *name;
+    int num_of_mailboxs;
+    can_ctrl_t *const p_api_ctrl;
+    can_cfg_t const *const p_cfg;
+};
+
+struct ra_can
+{
+    struct rt_can_device can_dev;
+    struct ra_can_config *config;
+    can_callback_args_t *callback_args;
+};
+
+struct ra_baud_rate_tab
+{
+    rt_uint32_t baud_rate;
+    rt_uint32_t sjw;
+    rt_uint32_t ts1;
+    rt_uint32_t ts2;
+    rt_uint32_t prescaler;
+};
+
+int rt_hw_can_init(void);
+
+#endif

bsp/renesas/ra6m4-iot/drivers/drv_common.c

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-7      SummerGift   first version
+ */
+
+#include <drv_common.h>
+#include <bsp_api.h>
+#include "board.h"
+
+#ifdef RT_USING_PIN
+    #include <drv_gpio.h>
+#endif
+
+#ifdef RT_USING_SERIAL
+    #ifdef RT_USING_SERIAL_V2
+        #include <drv_usart_v2.h>
+    #else
+        #include <drv_usart.h>
+    #endif
+#endif
+
+#ifdef RT_USING_FINSH
+#include <finsh.h>
+static void reboot(uint8_t argc, char **argv)
+{
+    rt_hw_cpu_reset();
+}
+MSH_CMD_EXPORT(reboot, Reboot System);
+#endif /* RT_USING_FINSH */
+
+/* SysTick configuration */
+void rt_hw_systick_init(void)
+{
+    SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
+    NVIC_SetPriority(SysTick_IRQn, 0xFF);
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+
+/**
+  * @brief  This function is executed in case of error occurrence.
+  * @param  None
+  * @retval None
+  */
+void _Error_Handler(char *s, int num)
+{
+    /* USER CODE BEGIN Error_Handler */
+    /* User can add his own implementation to report the HAL error return state */
+    while (1)
+    {
+    }
+    /* USER CODE END Error_Handler */
+}
+
+/**
+ * This function will delay for some us.
+ *
+ * @param us the delay time of us
+ */
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    rt_uint32_t ticks;
+    rt_uint32_t told, tnow, tcnt = 0;
+    rt_uint32_t reload = SysTick->LOAD;
+
+    ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
+    told = SysTick->VAL;
+    while (1)
+    {
+        tnow = SysTick->VAL;
+        if (tnow != told)
+        {
+            if (tnow < told)
+            {
+                tcnt += told - tnow;
+            }
+            else
+            {
+                tcnt += reload - tnow + told;
+            }
+            told = tnow;
+            if (tcnt >= ticks)
+            {
+                break;
+            }
+        }
+    }
+}
+
+/**
+ * This function will initial STM32 board.
+ */
+RT_WEAK void rt_hw_board_init()
+{
+
+    rt_hw_systick_init();
+
+    /* Heap initialization */
+#if defined(RT_USING_HEAP)
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+
+    /* Pin driver initialization is open by default */
+#ifdef RT_USING_PIN
+    rt_hw_pin_init();
+#endif
+
+    /* USART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_usart_init();
+#endif
+
+    /* Set the shell console output device */
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+    /* Board underlying hardware initialization */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+FSP_CPP_HEADER
+void R_BSP_WarmStart(bsp_warm_start_event_t event);
+FSP_CPP_FOOTER
+
+/*******************************************************************************************************************//**
+ * This function is called at various points during the startup process.  This implementation uses the event that is
+ * called right before main() to set up the pins.
+ *
+ * @param[in]  event    Where at in the start up process the code is currently at
+ **********************************************************************************************************************/
+void R_BSP_WarmStart (bsp_warm_start_event_t event)
+{
+    if (BSP_WARM_START_RESET == event)
+    {
+#if BSP_FEATURE_FLASH_LP_VERSION != 0
+
+        /* Enable reading from data flash. */
+        R_FACI_LP->DFLCTL = 1U;
+
+        /* Would normally have to wait tDSTOP(6us) for data flash recovery. Placing the enable here, before clock and
+         * C runtime initialization, should negate the need for a delay since the initialization will typically take more than 6us. */
+#endif
+    }
+
+    if (BSP_WARM_START_POST_C == event)
+    {
+        /* C runtime environment and system clocks are setup. */
+
+        /* Configure pins. */
+        R_IOPORT_Open(&g_ioport_ctrl, g_ioport.p_cfg);
+    }
+}
+
+#if BSP_TZ_SECURE_BUILD
+
+BSP_CMSE_NONSECURE_ENTRY void template_nonsecure_callable ();
+
+/* Trustzone Secure Projects require at least one nonsecure callable function in order to build (Remove this if it is not required to build). */
+BSP_CMSE_NONSECURE_ENTRY void template_nonsecure_callable ()
+{
+
+}
+#endif
\ No newline at end of file

bsp/renesas/ra6m4-iot/drivers/drv_common.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-7      SummerGift   first version
+ */
+
+#ifndef __DRV_COMMON_H__
+#define __DRV_COMMON_H__
+
+#include <rtthread.h>
+#include <rthw.h>
+#ifdef RT_USING_DEVICE
+    #include <rtdevice.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void _Error_Handler(char *s, int num);
+
+#ifndef Error_Handler
+#define Error_Handler() _Error_Handler(__FILE__, __LINE__)
+#endif
+
+#define DMA_NOT_AVAILABLE ((DMA_INSTANCE_TYPE *)0xFFFFFFFFU)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/renesas/ra6m4-iot/drivers/drv_dac.c

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-19     Mr.Tiger     first version
+ */
+
+#include <rtthread.h>
+#include "drv_config.h"
+#ifdef RT_USING_DAC
+
+//#define DRV_DEBUG
+#define DBG_TAG              "drv.dac"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+#include <rtdbg.h>
+
+struct ra_dac_map ra_dac[] =
+{
+#ifdef BSP_USING_DAC0
+    {'0', &g_dac0_cfg, &g_dac0_ctrl},
+#endif
+#ifdef BSP_USING_DAC1
+    {'1', &g_dac1_cfg, &g_dac1_ctrl},
+#endif
+};
+
+#ifdef BSP_USING_DAC0
+struct rt_dac_device dac0_device;
+struct ra_dac_dev _ra_dac0_device = {.ra_dac_device_t = &dac0_device, .ra_dac_map_dev = &ra_dac[0]};
+#endif
+
+#ifdef BSP_USING_DAC1
+struct rt_dac_device dac1_device;
+struct ra_dac_dev _ra_dac1_device = {.ra_dac_device_t = &dac1_device, .ra_dac_map_dev = &ra_dac[1]};
+#endif
+
+rt_err_t ra_dac_disabled(struct rt_dac_device *device, rt_uint32_t channel)
+{
+    RT_ASSERT(device != RT_NULL);
+    struct ra_dac_map *dac = (struct ra_dac_map *)device->parent.user_data;
+    if (FSP_SUCCESS != R_DAC_Stop((dac_ctrl_t *)dac->g_ctrl))
+    {
+        LOG_E("dac%c stop failed.", dac->name);
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+rt_err_t ra_dac_enabled(struct rt_dac_device *device, rt_uint32_t channel)
+{
+    RT_ASSERT(device != RT_NULL);
+    struct ra_dac_map *dac = (struct ra_dac_map *)device->parent.user_data;
+    if (FSP_SUCCESS != R_DAC_Start((dac_ctrl_t *)dac->g_ctrl))
+    {
+        LOG_E("dac%c start failed.", dac->name);
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+rt_err_t ra_dac_write(struct rt_dac_device *device, rt_uint32_t channel, rt_uint32_t *value)
+{
+    RT_ASSERT(device != RT_NULL);
+    struct ra_dac_map *dac = (struct ra_dac_map *)device->parent.user_data;
+    if (FSP_SUCCESS != R_DAC_Write((dac_ctrl_t *)dac->g_ctrl, *value))
+    {
+        LOG_E("dac%c set value failed.", dac->name);
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+}
+
+struct rt_dac_ops ra_dac_ops =
+{
+    .disabled = ra_dac_disabled,
+    .enabled  = ra_dac_enabled,
+    .convert  = ra_dac_write,
+};
+
+static int ra_dac_init(void)
+{
+#ifdef BSP_USING_DAC0
+    _ra_dac0_device.ra_dac_device_t->ops = &ra_dac_ops;
+    R_DAC_Open((dac_ctrl_t *)_ra_dac0_device.ra_dac_map_dev->g_ctrl, (dac_cfg_t const *)_ra_dac0_device.ra_dac_map_dev->g_cfg);
+    if (FSP_SUCCESS != rt_hw_dac_register(_ra_dac0_device.ra_dac_device_t, "dac0", &ra_dac_ops, (void *)_ra_dac0_device.ra_dac_map_dev))
+    {
+        LOG_E("dac0 register failed");
+        return -RT_ERROR;
+    }
+#endif
+
+#ifdef BSP_USING_DAC1
+    _ra_dac1_device.ra_dac_device_t->ops = &ra_dac_ops;
+    R_DAC_Open((dac_ctrl_t *)_ra_dac1_device.ra_dac_map_dev->g_ctrl, (dac_cfg_t const *) _ra_dac1_device.ra_dac_map_dev->g_cfg);
+    if (FSP_SUCCESS != rt_hw_dac_register(_ra_dac1_device.ra_dac_device_t, "dac1", &ra_dac_ops, (void *)_ra_dac1_device.ra_dac_map_dev))
+    {
+        LOG_E("dac1 register failed");
+        return -RT_ERROR;
+    }
+#endif
+
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(ra_dac_init);
+
+#endif

bsp/renesas/ra6m4-iot/drivers/drv_flash.c

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-30     flybreak     first version
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+
+#include "board.h"
+#include "hal_data.h"
+#include "drv_flash.h"
+
+#include <rtthread.h>
+
+#if defined(PKG_USING_FAL)
+    #include "fal.h"
+#endif
+
+//#define DRV_DEBUG
+#define LOG_TAG                "drv.flash"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+#include <rtdbg.h>
+
+int _flash_init(void)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    /* Open Flash_HP */
+    err = R_FLASH_HP_Open(&g_flash_ctrl, &g_flash_cfg);
+    /* Handle Error */
+    if (FSP_SUCCESS != err)
+    {
+        LOG_E("\r\n Flah_HP_Open API failed");
+    }
+    /* Setup Default  Block 0 as Startup Setup Block */
+    err = R_FLASH_HP_StartUpAreaSelect(&g_flash_ctrl, FLASH_STARTUP_AREA_BLOCK0, true);
+    if (err != FSP_SUCCESS)
+    {
+        LOG_E("\r\n Flah_HP_StartUpAreaSelect API failed");
+    }
+    return 0;
+}
+
+/**
+ * Read data from flash.
+ * @note This operation's units is word.
+ *
+ * @param addr flash address
+ * @param buf buffer to store read data
+ * @param size read bytes size
+ *
+ * @return result
+ */
+int _flash_read(rt_uint32_t addr, rt_uint8_t *buf, size_t size)
+{
+    size_t i;
+
+    for (i = 0; i < size; i++, buf++, addr++)
+    {
+        *buf = *(rt_uint8_t *) addr;
+    }
+
+    return size;
+}
+
+/**
+ * Write data to flash.
+ * @note This operation's units is word.
+ * @note This operation must after erase. @see flash_erase.
+ *
+ * @param addr flash address
+ * @param buf the write data buffer
+ * @param size write bytes size
+ *
+ * @return result
+ */
+int _flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
+{
+    rt_err_t result      = RT_EOK;
+    rt_base_t level;
+    fsp_err_t err = FSP_SUCCESS;
+    size_t written_size = 0;
+
+    if (size % BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE)
+    {
+        LOG_E("Flash Write size must be an integer multiple of %d", BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE);
+        return -RT_EINVAL;
+    }
+
+    while (written_size < size)
+    {
+        level = rt_hw_interrupt_disable();
+        R_FLASH_HP_Reset(&g_flash_ctrl);
+        /* Write code flash data*/
+        err = R_FLASH_HP_Write(&g_flash_ctrl, (uint32_t)(buf + written_size), addr + written_size, BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE);
+        rt_hw_interrupt_enable(level);
+
+        /* Error Handle */
+        if (FSP_SUCCESS != err)
+        {
+            LOG_E("Write API failed");
+            return -RT_EIO;
+        }
+
+        written_size += BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE;
+    }
+
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+
+    return size;
+}
+
+/**
+ * Erase data on flash.
+ * @note This operation is irreversible.
+ * @note This operation's units is different which on many chips.
+ *
+ * @param addr flash address
+ * @param size erase bytes size
+ *
+ * @return result
+ */
+int _flash_erase_8k(rt_uint32_t addr, size_t size)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    rt_base_t level;
+
+    if ((addr + size) > BSP_FEATURE_FLASH_HP_CF_REGION0_SIZE)
+    {
+        LOG_E("ERROR: erase outrange flash size! addr is (0x%p)\n", (void *)(addr + size));
+        return -RT_EINVAL;
+    }
+
+    if (size < 1)
+    {
+        return -RT_EINVAL;
+    }
+
+    level = rt_hw_interrupt_disable();
+    R_FLASH_HP_Reset(&g_flash_ctrl);
+    /* Erase Block */
+    err = R_FLASH_HP_Erase(&g_flash_ctrl, RT_ALIGN_DOWN(addr, FLASH_HP_CF_BLOCK_SIZE_8KB), (size - 1) / BSP_FEATURE_FLASH_HP_CF_REGION0_BLOCK_SIZE + 1);
+    rt_hw_interrupt_enable(level);
+
+    if (err != FSP_SUCCESS)
+    {
+        LOG_E("Erase API failed");
+        return -RT_EIO;
+    }
+
+    LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
+    return size;
+}
+
+int _flash_erase_32k(rt_uint32_t addr, size_t size)
+{
+    fsp_err_t err = FSP_SUCCESS;
+    rt_base_t level;
+
+    if (size < 1)
+    {
+        return -RT_EINVAL;
+    }
+
+    level = rt_hw_interrupt_disable();
+    R_FLASH_HP_Reset(&g_flash_ctrl);
+    /* Erase Block */
+    err = R_FLASH_HP_Erase(&g_flash_ctrl, RT_ALIGN_DOWN(addr, FLASH_HP_CF_BLOCK_SIZE_32KB), (size - 1) / BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE + 1);
+    rt_hw_interrupt_enable(level);
+
+    if (err != FSP_SUCCESS)
+    {
+        LOG_E("Erase API failed");
+        return -RT_EIO;
+    }
+
+    LOG_D("erase done: addr (0x%p), size %d", (void *)addr, size);
+    return size;
+}
+
+#if defined(PKG_USING_FAL)
+
+static int fal_flash_read_8k(long offset, rt_uint8_t *buf, size_t size);
+static int fal_flash_read_32k(long offset, rt_uint8_t *buf, size_t size);
+
+static int fal_flash_write_8k(long offset, const rt_uint8_t *buf, size_t size);
+static int fal_flash_write_32k(long offset, const rt_uint8_t *buf, size_t size);
+
+static int fal_flash_erase_8k(long offset, size_t size);
+static int fal_flash_erase_32k(long offset, size_t size);
+
+const struct fal_flash_dev _onchip_flash_8k = { "onchip_flash_8k", FLASH_HP_CF_BLCOK_0, FLASH_HP_CF_BLOCK_8, (8 * 1024), {_flash_init, fal_flash_read_8k, fal_flash_write_8k, fal_flash_erase_8k} };
+const struct fal_flash_dev _onchip_flash_32k = { "onchip_flash_32k", FLASH_HP_CF_BLOCK_8, 32 * 30 * 1024, (32 * 1024), {_flash_init, fal_flash_read_32k, fal_flash_write_32k, fal_flash_erase_32k} };
+
+static int fal_flash_read_8k(long offset, rt_uint8_t *buf, size_t size)
+{
+    return _flash_read(_onchip_flash_8k.addr + offset, buf, size);
+}
+
+static int fal_flash_read_32k(long offset, rt_uint8_t *buf, size_t size)
+{
+    return _flash_read(_onchip_flash_32k.addr + offset, buf, size);
+}
+
+static int fal_flash_write_8k(long offset, const rt_uint8_t *buf, size_t size)
+{
+    return _flash_write(_onchip_flash_8k.addr + offset, buf, size);
+}
+
+static int fal_flash_write_32k(long offset, const rt_uint8_t *buf, size_t size)
+{
+    return _flash_write(_onchip_flash_32k.addr + offset, buf, size);
+}
+
+static int fal_flash_erase_8k(long offset, size_t size)
+{
+    return _flash_erase_8k(_onchip_flash_8k.addr + offset, size);
+}
+
+static int fal_flash_erase_32k(long offset, size_t size)
+{
+    return _flash_erase_32k(_onchip_flash_32k.addr + offset, size);
+}
+
+int flash_test(void)
+{
+#define TEST_OFF (_onchip_flash_32k.len - BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE)
+    const struct fal_partition *param;
+    uint8_t write_buffer[BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE] = {0};
+    uint8_t read_buffer[BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE] = {0};
+
+    /* Set write buffer, clear read buffer */
+    for (uint8_t index = 0; index < BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE; index++)
+    {
+        write_buffer[index] = index;
+        read_buffer[index] = 0;
+    }
+
+    fal_init();
+
+    param = fal_partition_find("param");
+    if (param == RT_NULL)
+    {
+        LOG_E("not find partition param!");
+        return -1;
+    }
+    LOG_I("Erase Start...");
+    fal_partition_erase(param, TEST_OFF, BSP_FEATURE_FLASH_HP_CF_REGION1_BLOCK_SIZE);
+    LOG_I("Erase succeeded!");
+    LOG_I("Write Start...");
+    fal_partition_write(param, TEST_OFF, write_buffer, sizeof(write_buffer));
+    LOG_I("Write succeeded!");
+    LOG_I("Read Start...");
+    fal_partition_read(param, TEST_OFF, read_buffer, BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE);
+    LOG_I("Read succeeded!");
+
+    for (int i = 0; i < BSP_FEATURE_FLASH_HP_CF_WRITE_SIZE; i++)
+    {
+        if (read_buffer[i] != write_buffer[i])
+        {
+            LOG_E("Data verification failed!");
+            return -1;
+        }
+    }
+
+    LOG_I("Data verification succeeded!");
+    return 0;
+}
+MSH_CMD_EXPORT(flash_test, "drv flash test.");
+
+#endif

bsp/renesas/ra6m4-iot/drivers/drv_flash.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-11-30     flybreak     first version
+ */
+
+#ifndef __DRV_FLASH_H__
+#define __DRV_FLASH_H__
+
+#include <rtthread.h>
+#include "rtdevice.h"
+#include <rthw.h>
+#include <drv_common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Code Flash */
+#define FLASH_HP_CF_BLOCK_SIZE_32KB       (32*1024)    /* Block Size 32 KB */
+#define FLASH_HP_CF_BLOCK_SIZE_8KB        (8*1024)     /* Block Size 8KB */
+
+#define FLASH_HP_CF_BLCOK_0               0x00000000U  /*    8 KB:  0x00000000 - 0x00001FFF */
+#define FLASH_HP_CF_BLOCK_1               0x00002000U  /*    8 KB:  0x00002000 - 0x00003FFF */
+#define FLASH_HP_CF_BLOCK_2               0x00004000U  /*    8 KB:  0x00004000 - 0x00005FFF */
+#define FLASH_HP_CF_BLOCK_3               0x00006000U  /*    8 KB:  0x00006000 - 0x00007FFF */
+#define FLASH_HP_CF_BLOCK_4               0x00008000U  /*    8 KB:  0x00008000 - 0x00009FFF */
+#define FLASH_HP_CF_BLOCK_5               0x0000A000U  /*    8 KB:  0x0000A000 - 0x0000BFFF */
+#define FLASH_HP_CF_BLOCK_6               0x0000C000U  /*    8 KB:  0x0000C000 - 0x0000DFFF */
+#define FLASH_HP_CF_BLOCK_7               0x0000E000U  /*    8 KB:  0x0000E000 - 0x0000FFFF */
+#define FLASH_HP_CF_BLOCK_8               0x00010000U  /*   32 KB: 0x00010000 - 0x00017FFF */
+#define FLASH_HP_CF_BLOCK_9               0x00018000U  /*   32 KB: 0x00018000 - 0x0001FFFF */
+#define FLASH_HP_CF_BLCOK_10              0x00020000U  /*   32 KB: 0x00020000 - 0x0004FFFF */
+
+#define FLASH_HP_DF_BLOCK_SIZE            (64)
+/* Data Flash */
+#if (defined (BOARD_RA6M4_EK) || defined (BOARD_RA6M5_EK) || defined (BOARD_RA4M3_EK)||defined(BOARD_RA4M2_EK))
+
+#define FLASH_HP_DF_BLOCK_0               0x08000000U /*   64 B:  0x40100000 - 0x4010003F */
+#define FLASH_HP_DF_BLOCK_1               0x08000040U /*   64 B:  0x40100040 - 0x4010007F */
+#define FLASH_HP_DF_BLOCK_2               0x08000080U /*   64 B:  0x40100080 - 0x401000BF */
+#define FLASH_HP_DF_BLOCK_3               0x080000C0U /*   64 B:  0x401000C0 - 0x401000FF */
+
+#else
+
+#define FLASH_HP_DF_BLOCK_0               0x40100000U /*   64 B:  0x40100000 - 0x4010003F */
+#define FLASH_HP_DF_BLOCK_1               0x40100040U /*   64 B:  0x40100040 - 0x4010007F */
+#define FLASH_HP_DF_BLOCK_2               0x40100080U /*   64 B:  0x40100080 - 0x401000BF */
+#define FLASH_HP_DF_BLOCK_3               0x401000C0U /*   64 B:  0x401000C0 - 0x401000FF */
+
+#endif
+
+#define BLOCK_SIZE                        (128)
+#define BLOCK_NUM                         (2)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __DRV_FLASH_H__ */

bsp/renesas/ra6m4-iot/drivers/drv_gpio.c

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-07-29     KyleChan          first version
+ */
+
+#include <drv_gpio.h>
+
+#ifdef RT_USING_PIN
+
+#define DBG_TAG              "drv.gpio"
+#ifdef DRV_DEBUG
+    #define DBG_LVL               DBG_LOG
+#else
+    #define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+
+#ifdef R_ICU_H
+static rt_base_t ra_pin_get_irqx(rt_uint32_t pin)
+{
+    switch (pin)
+    {
+    case BSP_IO_PORT_04_PIN_00:
+    case BSP_IO_PORT_02_PIN_06:
+    case BSP_IO_PORT_01_PIN_05:
+        return 0;
+
+    case BSP_IO_PORT_02_PIN_05:
+    case BSP_IO_PORT_01_PIN_01:
+    case BSP_IO_PORT_01_PIN_04:
+        return 1;
+
+    case BSP_IO_PORT_02_PIN_03:
+    case BSP_IO_PORT_01_PIN_00:
+    case BSP_IO_PORT_02_PIN_13:
+        return 2;
+
+    case BSP_IO_PORT_02_PIN_02:
+    case BSP_IO_PORT_01_PIN_10:
+    case BSP_IO_PORT_02_PIN_12:
+        return 3;
+
+    case BSP_IO_PORT_04_PIN_02:
+    case BSP_IO_PORT_01_PIN_11:
+    case BSP_IO_PORT_04_PIN_11:
+        return 4;
+
+    case BSP_IO_PORT_04_PIN_01:
+    case BSP_IO_PORT_03_PIN_02:
+    case BSP_IO_PORT_04_PIN_10:
+        return 5;
+
+    case BSP_IO_PORT_03_PIN_01:
+    case BSP_IO_PORT_00_PIN_00:
+    case BSP_IO_PORT_04_PIN_09:
+        return 6;
+
+    case BSP_IO_PORT_00_PIN_01:
+    case BSP_IO_PORT_04_PIN_08:
+        return 7;
+
+    case BSP_IO_PORT_00_PIN_02:
+    case BSP_IO_PORT_03_PIN_05:
+    case BSP_IO_PORT_04_PIN_15:
+        return 8;
+
+    case BSP_IO_PORT_00_PIN_04:
+    case BSP_IO_PORT_03_PIN_04:
+    case BSP_IO_PORT_04_PIN_14:
+        return 9;
+
+    case BSP_IO_PORT_00_PIN_05:
+    case BSP_IO_PORT_07_PIN_09:
+        return 10;
+
+    case BSP_IO_PORT_05_PIN_01:
+    case BSP_IO_PORT_00_PIN_06:
+    case BSP_IO_PORT_07_PIN_08:
+        return 11;
+
+    case BSP_IO_PORT_05_PIN_02:
+    case BSP_IO_PORT_00_PIN_08:
+        return 12;
+
+    case BSP_IO_PORT_00_PIN_15:
+    case BSP_IO_PORT_00_PIN_09:
+        return 13;
+
+    case BSP_IO_PORT_04_PIN_03:
+    case BSP_IO_PORT_05_PIN_12:
+    case BSP_IO_PORT_05_PIN_05:
+        return 14;
+
+    case BSP_IO_PORT_04_PIN_04:
+    case BSP_IO_PORT_05_PIN_11:
+    case BSP_IO_PORT_05_PIN_06:
+        return 15;
+
+    default  :
+        return -1;
+    }
+}
+
+static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
+{
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+};
+
+#define RA_IRQ_MAX  16
+struct ra_pin_irq_map pin_irq_map[RA_IRQ_MAX] = {0};
+
+static void ra_pin_map_init(void)
+{
+#ifdef VECTOR_NUMBER_ICU_IRQ0
+    pin_irq_map[0].irq_ctrl = &g_external_irq0_ctrl;
+    pin_irq_map[0].irq_cfg = &g_external_irq0_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ1
+    pin_irq_map[1].irq_ctrl = &g_external_irq1_ctrl;
+    pin_irq_map[1].irq_cfg = &g_external_irq1_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ2
+    pin_irq_map[2].irq_ctrl = &g_external_irq2_ctrl;
+    pin_irq_map[2].irq_cfg = &g_external_irq2_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ3
+    pin_irq_map[3].irq_ctrl = &g_external_irq3_ctrl;
+    pin_irq_map[3].irq_cfg = &g_external_irq3_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ4
+    pin_irq_map[4].irq_ctrl = &g_external_irq4_ctrl;
+    pin_irq_map[4].irq_cfg = &g_external_irq4_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ5
+    pin_irq_map[5].irq_ctrl = &g_external_irq5_ctrl;
+    pin_irq_map[5].irq_cfg = &g_external_irq5_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ6
+    pin_irq_map[6].irq_ctrl = &g_external_irq6_ctrl;
+    pin_irq_map[6].irq_cfg = &g_external_irq6_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ7
+    pin_irq_map[7].irq_ctrl = &g_external_irq7_ctrl;
+    pin_irq_map[7].irq_cfg = &g_external_irq7_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ8
+    pin_irq_map[8].irq_ctrl = &g_external_irq8_ctrl;
+    pin_irq_map[8].irq_cfg = &g_external_irq8_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ9
+    pin_irq_map[9].irq_ctrl = &g_external_irq9_ctrl;
+    pin_irq_map[9].irq_cfg = &g_external_irq9_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ10
+    pin_irq_map[10].irq_ctrl = &g_external_irq10_ctrl;
+    pin_irq_map[10].irq_cfg = &g_external_irq10_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ11
+    pin_irq_map[11].irq_ctrl = &g_external_irq11_ctrl;
+    pin_irq_map[11].irq_cfg = &g_external_irq11_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ12
+    pin_irq_map[12].irq_ctrl = &g_external_irq12_ctrl;
+    pin_irq_map[12].irq_cfg = &g_external_irq12_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ13
+    pin_irq_map[13].irq_ctrl = &g_external_irq13_ctrl;
+    pin_irq_map[13].irq_cfg = &g_external_irq13_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ14
+    pin_irq_map[14].irq_ctrl = &g_external_irq14_ctrl;
+    pin_irq_map[14].irq_cfg = &g_external_irq14_cfg;
+#endif
+#ifdef VECTOR_NUMBER_ICU_IRQ15
+    pin_irq_map[15].irq_ctrl = &g_external_irq15_ctrl;
+    pin_irq_map[15].irq_cfg = &g_external_irq15_cfg;
+#endif
+}
+#endif  /* R_ICU_H */
+
+static void ra_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    fsp_err_t err;
+    /* Initialize the IOPORT module and configure the pins */
+    err = R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg);
+
+    if (err != FSP_SUCCESS)
+    {
+        LOG_E("GPIO open failed");
+        return;
+    }
+
+    switch (mode)
+    {
+    case PIN_MODE_OUTPUT:
+        err = R_IOPORT_PinCfg(&g_ioport_ctrl, pin, BSP_IO_DIRECTION_OUTPUT);
+        if (err != FSP_SUCCESS)
+        {
+            LOG_E("PIN_MODE_OUTPUT configuration failed");
+            return;
+        }
+        break;
+
+    case PIN_MODE_INPUT:
+        err = R_IOPORT_PinCfg(&g_ioport_ctrl, pin, BSP_IO_DIRECTION_INPUT);
+        if (err != FSP_SUCCESS)
+        {
+            LOG_E("PIN_MODE_INPUT configuration failed");
+            return;
+        }
+        break;
+
+    case PIN_MODE_OUTPUT_OD:
+        err = R_IOPORT_PinCfg(&g_ioport_ctrl, pin, IOPORT_CFG_NMOS_ENABLE);
+        if (err != FSP_SUCCESS)
+        {
+            LOG_E("PIN_MODE_OUTPUT_OD configuration failed");
+            return;
+        }
+        break;
+    }
+}
+
+static void ra_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    bsp_io_level_t level = BSP_IO_LEVEL_HIGH;
+
+    if (value != level)
+    {
+        level = BSP_IO_LEVEL_LOW;
+    }
+
+    R_BSP_PinAccessEnable();
+    R_BSP_PinWrite(pin, level);
+    R_BSP_PinAccessDisable();
+}
+
+static int ra_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    if ((pin > RA_MAX_PIN_VALUE) || (pin < RA_MIN_PIN_VALUE))
+    {
+        LOG_E("GPIO pin value is illegal");
+        return -RT_ERROR;
+    }
+    return R_BSP_PinRead(pin);
+}
+
+static rt_err_t ra_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+{
+#ifdef R_ICU_H
+    rt_err_t err;
+    rt_int32_t irqx = ra_pin_get_irqx(pin);
+    if (PIN_IRQ_ENABLE == enabled)
+    {
+        if (0 <= irqx && irqx < sizeof(pin_irq_map) / sizeof(pin_irq_map[0]))
+        {
+            err = R_ICU_ExternalIrqOpen((external_irq_ctrl_t *const)pin_irq_map[irqx].irq_ctrl,
+                                        (external_irq_cfg_t const * const)pin_irq_map[irqx].irq_cfg);
+            /* Handle error */
+            if (FSP_SUCCESS != err)
+            {
+                /* ICU Open failure message */
+                LOG_E("\r\n**R_ICU_ExternalIrqOpen API FAILED**\r\n");
+                return -RT_ERROR;
+            }
+
+            err = R_ICU_ExternalIrqEnable((external_irq_ctrl_t *const)pin_irq_map[irqx].irq_ctrl);
+            /* Handle error */
+            if (FSP_SUCCESS != err)
+            {
+                /* ICU Enable failure message */
+                LOG_E("\r\n**R_ICU_ExternalIrqEnable API FAILED**\r\n");
+                return -RT_ERROR;
+            }
+        }
+    }
+    else if (PIN_IRQ_DISABLE == enabled)
+    {
+        err = R_ICU_ExternalIrqDisable((external_irq_ctrl_t *const)pin_irq_map[irqx].irq_ctrl);
+        if (FSP_SUCCESS != err)
+        {
+            /* ICU Disable failure message */
+            LOG_E("\r\n**R_ICU_ExternalIrqDisable API FAILED**\r\n");
+            return -RT_ERROR;
+        }
+        err = R_ICU_ExternalIrqClose((external_irq_ctrl_t *const)pin_irq_map[irqx].irq_ctrl);
+        if (FSP_SUCCESS != err)
+        {
+            /* ICU Close failure message */
+            LOG_E("\r\n**R_ICU_ExternalIrqClose API FAILED**\r\n");
+            return -RT_ERROR;
+        }
+    }
+    return RT_EOK;
+#else
+    return -RT_ERROR;
+#endif
+}
+
+static rt_err_t ra_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                                  rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+#ifdef R_ICU_H
+    rt_int32_t irqx = ra_pin_get_irqx(pin);
+    if (0 <= irqx && irqx < (sizeof(pin_irq_map) / sizeof(pin_irq_map[0])))
+    {
+        int level = rt_hw_interrupt_disable();
+        if (pin_irq_hdr_tab[irqx].pin == irqx &&
+                pin_irq_hdr_tab[irqx].hdr == hdr &&
+                pin_irq_hdr_tab[irqx].mode == mode &&
+                pin_irq_hdr_tab[irqx].args == args)
+        {
+            rt_hw_interrupt_enable(level);
+            return RT_EOK;
+        }
+        if (pin_irq_hdr_tab[irqx].pin != -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return RT_EBUSY;
+        }
+        pin_irq_hdr_tab[irqx].pin = irqx;
+        pin_irq_hdr_tab[irqx].hdr = hdr;
+        pin_irq_hdr_tab[irqx].mode = mode;
+        pin_irq_hdr_tab[irqx].args = args;
+        rt_hw_interrupt_enable(level);
+    }
+    else return -RT_ERROR;
+    return RT_EOK;
+#else
+    return -RT_ERROR;
+#endif
+}
+
+static rt_err_t ra_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+{
+#ifdef R_ICU_H
+    rt_int32_t irqx = ra_pin_get_irqx(pin);
+    if (0 <= irqx && irqx < sizeof(pin_irq_map) / sizeof(pin_irq_map[0]))
+    {
+        int level = rt_hw_interrupt_disable();
+        if (pin_irq_hdr_tab[irqx].pin == -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return RT_EOK;
+        }
+        pin_irq_hdr_tab[irqx].pin = -1;
+        pin_irq_hdr_tab[irqx].hdr = RT_NULL;
+        pin_irq_hdr_tab[irqx].mode = 0;
+        pin_irq_hdr_tab[irqx].args = RT_NULL;
+        rt_hw_interrupt_enable(level);
+    }
+    else
+    {
+        return -RT_ERROR;
+    }
+    return RT_EOK;
+#else
+    return -RT_ERROR;
+#endif
+}
+
+static rt_base_t ra_pin_get(const char *name)
+{
+    int pin_number = -1, port = -1, pin = -1;
+    if (rt_strlen(name) != 4)
+        return -1;
+    if ((name[0] == 'P') || (name[0] == 'p'))
+    {
+        if ('0' <= (int)name[1] && (int)name[1] <= '9')
+        {
+            port = ((int)name[1] - 48) * 16 * 16;
+            if ('0' <= (int)name[2] && (int)name[2] <= '9')
+            {
+                if ('0' <= (int)name[3] && (int)name[3] <= '9')
+                {
+                    pin = ((int)name[2] - 48) * 10;
+                    pin += (int)name[3] - 48;
+                    pin_number = port + pin;
+                }
+                else return -1;
+            }
+            else return -1;
+        }
+        else return -1;
+    }
+    return pin_number;
+}
+
+const static struct rt_pin_ops _ra_pin_ops =
+{
+    .pin_mode       = ra_pin_mode,
+    .pin_write      = ra_pin_write,
+    .pin_read       = ra_pin_read,
+    .pin_attach_irq = ra_pin_attach_irq,
+    .pin_detach_irq = ra_pin_dettach_irq,
+    .pin_irq_enable = ra_pin_irq_enable,
+    .pin_get        = ra_pin_get,
+};
+
+int rt_hw_pin_init(void)
+{
+#ifdef R_ICU_H
+    ra_pin_map_init();
+#endif
+    return rt_device_pin_register("pin", &_ra_pin_ops, RT_NULL);
+}
+
+#ifdef R_ICU_H
+void irq0_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (0 == pin_irq_hdr_tab[0].pin)
+    {
+        pin_irq_hdr_tab[0].hdr(pin_irq_hdr_tab[0].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq1_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (1 == pin_irq_hdr_tab[1].pin)
+    {
+        pin_irq_hdr_tab[1].hdr(pin_irq_hdr_tab[1].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq2_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (2 == pin_irq_hdr_tab[2].pin)
+    {
+        pin_irq_hdr_tab[2].hdr(pin_irq_hdr_tab[2].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq3_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (3 == pin_irq_hdr_tab[3].pin)
+    {
+        pin_irq_hdr_tab[3].hdr(pin_irq_hdr_tab[3].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq4_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (4 == pin_irq_hdr_tab[4].pin)
+    {
+        pin_irq_hdr_tab[4].hdr(pin_irq_hdr_tab[4].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq5_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (5 == pin_irq_hdr_tab[5].pin)
+    {
+        pin_irq_hdr_tab[5].hdr(pin_irq_hdr_tab[5].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq6_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (6 == pin_irq_hdr_tab[6].pin)
+    {
+        pin_irq_hdr_tab[6].hdr(pin_irq_hdr_tab[6].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq7_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (7 == pin_irq_hdr_tab[7].pin)
+    {
+        pin_irq_hdr_tab[7].hdr(pin_irq_hdr_tab[7].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq8_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (8 == pin_irq_hdr_tab[8].pin)
+    {
+        pin_irq_hdr_tab[8].hdr(pin_irq_hdr_tab[8].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq9_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (9 == pin_irq_hdr_tab[9].pin)
+    {
+        pin_irq_hdr_tab[9].hdr(pin_irq_hdr_tab[9].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq10_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (10 == pin_irq_hdr_tab[10].pin)
+    {
+        pin_irq_hdr_tab[10].hdr(pin_irq_hdr_tab[10].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq11_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (11 == pin_irq_hdr_tab[11].pin)
+    {
+        pin_irq_hdr_tab[11].hdr(pin_irq_hdr_tab[11].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq12_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (12 == pin_irq_hdr_tab[12].pin)
+    {
+        pin_irq_hdr_tab[12].hdr(pin_irq_hdr_tab[12].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq13_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (13 == pin_irq_hdr_tab[13].pin)
+    {
+        pin_irq_hdr_tab[13].hdr(pin_irq_hdr_tab[13].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq14_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (14 == pin_irq_hdr_tab[14].pin)
+    {
+        pin_irq_hdr_tab[14].hdr(pin_irq_hdr_tab[14].args);
+    }
+    rt_interrupt_leave();
+};
+
+void irq15_callback(external_irq_callback_args_t *p_args)
+{
+    rt_interrupt_enter();
+    if (15 == pin_irq_hdr_tab[15].pin)
+    {
+        pin_irq_hdr_tab[15].hdr(pin_irq_hdr_tab[15].args);
+    }
+    rt_interrupt_leave();
+};
+#endif /* R_ICU_H */
+
+#endif /* RT_USING_PIN */

bsp/renesas/ra6m4-iot/drivers/drv_gpio.h

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-07-29     KyleChan          first version
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include <board.h>
+#include <rthw.h>
+#include <rtdbg.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <drv_common.h>
+#include <hal_data.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RA_MIN_PIN_VALUE    BSP_IO_PORT_00_PIN_00
+#define RA_MAX_PIN_VALUE    BSP_IO_PORT_11_PIN_15
+
+#ifdef R_ICU_H
+struct ra_pin_irq_map
+{
+    const icu_instance_ctrl_t     *irq_ctrl;
+    const external_irq_cfg_t      *irq_cfg;
+};
+#endif
+
+int rt_hw_pin_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DRV_GPIO_H__ */
\ No newline at end of file

bsp/renesas/ra6m4-iot/drivers/drv_pwm.c

+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-10-25     KevinXu      first version
+ */
+
+#include "drv_pwm.h"
+
+#ifdef RT_USING_PWM
+
+/* Declare the control function first */
+static rt_err_t drv_pwm_control(struct rt_device_pwm *, int, void *);
+static struct rt_pwm_ops drv_ops =
+{
+    drv_pwm_control
+};
+
+static struct ra_pwm ra6m4_pwm_obj[BSP_PWMS_NUM] =
+{
+#ifdef BSP_USING_PWM0
+    [BSP_PWM0_INDEX] = PWM_DRV_INITIALIZER(0),
+#endif
+#ifdef BSP_USING_PWM1
+    [BSP_PWM1_INDEX] = PWM_DRV_INITIALIZER(1),
+#endif
+#ifdef BSP_USING_PWM2
+    [BSP_PWM2_INDEX] = PWM_DRV_INITIALIZER(2),
+#endif
+#ifdef BSP_USING_PWM3
+    [BSP_PWM3_INDEX] = PWM_DRV_INITIALIZER(3),
+#endif
+#ifdef BSP_USING_PWM4
+    [BSP_PWM4_INDEX] = PWM_DRV_INITIALIZER(4),
+#endif
+#ifdef BSP_USING_PWM5
+    [BSP_PWM5_INDEX] = PWM_DRV_INITIALIZER(5),
+#endif
+#ifdef BSP_USING_PWM6
+    [BSP_PWM6_INDEX] = PWM_DRV_INITIALIZER(6),
+#endif
+#ifdef BSP_USING_PWM7
+    [BSP_PWM7_INDEX] = PWM_DRV_INITIALIZER(7),
+#endif
+#ifdef BSP_USING_PWM8
+    [BSP_PWM8_INDEX] = PWM_DRV_INITIALIZER(8),
+#endif
+#ifdef BSP_USING_PWM9
+    [BSP_PWM9_INDEX] = PWM_DRV_INITIALIZER(9),
+#endif
+};
+
+
+/* Convert the raw PWM period counts into ns */
+static rt_uint32_t _convert_counts_ns(uint32_t source_div, uint32_t raw)
+{
+    uint32_t pclkd_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD) >> source_div;
+    uint32_t ns = (uint32_t)(((uint64_t)raw * 1000000000ULL) / pclkd_freq_hz);
+    return ns;
+}
+
+/* Convert ns into raw PWM period counts */
+static rt_uint32_t _convert_ns_counts(uint32_t source_div, uint32_t raw)
+{
+    uint32_t pclkd_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD) >> source_div;
+    uint32_t counts = (uint32_t)(((uint64_t)raw * (uint64_t)pclkd_freq_hz) / 1000000000ULL);
+    return counts;
+}
+
+
+/* PWM_CMD_ENABLE or PWM_CMD_DISABLE */
+static rt_err_t drv_pwm_enable(struct ra_pwm *device,
+                               struct rt_pwm_configuration *configuration,
+                               rt_bool_t enable)
+{
+    fsp_err_t err = FSP_SUCCESS;
+
+    if (enable)
+    {
+        err = R_GPT_Start(device->g_ctrl);
+    }
+    else
+    {
+        err = R_GPT_Stop(device->g_ctrl);
+    }
+
+    return (err == FSP_SUCCESS) ? RT_EOK : -RT_ERROR;
+}
+
+/* PWM_CMD_GET */
+static rt_err_t drv_pwm_get(struct ra_pwm *device,
+                            struct rt_pwm_configuration *configuration)
+{
+    timer_info_t info;
+    if (R_GPT_InfoGet(device->g_ctrl, &info) != FSP_SUCCESS)
+        return -RT_ERROR;
+
+    configuration->pulse =
+        _convert_counts_ns(device->g_cfg->source_div, device->g_cfg->duty_cycle_counts);
+    configuration->period =
+        _convert_counts_ns(device->g_cfg->source_div, info.period_counts);
+    configuration->channel = device->g_cfg->channel;
+
+    return RT_EOK;
+}
+
+/* PWM_CMD_SET */
+static rt_err_t drv_pwm_set(struct ra_pwm *device,
+                            struct rt_pwm_configuration *conf)
+{
+    uint32_t counts;
+    fsp_err_t fsp_erra;
+    fsp_err_t fsp_errb;
+    rt_err_t rt_err;
+    uint32_t pulse;
+    uint32_t period;
+    struct rt_pwm_configuration orig_conf;
+
+    rt_err = drv_pwm_get(device, &orig_conf);
+    if (rt_err != RT_EOK)
+    {
+        return rt_err;
+    }
+
+    /* Pulse cannot last longer than period. */
+    period = conf->period;
+    pulse = (period >= conf->pulse) ? conf->pulse : period;
+
+    /* Not to set period again if it's not changed. */
+    if (period != orig_conf.period)
+    {
+        counts = _convert_ns_counts(device->g_cfg->source_div, period);
+        fsp_erra = R_GPT_PeriodSet(device->g_ctrl, counts);
+        if (fsp_erra != FSP_SUCCESS)
+        {
+            return -RT_ERROR;
+        }
+    }
+
+    /* Two pins of a channel will not be separated. */
+    counts = _convert_ns_counts(device->g_cfg->source_div, pulse);
+    fsp_erra = R_GPT_DutyCycleSet(device->g_ctrl, counts, GPT_IO_PIN_GTIOCA);
+    fsp_errb = R_GPT_DutyCycleSet(device->g_ctrl, counts, GPT_IO_PIN_GTIOCB);
+    if (fsp_erra != FSP_SUCCESS || fsp_errb != FSP_SUCCESS)
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * Implement of control method in struct rt_pwm_ops.
+ */
+static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
+{
+    struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
+    struct ra_pwm *pwm_device = (struct ra_pwm *)device->parent.user_data;
+
+    /**
+     * There's actually only one GPT timer with 10 channels. In this case, the
+     * timer is separated into 10 PWM devices, so each device has only one
+     * channel.
+     */
+    if (configuration->channel != 0)
+    {
+        return -RT_EINVAL;
+    }
+
+    switch (cmd)
+    {
+    case PWM_CMD_ENABLE:
+        return drv_pwm_enable(pwm_device, configuration, RT_TRUE);
+    case PWM_CMD_DISABLE:
+        return drv_pwm_enable(pwm_device, configuration, RT_FALSE);
+    case PWM_CMD_GET:
+        return drv_pwm_get(pwm_device, configuration);
+    case PWM_CMD_SET:
+        return drv_pwm_set(pwm_device, configuration);
+    default:
+        return -RT_EINVAL;
+    }
+
+    return RT_EOK;
+}
+
+/**
+ * This is to register the PWM device
+ *
+ * Note that the PWM driver only supports one fixed pin.
+ */
+int rt_hw_pwm_init(void)
+{
+    rt_err_t ret = RT_EOK;
+    rt_err_t rt_err = RT_EOK;
+    fsp_err_t fsp_err = FSP_SUCCESS;
+
+    for (int i = 0; i < BSP_PWMS_NUM; i++)
+    {
+        fsp_err = R_GPT_Open(ra6m4_pwm_obj[i].g_ctrl,
+                             ra6m4_pwm_obj[i].g_cfg);
+
+        rt_err = rt_device_pwm_register(&ra6m4_pwm_obj[i].pwm_device,
+                                        ra6m4_pwm_obj[i].name,
+                                        &drv_ops,
+                                        &ra6m4_pwm_obj[i]);
+
+        if (fsp_err != FSP_SUCCESS || rt_err != RT_EOK)
+        {
+            ret = -RT_ERROR;
+        }
+    }
+
+    return ret;
+}
+INIT_BOARD_EXPORT(rt_hw_pwm_init);
+#endif /* RT_USING_PWM */