[bsp]add bsp essemi/es32f369x.

bsp/essemi/es32f369x/.config

+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=100
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_DEBUG=y
+CONFIG_RT_DEBUG_COLOR=y
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_USING_MEMPOOL=y
+# CONFIG_RT_USING_MEMHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x40002
+# CONFIG_RT_USING_CPU_FFS is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+
+#
+# C++ features
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Command shell
+#
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_CMD_SIZE=80
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_USING_MSH_DEFAULT=y
+CONFIG_FINSH_USING_MSH_ONLY=y
+CONFIG_FINSH_ARG_MAX=10
+
+#
+# Device virtual file system
+#
+# CONFIG_RT_USING_DFS is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_PIPE_BUFSZ=512
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+CONFIG_RT_USING_CAN=y
+# CONFIG_RT_CAN_USING_HDR is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+CONFIG_RT_USING_I2C=y
+# CONFIG_RT_USING_I2C_BITOPS is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# POSIX layer and C standard library
+#
+# CONFIG_RT_USING_LIBC is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_LIBC_USING_TIME is not set
+
+#
+# Network
+#
+
+#
+# Socket abstraction layer
+#
+# CONFIG_RT_USING_SAL is not set
+
+#
+# Network interface device
+#
+# CONFIG_RT_USING_NETDEV is not set
+
+#
+# light weight TCP/IP stack
+#
+# CONFIG_RT_USING_LWIP is not set
+
+#
+# AT commands
+#
+# CONFIG_RT_USING_AT is not set
+
+#
+# VBUS(Virtual Software BUS)
+#
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_libsodium is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+
+#
+# language packages
+#
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+
+#
+# multimedia packages
+#
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+
+#
+# system packages
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_CMSIS is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+
+#
+# miscellaneous packages
+#
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_UKAL is not set
+CONFIG_SOC_ES32F3696LT=y
+
+#
+# Hardware Drivers Config
+#
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+
+#
+# UART Drivers
+#
+CONFIG_BSP_USING_UART0=y
+# CONFIG_BSP_USING_UART1 is not set
+# CONFIG_BSP_USING_UART2 is not set
+# CONFIG_BSP_USING_UART3 is not set
+# CONFIG_BSP_USING_UART4 is not set
+# CONFIG_BSP_USING_UART5 is not set
+
+#
+# SPI Drivers
+#
+# CONFIG_BSP_USING_SPI0 is not set
+# CONFIG_BSP_USING_SPI1 is not set
+# CONFIG_BSP_USING_SPI2 is not set
+
+#
+# I2C Drivers
+#
+# CONFIG_BSP_USING_I2C0 is not set
+# CONFIG_BSP_USING_I2C1 is not set
+
+#
+# CAN Drivers
+#
+# CONFIG_BSP_USING_CAN is not set
+
+#
+# Onboard Peripheral Drivers
+#
+
+#
+# Offboard Peripheral Drivers
+#

bsp/essemi/es32f369x/Kconfig

+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_ES32F3696LT
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+source "drivers/Kconfig"

bsp/essemi/es32f369x/README.md

+# ES-PDS-ES32F369x 开发板 BSP 说明
+标签： EastSoft、国产MCU、Cortex-M3、ES32F3696LT
+
+## 1. 简介
+
+本文档为上海东软载波微电子开发团队为 ES-PDS-ES32F369x 开发板提供的 BSP (板级支持包) 说明。
+通过阅读本文档，开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。
+
+### 1.1  开发板介绍
+
+主要内容如下：
+ES-PDS-ES32F369x 是东软载波微电子官方推出的一款基于 ARM Cortex-M3 内核的开发板，最高主频为 96MHz，可满足基础功能测试及高端功能扩展等开发需求。
+
+开发板外观如下图所示：
+
+ES-PDS-ES32F369x-V1.2
+
+![ES32F0654](figures/ES-PDS-ES32F369x-V1.2.jpg)
+
+该开发板常用 **板载资源** 如下：
+
+- MCU：ES32F3696LT，主频 96MHz，96KB SRAM，512KB FLASH，50 GPIOs
+- 外部模块：SPI FLASH (MX25L64，8MB)、I2C EEPROM (M24C04，512B)
+- 常用外设
+  - 可调电阻：1个(PA05)
+  - LED：2个，(PF00/PF01)
+  - 按键：6个，PB02、PB12、PC10、PC11、PC12、RESET(MRST)
+- 常用接口：GPIO、UART、SPI、I2C、CAN
+- 调试接口，ESLinkⅡ(EastSoft 官方推出的开发工具，有标准版和mini版两种版本，均自带 CDC 串口功能) SWD 下载
+
+外设支持:
+
+本 BSP 目前对外设的支持情况如下：
+
+| **板载外设** | **支持情况** | **备注**         |
+| :----------- | :----------: | :--------------- |
+| SPI FLASH    |     支持     | SPI0             |
+| **片上外设** | **支持情况** | **备注**         |
+| GPIO         |     支持     | 50 GPIOs         |
+| UART         |     支持     | UART0/1/2/3/4/5  |
+| SPI          |     支持     | SPI0/1/2         |
+| I2C          |     支持     | I2C0/1           |
+| CAN          |     支持     | CAN0             |
+
+### 1.2  注意事项
+
+更多详细信息请咨询[上海东软载波微电子技术支持](http://www.essemi.com/)
+
+## 2. 快速上手
+
+本 BSP 为开发者提供 MDK5 工程。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。
+
+### 硬件连接
+
+使用 ESLinkⅡ (自带 CDC 串口)或 Jlink 等调试工具连接开发板到 PC，拨动开关选择使用调试工具供电或使用外部电源供电。若使用 Jlink 等调试工具，还需要将 UART0_TX(PB10)、UART0_RX(PB11)、GND 接到串口工具上。
+
+使用ESlinkⅡ(mini)连接开发板如下图所示：
+
+ESLinkⅡ(mini) + ES-PDS-ES32F369x-V1.2
+
+![ESLinkII](figures/ESLinkII-mini.jpg)
+
+### 编译下载
+
+双击 project.uvprojx 文件，打开 MDK5 工程，工程默认配置使用 JLink 下载程序，在通过 JLink 连接开发板的基础上，点击下载按钮即可下载程序到开发板，如果使用 ESLinkⅡ，则选择 "CMSIS-DAP Debugger"，连接正常后即可编译并下载程序到开发板。
+
+### 运行结果
+
+下载程序成功之后，系统会自动运行，观察串口输出的信息，同时开发板LED闪烁。
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.2 build Jan 23 2020
+ 2006 - 2019 Copyright by rt-thread team
+msh>
+```
+## 3. 进阶使用
+
+此 BSP 默认只开启了 GPIO 和 uart0 的功能，如果需使用更多高级功能，需要利用 ENV 工具对 BSP 进行配置，步骤如下：
+
+1. 在 bsp 下打开 env 工具。
+
+2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
+
+3. 输入`pkgs --update`命令更新软件包。
+
+4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
+
+更多 Env 工具的详细介绍请参考 [RT-Thread 文档中心](https://www.rt-thread.org/document/site/)
+
+## 4. 联系人信息
+
+- [wangyongquan](https://github.com/wangyq2018) 
+
+## 5. 参考
+
+- [ EastSoft 官网](http://www.essemi.com)
+

bsp/essemi/es32f369x/SConscript

+# for module compiling
+import os
+Import('RTT_ROOT')
+
+objs = []
+cwd = str(Dir('#'))
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/essemi/es32f369x/SConstruct

+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/essemi/es32f369x/applications/SConscript

+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+
+CPPPATH = [cwd, str(Dir('#'))]
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/essemi/es32f369x/applications/main.c

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#define LED_PIN 18
+
+int main(void)
+{
+    int count = 1;
+    /* set PF00 pin mode to output */
+    rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
+
+    while (count++)
+    {
+        rt_pin_write(LED_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+    return RT_EOK;
+}

bsp/essemi/es32f369x/drivers/Kconfig

+menu "Hardware Drivers Config"
+
+    menu "On-chip Peripheral Drivers"
+        config BSP_USING_GPIO
+            bool "Enable GPIO"
+            select RT_USING_PIN
+            default y
+
+        menu "UART Drivers"
+            config BSP_USING_UART0
+                bool "Enable UART0 PB10/PB11(T/R)"
+                select RT_USING_SERIAL
+                default n
+
+            config BSP_USING_UART1
+                bool "Enable UART1 PC10/PC11(T/R)"
+                select RT_USING_SERIAL
+                default n
+
+            config BSP_USING_UART2
+                bool "Enable UART2 PC12/PD02(T/R)"
+                select RT_USING_SERIAL
+                default y
+                depends on !BSP_USING_HWTIMER1
+
+            config BSP_USING_UART3
+                bool "Enable UART3 PC04/PC05(T/R)"
+                select RT_USING_SERIAL
+                default n
+                depends on !BSP_USING_HWTIMER2
+
+            
+            config BSP_USING_UART4
+                bool "Enable UART4 PB06/PB07(T/R)"
+                select RT_USING_SERIAL
+                default n
+                depends on !BSP_USING_I2C0
+
+            config BSP_USING_UART5
+                bool "Enable UART5 PB09/PB08(T/R)"
+                select RT_USING_SERIAL
+                default n
+        endmenu
+
+        menu "SPI Drivers"
+            config BSP_USING_SPI0
+                bool "Enable SPI0 BUS PB03/PB04/PB05(CLK/MISO/MOSI)"
+                select RT_USING_SPI
+                select RT_USING_PIN
+                default n
+
+            config BSP_USING_SPI1
+                bool "Enable SPI1 BUS PC01/PC02/PC03(CLK/MISO/MOSI)"
+                select RT_USING_SPI
+                select RT_USING_PIN
+                default n
+
+            config BSP_USING_SPI2
+                bool "Enable SPI2 BUS PC05/PB00/PB01(CLK/MISO/MOSI)"
+                select RT_USING_SPI
+                select RT_USING_PIN
+                default n
+        endmenu
+
+        menu "I2C Drivers"
+            config BSP_USING_I2C0
+                bool "Enable I2C0 BUS PB08/PB09(SCL/SDA)"
+                select RT_USING_I2C
+                default n
+
+            config BSP_USING_I2C1
+                bool "Enable I2C1 BUS PB10/PB11(SCL/SDA)"
+                select RT_USING_I2C
+                default n
+        endmenu
+
+        menu "CAN Drivers"
+            config BSP_USING_CAN
+                bool "Enable CAN BUS PB08/PB09(RX/TX)"
+                select RT_USING_CAN
+                default n
+        endmenu
+    endmenu
+
+    menu "Onboard Peripheral Drivers"
+
+    endmenu
+
+    menu "Offboard Peripheral Drivers"
+
+    endmenu
+
+endmenu

bsp/essemi/es32f369x/drivers/SConscript

+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split('''
+board.c
+''')
+
+# add gpio code
+if GetDepend('RT_USING_PIN'):
+    src += ['drv_gpio.c']
+
+# add serial driver code
+if  GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3') or \
+    GetDepend('BSP_USING_UART4') or GetDepend('BSP_USING_UART5'):
+    src += ['drv_uart.c']
+
+# add spi driver code
+if  GetDepend('BSP_USING_SPI0') or GetDepend('BSP_USING_SPI1') or GetDepend('BSP_USING_SPI2'):
+    src += ['drv_spi.c']
+
+# add i2c driver code
+if  GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'):
+    src += ['drv_i2c.c']
+
+# add can driver code
+if  GetDepend('BSP_USING_CAN'):
+    src += ['drv_can.c']
+
+CPPPATH = [cwd]
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/essemi/es32f369x/drivers/board.c

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "board.h"
+#include "drv_uart.h"
+#include "drv_gpio.h"
+#include <ald_cmu.h>
+#include <ald_gpio.h>
+
+/**
+ * @addtogroup es32f3
+ */
+
+/*@{*/
+
+/*******************************************************************************
+* Function Name  : NVIC_Configuration
+* Description    : Configures Vector Table base location.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_Configuration(void)
+{
+}
+
+/*******************************************************************************
+ * Function Name  : SystemClock_Configuration
+ * Description    : Configures the System Clock.
+ * Input          : None
+ * Output         : None
+ * Return         : None
+ *******************************************************************************/
+void  SystemClock_Config(void)
+{
+    /* hosc 12MHz, from hosc/3 pll to 96MHz */
+    ald_cmu_pll1_config(CMU_PLL1_INPUT_HOSC_3, CMU_PLL1_OUTPUT_96M);
+    /*  SYSCLK 96MHz */
+    ald_cmu_clock_config(CMU_CLOCK_PLL1, 96000000);
+    ald_cmu_perh_clock_config(CMU_PERH_ALL, ENABLE);
+}
+
+/*******************************************************************************
+ * Function Name  : SysTick_Configuration
+ * Description    : Configures the SysTick for OS tick.
+ * Input          : None
+ * Output         : None
+ * Return         : None
+ *******************************************************************************/
+void  SysTick_Configuration(void)
+{
+    /* ticks = sysclk / RT_TICK_PER_SECOND */
+    SysTick_Config(ald_cmu_get_sys_clock() / RT_TICK_PER_SECOND);
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    rt_tick_increase();
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/*@}*/
+/**
+ * This function will initial ES32F3 board.
+ */
+void rt_hw_board_init(void)
+{
+    /* NVIC Configuration */
+    NVIC_Configuration();
+    /*System Clock Configuration */
+    SystemClock_Config();
+    /* Configure the SysTick */
+    SysTick_Configuration();
+
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+#endif
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+}
+
+/**
+ * This function will delay for some us.
+ *
+ * @param us the delay time of us
+ */
+void rt_hw_us_delay(rt_uint32_t us)
+{
+    unsigned int start, now, delta, reload, us_tick;
+    start = SysTick->VAL;
+    reload = SysTick->LOAD;
+    us_tick = ald_cmu_get_sys_clock() / 1000000UL;
+    do
+    {
+        now = SysTick->VAL;
+        delta = start > now ? start - now : reload + start - now;
+    }
+    while (delta <  us_tick * us);
+}

bsp/essemi/es32f369x/drivers/board.h

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ */
+
+// <<< Use Configuration Wizard in Context Menu >>>
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <es32f36xx.h>
+
+#define ES32F3_SRAM_SIZE    0x80000
+#define ES32F3_SRAM_END     (0x20000000 + ES32F3_SRAM_SIZE)
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+    extern int Image$$RW_IRAM1$$ZI$$Limit;
+    #define HEAP_BEGIN  ((void *)&Image$$RW_IRAM1$$ZI$$Limit)
+#elif __ICCARM__
+    #pragma section="HEAP"
+    #define HEAP_BEGIN  (__segment_end("HEAP"))
+#else
+    extern int __bss_end;
+    #define HEAP_BEGIN  ((void *)&__bss_end)
+#endif
+
+#define HEAP_END    ES32F3_SRAM_END
+
+void rt_hw_board_init(void);
+
+#endif

bsp/essemi/es32f369x/drivers/drv_can.c

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ */
+
+#include "drv_can.h"
+
+#ifdef BSP_USING_CAN
+
+static struct es32f3_can can;
+
+/* attention !!! baud calculation example: Pclk / ((sjw + seg1 + seg2) * psc)  48 / ((1 + 3 + 2) * 8) = 1MHz */
+static const struct es32f3_baud_rate_tab can_baud_rate_tab[] =
+{
+    {CAN1MBaud, 8},
+    {CAN800kBaud, 10},
+    {CAN500kBaud, 16},
+    {CAN250kBaud, 32},
+    {CAN125kBaud, 64},
+    {CAN100kBaud, 80},
+    {CAN50kBaud, 160},
+    {CAN20kBaud, 400},
+    {CAN10kBaud, 800}
+};
+
+static rt_uint32_t get_can_baud_index(rt_uint32_t baud)
+{
+    rt_uint32_t len, index;
+
+    len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]);
+    for (index = 0; index < len; index++)
+    {
+        if (can_baud_rate_tab[index].baud_rate == baud)
+            return index;
+    }
+
+    return 0; /* default baud is CAN1MBaud */
+}
+
+static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configure *cfg)
+{
+    struct es32f3_can *drv_can;
+    rt_uint32_t baud_index;
+
+    RT_ASSERT(can_device);
+    RT_ASSERT(cfg);
+    drv_can = (struct es32f3_can *)can_device->parent.user_data;
+    RT_ASSERT(drv_can);
+
+    drv_can->CanHandle.perh = CAN0;
+    drv_can->CanHandle.init.ttcm = DISABLE;
+    drv_can->CanHandle.init.abom = ENABLE;
+    drv_can->CanHandle.init.awk = DISABLE;
+    drv_can->CanHandle.init.artx = DISABLE;
+    drv_can->CanHandle.init.rfom   = DISABLE;
+    drv_can->CanHandle.init.txmp   = ENABLE;
+
+    switch (cfg->mode)
+    {
+    case RT_CAN_MODE_NORMAL:
+        drv_can->CanHandle.init.mode = CAN_MODE_NORMAL;
+        break;
+    case RT_CAN_MODE_LISEN:
+        drv_can->CanHandle.init.mode = CAN_MODE_SILENT;
+        break;
+    case RT_CAN_MODE_LOOPBACK:
+        drv_can->CanHandle.init.mode = CAN_MODE_LOOPBACK;
+        break;
+    case RT_CAN_MODE_LOOPBACKANLISEN:
+        drv_can->CanHandle.init.mode = CAN_MODE_SILENT_LOOPBACK;
+        break;
+    }
+
+    baud_index = get_can_baud_index(cfg->baud_rate);
+    drv_can->CanHandle.init.sjw = CAN_SJW_1;
+    drv_can->CanHandle.init.seg1 = CAN_SEG1_3;
+    drv_can->CanHandle.init.seg2 = CAN_SEG2_2;
+    drv_can->CanHandle.init.psc = can_baud_rate_tab[baud_index].config_data;
+    /* init can */
+    if (ald_can_init(&drv_can->CanHandle) != OK)
+    {
+        return -RT_ERROR;
+    }
+    /* default filter config */
+    ald_can_filter_config(&drv_can->CanHandle, &drv_can->FilterConfig);
+
+    return RT_EOK;
+}
+
+static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *arg)
+{
+    rt_uint32_t argval;
+    struct es32f3_can *drv_can;
+    struct rt_can_filter_config *filter_cfg;
+
+    RT_ASSERT(can_device != RT_NULL);
+    drv_can = (struct es32f3_can *)can_device->parent.user_data;
+    RT_ASSERT(drv_can != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        argval = (rt_uint32_t) arg;
+        if (argval == RT_DEVICE_FLAG_INT_RX)
+        {
+            ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_FP0 | CAN_IT_FF0 | CAN_IT_FOV0 |
+                                     CAN_IT_FP1 | CAN_IT_FF1 | CAN_IT_FOV1), DISABLE);
+        }
+        else if (argval == RT_DEVICE_FLAG_INT_TX)
+        {
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_TXM, DISABLE);
+        }
+        else if (argval == RT_DEVICE_CAN_INT_ERR)
+        {
+            ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_WARN | CAN_IT_PERR | CAN_IT_BOF |
+                                     CAN_IT_PRERR | CAN_IT_ERR), DISABLE);
+        }
+        break;
+    case RT_DEVICE_CTRL_SET_INT:
+        argval = (rt_uint32_t) arg;
+        if (argval == RT_DEVICE_FLAG_INT_RX)
+        {
+            NVIC_SetPriority(CAN0_RX0_IRQn, 1);
+            NVIC_EnableIRQ(CAN0_RX0_IRQn);
+
+            NVIC_SetPriority(CAN0_RX0_IRQn, 1);
+            NVIC_EnableIRQ(CAN0_RX0_IRQn);
+
+            ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_FP0 | CAN_IT_FF0 | CAN_IT_FOV0 |
+                                     CAN_IT_FP1 | CAN_IT_FF1 | CAN_IT_FOV1), ENABLE);
+        }
+        else if (argval == RT_DEVICE_FLAG_INT_TX)
+        {
+            NVIC_SetPriority(CAN0_TX_IRQn, 1);
+            NVIC_EnableIRQ(CAN0_TX_IRQn);
+
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_TXM, ENABLE);
+        }
+        else if (argval == RT_DEVICE_CAN_INT_ERR)
+        {
+            NVIC_SetPriority(CAN0_EXCEPTION_IRQn, 1);
+            NVIC_EnableIRQ(CAN0_EXCEPTION_IRQn);
+
+            ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_WARN | CAN_IT_PERR | CAN_IT_BOF |
+                                     CAN_IT_PRERR | CAN_IT_ERR), ENABLE);
+        }
+        break;
+    case RT_CAN_CMD_SET_FILTER:
+        if (RT_NULL == arg)
+        {
+            /* default filter config */
+            ald_can_filter_config(&drv_can->CanHandle, &drv_can->FilterConfig);
+        }
+        else
+        {
+            filter_cfg = (struct rt_can_filter_config *)arg;
+            /* get default filter */
+            for (int i = 0; i < filter_cfg->count; i++)
+            {
+                drv_can->FilterConfig.number = filter_cfg->items[i].hdr;
+                drv_can->FilterConfig.id_high = (filter_cfg->items[i].id >> 13) & 0xFFFF;
+                drv_can->FilterConfig.id_low = ((filter_cfg->items[i].id << 3) |
+                                                (filter_cfg->items[i].ide << 2) |
+                                                (filter_cfg->items[i].rtr << 1)) & 0xFFFF;
+                drv_can->FilterConfig.mask_id_high = (filter_cfg->items[i].mask >> 16) & 0xFFFF;
+                drv_can->FilterConfig.mask_id_low = filter_cfg->items[i].mask & 0xFFFF;
+                drv_can->FilterConfig.mode = (can_filter_mode_t)filter_cfg->items[i].mode;
+                /* Filter conf */
+                ald_can_filter_config(&drv_can->CanHandle, &drv_can->FilterConfig);
+            }
+        }
+        break;
+    case RT_CAN_CMD_SET_MODE:
+        argval = (rt_uint32_t) arg;
+        if (argval != RT_CAN_MODE_NORMAL &&
+                argval != RT_CAN_MODE_LISEN &&
+                argval != RT_CAN_MODE_LOOPBACK &&
+                argval != RT_CAN_MODE_LOOPBACKANLISEN)
+        {
+            return -RT_ERROR;
+        }
+        if (argval != drv_can->device.config.mode)
+        {
+            drv_can->device.config.mode = argval;
+            return _can_config(&drv_can->device, &drv_can->device.config);
+        }
+        break;
+    case RT_CAN_CMD_SET_BAUD:
+        argval = (rt_uint32_t) arg;
+        if (argval != CAN1MBaud &&
+                argval != CAN800kBaud &&
+                argval != CAN500kBaud &&
+                argval != CAN250kBaud &&
+                argval != CAN125kBaud &&
+                argval != CAN100kBaud &&
+                argval != CAN50kBaud  &&
+                argval != CAN20kBaud  &&
+                argval != CAN10kBaud)
+        {
+            return -RT_ERROR;
+        }
+        if (argval != drv_can->device.config.baud_rate)
+        {
+            drv_can->device.config.baud_rate = argval;
+            return _can_config(&drv_can->device, &drv_can->device.config);
+        }
+        break;
+    case RT_CAN_CMD_SET_PRIV:
+        argval = (rt_uint32_t) arg;
+        if (argval != RT_CAN_MODE_PRIV &&
+                argval != RT_CAN_MODE_NOPRIV)
+        {
+            return -RT_ERROR;
+        }
+        if (argval != drv_can->device.config.privmode)
+        {
+            drv_can->device.config.privmode = argval;
+            return _can_config(&drv_can->device, &drv_can->device.config);
+        }
+        break;
+    case RT_CAN_CMD_GET_STATUS:
+    {
+        rt_uint32_t errtype;
+        errtype = drv_can->CanHandle.perh->ERRSTAT;
+        drv_can->device.status.rcverrcnt = errtype >> 24;
+        drv_can->device.status.snderrcnt = (errtype >> 16 & 0xFF);
+        drv_can->device.status.lasterrtype = errtype & 0x70;
+        drv_can->device.status.errcode = errtype & 0x07;
+
+        rt_memcpy(arg, &drv_can->device.status, sizeof(drv_can->device.status));
+    }
+    break;
+    }
+
+    return RT_EOK;
+}
+
+static int _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num)
+{
+    can_handle_t *h_can;
+    h_can = &((struct es32f3_can *) can->parent.user_data)->CanHandle;
+    struct rt_can_msg *pmsg = (struct rt_can_msg *) buf;
+    can_tx_msg_t txheader = {0};
+    can_state_t state = h_can->state;
+
+    /* Check the parameters */
+    RT_ASSERT(IS_CAN_DATA_LEN(pmsg->len));
+
+    if ((state == CAN_STATE_READY) ||
+            (state == CAN_STATE_BUSY_RX))
+    {
+        /*check select mailbox  is empty */
+        switch (1 << box_num)
+        {
+        case CAN_TX_MAILBOX_0:
+            if (ald_can_get_flag_status(h_can, CAN_FLAG_TXM0) != SET)
+            {
+                /* Change CAN state */
+                h_can->state = CAN_STATE_ERROR;
+                /* Return function status */
+                return -RT_ERROR;
+            }
+            break;
+        case CAN_TX_MAILBOX_1:
+            if (ald_can_get_flag_status(h_can, CAN_FLAG_TXM1) != SET)
+            {
+                /* Change CAN state */
+                h_can->state = CAN_STATE_ERROR;
+                /* Return function status */
+                return -RT_ERROR;
+            }
+            break;
+        case CAN_TX_MAILBOX_2:
+            if (ald_can_get_flag_status(h_can, CAN_FLAG_TXM2) != SET)
+            {
+                /* Change CAN state */
+                h_can->state = CAN_STATE_ERROR;
+                /* Return function status */
+                return -RT_ERROR;
+            }
+            break;
+        default:
+            RT_ASSERT(0);
+            break;
+        }
+
+        if (RT_CAN_STDID == pmsg->ide)
+        {
+            txheader.type = CAN_ID_STD;
+            RT_ASSERT(IS_CAN_STDID(pmsg->id));
+            txheader.std = pmsg->id;
+        }
+        else
+        {
+            txheader.type = CAN_ID_EXT;
+            RT_ASSERT(IS_CAN_EXTID(pmsg->id));
+            txheader.ext = pmsg->id;
+        }
+
+        if (RT_CAN_DTR == pmsg->rtr)
+        {
+            txheader.rtr = CAN_RTR_DATA;
+        }
+        else
+        {
+            txheader.rtr = CAN_RTR_REMOTE;
+        }
+        /* clear TIR */
+        h_can->perh->TxMailBox[box_num].TXID &= CAN_TXID0_TXMREQ_MSK;
+        /* Set up the Id */
+        if (RT_CAN_STDID == pmsg->ide)
+        {
+            h_can->perh->TxMailBox[box_num].TXID |= (txheader.std << CAN_TXID0_STDID_POSS) | txheader.rtr;
+        }
+        else
+        {
+            h_can->perh->TxMailBox[box_num].TXID |= (txheader.ext << CAN_TXID0_EXID_POSS) | txheader.type | txheader.rtr;
+        }
+        /* Set up the DLC */
+        h_can->perh->TxMailBox[box_num].TXFCON = pmsg->len & 0x0FU;
+        /* Set up the data field */
+        WRITE_REG(h_can->perh->TxMailBox[box_num].TXDH,
+                  ((uint32_t)pmsg->data[7] << CAN_TXDH0_BYTE7_POSS) |
+                  ((uint32_t)pmsg->data[6] << CAN_TXDH0_BYTE6_POSS) |
+                  ((uint32_t)pmsg->data[5] << CAN_TXDH0_BYTE5_POSS) |
+                  ((uint32_t)pmsg->data[4] << CAN_TXDH0_BYTE4_POSS));
+        WRITE_REG(h_can->perh->TxMailBox[box_num].TXDL,
+                  ((uint32_t)pmsg->data[3] << CAN_TXDL0_BYTE3_POSS) |
+                  ((uint32_t)pmsg->data[2] << CAN_TXDL0_BYTE2_POSS) |
+                  ((uint32_t)pmsg->data[1] << CAN_TXDL0_BYTE1_POSS) |
+                  ((uint32_t)pmsg->data[0] << CAN_TXDL0_BYTE0_POSS));
+        /* Request transmission */
+        SET_BIT(h_can->perh->TxMailBox[box_num].TXID, CAN_TXID0_TXMREQ_MSK);
+
+        return RT_EOK;
+    }
+    else
+    {
+        /* Update error code */
+        h_can->err |= 0x00040000U;
+
+        return -RT_ERROR;
+    }
+}
+
+static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
+{
+    can_handle_t *h_can;
+    struct rt_can_msg *pmsg;
+    can_rx_msg_t rxheader = {0};
+
+    RT_ASSERT(can);
+
+    h_can = &((struct es32f3_can *)can->parent.user_data)->CanHandle;
+    pmsg = (struct rt_can_msg *) buf;
+
+    /* get data */
+    if (ald_can_recv(h_can, (can_rx_fifo_t)fifo, &rxheader, 0xFFFF) != OK)
+        return -RT_ERROR;
+    pmsg->data[0] = rxheader.data[0];
+    pmsg->data[1] = rxheader.data[1];
+    pmsg->data[2] = rxheader.data[2];
+    pmsg->data[3] = rxheader.data[3];
+    pmsg->data[4] = rxheader.data[4];
+    pmsg->data[5] = rxheader.data[5];
+    pmsg->data[6] = rxheader.data[6];
+    pmsg->data[7] = rxheader.data[7];
+
+    /* get id */
+    if (CAN_ID_STD == rxheader.type)
+    {
+        pmsg->ide = RT_CAN_STDID;
+        pmsg->id = rxheader.std;
+    }
+    else
+    {
+        pmsg->ide = RT_CAN_EXTID;
+        pmsg->id = rxheader.ext;
+    }
+    /* get type */
+    if (CAN_RTR_DATA == rxheader.rtr)
+    {
+        pmsg->rtr = RT_CAN_DTR;
+    }
+    else
+    {
+        pmsg->rtr = RT_CAN_RTR;
+    }
+    /* get len */
+    pmsg->len = rxheader.len;
+    /* get hdr */
+    pmsg->hdr = (rxheader.fmi + 1) >> 1;
+
+    return RT_EOK;
+}
+
+
+static const struct rt_can_ops _can_ops =
+{
+    _can_config,
+    _can_control,
+    _can_sendmsg,
+    _can_recvmsg,
+};
+
+static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo)
+{
+    can_handle_t *h_can;
+    RT_ASSERT(can);
+    h_can = &((struct es32f3_can *) can->parent.user_data)->CanHandle;
+
+    switch (fifo)
+    {
+    case CAN_RX_FIFO0:
+        /* Check Overrun flag for FIFO0 */
+        if (ald_can_get_flag_status(h_can, CAN_FLAG_FOV0) && ald_can_get_it_status(h_can, CAN_IT_FOV0))
+        {
+            /* Clear FIFO0 Overrun Flag */
+            ald_can_clear_flag_status(h_can, CAN_FLAG_FOV0);
+            rt_hw_can_isr(can, RT_CAN_EVENT_RXOF_IND | fifo << 8);
+        }
+        /* RX interrupt */
+        else
+        {
+            /* save to user list */
+            rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8);
+            /* Clear FIFO0 rx Flag */
+            SET_BIT(h_can->perh->RXF0, CAN_RXF0_FREE_MSK);
+        }
+        break;
+    case CAN_RX_FIFO1:
+        /* Check Overrun flag for FIFO1 */
+        if (ald_can_get_flag_status(h_can, CAN_FLAG_FOV1) && ald_can_get_it_status(h_can, CAN_IT_FOV1))
+        {
+            /* Clear FIFO1 Overrun Flag */
+            ald_can_clear_flag_status(h_can, CAN_FLAG_FOV1);
+            rt_hw_can_isr(can, RT_CAN_EVENT_RXOF_IND | fifo << 8);
+        }
+        /* RX interrupt */
+        else
+        {
+            /* save to user list */
+            rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8);
+            /* Clear FIFO0 rx Flag */
+            SET_BIT(h_can->perh->RXF1, CAN_RXF1_FREE_MSK);
+        }
+        break;
+    }
+}
+
+/**
+ * @brief This function handles CAN0 TX interrupts. transmit fifo0/1/2 is empty can trigger this interrupt
+ */
+void CAN0_TX_Handler(void)
+{
+    rt_interrupt_enter();
+    can_handle_t *h_can;
+    h_can = &can.CanHandle;
+
+    /* TX interrupt. transmit fifo0/1/2 is empty can trigger this interrupt */
+    if (ald_can_get_flag_status(h_can, CAN_FLAG_M0REQC) && ald_can_get_it_status(h_can, CAN_IT_TXM))
+    {
+        if (ald_can_get_flag_status(h_can, CAN_FLAG_M0TXC))
+        {
+            rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_DONE | 0 << 8);
+        }
+        else
+        {
+            rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
+        }
+        /* Clear transmission status flag M0REQC */
+        ald_can_clear_flag_status(h_can, CAN_FLAG_M0REQC);
+    }
+    else if (ald_can_get_flag_status(h_can, CAN_FLAG_M1REQC) && ald_can_get_it_status(h_can, CAN_IT_TXM))
+    {
+        if (ald_can_get_flag_status(h_can, CAN_FLAG_M1TXC))
+        {
+            rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_DONE | 1 << 8);
+        }
+        else
+        {
+            rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
+        }
+        ald_can_clear_flag_status(h_can, CAN_FLAG_M1REQC);
+    }
+    else if (ald_can_get_flag_status(h_can, CAN_FLAG_M2REQC) && ald_can_get_it_status(h_can, CAN_IT_TXM))
+    {
+        if (ald_can_get_flag_status(h_can, CAN_FLAG_M2REQC))
+        {
+            rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_DONE | 2 << 8);
+        }
+        else
+        {
+            rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
+        }
+        ald_can_clear_flag_status(h_can, CAN_FLAG_M2REQC);
+    }
+
+    rt_interrupt_leave();
+}
+
+/**
+ * @brief This function handles CAN0 RX0 interrupts.
+ */
+void CAN0_RX0_Handler(void)
+{
+    rt_interrupt_enter();
+    _can_rx_isr(&can.device, CAN_RX_FIFO0);
+    rt_interrupt_leave();
+}
+
+/**
+ * @brief This function handles CAN0 RX1 interrupts.
+ */
+void CAN0_RX1_Handler(void)
+{
+    rt_interrupt_enter();
+    _can_rx_isr(&can.device, CAN_RX_FIFO1);
+    rt_interrupt_leave();
+}
+
+/**
+ * @brief This function handles CAN interrupts.
+ */
+void CAN0_EXCEPTION_Handler(void)
+{
+    rt_interrupt_enter();
+
+    rt_uint32_t errtype;
+    can_handle_t *h_can;
+
+    h_can = &can.CanHandle;
+    errtype = h_can->perh->ERRSTAT;
+
+    switch ((errtype & 0x70) >> 4)
+    {
+    case RT_CAN_BUS_BIT_PAD_ERR:
+        can.device.status.bitpaderrcnt++;
+        break;
+    case RT_CAN_BUS_FORMAT_ERR:
+        can.device.status.formaterrcnt++;
+        break;
+    case RT_CAN_BUS_ACK_ERR:/* attention !!! test ack err's unit is transmit unit */
+        can.device.status.ackerrcnt++;
+        if (!READ_BIT(can.CanHandle.perh->TXSTAT, CAN_FLAG_M0TXC))
+            rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 0 << 8);
+        else if (!READ_BIT(can.CanHandle.perh->TXSTAT, CAN_FLAG_M0TXC))
+            rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 1 << 8);
+        else if (!READ_BIT(can.CanHandle.perh->TXSTAT, CAN_FLAG_M0TXC))
+            rt_hw_can_isr(&can.device, RT_CAN_EVENT_TX_FAIL | 2 << 8);
+        break;
+    case RT_CAN_BUS_IMPLICIT_BIT_ERR:
+    case RT_CAN_BUS_EXPLICIT_BIT_ERR:
+        can.device.status.biterrcnt++;
+        break;
+    case RT_CAN_BUS_CRC_ERR:
+        can.device.status.crcerrcnt++;
+        break;
+    }
+
+    can.device.status.lasterrtype = errtype & 0x70;
+    can.device.status.rcverrcnt = errtype >> 24;
+    can.device.status.snderrcnt = (errtype >> 16 & 0xFF);
+    can.device.status.errcode = errtype & 0x07;
+    h_can->perh->IFC |= CAN_IFC_ERRIFC_MSK;
+
+    rt_interrupt_leave();
+}
+
+int rt_hw_can_init(void)
+{
+    gpio_init_t h_gpio;
+    struct can_configure config = CANDEFAULTCONFIG;
+
+    config.privmode = RT_CAN_MODE_NOPRIV;
+    config.ticks = 50;
+#ifdef RT_CAN_USING_HDR
+    config.maxhdr = 14;
+#endif
+
+    /* Initialize can common pin */
+    h_gpio.odos = GPIO_PUSH_PULL;
+    h_gpio.pupd = GPIO_PUSH_UP;
+    h_gpio.podrv = GPIO_OUT_DRIVE_1;
+    h_gpio.nodrv = GPIO_OUT_DRIVE_0_1;
+    h_gpio.flt  = GPIO_FILTER_DISABLE;
+    h_gpio.type = GPIO_TYPE_TTL;
+    h_gpio.func = GPIO_FUNC_3;
+
+    /* Initialize can rx pin */
+    h_gpio.mode = GPIO_MODE_INPUT;
+    ald_gpio_init(GPIOB, GPIO_PIN_8, &h_gpio);
+
+    /* Initialize can tx pin */
+    h_gpio.mode = GPIO_MODE_OUTPUT;
+    ald_gpio_init(GPIOB, GPIO_PIN_9, &h_gpio);
+
+    /* config default filter */
+    can_filter_t filter = {0};
+    filter.id_high = 0x0000;
+    filter.id_low = 0x0000;
+    filter.mask_id_high = 0x0000;
+    filter.mask_id_low = 0x0000;
+    filter.fifo = CAN_FILTER_FIFO0;
+    filter.number = 0;
+    filter.mode = CAN_FILTER_MODE_MASK;
+    filter.scale = CAN_FILTER_SCALE_32;
+    filter.active = ENABLE;
+    filter.bank_number = 14;
+
+    can.FilterConfig = filter;
+    can.device.config = config;
+    /* register CAN1 device */
+    rt_hw_can_register(&can.device, "can", &_can_ops, &can);
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_can_init);
+
+#endif /* BSP_USING_CAN */

bsp/essemi/es32f369x/drivers/drv_can.h

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ */
+
+#ifndef DRV_CAN_H__
+#define DRV_CAN_H__
+
+#include <board.h>
+#include <rtdevice.h>
+#include <rtthread.h>
+
+#include <ald_can.h>
+#include <ald_gpio.h>
+
+struct es32f3_baud_rate_tab
+{
+    rt_uint32_t baud_rate;
+    rt_uint32_t config_data;
+};
+
+/* es32f3 can device */
+struct es32f3_can
+{
+    can_handle_t CanHandle;
+    can_filter_t FilterConfig;
+    struct rt_can_device device;     /* inherit from can device */
+};
+
+int rt_hw_can_init(void);
+
+#endif /*DRV_CAN_H__ */

bsp/essemi/es32f369x/drivers/drv_gpio.c

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ */
+
+#include <rthw.h>
+#include <rtdevice.h>
+#include "board.h"
+#include "drv_gpio.h"
+#include <ald_cmu.h>
+#include <ald_gpio.h>
+
+#ifdef RT_USING_PIN
+
+#define __ES32F0_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_PIN_##gpio_index}
+#define __ES32F0_PIN_DEFAULT {-1, 0, 0}
+
+/* ES32F0 GPIO driver */
+struct pin_index
+{
+    int index;
+    GPIO_TypeDef *gpio;
+    uint32_t pin;
+};
+
+static const struct pin_index pins[] =
+{
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN(2, C, 13),
+    __ES32F0_PIN(3, C, 14),
+    __ES32F0_PIN(4, C, 15),
+    __ES32F0_PIN(5, H, 0),
+    __ES32F0_PIN(6, H, 1),
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN(8, C, 0),
+    __ES32F0_PIN(9, C, 1),
+    __ES32F0_PIN(10, C, 2),
+    __ES32F0_PIN(11, C, 3),
+    __ES32F0_PIN(12, H, 3),
+    __ES32F0_PIN(13, H, 4),
+    __ES32F0_PIN(14, A, 0),
+    __ES32F0_PIN(15, A, 1),
+    __ES32F0_PIN(16, A, 2),
+    __ES32F0_PIN(17, A, 3),
+    __ES32F0_PIN(18, F, 0),
+    __ES32F0_PIN(19, F, 1),
+    __ES32F0_PIN(20, A, 4),
+    __ES32F0_PIN(21, A, 5),
+    __ES32F0_PIN(22, A, 6),
+    __ES32F0_PIN(23, A, 7),
+    __ES32F0_PIN(24, C, 4),
+    __ES32F0_PIN(25, C, 5),
+    __ES32F0_PIN(26, B, 0),
+    __ES32F0_PIN(27, B, 1),
+    __ES32F0_PIN(28, B, 2),
+    __ES32F0_PIN(29, B, 10),
+    __ES32F0_PIN(30, B, 11),
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN(33, B, 12),
+    __ES32F0_PIN(34, B, 13),
+    __ES32F0_PIN(35, B, 14),
+    __ES32F0_PIN(36, B, 15),
+    __ES32F0_PIN(37, C, 6),
+    __ES32F0_PIN(38, C, 7),
+    __ES32F0_PIN(39, C, 8),
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN(46, A, 13),
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN(49, A, 14),
+    __ES32F0_PIN(50, A, 15),
+    __ES32F0_PIN(51, C, 10),
+    __ES32F0_PIN(52, C, 11),
+    __ES32F0_PIN(53, C, 12),
+    __ES32F0_PIN(54, D, 2),
+    __ES32F0_PIN(55, B, 3),
+    __ES32F0_PIN(56, B, 4),
+    __ES32F0_PIN(57, B, 5),
+    __ES32F0_PIN(58, B, 6),
+    __ES32F0_PIN(59, B, 7),
+    __ES32F0_PIN(60, H, 2),
+    __ES32F0_PIN(61, B, 8),
+    __ES32F0_PIN(62, B, 9),
+    __ES32F0_PIN_DEFAULT,
+    __ES32F0_PIN_DEFAULT,
+};
+
+struct pin_irq_map
+{
+    rt_uint16_t pinbit;
+    IRQn_Type irqno;
+};
+static const struct pin_irq_map pin_irq_map[] =
+{
+    {GPIO_PIN_0, EXTI0_IRQn},
+    {GPIO_PIN_1, EXTI1_IRQn},
+    {GPIO_PIN_2, EXTI2_IRQn},
+    {GPIO_PIN_3, EXTI3_IRQn},
+    {GPIO_PIN_4, EXTI4_IRQn},
+    {GPIO_PIN_5, EXTI5_IRQn},
+    {GPIO_PIN_6, EXTI6_IRQn},
+    {GPIO_PIN_7, EXTI7_IRQn},
+    {GPIO_PIN_8, EXTI8_IRQn},
+    {GPIO_PIN_9, EXTI9_IRQn},
+    {GPIO_PIN_10, EXTI10_IRQn},
+    {GPIO_PIN_11, EXTI11_IRQn},
+    {GPIO_PIN_12, EXTI12_IRQn},
+    {GPIO_PIN_13, EXTI13_IRQn},
+    {GPIO_PIN_14, EXTI14_IRQn},
+    {GPIO_PIN_15, EXTI15_IRQn},
+};
+
+struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
+{
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+};
+
+#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
+const struct pin_index *get_pin(uint8_t pin)
+{
+    const struct pin_index *index;
+    if (pin < ITEM_NUM(pins))
+    {
+        index = &pins[pin];
+        if (index->index == -1)
+            index = RT_NULL;
+    }
+    else
+    {
+        index = RT_NULL;
+    }
+    return index;
+};
+
+void es32f3_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    const struct pin_index *index;
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+    ald_gpio_write_pin(index->gpio, index->pin, value);
+}
+
+int es32f3_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    int value;
+    const struct pin_index *index;
+    value = PIN_LOW;
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return value;
+    }
+    value = ald_gpio_read_pin(index->gpio, index->pin);
+    return value;
+}
+
+void es32f3_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    const struct pin_index *index;
+    gpio_init_t gpio_initstruct;
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+
+    /* Configure GPIO_InitStructure */
+    gpio_initstruct.mode = GPIO_MODE_OUTPUT;
+    gpio_initstruct.func = GPIO_FUNC_1;
+    gpio_initstruct.podrv = GPIO_OUT_DRIVE_1;
+    gpio_initstruct.nodrv = GPIO_OUT_DRIVE_0_1;
+    gpio_initstruct.type = GPIO_TYPE_CMOS;
+    gpio_initstruct.pupd = GPIO_FLOATING;
+    gpio_initstruct.odos = GPIO_PUSH_PULL;
+
+    if (mode == PIN_MODE_OUTPUT)
+    {
+        /* output setting */
+        gpio_initstruct.mode = GPIO_MODE_OUTPUT;
+        gpio_initstruct.pupd = GPIO_FLOATING;
+    }
+    else if (mode == PIN_MODE_INPUT)
+    {
+        /* input setting: not pull. */
+        gpio_initstruct.mode = GPIO_MODE_INPUT;
+        gpio_initstruct.pupd = GPIO_FLOATING;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLUP)
+    {
+        /* input setting: pull up. */
+        gpio_initstruct.mode = GPIO_MODE_INPUT;
+        gpio_initstruct.pupd = GPIO_PUSH_UP;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLDOWN)
+    {
+        /* input setting: pull down. */
+        gpio_initstruct.mode = GPIO_MODE_INPUT;
+        gpio_initstruct.pupd = GPIO_PUSH_DOWN;
+    }
+    else if (mode == PIN_MODE_OUTPUT_OD)
+    {
+        /* output setting: od. */
+        gpio_initstruct.mode = GPIO_MODE_OUTPUT;
+        gpio_initstruct.pupd = GPIO_FLOATING;
+        gpio_initstruct.odos = GPIO_OPEN_DRAIN;
+    }
+    ald_gpio_init(index->gpio, index->pin, &gpio_initstruct);
+}
+
+rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin)
+{
+    rt_int32_t mapindex = gpio_pin & 0x00FF;
+    if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_NULL;
+    }
+    return &pin_irq_map[mapindex];
+};
+
+rt_err_t es32f3_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                               rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex;
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+    /* pin no. convert to dec no. */
+    for (irqindex = 0; irqindex < 16; irqindex++)
+    {
+        if ((0x01 << irqindex) == index->pin)
+        {
+            break;
+        }
+    }
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_ENOSYS;
+    }
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == pin &&
+            pin_irq_hdr_tab[irqindex].hdr == hdr &&
+            pin_irq_hdr_tab[irqindex].mode == mode &&
+            pin_irq_hdr_tab[irqindex].args == args)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    if (pin_irq_hdr_tab[irqindex].pin != -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EBUSY;
+    }
+    pin_irq_hdr_tab[irqindex].pin = pin;
+    pin_irq_hdr_tab[irqindex].hdr = hdr;
+    pin_irq_hdr_tab[irqindex].mode = mode;
+    pin_irq_hdr_tab[irqindex].args = args;
+    rt_hw_interrupt_enable(level);
+    return RT_EOK;
+}
+
+rt_err_t es32f3_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+    irqindex = index->pin & 0x00FF;
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_ENOSYS;
+    }
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    pin_irq_hdr_tab[irqindex].pin = -1;
+    pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
+    pin_irq_hdr_tab[irqindex].mode = 0;
+    pin_irq_hdr_tab[irqindex].args = RT_NULL;
+    rt_hw_interrupt_enable(level);
+    return RT_EOK;
+}
+
+rt_err_t es32f3_pin_irq_enable(struct rt_device *device, rt_base_t pin,
+                               rt_uint32_t enabled)
+{
+    const struct pin_index *index;
+    const struct pin_irq_map *irqmap;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+    /* Configure GPIO_InitStructure & EXTI_InitStructure */
+    gpio_init_t gpio_initstruct;
+    exti_init_t exti_initstruct;
+    exti_initstruct.filter = DISABLE;
+    exti_initstruct.cks = EXTI_FILTER_CLOCK_10K;
+    exti_initstruct.filter_time = 0x0;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+    if (enabled == PIN_IRQ_ENABLE)
+    {
+        /* pin no. convert to dec no. */
+        for (irqindex = 0; irqindex < 16; irqindex++)
+        {
+            if ((0x01 << irqindex) == index->pin)
+            {
+                break;
+            }
+        }
+        if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+        {
+            return RT_ENOSYS;
+        }
+        level = rt_hw_interrupt_disable();
+        if (pin_irq_hdr_tab[irqindex].pin == -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return RT_ENOSYS;
+        }
+        irqmap = &pin_irq_map[irqindex];
+        ald_gpio_exti_init(index->gpio, index->pin, &exti_initstruct);
+        /* Configure GPIO_InitStructure */
+        gpio_initstruct.mode = GPIO_MODE_INPUT;
+        gpio_initstruct.func = GPIO_FUNC_1;
+        switch (pin_irq_hdr_tab[irqindex].mode)
+        {
+        case PIN_IRQ_MODE_RISING:
+            gpio_initstruct.pupd = GPIO_PUSH_DOWN;
+            ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_RISING_EDGE, ENABLE);
+            break;
+        case PIN_IRQ_MODE_FALLING:
+            gpio_initstruct.pupd = GPIO_PUSH_UP;
+            ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_TRAILING_EDGE, ENABLE);
+            break;
+        case PIN_IRQ_MODE_RISING_FALLING:
+            gpio_initstruct.pupd = GPIO_FLOATING;
+            ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_BOTH_EDGE, ENABLE);
+            break;
+        }
+        ald_gpio_init(index->gpio, index->pin, &gpio_initstruct);
+        NVIC_EnableIRQ(irqmap->irqno);
+        rt_hw_interrupt_enable(level);
+    }
+    else if (enabled == PIN_IRQ_DISABLE)
+    {
+        irqmap = get_pin_irq_map(index->pin);
+        if (irqmap == RT_NULL)
+        {
+            return RT_ENOSYS;
+        }
+        NVIC_DisableIRQ(irqmap->irqno);
+    }
+    else
+    {
+        return RT_ENOSYS;
+    }
+    return RT_EOK;
+}
+
+const static struct rt_pin_ops _es32f3_pin_ops =
+{
+    es32f3_pin_mode,
+    es32f3_pin_write,
+    es32f3_pin_read,
+    es32f3_pin_attach_irq,
+    es32f3_pin_detach_irq,
+    es32f3_pin_irq_enable,
+};
+
+int rt_hw_pin_init(void)
+{
+    int result;
+    ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE);
+    result = rt_device_pin_register("pin", &_es32f3_pin_ops, RT_NULL);
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_pin_init);
+
+rt_inline void pin_irq_hdr(uint16_t GPIO_Pin)
+{
+    uint16_t irqno;
+    /* pin no. convert to dec no. */
+    for (irqno = 0; irqno < 16; irqno++)
+    {
+        if ((0x01 << irqno) == GPIO_Pin)
+        {
+            break;
+        }
+    }
+    if (irqno == 16)
+        return;
+    if (pin_irq_hdr_tab[irqno].hdr)
+    {
+        pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
+    }
+}
+
+void GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+    if (ald_gpio_exti_get_flag_status(GPIO_Pin) != RESET)
+    {
+        ald_gpio_exti_clear_flag_status(GPIO_Pin);
+        pin_irq_hdr(GPIO_Pin);
+    }
+}
+
+void EXTI0_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_Callback(GPIO_PIN_0);
+    rt_interrupt_leave();
+}
+
+void EXTI1_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_Callback(GPIO_PIN_1);
+    rt_interrupt_leave();
+}
+
+void EXTI2_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_Callback(GPIO_PIN_2);
+    rt_interrupt_leave();
+}
+
+void EXTI3_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_Callback(GPIO_PIN_3);
+    rt_interrupt_leave();
+}
+
+void EXTI4_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_Callback(GPIO_PIN_4);
+    rt_interrupt_leave();
+}
+
+void EXTI5_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_Callback(GPIO_PIN_5);
+    rt_interrupt_leave();
+}
+
+void EXTI6_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_Callback(GPIO_PIN_6);
+    rt_interrupt_leave();
+}
+
+void EXTI7_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_Callback(GPIO_PIN_7);
+    rt_interrupt_leave();
+}
+
+void EXTI8_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_Callback(GPIO_PIN_8);
+    rt_interrupt_leave();
+}
+
+void EXTI9_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_Callback(GPIO_PIN_9);
+    rt_interrupt_leave();
+}
+
+void EXTI10_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_Callback(GPIO_PIN_10);
+    rt_interrupt_leave();
+}
+
+void EXTI11_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_Callback(GPIO_PIN_11);
+    rt_interrupt_leave();
+}
+
+void EXTI12_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_Callback(GPIO_PIN_12);
+    rt_interrupt_leave();
+}
+
+void EXTI13_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_Callback(GPIO_PIN_13);
+    rt_interrupt_leave();
+}
+
+void EXTI14_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_Callback(GPIO_PIN_14);
+    rt_interrupt_leave();
+}
+
+void EXTI15_Handler(void)
+{
+    rt_interrupt_enter();
+    GPIO_EXTI_Callback(GPIO_PIN_15);
+    rt_interrupt_leave();
+}
+
+#endif

bsp/essemi/es32f369x/drivers/drv_gpio.h

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ */
+
+#ifndef DRV_GPIO_H__
+#define DRV_GPIO_H__
+
+int rt_hw_pin_init(void);
+
+#endif

bsp/essemi/es32f369x/drivers/drv_i2c.c

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ * 2019-11-01     wangyq        update libraries
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+#include "drv_i2c.h"
+#include <ald_i2c.h>
+#include <ald_gpio.h>
+
+#ifdef RT_USING_I2C
+
+#define TIMEOUT 0x0FFF
+
+/* I2C struct definition */
+#ifdef BSP_USING_I2C0
+    static i2c_handle_t _h_i2c0;
+#endif
+
+#ifdef BSP_USING_I2C1
+    static i2c_handle_t _h_i2c1;
+#endif
+
+static void _i2c_init(void)
+{
+    gpio_init_t gpio_instruct;
+
+    /* Initialize I2C Pin */
+    gpio_instruct.mode = GPIO_MODE_OUTPUT;
+    gpio_instruct.odos = GPIO_PUSH_PULL;
+    gpio_instruct.pupd = GPIO_PUSH_UP;
+    gpio_instruct.podrv = GPIO_OUT_DRIVE_1;
+    gpio_instruct.nodrv = GPIO_OUT_DRIVE_0_1;
+    gpio_instruct.flt  = GPIO_FILTER_DISABLE;
+    gpio_instruct.type = GPIO_TYPE_CMOS;
+    gpio_instruct.func = GPIO_FUNC_5;
+
+#ifdef BSP_USING_I2C0
+    /* Initialize I2C Function */
+    _h_i2c0.perh = I2C0;
+    _h_i2c0.init.clk_speed    = 100000;
+    _h_i2c0.init.own_addr1    = 0x0A;
+    _h_i2c0.init.addr_mode    = I2C_ADDR_7BIT;
+    _h_i2c0.init.general_call = I2C_GENERALCALL_DISABLE;
+    _h_i2c0.init.no_stretch   = I2C_NOSTRETCH_ENABLE;
+
+    ald_i2c_reset(&_h_i2c0);
+    ald_i2c_init(&_h_i2c0);
+    /* PB8->I2C0_SCL, PB9->I2C0_SDA */
+    ald_gpio_init(GPIOB, GPIO_PIN_8 | GPIO_PIN_9, &gpio_instruct);
+#endif
+
+#ifdef BSP_USING_I2C1
+    /* Initialize i2c function */
+    _h_i2c1.perh = I2C1;
+    _h_i2c1.init.clk_speed    = 100000;
+    _h_i2c1.init.own_addr1    = 0xA0;
+    _h_i2c1.init.addr_mode    = I2C_ADDR_7BIT;
+    _h_i2c1.init.general_call = I2C_GENERALCALL_DISABLE;
+    _h_i2c1.init.no_stretch   = I2C_NOSTRETCH_ENABLE;
+
+    ald_i2c_reset(&_h_i2c1);
+    ald_i2c_init(&_h_i2c1);
+    /* PA05->I2C1_SCL, PA06->I2C1_SDA */
+    ald_gpio_init(GPIOA, GPIO_PIN_5 | GPIO_PIN_6, &gpio_instruct);
+#endif
+}
+
+static rt_size_t es32f3_master_xfer(struct rt_i2c_bus_device *bus,
+                                    struct rt_i2c_msg msgs[],
+                                    rt_uint32_t num)
+{
+    struct rt_i2c_msg *msg;
+    rt_uint32_t i;
+    rt_err_t ret = RT_ERROR;
+
+    for (i = 0; i < num; i++)
+    {
+        msg = &msgs[i];
+        if (msg->flags & RT_I2C_RD)
+        {
+            if (ald_i2c_master_recv(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0)
+            {
+                i2c_dbg("i2c bus write failed,i2c bus stop!\n");
+                goto out;
+            }
+        }
+        else
+        {
+            if (ald_i2c_master_send(bus->priv, msg->addr << 1, msg->buf, msg->len, TIMEOUT) != 0)
+            {
+                i2c_dbg("i2c bus write failed,i2c bus stop!\n");
+                goto out;
+            }
+        }
+    }
+
+    ret = i;
+
+out:
+    i2c_dbg("send stop condition\n");
+
+    return ret;
+}
+
+const struct rt_i2c_bus_device_ops es32f3_i2c_ops =
+{
+    es32f3_master_xfer,
+    RT_NULL,
+    RT_NULL,
+};
+
+int rt_hw_i2c_init(void)
+{
+    int result = RT_EOK;
+
+    _i2c_init();
+
+#ifdef BSP_USING_I2C0
+    /* define i2c Instance */
+    static struct rt_i2c_bus_device _i2c_device0;
+    rt_memset((void *)&_i2c_device0, 0, sizeof(struct rt_i2c_bus_device));
+
+    _i2c_device0.ops = &es32f3_i2c_ops;
+    _i2c_device0.priv = &_h_i2c0;
+    result = rt_i2c_bus_device_register(&_i2c_device0, "i2c0");
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+#endif
+
+#ifdef BSP_USING_I2C1
+    /* define i2c Instance */
+    static struct rt_i2c_bus_device _i2c_device1;
+    rt_memset((void *)&_i2c_device1, 0, sizeof(struct rt_i2c_bus_device));
+
+    _i2c_device1.ops = &es32f3_i2c_ops;
+    _i2c_device1.priv = &_h_i2c1;
+    rt_i2c_bus_device_register(&_i2c_device1, "i2c1");
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+#endif
+
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rt_hw_i2c_init);
+
+#endif

bsp/essemi/es32f369x/drivers/drv_i2c.h

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ */
+
+#ifndef DRV_I2C_H__
+#define DRV_I2C_H__
+
+int rt_hw_i2c_init(void);
+
+#endif

bsp/essemi/es32f369x/drivers/drv_spi.c

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ * 2019-11-01     wangyq        update libraries
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <string.h>
+#include <rthw.h>
+#include "board.h"
+#include "drv_spi.h"
+#include <ald_spi.h>
+#include <ald_gpio.h>
+#include <ald_cmu.h>
+
+#ifdef RT_USING_SPI
+
+#define SPITIMEOUT 0xFFFF
+
+rt_err_t spi_configure(struct rt_spi_device *device,
+                       struct rt_spi_configuration *cfg)
+{
+    spi_handle_t *hspi;
+    hspi = (spi_handle_t *)device->bus->parent.user_data;
+
+    /* config spi mode */
+    if (cfg->mode & RT_SPI_SLAVE)
+    {
+        hspi->init.mode = SPI_MODE_SLAVER;
+    }
+    else
+    {
+        hspi->init.mode = SPI_MODE_MASTER;
+    }
+    if (cfg->mode & RT_SPI_3WIRE)
+    {
+        hspi->init.dir = SPI_DIRECTION_1LINE;
+    }
+    else
+    {
+        hspi->init.dir = SPI_DIRECTION_2LINES;
+    }
+    if (cfg->data_width == 8)
+    {
+        hspi->init.data_size = SPI_DATA_SIZE_8;
+    }
+    else if (cfg->data_width == 16)
+    {
+        hspi->init.data_size = SPI_DATA_SIZE_16;
+    }
+
+    if (cfg->mode & RT_SPI_CPHA)
+    {
+        hspi->init.phase = SPI_CPHA_SECOND;
+    }
+    else
+    {
+        hspi->init.phase = SPI_CPHA_FIRST;
+    }
+    if (cfg->mode & RT_SPI_CPOL)
+    {
+        hspi->init.polarity = SPI_CPOL_HIGH;
+    }
+    else
+    {
+        hspi->init.polarity = SPI_CPOL_LOW;
+    }
+    if (cfg->mode & RT_SPI_NO_CS)
+    {
+        hspi->init.ss_en = DISABLE;
+    }
+    else
+    {
+        hspi->init.ss_en = ENABLE;
+    }
+
+    /* config spi clock */
+    if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 2)
+    {
+        /* pclk1 max speed 48MHz, spi master max speed 10MHz */
+        if (ald_cmu_get_pclk1_clock() / 2 <= 10000000)
+        {
+            hspi->init.baud = SPI_BAUD_2;
+        }
+        else if (ald_cmu_get_pclk1_clock() / 4 <= 10000000)
+        {
+            hspi->init.baud = SPI_BAUD_4;
+        }
+        else
+        {
+            hspi->init.baud = SPI_BAUD_8;
+        }
+    }
+    else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 4)
+    {
+        /* pclk1 max speed 48MHz, spi master max speed 10MHz */
+        if (ald_cmu_get_pclk1_clock() / 4 <= 10000000)
+        {
+            hspi->init.baud = SPI_BAUD_4;
+        }
+        else
+        {
+            hspi->init.baud = SPI_BAUD_8;
+        }
+    }
+    else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 8)
+    {
+        hspi->init.baud = SPI_BAUD_8;
+    }
+    else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 16)
+    {
+        hspi->init.baud = SPI_BAUD_16;
+    }
+    else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 32)
+    {
+        hspi->init.baud = SPI_BAUD_32;
+    }
+    else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 64)
+    {
+        hspi->init.baud = SPI_BAUD_64;
+    }
+    else if (cfg->max_hz >= ald_cmu_get_pclk1_clock() / 128)
+    {
+        hspi->init.baud = SPI_BAUD_128;
+    }
+    else
+    {
+        hspi->init.baud = SPI_BAUD_256;
+    }
+    hspi->init.ss_en    = DISABLE;
+    hspi->init.crc_calc = DISABLE;
+    ald_spi_init(hspi);
+    return RT_EOK;
+}
+
+static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
+{
+    rt_err_t res;
+    spi_handle_t *hspi;
+    struct es32f3_hw_spi_cs *cs;
+
+    RT_ASSERT(device != RT_NULL);
+    RT_ASSERT(device->bus != RT_NULL);
+    RT_ASSERT(device->bus->parent.user_data != RT_NULL);
+    RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL);
+
+    hspi = (spi_handle_t *)device->bus->parent.user_data;
+    cs = device->parent.user_data;
+
+    /* send & receive */
+    if ((message->send_buf != RT_NULL) && (message->recv_buf != RT_NULL))
+    {
+        if (message->cs_take)
+        {
+            rt_pin_write(cs->pin, 0);
+        }
+        res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf,
+                                (rt_int32_t)message->length, SPITIMEOUT);
+        if (message->cs_release)
+        {
+            rt_pin_write(cs->pin, 1);
+        }
+        if (res != RT_EOK)
+            return RT_ERROR;
+    }
+    else
+    {
+        /* only send data */
+        if (message->recv_buf == RT_NULL)
+        {
+            if (message->cs_take)
+            {
+                rt_pin_write(cs->pin, 0);
+            }
+            res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT);
+            if (message->cs_release)
+            {
+                rt_pin_write(cs->pin, 1);
+            }
+            if (res != RT_EOK)
+                return RT_ERROR;
+        }
+        /* only receive data */
+        if (message->send_buf == RT_NULL)
+        {
+            if (message->cs_take)
+            {
+                rt_pin_write(cs->pin, 0);
+            }
+            res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT);
+            if (message->cs_release)
+            {
+                rt_pin_write(cs->pin, 1);
+            }
+            if (res != RT_EOK)
+                return RT_ERROR;
+        }
+    }
+
+    return message->length;
+}
+
+const struct rt_spi_ops es32f3_spi_ops =
+{
+    spi_configure,
+    spixfer,
+};
+
+rt_err_t es32f3_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name)
+{
+    /* define spi Instance */
+    struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
+    RT_ASSERT(spi_device != RT_NULL);
+    struct es32f3_hw_spi_cs *cs_pin = (struct es32f3_hw_spi_cs *)rt_malloc(sizeof(struct es32f3_hw_spi_cs));
+    RT_ASSERT(cs_pin != RT_NULL);
+    cs_pin->pin = pin;
+    rt_pin_mode(pin, PIN_MODE_OUTPUT);
+    rt_pin_write(pin, 1);
+    return rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
+}
+
+#ifdef BSP_USING_SPI0
+    static struct rt_spi_bus _spi_bus0;
+    static spi_handle_t _spi0;
+#endif
+
+#ifdef BSP_USING_SPI1
+    static struct rt_spi_bus _spi_bus1;
+    static spi_handle_t _spi1;
+#endif
+
+#ifdef BSP_USING_SPI2
+    static struct rt_spi_bus _spi_bus2;
+    static spi_handle_t _spi2;
+#endif
+
+int rt_hw_spi_init(void)
+{
+    int result = RT_EOK;
+
+    struct rt_spi_bus *spi_bus;
+    spi_handle_t *spi;
+    gpio_init_t gpio_instruct;
+
+#ifdef BSP_USING_SPI0
+    _spi0.perh = SPI0;
+    spi_bus = &_spi_bus0;
+    spi = &_spi0;
+
+    /* SPI0 gpio init */
+    gpio_instruct.mode = GPIO_MODE_OUTPUT;
+    gpio_instruct.odos = GPIO_PUSH_PULL;
+    gpio_instruct.podrv = GPIO_OUT_DRIVE_1;
+    gpio_instruct.nodrv = GPIO_OUT_DRIVE_1;
+    gpio_instruct.func = GPIO_FUNC_4;
+    gpio_instruct.type = GPIO_TYPE_TTL;
+    gpio_instruct.flt  = GPIO_FILTER_DISABLE;
+
+    /* PB3->SPI0_SCK, PB5->SPI0_MOSI */
+    ald_gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct);
+
+    /* PB4->SPI0_MISO */
+    gpio_instruct.mode = GPIO_MODE_INPUT;
+    ald_gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct);
+
+    spi_bus->parent.user_data = spi;
+    result = rt_spi_bus_register(spi_bus, "spi0", &es32f3_spi_ops);
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+#endif
+
+#ifdef BSP_USING_SPI1
+    _spi1.perh = SPI1;
+    spi_bus = &_spi_bus1;
+    spi = &_spi1;
+
+    /* SPI1 gpio init */
+    gpio_instruct.mode = GPIO_MODE_OUTPUT;
+    gpio_instruct.odos = GPIO_PUSH_PULL;
+    gpio_instruct.podrv = GPIO_OUT_DRIVE_1;
+    gpio_instruct.nodrv = GPIO_OUT_DRIVE_1;
+    gpio_instruct.func = GPIO_FUNC_4;
+    gpio_instruct.type = GPIO_TYPE_TTL;
+    gpio_instruct.flt  = GPIO_FILTER_DISABLE;
+
+    /* PC01->SPI1_SCK, PC03->SPI1_MOSI */
+    ald_gpio_init(GPIOC, GPIO_PIN_1 | GPIO_PIN_3, &gpio_instruct);
+
+    /* PC02->SPI1_MISO */
+    gpio_instruct.mode = GPIO_MODE_INPUT;
+    ald_gpio_init(GPIOC, GPIO_PIN_2, &gpio_instruct);
+
+    spi_bus->parent.user_data = spi;
+    result = rt_spi_bus_register(spi_bus, "spi1", &es32f3_spi_ops);
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+#endif
+
+#ifdef BSP_USING_SPI2
+    _spi1.perh = SPI2;
+    spi_bus = &_spi_bus2;
+    spi = &_spi2;
+
+    /* SPI2 gpio init */
+    gpio_instruct.mode = GPIO_MODE_OUTPUT;
+    gpio_instruct.odos = GPIO_PUSH_PULL;
+    gpio_instruct.podrv = GPIO_OUT_DRIVE_1;
+    gpio_instruct.nodrv = GPIO_OUT_DRIVE_1;
+    gpio_instruct.func = GPIO_FUNC_5;
+    gpio_instruct.type = GPIO_TYPE_TTL;
+    gpio_instruct.flt  = GPIO_FILTER_DISABLE;
+
+    /* PC05->SPI1_SCK, PB01->SPI1_MOSI */
+    ald_gpio_init(GPIOC, GPIO_PIN_5 | GPIO_PIN_1, &gpio_instruct);
+
+    /* PB00->SPI1_MISO */
+    gpio_instruct.mode = GPIO_MODE_INPUT;
+    ald_gpio_init(GPIOB, GPIO_PIN_0, &gpio_instruct);
+
+    spi_bus->parent.user_data = spi;
+    result = rt_spi_bus_register(spi_bus, "spi2", &es32f3_spi_ops);
+    if (result != RT_EOK)
+    {
+        return result;
+    }
+#endif
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_spi_init);
+
+#endif

bsp/essemi/es32f369x/drivers/drv_spi.h

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ */
+
+#ifndef DRV_SPI_H__
+#define DRV_SPI_H__
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <rtdevice.h>
+
+struct es32f3_hw_spi_cs
+{
+    rt_uint32_t pin;
+};
+
+/* cannot be used before completion init */
+rt_err_t es32f3_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name);
+int rt_hw_spi_init(void);
+
+#endif

bsp/essemi/es32f369x/drivers/drv_uart.c

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+#include "drv_uart.h"
+#include <ald_gpio.h>
+#include <ald_uart.h>
+#include <ald_cmu.h>
+
+#ifdef RT_USING_SERIAL
+
+/* es32 uart driver */
+struct es32_uart
+{
+    uart_handle_t huart;
+    IRQn_Type irq;
+};
+
+static rt_err_t es32f3x_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    gpio_init_t gpio_initstructure;
+    struct es32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+    uart = (struct es32_uart *)serial->parent.user_data;
+
+    /* Initialize tx pin */
+    gpio_initstructure.mode = GPIO_MODE_OUTPUT;
+    gpio_initstructure.odos = GPIO_PUSH_PULL;
+    gpio_initstructure.pupd = GPIO_PUSH_UP;
+    gpio_initstructure.podrv = GPIO_OUT_DRIVE_1;
+    gpio_initstructure.nodrv = GPIO_OUT_DRIVE_0_1;
+    gpio_initstructure.flt  = GPIO_FILTER_DISABLE;
+    gpio_initstructure.type = GPIO_TYPE_TTL;
+
+#ifdef BSP_USING_UART0
+    gpio_initstructure.func = GPIO_FUNC_3;
+    ald_gpio_init(GPIOB, GPIO_PIN_10, &gpio_initstructure);
+
+    /* Initialize rx pin ,the same as txpin except mode */
+    gpio_initstructure.mode = GPIO_MODE_INPUT;
+    ald_gpio_init(GPIOB, GPIO_PIN_11, &gpio_initstructure);
+
+    ald_cmu_perh_clock_config(CMU_PERH_UART0, ENABLE);
+#endif /* uart0 gpio init */
+
+#ifdef BSP_USING_UART1
+    gpio_initstructure.func = GPIO_FUNC_3;
+    ald_gpio_init(GPIOC, GPIO_PIN_10, &gpio_initstructure);
+
+    /* Initialize rx pin ,the same as txpin except mode */
+    gpio_initstructure.mode = GPIO_MODE_INPUT;
+    ald_gpio_init(GPIOC, GPIO_PIN_11, &gpio_initstructure);
+
+    ald_cmu_perh_clock_config(CMU_PERH_UART1, ENABLE);
+#endif /* uart1 gpio init */
+
+#ifdef BSP_USING_UART2
+    gpio_initstructure.func = GPIO_FUNC_5;
+    ald_gpio_init(GPIOC, GPIO_PIN_12, &gpio_initstructure);
+
+    /* Initialize rx pin ,the same as txpin except mode */
+    gpio_initstructure.mode = GPIO_MODE_INPUT;
+    ald_gpio_init(GPIOD, GPIO_PIN_2, &gpio_initstructure);
+
+    ald_cmu_perh_clock_config(CMU_PERH_UART2, ENABLE);
+#endif /* uart2 gpio init */
+
+#ifdef BSP_USING_UART3
+    gpio_initstructure.func = GPIO_FUNC_4;
+    ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstructure);
+
+    /* Initialize rx pin ,the same as txpin except mode */
+    gpio_initstructure.mode = GPIO_MODE_INPUT;
+    ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstructure);
+
+    ald_cmu_perh_clock_config(CMU_PERH_UART3, ENABLE);
+#endif /* uart3 gpio init */
+
+#ifdef BSP_USING_UART4
+    gpio_initstructure.func = GPIO_FUNC_3;
+    ald_gpio_init(GPIOB, GPIO_PIN_6, &gpio_initstructure);
+
+    /* Initialize rx pin ,the same as txpin except mode */
+    gpio_initstructure.mode = GPIO_MODE_INPUT;
+    ald_gpio_init(GPIOB, GPIO_PIN_7, &gpio_initstructure);
+
+    ald_cmu_perh_clock_config(CMU_PERH_UART4, ENABLE);
+#endif /* uart4 gpio init */
+
+#ifdef BSP_USING_UART5
+    gpio_initstructure.func = GPIO_FUNC_4;
+    ald_gpio_init(GPIOB, GPIO_PIN_9, &gpio_initstructure);
+
+    /* Initialize rx pin ,the same as txpin except mode */
+    gpio_initstructure.mode = GPIO_MODE_INPUT;
+    ald_gpio_init(GPIOB, GPIO_PIN_8, &gpio_initstructure);
+
+    ald_cmu_perh_clock_config(CMU_PERH_UART5, ENABLE);
+#endif /* uart5 gpio init */
+
+    ald_uart_tx_fifo_config(&uart->huart, UART_TXFIFO_EMPTY, 1);
+    ald_uart_rx_fifo_config(&uart->huart, UART_RXFIFO_1BYTE, 1);
+
+    uart->huart.init.mode        = UART_MODE_UART;
+    uart->huart.init.baud        = cfg->baud_rate;
+    uart->huart.init.word_length = (uart_word_length_t)(8 - cfg->data_bits);
+    uart->huart.init.parity = (uart_parity_t)(cfg->parity == PARITY_EVEN ? UART_PARITY_EVEN : cfg->parity);
+    uart->huart.init.fctl        = UART_HW_FLOW_CTL_DISABLE;
+    ald_uart_init(&uart->huart);
+
+    if (cfg->bit_order == BIT_ORDER_MSB)
+    {
+        UART_MSB_FIRST_ENABLE(&uart->huart);
+    }
+    else
+    {
+        UART_MSB_FIRST_DISABLE(&uart->huart);
+    }
+
+    if (cfg->invert == NRZ_INVERTED)
+    {
+        UART_DATA_INV_ENABLE(&uart->huart);
+    }
+    else
+    {
+        UART_DATA_INV_DISABLE(&uart->huart);
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t es32f3x_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct es32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = (struct es32_uart *)serial->parent.user_data;
+    switch (cmd)
+    {
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        NVIC_DisableIRQ(uart->irq);
+        /* disable interrupt */
+        ald_uart_interrupt_config(&uart->huart, UART_IT_RFTH, DISABLE);
+        break;
+
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        NVIC_EnableIRQ(uart->irq);
+        /* enable interrupt */
+        ald_uart_interrupt_config(&uart->huart, UART_IT_RFTH, ENABLE);
+        break;
+    }
+
+    return RT_EOK;
+}
+
+static int es32f3x_putc(struct rt_serial_device *serial, char c)
+{
+    struct es32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct es32_uart *)serial->parent.user_data;
+
+    while (ald_uart_get_status(&uart->huart, UART_STATUS_TFEMPTY) == RESET)
+        ;
+    WRITE_REG(uart->huart.perh->TXBUF, c);
+
+    return 1;
+}
+
+static int es32f3x_getc(struct rt_serial_device *serial)
+{
+    int ch = -1;
+    struct es32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct es32_uart *)serial->parent.user_data;
+
+    if (ald_uart_get_status(&uart->huart, UART_STATUS_RFTH))
+    {
+        ch = (uint8_t)(uart->huart.perh->RXBUF & 0xFF);
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops es32f3x_uart_ops =
+{
+    es32f3x_configure,
+    es32f3x_control,
+    es32f3x_putc,
+    es32f3x_getc,
+};
+
+#ifdef BSP_USING_UART0
+/* UART0 device driver structure */
+struct es32_uart uart0 =
+{
+    {UART0},
+    UART0_IRQn
+};
+
+struct rt_serial_device serial0;
+
+void UART0_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if ((ald_uart_get_mask_flag_status(&uart0.huart, UART_IF_RFTH)) != RESET)
+    {
+        ald_uart_clear_flag_status(&uart0.huart, UART_IF_RFTH);
+        rt_hw_serial_isr(&serial0, RT_SERIAL_EVENT_RX_IND);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART0 */
+
+#ifdef BSP_USING_UART1
+/* UART1 device driver structure */
+struct es32_uart uart1 =
+{
+    {UART1},
+    UART1_IRQn
+};
+
+struct rt_serial_device serial1;
+
+void UART1_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if ((ald_uart_get_mask_flag_status(&uart1.huart, UART_IF_RFTH)) != RESET)
+    {
+        ald_uart_clear_flag_status(&uart1.huart, UART_IF_RFTH);
+        rt_hw_serial_isr(&serial1, RT_SERIAL_EVENT_RX_IND);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART1 */
+
+#ifdef BSP_USING_UART2
+/* UART2 device driver structure */
+struct es32_uart uart2 =
+{
+    {UART2},
+    UART2_IRQn
+};
+
+struct rt_serial_device serial2;
+
+void UART2_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if ((ald_uart_get_mask_flag_status(&uart2.huart, UART_IF_RFTH)) != RESET)
+    {
+        ald_uart_clear_flag_status(&uart2.huart, UART_IF_RFTH);
+        rt_hw_serial_isr(&serial2, RT_SERIAL_EVENT_RX_IND);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART2 */
+
+#ifdef BSP_USING_UART3
+/* UART3 device driver structure */
+struct es32_uart uart3 =
+{
+    {UART3},
+    UART3_IRQn
+};
+
+struct rt_serial_device serial3;
+
+void UART3_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if ((ald_uart_get_mask_flag_status(&uart3.huart, UART_IF_RFTH)) != RESET)
+    {
+        ald_uart_clear_flag_status(&uart3.huart, UART_IF_RFTH);
+        rt_hw_serial_isr(&serial3, RT_SERIAL_EVENT_RX_IND);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART3 */
+
+#ifdef BSP_USING_UART4
+/* UART4 device driver structure */
+struct es32_uart uart4 =
+{
+    {UART4},
+    UART4_IRQn
+};
+
+struct rt_serial_device serial4;
+
+void UART4_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if ((ald_uart_get_mask_flag_status(&uart4.huart, UART_IF_RFTH)) != RESET)
+    {
+        ald_uart_clear_flag_status(&uart4.huart, UART_IF_RFTH);
+        rt_hw_serial_isr(&serial4, RT_SERIAL_EVENT_RX_IND);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART4 */
+
+#ifdef BSP_USING_UART5
+/* UART5 device driver structure */
+struct es32_uart uart5 =
+{
+    {UART5},
+    UART5_IRQn
+};
+
+struct rt_serial_device serial5;
+
+void UART5_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if ((ald_uart_get_mask_flag_status(&uart5.huart, UART_IF_RFTH)) != RESET)
+    {
+        ald_uart_clear_flag_status(&uart5.huart, UART_IF_RFTH);
+        rt_hw_serial_isr(&serial5, RT_SERIAL_EVENT_RX_IND);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART5 */
+
+int rt_hw_uart_init(void)
+{
+    struct es32_uart *uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+#ifdef BSP_USING_UART0
+    uart = &uart0;
+    serial0.ops = &es32f3x_uart_ops;
+    serial0.config = config;
+
+    /* register UART0 device */
+    rt_hw_serial_register(&serial0, "uart0",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* BSP_USING_UART0 */
+
+#ifdef BSP_USING_UART1
+    uart = &uart1;
+    serial1.ops = &es32f3x_uart_ops;
+    serial1.config = config;
+
+    /* register UART1 device */
+    rt_hw_serial_register(&serial1, "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* BSP_USING_UART1 */
+
+#ifdef BSP_USING_UART2
+    uart = &uart2;
+    serial2.ops = &es32f3x_uart_ops;
+    serial2.config = config;
+
+    /* register UART2 device */
+    rt_hw_serial_register(&serial2, "uart2",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* BSP_USING_UART2 */
+
+#ifdef BSP_USING_UART3
+    uart = &uart3;
+    serial3.ops = &es32f3x_uart_ops;
+    serial3.config = config;
+
+    /* register UART3 device */
+    rt_hw_serial_register(&serial3, "uart3",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* BSP_USING_UART3 */
+
+#ifdef BSP_USING_UART4
+    uart = &uart4;
+    serial4.ops = &es32f3x_uart_ops;
+    serial4.config = config;
+
+    /* register UART4 device */
+    rt_hw_serial_register(&serial4, "uart4",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* BSP_USING_UART4 */
+
+#ifdef BSP_USING_UART5
+    uart = &uart5;
+    serial5.ops = &es32f3x_uart_ops;
+    serial5.config = config;
+
+    /* register UART5 device */
+    rt_hw_serial_register(&serial5, "uart5",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* BSP_USING_UART5 */
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_uart_init);
+
+#endif

bsp/essemi/es32f369x/drivers/drv_uart.h

+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author        Notes
+ * 2020-01-14     wangyq        the first version
+ */
+
+#ifndef DRV_UART_H__
+#define DRV_UART_H__
+
+int rt_hw_uart_init(void);
+
+#endif

bsp/essemi/es32f369x/drivers/linker_scripts/link.sct

+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20000000 0x00018000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+

bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/iar/startup_es32f36xx.s

+;*******************************************************************************
+; file       : startup_es32f36xx.s
+; description: es32f36xx Device Startup File
+; author     : AE Team
+; data       : 04 Jul 2019
+; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+;*******************************************************************************
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)				;0,  load top of stack
+                DCD     RESET_Handler                   ;1,  reset handler
+                DCD     NMI_Handler                     ;2,  nmi handler
+                DCD     HardFault_Handler               ;3,  hard fault handler
+                DCD     MemManage_Handler               ;4,  MPU Fault Handler
+                DCD     BusFault_Handler                ;5,  Bus Fault Handler
+                DCD     UsageFault_Handler              ;6,  Usage Fault Handler
+                DCD     0                               ;7,  Reserved
+                DCD     0                               ;8,  Reserved
+                DCD     0                               ;9,  Reserved
+                DCD     0                               ;10, Reserved
+                DCD     SVC_Handler                     ;11, svcall handler
+                DCD     DebugMon_Handler                ;12, Debug Monitor Handler
+                DCD     0                               ;13, Reserved
+                DCD     PendSV_Handler                  ;14, pendsv handler
+                DCD     SysTick_Handler                 ;15, systick handler
+                DCD     WWDG_Handler                    ;16, irq0    WWDG handler
+                DCD     IWDG_Handler                    ;17, irq1    IWDG handler
+                DCD     LVD_Handler                     ;18, irq2    LVD handler
+                DCD     RTC_Handler                     ;19, irq3    RTC handler
+                DCD     0                               ;20, irq4    Reserved
+                DCD     0                               ;21, irq5    Reserved
+                DCD     CMU_Handler                     ;22, irq6    CMU handler
+                DCD     ADC0_Handler                    ;23, irq7    ADC0 handler
+                DCD     CAN0_TX_Handler                 ;24, irq8    CAN0_TX handler
+                DCD     CAN0_RX0_Handler                ;25, irq9    CAN0_RX0 handler
+                DCD     CAN0_RX1_Handler                ;26, irq10   CAN0_RX1 handler
+                DCD     CAN0_EXCEPTION_Handler          ;27, irq11   CAN0_EXCEPTION handler
+                DCD     AD16C4T0_BRK_Handler            ;28, irq12   AD16C4T0_BRK handler
+                DCD     AD16C4T0_UP_Handler             ;29, irq13   AD16C4T0_UP handler
+                DCD     AD16C4T0_TRIG_COM_Handler       ;30, irq14   AD16C4T0_TRIG_COM handler
+                DCD     AD16C4T0_CC_Handler             ;31, irq15   AD16C4T0_CC handler
+                DCD     AD16C4T1_BRK_Handler            ;32, irq16   AD16C4T1_BRK handler
+                DCD     AD16C4T1_UP_Handler             ;33, irq17   AD16C4T1_UP handler
+                DCD     AD16C4T1_TRIG_COM_Handler       ;34, irq18   AD16C4T1_TRIG_COM handler
+                DCD     AD16C4T1_CC_Handler             ;35, irq19   AD16C4T1_CC handler
+                DCD     GP32C4T0_Handler                ;36, irq20   GP32C4T0 handler
+                DCD     GP32C4T1_Handler                ;37, irq21   GP32C4T1 handler
+                DCD     BS16T0_Handler                  ;38, irq22   BS16T0 handler
+                DCD     BS16T1_Handler                  ;39, irq23   BS16T1 handler
+                DCD     GP16C4T0_Handler                ;40, irq24   GP16C4T0 handler
+                DCD     GP16C4T1_Handler                ;41, irq25   GP16C4T1 handler
+                DCD     0                               ;42, irq26   Reserved
+                DCD     DAC0_CH0_Handler                ;43, irq27   DAC0_CH0 handler
+                DCD     I2C0_EV_Handler                 ;44, irq28   I2C0_EV handler
+                DCD     I2C0_ERR_Handler                ;45, irq29   I2C0_ERR handler
+                DCD     I2C1_EV_Handler                 ;46, irq30   I2C1_EV handler
+                DCD     I2C1_ERR_Handler                ;47, irq31   I2C1_ERR handler
+                DCD     SPI0_I2S0_Handler               ;48, irq32   SPI0_I2S0 handler
+                DCD     SPI1_I2S1_Handler               ;49, irq33   SPI1_I2S1 handler
+                DCD     UART0_Handler                   ;50, irq34   UART0 handler
+                DCD     UART1_Handler                   ;51, irq35   UART1 handler
+                DCD     UART2_Handler                   ;52, irq36   UART2 handler
+                DCD     UART3_Handler                   ;53, irq37   UART3 handler
+                DCD     UART4_Handler                   ;54, irq38   UART4 handler
+                DCD     UART5_Handler                   ;55, irq39   UART5 handler
+                DCD     0                               ;56, irq40   Reserved
+                DCD     0                               ;57, irq41   Reserved
+                DCD     CRYPT_Handler                   ;58, irq42   CRYPT handler
+                DCD     ACMP0_Handler                   ;59, irq43   ACMP0 handler
+                DCD     ACMP1_Handler                   ;60, irq44   ACMP1 handler
+                DCD     SPI2_I2S2_Handler               ;61, irq45   SPI2_I2S2 handler
+                DCD     0                               ;62, irq46   Reserved
+                DCD     EBI_Handler                     ;63, irq47   EBI handler
+                DCD     TRNG_Handler                    ;64, irq48   TRNG handler
+                DCD     TSENSE_Handler                  ;65, irq49   TSENSE handler
+                DCD     EXTI0_Handler                   ;66, irq50   EXTI0 handler
+                DCD     EXTI1_Handler                   ;67, irq51   EXTI1 handler
+                DCD     EXTI2_Handler                   ;68, irq52   EXTI2 handler
+                DCD     EXTI3_Handler                   ;69, irq53   EXTI3 handler
+                DCD     EXTI4_Handler                   ;70, irq54   EXTI4 handler
+                DCD     EXTI5_Handler                   ;71, irq55   EXTI5 handler
+                DCD     EXTI6_Handler                   ;72, irq56   EXTI6 handler
+                DCD     EXTI7_Handler                   ;73, irq57   EXTI7 handler
+                DCD     EXTI8_Handler                   ;74, irq58   EXTI8 handler
+                DCD     EXTI9_Handler                   ;75, irq59   EXTI9 handler
+                DCD     EXTI10_Handler                  ;76, irq60   EXTI10 handler
+                DCD     EXTI11_Handler                  ;77, irq61   EXTI11 handler
+                DCD     EXTI12_Handler                  ;78, irq62   EXTI12 handler
+                DCD     EXTI13_Handler                  ;79, irq63   EXTI13 handler
+                DCD     EXTI14_Handler                  ;80, irq64   EXTI14 handler
+                DCD     EXTI15_Handler                  ;81, irq65   EXTI15 handler
+                DCD     DMA_Handler                     ;82, irq66   DMA handler
+                DCD     ADC1_Handler                    ;83, irq67   ADC1 handler
+                DCD     DAC0_CH1_Handler                ;84, irq68   DAC0_CH1 handler
+                DCD     QSPI_Handler                    ;85, irq69   QSPI handler
+                DCD     USB_INT_Handler                 ;86, irq70   USB_INT handler
+                DCD     USB_DMA_Handler                 ;87, irq71   USB_DMA handler
+                DCD     ACMP2_Handler                   ;88, irq72   ACMP2 handler
+        
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+
+        PUBWEAK RESET_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+RESET_Handler
+        LDR     R0, =__iar_program_start
+        BX      R0
+        
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler	
+	
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler	
+	
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler	
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+		
+	PUBWEAK DebugMon_Handler
+	SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+	B DebugMon_Handler
+
+    	PUBWEAK PendSV_Handler
+    	SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+    	B PendSV_Handler
+
+   	PUBWEAK SysTick_Handler
+    	SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+    	B SysTick_Handler
+
+        PUBWEAK WWDG_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_Handler
+        B WWDG_Handler
+
+        PUBWEAK IWDG_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+IWDG_Handler
+        B IWDG_Handler
+
+        PUBWEAK LVD_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LVD_Handler
+        B LVD_Handler
+
+        PUBWEAK RTC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Handler
+        B RTC_Handler
+
+        PUBWEAK CMU_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CMU_Handler
+        B CMU_Handler
+
+        PUBWEAK ADC0_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC0_Handler
+        B ADC0_Handler
+
+        PUBWEAK CAN0_TX_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_TX_Handler
+        B CAN0_TX_Handler
+
+        PUBWEAK CAN0_RX0_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_RX0_Handler
+        B CAN0_RX0_Handler
+
+        PUBWEAK CAN0_RX1_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_RX1_Handler
+        B CAN0_RX1_Handler
+
+        PUBWEAK CAN0_EXCEPTION_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN0_EXCEPTION_Handler
+        B CAN0_EXCEPTION_Handler
+
+        PUBWEAK AD16C4T0_BRK_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AD16C4T0_BRK_Handler
+        B AD16C4T0_BRK_Handler
+
+        PUBWEAK AD16C4T0_UP_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AD16C4T0_UP_Handler
+        B AD16C4T0_UP_Handler
+
+        PUBWEAK AD16C4T0_TRIG_COM_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AD16C4T0_TRIG_COM_Handler
+        B AD16C4T0_TRIG_COM_Handler
+
+        PUBWEAK AD16C4T0_CC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AD16C4T0_CC_Handler
+        B AD16C4T0_CC_Handler
+
+        PUBWEAK AD16C4T1_BRK_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AD16C4T1_BRK_Handler
+        B AD16C4T1_BRK_Handler
+
+        PUBWEAK AD16C4T1_UP_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AD16C4T1_UP_Handler
+        B AD16C4T1_UP_Handler
+
+        PUBWEAK AD16C4T1_TRIG_COM_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AD16C4T1_TRIG_COM_Handler
+        B AD16C4T1_TRIG_COM_Handler
+
+        PUBWEAK AD16C4T1_CC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AD16C4T1_CC_Handler
+        B AD16C4T1_CC_Handler
+
+        PUBWEAK GP32C4T0_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GP32C4T0_Handler
+        B GP32C4T0_Handler
+
+        PUBWEAK GP32C4T1_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GP32C4T1_Handler
+        B GP32C4T1_Handler
+
+        PUBWEAK BS16T0_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BS16T0_Handler
+        B BS16T0_Handler
+
+        PUBWEAK BS16T1_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BS16T1_Handler
+        B BS16T1_Handler
+
+        PUBWEAK GP16C4T0_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GP16C4T0_Handler
+        B GP16C4T0_Handler
+
+        PUBWEAK GP16C4T1_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GP16C4T1_Handler
+        B GP16C4T1_Handler
+
+        PUBWEAK DAC0_CH0_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DAC0_CH0_Handler
+        B DAC0_CH0_Handler
+
+        PUBWEAK I2C0_EV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C0_EV_Handler
+        B I2C0_EV_Handler
+
+        PUBWEAK I2C0_ERR_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C0_ERR_Handler
+        B I2C0_ERR_Handler
+
+        PUBWEAK I2C1_EV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_Handler
+        B I2C1_EV_Handler
+
+        PUBWEAK I2C1_ERR_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ERR_Handler
+        B I2C1_ERR_Handler
+
+        PUBWEAK SPI0_I2S0_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI0_I2S0_Handler
+        B SPI0_I2S0_Handler
+
+        PUBWEAK SPI1_I2S1_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_I2S1_Handler
+        B SPI1_I2S1_Handler
+
+        PUBWEAK UART0_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART0_Handler
+        B UART0_Handler
+
+        PUBWEAK UART1_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART1_Handler
+        B UART1_Handler
+
+        PUBWEAK UART2_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART2_Handler
+        B UART2_Handler
+
+        PUBWEAK UART3_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART3_Handler
+        B UART3_Handler
+
+        PUBWEAK UART4_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_Handler
+        B UART4_Handler
+
+        PUBWEAK UART5_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_Handler
+        B UART5_Handler
+
+        PUBWEAK CRYPT_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRYPT_Handler
+        B CRYPT_Handler
+
+        PUBWEAK ACMP0_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ACMP0_Handler
+        B ACMP0_Handler
+
+        PUBWEAK ACMP1_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ACMP1_Handler
+        B ACMP1_Handler
+
+        PUBWEAK SPI2_I2S2_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_I2S2_Handler
+        B SPI2_I2S2_Handler
+
+        PUBWEAK EBI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EBI_Handler
+        B EBI_Handler
+
+        PUBWEAK TRNG_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TRNG_Handler
+        B TRNG_Handler
+
+        PUBWEAK TSENSE_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TSENSE_Handler
+        B TSENSE_Handler
+
+        PUBWEAK EXTI0_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_Handler
+        B EXTI0_Handler
+
+        PUBWEAK EXTI1_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_Handler
+        B EXTI1_Handler
+
+        PUBWEAK EXTI2_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_Handler
+        B EXTI2_Handler
+
+        PUBWEAK EXTI3_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_Handler
+        B EXTI3_Handler
+
+        PUBWEAK EXTI4_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_Handler
+        B EXTI4_Handler
+
+        PUBWEAK EXTI5_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI5_Handler
+        B EXTI5_Handler
+
+        PUBWEAK EXTI6_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI6_Handler
+        B EXTI6_Handler
+
+        PUBWEAK EXTI7_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI7_Handler
+        B EXTI7_Handler
+
+        PUBWEAK EXTI8_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI8_Handler
+        B EXTI8_Handler
+
+        PUBWEAK EXTI9_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_Handler
+        B EXTI9_Handler
+
+        PUBWEAK EXTI10_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI10_Handler
+        B EXTI10_Handler
+
+        PUBWEAK EXTI11_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI11_Handler
+        B EXTI11_Handler
+
+        PUBWEAK EXTI12_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI12_Handler
+        B EXTI12_Handler
+
+        PUBWEAK EXTI13_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI13_Handler
+        B EXTI13_Handler
+
+        PUBWEAK EXTI14_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI14_Handler
+        B EXTI14_Handler
+
+        PUBWEAK EXTI15_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_Handler
+        B EXTI15_Handler
+
+        PUBWEAK DMA_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA_Handler
+        B DMA_Handler
+
+        PUBWEAK ADC1_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC1_Handler
+        B ADC1_Handler
+
+        PUBWEAK DAC0_CH1_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DAC0_CH1_Handler
+        B DAC0_CH1_Handler
+
+        PUBWEAK QSPI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+QSPI_Handler
+        B QSPI_Handler
+
+        PUBWEAK USB_INT_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_INT_Handler
+        B USB_INT_Handler
+
+        PUBWEAK USB_DMA_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_DMA_Handler
+        B USB_DMA_Handler
+
+        PUBWEAK ACMP2_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ACMP2_Handler
+        B ACMP2_Handler
+
+        END

bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/Startup/keil/startup_es32f36xx.s

+;*******************************************************************************
+; file       : startup_es32f36xx.s
+; description: es32f36xx Device Startup File
+; author     : AE Team
+; data       : 23 Jan 2019
+; Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+;*******************************************************************************
+
+;Stack Configuration------------------------------------------------------------
+Stack_Size      EQU     0x00000800
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+;-------------------------------------------------------------------------------
+
+;Heap Configuration-------------------------------------------------------------
+Heap_Size       EQU     0x00000000
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+;-------------------------------------------------------------------------------
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset-------------------------------------
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+
+__Vectors       DCD     __initial_sp                    ;0,  load top of stack
+                DCD     RESET_Handler                   ;1,  reset handler
+                DCD     NMI_Handler                     ;2,  nmi handler
+                DCD     HardFault_Handler               ;3,  hard fault handler
+                DCD     MemManage_Handler               ;4,  MPU Fault Handler
+                DCD     BusFault_Handler                ;5,  Bus Fault Handler
+                DCD     UsageFault_Handler              ;6,  Usage Fault Handler
+                DCD     0                               ;7,  Reserved
+                DCD     0                               ;8,  Reserved
+                DCD     0                               ;9,  Reserved
+                DCD     0                               ;10, Reserved
+                DCD     SVC_Handler                     ;11, svcall handler
+                DCD     DebugMon_Handler                ;12, Debug Monitor Handler
+                DCD     0                               ;13, Reserved
+                DCD     PendSV_Handler                  ;14, pendsv handler
+                DCD     SysTick_Handler                 ;15, systick handler
+                DCD     WWDG_Handler                    ;16, irq0    WWDG handler
+                DCD     IWDG_Handler                    ;17, irq1    IWDG handler
+                DCD     LVD_Handler                     ;18, irq2    LVD handler
+                DCD     RTC_Handler                     ;19, irq3    RTC handler
+                DCD     0                               ;20, irq4    Reserved
+                DCD     0                               ;21, irq5    Reserved
+                DCD     CMU_Handler                     ;22, irq6    CMU handler
+                DCD     ADC0_Handler                    ;23, irq7    ADC0 handler
+                DCD     CAN0_TX_Handler                 ;24, irq8    CAN0_TX handler
+                DCD     CAN0_RX0_Handler                ;25, irq9    CAN0_RX0 handler
+                DCD     CAN0_RX1_Handler                ;26, irq10   CAN0_RX1 handler
+                DCD     CAN0_EXCEPTION_Handler          ;27, irq11   CAN0_EXCEPTION handler
+                DCD     AD16C4T0_BRK_Handler            ;28, irq12   AD16C4T0_BRK handler
+                DCD     AD16C4T0_UP_Handler             ;29, irq13   AD16C4T0_UP handler
+                DCD     AD16C4T0_TRIG_COM_Handler       ;30, irq14   AD16C4T0_TRIG_COM handler
+                DCD     AD16C4T0_CC_Handler             ;31, irq15   AD16C4T0_CC handler
+                DCD     AD16C4T1_BRK_Handler            ;32, irq16   AD16C4T1_BRK handler
+                DCD     AD16C4T1_UP_Handler             ;33, irq17   AD16C4T1_UP handler
+                DCD     AD16C4T1_TRIG_COM_Handler       ;34, irq18   AD16C4T1_TRIG_COM handler
+                DCD     AD16C4T1_CC_Handler             ;35, irq19   AD16C4T1_CC handler
+                DCD     GP32C4T0_Handler                ;36, irq20   GP32C4T0 handler
+                DCD     GP32C4T1_Handler                ;37, irq21   GP32C4T1 handler
+                DCD     BS16T0_Handler                  ;38, irq22   BS16T0 handler
+                DCD     BS16T1_Handler                  ;39, irq23   BS16T1 handler
+                DCD     GP16C4T0_Handler                ;40, irq24   GP16C4T0 handler
+                DCD     GP16C4T1_Handler                ;41, irq25   GP16C4T1 handler
+                DCD     0                               ;42, irq26   Reserved
+                DCD     DAC0_CH0_Handler                ;43, irq27   DAC0_CH0 handler
+                DCD     I2C0_EV_Handler                 ;44, irq28   I2C0_EV handler
+                DCD     I2C0_ERR_Handler                ;45, irq29   I2C0_ERR handler
+                DCD     I2C1_EV_Handler                 ;46, irq30   I2C1_EV handler
+                DCD     I2C1_ERR_Handler                ;47, irq31   I2C1_ERR handler
+                DCD     SPI0_I2S0_Handler               ;48, irq32   SPI0_I2S0 handler
+                DCD     SPI1_I2S1_Handler               ;49, irq33   SPI1_I2S1 handler
+                DCD     UART0_Handler                   ;50, irq34   UART0 handler
+                DCD     UART1_Handler                   ;51, irq35   UART1 handler
+                DCD     UART2_Handler                   ;52, irq36   UART2 handler
+                DCD     UART3_Handler                   ;53, irq37   UART3 handler
+                DCD     UART4_Handler                   ;54, irq38   UART4 handler
+                DCD     UART5_Handler                   ;55, irq39   UART5 handler
+                DCD     0                               ;56, irq40   Reserved
+                DCD     0                               ;57, irq41   Reserved
+                DCD     CRYPT_Handler                   ;58, irq42   CRYPT handler
+                DCD     ACMP0_Handler                   ;59, irq43   ACMP0 handler
+                DCD     ACMP1_Handler                   ;60, irq44   ACMP1 handler
+                DCD     SPI2_I2S2_Handler               ;61, irq45   SPI2_I2S2 handler
+                DCD     0                               ;62, irq46   Reserved
+                DCD     EBI_Handler                     ;63, irq47   EBI handler
+                DCD     TRNG_Handler                    ;64, irq48   TRNG handler
+                DCD     TSENSE_Handler                  ;65, irq49   TSENSE handler
+                DCD     EXTI0_Handler                   ;66, irq50   EXTI0 handler
+                DCD     EXTI1_Handler                   ;67, irq51   EXTI1 handler
+                DCD     EXTI2_Handler                   ;68, irq52   EXTI2 handler
+                DCD     EXTI3_Handler                   ;69, irq53   EXTI3 handler
+                DCD     EXTI4_Handler                   ;70, irq54   EXTI4 handler
+                DCD     EXTI5_Handler                   ;71, irq55   EXTI5 handler
+                DCD     EXTI6_Handler                   ;72, irq56   EXTI6 handler
+                DCD     EXTI7_Handler                   ;73, irq57   EXTI7 handler
+                DCD     EXTI8_Handler                   ;74, irq58   EXTI8 handler
+                DCD     EXTI9_Handler                   ;75, irq59   EXTI9 handler
+                DCD     EXTI10_Handler                  ;76, irq60   EXTI10 handler
+                DCD     EXTI11_Handler                  ;77, irq61   EXTI11 handler
+                DCD     EXTI12_Handler                  ;78, irq62   EXTI12 handler
+                DCD     EXTI13_Handler                  ;79, irq63   EXTI13 handler
+                DCD     EXTI14_Handler                  ;80, irq64   EXTI14 handler
+                DCD     EXTI15_Handler                  ;81, irq65   EXTI15 handler
+                DCD     DMA_Handler                     ;82, irq66   DMA handler
+                DCD     ADC1_Handler                    ;83, irq67   ADC1 handler
+                DCD     DAC0_CH1_Handler                ;84, irq68   DAC0_CH1 handler
+                DCD     QSPI_Handler                    ;85, irq69   QSPI handler
+                DCD     USB_INT_Handler                 ;86, irq70   USB_INT handler
+                DCD     USB_DMA_Handler                 ;87, irq71   USB_DMA handler
+                DCD     ACMP2_Handler                   ;88, irq72   ACMP2 handler
+
+;-------------------------------------------------------------------------------
+                AREA    INT, CODE, READONLY             ;code begin
+
+;Reset Handler----------------------------------------------
+RESET_Handler   PROC
+	EXPORT  RESET_Handler                  [WEAK]
+	IMPORT  __main
+	LDR     R0, =__main
+	BX      R0
+	NOP
+	ALIGN
+	ENDP
+
+;system int-------------------------------------------------
+NMI_Handler     PROC                           ;int 2
+	EXPORT  NMI_Handler                    [WEAK]
+	B       .
+	ENDP
+
+HardFault_Handler \
+	PROC                                   ;int3
+	EXPORT  HardFault_Handler              [WEAK]
+	B       .
+	ENDP
+
+MemManage_Handler \
+	PROC                                   ;int4
+	EXPORT  MemManage_Handler              [WEAK]
+	B       .
+	ENDP
+
+BusFault_Handler \
+	PROC                                   ;int5
+	EXPORT  BusFault_Handler               [WEAK]
+	B       .
+	ENDP
+
+UsageFault_Handler \
+	PROC                                   ;int6
+	EXPORT  UsageFault_Handler             [WEAK]
+	B       .
+	ENDP
+
+SVC_Handler \
+	PROC                                   ;int11
+	EXPORT  SVC_Handler                    [WEAK]
+	B       .
+	ENDP
+
+DebugMon_Handler \
+	PROC                                   ;int12
+	EXPORT  DebugMon_Handler               [WEAK]
+	B       .
+	ENDP
+
+PendSV_Handler  \
+        PROC                                   ;int14
+	EXPORT  PendSV_Handler                 [WEAK]
+	B       .
+	ENDP
+
+SysTick_Handler \
+	PROC                                   ;int15
+	EXPORT  SysTick_Handler                [WEAK]
+	B       .
+	ENDP
+
+;peripheral module int -----------------------------------------------
+WWDG_Handler \
+	PROC                                   ;int16
+	EXPORT  WWDG_Handler                   [WEAK]
+	B       .
+	ENDP
+
+IWDG_Handler \
+	PROC                                   ;int17
+	EXPORT  IWDG_Handler                   [WEAK]
+	B       .
+	ENDP
+
+LVD_Handler \
+	PROC                                   ;int18
+	EXPORT  LVD_Handler                    [WEAK]
+	B       .
+	ENDP
+
+RTC_Handler \
+	PROC                                   ;int19
+	EXPORT  RTC_Handler                    [WEAK]
+	B       .
+	ENDP
+
+FLASH_Handler \
+	PROC                                   ;int21
+	EXPORT  FLASH_Handler                  [WEAK]
+	B       .
+	ENDP
+
+CMU_Handler \
+	PROC                                   ;int22
+	EXPORT  CMU_Handler                    [WEAK]
+	B       .
+	ENDP
+
+ADC0_Handler \
+	PROC                                   ;int23
+	EXPORT  ADC0_Handler                   [WEAK]
+	B       .
+	ENDP
+
+CAN0_TX_Handler \
+	PROC                                   ;int24
+	EXPORT  CAN0_TX_Handler                [WEAK]
+	B       .
+	ENDP
+
+CAN0_RX0_Handler \
+	PROC                                   ;int25
+	EXPORT  CAN0_RX0_Handler               [WEAK]
+	B       .
+	ENDP
+
+CAN0_RX1_Handler \
+	PROC                                   ;int26
+	EXPORT  CAN0_RX1_Handler               [WEAK]
+	B       .
+	ENDP
+
+CAN0_EXCEPTION_Handler \
+	PROC                                   ;int27
+	EXPORT  CAN0_EXCEPTION_Handler         [WEAK]
+	B       .
+	ENDP
+
+AD16C4T0_BRK_Handler \
+	PROC                                   ;int28
+	EXPORT  AD16C4T0_BRK_Handler           [WEAK]
+	B       .
+	ENDP
+
+AD16C4T0_UP_Handler \
+	PROC                                   ;int29
+	EXPORT  AD16C4T0_UP_Handler            [WEAK]
+	B       .
+	ENDP
+
+AD16C4T0_TRIG_COM_Handler \
+	PROC                                   ;int30
+	EXPORT  AD16C4T0_TRIG_COM_Handler      [WEAK]
+	B       .
+	ENDP
+
+AD16C4T0_CC_Handler \
+	PROC                                   ;int31
+	EXPORT  AD16C4T0_CC_Handler            [WEAK]
+	B       .
+	ENDP
+
+AD16C4T1_BRK_Handler \
+	PROC                                   ;int32
+	EXPORT  AD16C4T1_BRK_Handler           [WEAK]
+	B       .
+	ENDP
+
+AD16C4T1_UP_Handler \
+	PROC                                   ;int33
+	EXPORT  AD16C4T1_UP_Handler            [WEAK]
+	B       .
+	ENDP
+
+AD16C4T1_TRIG_COM_Handler \
+	PROC                                   ;int34
+	EXPORT  AD16C4T1_TRIG_COM_Handler      [WEAK]
+	B       .
+	ENDP
+
+AD16C4T1_CC_Handler \
+	PROC                                   ;int35
+	EXPORT  AD16C4T1_CC_Handler            [WEAK]
+	B       .
+	ENDP
+
+GP32C4T0_Handler \
+	PROC                                   ;int36
+	EXPORT  GP32C4T0_Handler               [WEAK]
+	B       .
+	ENDP
+
+GP32C4T1_Handler \
+	PROC                                   ;int37
+	EXPORT  GP32C4T1_Handler               [WEAK]
+	B       .
+	ENDP
+
+BS16T0_Handler \
+	PROC                                   ;int38
+	EXPORT  BS16T0_Handler                 [WEAK]
+	B       .
+	ENDP
+
+BS16T1_Handler \
+	PROC                                   ;int39
+	EXPORT  BS16T1_Handler                 [WEAK]
+	B       .
+	ENDP
+
+GP16C4T0_Handler \
+	PROC                                   ;int40
+	EXPORT  GP16C4T0_Handler               [WEAK]
+	B       .
+	ENDP
+
+GP16C4T1_Handler \
+	PROC                                   ;int41
+	EXPORT  GP16C4T1_Handler               [WEAK]
+	B       .
+	ENDP
+
+DAC0_CH0_Handler \
+	PROC                                   ;int43
+	EXPORT  DAC0_CH0_Handler               [WEAK]
+	B       .
+	ENDP
+
+I2C0_EV_Handler \
+	PROC                                   ;int44
+	EXPORT  I2C0_EV_Handler                [WEAK]
+	B       .
+	ENDP
+
+I2C0_ERR_Handler \
+	PROC                                   ;int45
+	EXPORT  I2C0_ERR_Handler               [WEAK]
+	B       .
+	ENDP
+
+I2C1_EV_Handler \
+	PROC                                   ;int46
+	EXPORT  I2C1_EV_Handler                [WEAK]
+	B       .
+	ENDP
+
+I2C1_ERR_Handler \
+	PROC                                   ;int47
+	EXPORT  I2C1_ERR_Handler               [WEAK]
+	B       .
+	ENDP
+
+SPI0_I2S0_Handler \
+	PROC                                   ;int48
+	EXPORT  SPI0_I2S0_Handler              [WEAK]
+	B       .
+	ENDP
+
+SPI1_I2S1_Handler \
+	PROC                                   ;int49
+	EXPORT  SPI1_I2S1_Handler              [WEAK]
+	B       .
+	ENDP
+
+UART0_Handler \
+	PROC                                   ;int50
+	EXPORT  UART0_Handler                  [WEAK]
+	B       .
+	ENDP
+
+UART1_Handler \
+	PROC                                   ;int51
+	EXPORT  UART1_Handler                  [WEAK]
+	B       .
+	ENDP
+
+UART2_Handler \
+	PROC                                   ;int52
+	EXPORT  UART2_Handler                  [WEAK]
+	B       .
+	ENDP
+
+UART3_Handler \
+	PROC                                   ;int53
+	EXPORT  UART3_Handler                  [WEAK]
+	B       .
+	ENDP
+
+UART4_Handler \
+	PROC                                   ;int54
+	EXPORT  UART4_Handler                 [WEAK]
+	B       .
+	ENDP
+
+UART5_Handler \
+	PROC                                   ;int55
+	EXPORT  UART5_Handler                 [WEAK]
+	B       .
+	ENDP
+
+CRYPT_Handler \
+	PROC                                   ;int58
+	EXPORT  CRYPT_Handler                  [WEAK]
+	B       .
+	ENDP
+
+ACMP0_Handler \
+	PROC                                   ;int59
+	EXPORT  ACMP0_Handler                  [WEAK]
+	B       .
+	ENDP
+
+ACMP1_Handler \
+	PROC                                   ;int60
+	EXPORT  ACMP1_Handler                  [WEAK]
+	B       .
+	ENDP
+
+SPI2_I2S2_Handler \
+	PROC                                   ;int61
+	EXPORT  SPI2_I2S2_Handler              [WEAK]
+	B       .
+	ENDP
+
+EBI_Handler \
+	PROC                                   ;int63
+	EXPORT  EBI_Handler                   [WEAK]
+	B       .
+	ENDP
+
+TRNG_Handler \
+	PROC                                   ;int64
+	EXPORT  TRNG_Handler                   [WEAK]
+	B       .
+	ENDP
+
+TSENSE_Handler \
+	PROC                                   ;int65
+	EXPORT  TSENSE_Handler                 [WEAK]
+	B       .
+	ENDP
+
+EXTI0_Handler \
+	PROC                                   ;int66
+	EXPORT  EXTI0_Handler                  [WEAK]
+	B       .
+	ENDP
+
+EXTI1_Handler \
+	PROC                                   ;int67
+	EXPORT  EXTI1_Handler                  [WEAK]
+	B       .
+	ENDP
+
+EXTI2_Handler \
+	PROC                                   ;int68
+	EXPORT  EXTI2_Handler                  [WEAK]
+	B       .
+	ENDP
+
+EXTI3_Handler \
+	PROC                                   ;int69
+	EXPORT  EXTI3_Handler                  [WEAK]
+	B       .
+	ENDP
+
+EXTI4_Handler \
+	PROC                                   ;int70
+	EXPORT  EXTI4_Handler                  [WEAK]
+	B       .
+	ENDP
+
+EXTI5_Handler \
+	PROC                                   ;int71
+	EXPORT  EXTI5_Handler                  [WEAK]
+	B       .
+	ENDP
+
+EXTI6_Handler \
+	PROC                                   ;int72
+	EXPORT  EXTI6_Handler                  [WEAK]
+	B       .
+	ENDP
+
+EXTI7_Handler \
+	PROC                                   ;int73
+	EXPORT  EXTI7_Handler                  [WEAK]
+	B       .
+	ENDP
+
+EXTI8_Handler \
+	PROC                                   ;int74
+	EXPORT  EXTI8_Handler                  [WEAK]
+	B       .
+	ENDP
+
+EXTI9_Handler \
+	PROC                                   ;int75
+	EXPORT  EXTI9_Handler                  [WEAK]
+	B       .
+	ENDP
+
+EXTI10_Handler \
+	PROC                                   ;int76
+	EXPORT  EXTI10_Handler                 [WEAK]
+	B       .
+	ENDP
+
+EXTI11_Handler \
+	PROC                                   ;int77
+	EXPORT  EXTI11_Handler                 [WEAK]
+	B       .
+	ENDP
+
+EXTI12_Handler \
+	PROC                                   ;int78
+	EXPORT  EXTI12_Handler                 [WEAK]
+	B       .
+	ENDP
+
+EXTI13_Handler \
+	PROC                                   ;int79
+	EXPORT  EXTI13_Handler                 [WEAK]
+	B       .
+	ENDP
+
+EXTI14_Handler \
+	PROC                                   ;int80
+	EXPORT  EXTI14_Handler                 [WEAK]
+	B       .
+	ENDP
+
+EXTI15_Handler \
+	PROC                                   ;int81
+	EXPORT  EXTI15_Handler                 [WEAK]
+	B       .
+	ENDP
+
+DMA_Handler \
+	PROC                                   ;int82
+	EXPORT  DMA_Handler                    [WEAK]
+	B       .
+	ENDP
+
+ADC1_Handler \
+	PROC                                   ;int83
+	EXPORT  ADC1_Handler                   [WEAK]
+	B       .
+	ENDP
+
+DAC0_CH1_Handler \
+	PROC                                   ;int84
+	EXPORT  DAC0_CH1_Handler               [WEAK]
+	B       .
+	ENDP
+
+QSPI_Handler \
+	PROC                                   ;int85
+	EXPORT  QSPI_Handler                   [WEAK]
+	B       .
+	ENDP
+
+USB_INT_Handler \
+	PROC                                   ;int86
+	EXPORT  USB_INT_Handler                [WEAK]
+	B       .
+	ENDP
+
+USB_DMA_Handler \
+	PROC                                   ;int87
+	EXPORT  USB_DMA_Handler                [WEAK]
+	B       .
+	ENDP
+
+ACMP2_Handler \
+	PROC                                   ;int88
+	EXPORT  ACMP2_Handler                  [WEAK]
+	B       .
+	ENDP
+
+; User Initial Stack & Heap-----------------------------------------------------
+	ALIGN
+	IF      :DEF:__MICROLIB
+
+	EXPORT  __initial_sp
+	EXPORT  __heap_base
+	EXPORT  __heap_limit
+
+	ELSE
+
+	IMPORT  __use_two_region_memory
+	EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+	LDR     R0, =  Heap_Mem
+	LDR     R1, = (Stack_Mem + Stack_Size)
+	LDR     R2, = (Heap_Mem +  Heap_Size)
+	LDR     R3, = Stack_Mem
+	BX      LR
+
+	ALIGN
+
+	ENDIF
+
+	END

bsp/essemi/es32f369x/libraries/CMSIS/Device/EastSoft/ES32F36xx/System/system_es32f36xx.c

+/**
+  *********************************************************************************
+  *
+  * @file    system_es32f3xx.c
+  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer
+  *
+  * @version V1.0
+  * @date    24 Dec 2019
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  *********************************************************************************
+  */
+
+#include "utils.h"
+
+
+/**
+  * @brief  Configuring system clock before startup.
+  * @note   This function must be used after reset.
+  * @retval None
+  */
+void system_init (void)
+{
+	/* do nothing */
+}
\ No newline at end of file

bsp/essemi/es32f369x/libraries/CMSIS/Include/arm_common_tables.h

+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_common_tables.h
+ * Description:  Extern declaration for common tables
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
+#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
+#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
+#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
+#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
+#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
+#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
+#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */

bsp/essemi/es32f369x/libraries/CMSIS/Include/arm_const_structs.h

+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_const_structs.h
+ * Description:  Constant structs that are initialized for user convenience.
+ *               For example, some can be given as arguments to the arm_cfft_f32() function.
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif

bsp/essemi/es32f369x/libraries/CMSIS/Include/cmsis_compiler.h

+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.0.4
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

bsp/essemi/es32f369x/libraries/CMSIS/Include/cmsis_version.h

+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

bsp/essemi/es32f369x/libraries/CMSIS/Include/tz_context.h

+/******************************************************************************
+ * @file     tz_context.h
+ * @brief    Context Management for Armv8-M TrustZone
+ * @version  V1.0.1
+ * @date     10. January 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef TZ_CONTEXT_H
+#define TZ_CONTEXT_H
+ 
+#include <stdint.h>
+ 
+#ifndef TZ_MODULEID_T
+#define TZ_MODULEID_T
+/// \details Data type that identifies secure software modules called by a process.
+typedef uint32_t TZ_ModuleId_t;
+#endif
+ 
+/// \details TZ Memory ID identifies an allocated memory slot.
+typedef uint32_t TZ_MemoryId_t;
+  
+/// Initialize secure context memory system
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_InitContextSystem_S (void);
+ 
+/// Allocate context memory for calling secure software modules in TrustZone
+/// \param[in]  module   identifies software modules called from non-secure mode
+/// \return value != 0 id TrustZone memory slot identifier
+/// \return value 0    no memory available or internal error
+TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
+ 
+/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
+ 
+/// Load secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
+ 
+/// Store secure context (called on RTOS thread context switch)
+/// \param[in]  id  TrustZone memory slot identifier
+/// \return execution status (1: success, 0: error)
+uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
+ 
+#endif  // TZ_CONTEXT_H

bsp/essemi/es32f369x/libraries/ES32F36xx_ALD_StdPeriph_Driver/Include/ald_calc.h

+/**
+  *********************************************************************************
+  *
+  * @file    ald_calc.h
+  * @brief   Header file of CALC module driver.
+  *
+  * @version V1.0
+  * @date    26 Jun 2019
+  * @author  AE Team
+  * @note
+  *
+  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  ********************************************************************************
+  */
+
+#ifndef __ALD_CALC_H__
+#define __ALD_CALC_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "utils.h"
+
+
+/** @addtogroup ES32FXXX_ALD
+  * @{
+  */
+
+/** @addtogroup CALC
+  * @{
+  */
+
+/** @addtogroup CALC_Public_Functions
+  * @{
+  */
+extern uint32_t ald_calc_sqrt(uint32_t data);
+extern uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder);
+extern int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder);
+extern flag_status_t ald_calc_get_dz_status(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALD_CALC_H__ */