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体验新版 GitCode,发现更多精彩内容 >>
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3071e35c
编写于
6月 19, 2013
作者:
B
Bernard Xiong
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差异文件
Merge pull request #109 from grissiom/rm48x50
Rm48x50
上级
ce176ee1
009239ce
变更
5
隐藏空白更改
内联
并排
Showing
5 changed file
with
69 addition
and
1 deletion
+69
-1
bsp/rm48x50/application/startup.c
bsp/rm48x50/application/startup.c
+5
-0
bsp/rm48x50/rtconfig.h
bsp/rm48x50/rtconfig.h
+1
-0
libcpu/arm/cortex-r4/context_ccs.asm
libcpu/arm/cortex-r4/context_ccs.asm
+10
-0
libcpu/arm/cortex-r4/cpu.c
libcpu/arm/cortex-r4/cpu.c
+52
-0
libcpu/arm/cortex-r4/interrupt.c
libcpu/arm/cortex-r4/interrupt.c
+1
-1
未找到文件。
bsp/rm48x50/application/startup.c
浏览文件 @
3071e35c
...
...
@@ -48,6 +48,11 @@ extern unsigned char * const system_data_end;
*/
void
rtthread_startup
(
void
)
{
/*// RM48 does not have cache implemented
*rt_hw_cpu_icache_enable();
*rt_hw_cpu_dcache_enable();
*/
/* init hardware interrupt */
rt_hw_interrupt_init
();
...
...
bsp/rm48x50/rtconfig.h
浏览文件 @
3071e35c
...
...
@@ -212,6 +212,7 @@
// </section>
#define RT_VFP_LAZY_STACKING
#define RT_USING_CPU_FFS
// </RDTConfigurator>
#endif
libcpu/arm/cortex-r4/context_ccs.asm
浏览文件 @
3071e35c
...
...
@@ -28,18 +28,22 @@
; * rt_base_t rt_hw_interrupt_disable();
; */
.def
rt_hw_interrupt_disable
.asmfunc
rt_hw_interrupt_disable
MRS
r0
,
cpsr
CPSID
IF
BX
lr
.endasmfunc
;/*
; * void rt_hw_interrupt_enable(rt_base_t level);
; */
.def
rt_hw_interrupt_enable
.asmfunc
rt_hw_interrupt_enable
MSR
cpsr_c
,
r0
BX
lr
.endasmfunc
;/*
; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
...
...
@@ -47,6 +51,7 @@ rt_hw_interrupt_enable
; * r1 --> to
; */
.def
rt_hw_context_switch
.asmfunc
rt_hw_context_switch
STMDB
sp
!
,
{
lr
}
; push pc (lr should be pushed in place of PC)
STMDB
sp
!
,
{
r0
-
r12
,
lr
}
; push lr & register file
...
...
@@ -88,12 +93,14 @@ __no_vfp_frame2
MSR
sp
sr_cxsf
,
r4
LDMIA
sp
!
,
{
r0
-
r12
,
lr
,
pc
}
^
; pop new task r0-r12, lr & pc, copy spsr to cpsr
.endasmfunc
;/*
; * void rt_hw_context_switch_to(rt_uint32 to);
; * r0 --> to
; */
.def
rt_hw_context_switch_to
.asmfunc
rt_hw_context_switch_to
LDR
sp
,
[
r0
]
; get new task stack pointer
...
...
@@ -112,12 +119,14 @@ __no_vfp_frame_to
MSR
sp
sr_cxsf
,
r4
LDMIA
sp
!
,
{
r0
-
r12
,
lr
,
pc
}
^
; pop new task r0-r12, lr & pc, copy spsr to cpsr
.endasmfunc
;/*
; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
; */
.def
rt_hw_context_switch_interrupt
.asmfunc
rt_hw_context_switch_interrupt
LDR
r2
,
pintflag
LDR
r3
,
[
r2
]
...
...
@@ -131,6 +140,7 @@ _reswitch
LDR
r2
,
ptothread
; set rt_interrupt_to_thread
STR
r1
,
[
r2
]
BX
lr
.endasmfunc
.def
IRQ_Handler
IRQ_Handler
...
...
libcpu/arm/cortex-r4/cpu.c
浏览文件 @
3071e35c
...
...
@@ -39,4 +39,56 @@ void rt_hw_cpu_shutdown()
while
(
1
);
}
#ifdef RT_USING_CPU_FFS
int
__rt_ffs
(
int
value
)
{
if
(
value
==
0
)
return
value
;
__asm
(
" rsb r1, r0, #0"
);
__asm
(
" and r1, r1, r0"
);
__asm
(
" clz r1, r1"
);
__asm
(
" rsb r0, r1, #32"
);
}
#endif
#ifdef __TI_COMPILER_VERSION__
void
rt_hw_cpu_icache_enable
()
{
__asm
(
" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data"
);
__asm
(
" ORR r1, r1, #0x1 <<12 ; instruction cache enable"
);
__asm
(
" MCR p15, #0, r0, c7, c5, #0 ; Invalidate entire instruction cache, r0 is ignored"
);
__asm
(
" MCR p15, #0, r1, c1, c0, #0 ; enabled instruction cache"
);
__asm
(
" ISB"
);
}
void
rt_hw_cpu_icache_disable
()
{
__asm
(
" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data"
);
__asm
(
" BIC r1, r1, #0x1 <<12 ; instruction cache enable"
);
__asm
(
" MCR p15, #0, r1, c1, c0, #0 ; disabled instruction cache"
);
__asm
(
" ISB"
);
}
void
rt_hw_cpu_dcache_enable
()
{
__asm
(
" MRC p15, #0, R1, c1, c0, #0 ; Read SCTLR configuration data"
);
__asm
(
" ORR R1, R1, #0x1 <<2"
);
__asm
(
" DSB"
);
__asm
(
" MCR p15, #0, r0, c15, c5, #0 ; Invalidate entire data cache"
);
__asm
(
" MCR p15, #0, R1, c1, c0, #0 ; enabled data cache"
);
}
void
rt_hw_cpu_dcache_disable
()
{
/* FIXME: Clean entire data cache. This routine depends on the data cache
* size. It can be omitted if it is known that the data cache has no dirty
* data. */
__asm
(
" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data"
);
__asm
(
" BIC r1, r1, #0x1 <<2"
);
__asm
(
" DSB"
);
__asm
(
" MCR p15, #0, r1, c1, c0, #0 ; disabled data cache"
);
}
#endif
/*@}*/
libcpu/arm/cortex-r4/interrupt.c
浏览文件 @
3071e35c
...
...
@@ -22,7 +22,7 @@
/* exception and interrupt handler table */
struct
rt_irq_desc
irq_desc
[
MAX_HANDLERS
];
extern
rt_uint32
_t
rt_interrupt_nest
;
extern
volatile
rt_uint8
_t
rt_interrupt_nest
;
/* exception and interrupt handler table */
rt_uint32_t
rt_interrupt_from_thread
,
rt_interrupt_to_thread
;
...
...
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