wangjiyang added bsp/evb4020 & modified libcpu/arm/sep4020

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1128 bbd45198-f89e-11dd-88c7-29a3b14d5316

libcpu/arm/sep4020/cpu.c

-/*
- * File      : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2006-08-23     Bernard      first version
- */
-
-#include <rtthread.h>
-
-
-/**
- * @addtogroup AT91SAM7X
- */
-/*@{*/
-
-/**
- * this function will reset CPU
- *
- */
-void rt_hw_cpu_reset()
-{
-}
-
-/**
- * this function will shutdown CPU
- *
- */
-void rt_hw_cpu_shutdown()
-{
-	rt_kprintf("shutdown...\n");
-
-	while (1);
-}
-
-/*@}*/
+/*
+ * File      : cpu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-03-13     Bernard      first version
+ */
+
+#include <rtthread.h>
+#include <sep4020.h>
+
+extern rt_uint32_t rt_hw_interrupt_disable(void);
+
+//TODO
+#warning I DON'T KNOW IF THE MMU OPERATION WORKS ON SEP4020
+
+/**
+ * @addtogroup S3C24X0
+ */
+/*@{*/
+
+#define ICACHE_MASK	(rt_uint32_t)(1 << 12)
+#define DCACHE_MASK	(rt_uint32_t)(1 << 2)
+
+#ifdef __GNUC__
+rt_inline rt_uint32_t cp15_rd(void)
+{
+	rt_uint32_t i;
+
+	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+	return i;
+}
+
+rt_inline void cache_enable(rt_uint32_t bit)
+{
+	__asm__ __volatile__(			\
+		"mrc  p15,0,r0,c1,c0,0\n\t"	\
+		"orr  r0,r0,%0\n\t"			\
+	   	"mcr  p15,0,r0,c1,c0,0"		\
+		:							\
+		:"r" (bit)					\
+		:"memory");
+}
+
+rt_inline void cache_disable(rt_uint32_t bit)
+{
+	__asm__ __volatile__(			\
+		"mrc  p15,0,r0,c1,c0,0\n\t"	\
+		"bic  r0,r0,%0\n\t"			\
+		"mcr  p15,0,r0,c1,c0,0"		\
+		:							\
+		:"r" (bit)					\
+		:"memory");
+}
+#endif
+
+#ifdef __CC_ARM
+rt_inline rt_uint32_t cp15_rd(void)
+{
+	rt_uint32_t i;
+
+	__asm
+	{
+		mrc p15, 0, i, c1, c0, 0
+	}
+
+	return i;
+}
+
+rt_inline void cache_enable(rt_uint32_t bit)
+{
+	rt_uint32_t value;
+
+	__asm
+	{
+		mrc p15, 0, value, c1, c0, 0
+		orr value, value, bit
+		mcr p15, 0, value, c1, c0, 0
+	}
+}
+
+rt_inline void cache_disable(rt_uint32_t bit)
+{
+	rt_uint32_t value;
+
+	__asm
+	{
+		mrc p15, 0, value, c1, c0, 0
+		bic value, value, bit
+		mcr p15, 0, value, c1, c0, 0
+	}
+}
+#endif
+
+/**
+ * enable I-Cache
+ *
+ */
+void rt_hw_cpu_icache_enable()
+{
+	cache_enable(ICACHE_MASK);
+}
+
+/**
+ * disable I-Cache
+ *
+ */
+void rt_hw_cpu_icache_disable()
+{
+	cache_disable(ICACHE_MASK);
+}
+
+/**
+ * return the status of I-Cache
+ *
+ */
+rt_base_t rt_hw_cpu_icache_status()
+{
+	return (cp15_rd() & ICACHE_MASK);
+}
+
+/**
+ * enable D-Cache
+ *
+ */
+void rt_hw_cpu_dcache_enable()
+{
+	cache_enable(DCACHE_MASK);
+}
+
+/**
+ * disable D-Cache
+ *
+ */
+void rt_hw_cpu_dcache_disable()
+{
+	cache_disable(DCACHE_MASK);
+}
+
+/**
+ * return the status of D-Cache
+ *
+ */
+rt_base_t rt_hw_cpu_dcache_status()
+{
+	return (cp15_rd() & DCACHE_MASK);
+}
+
+/**
+ * reset cpu by dog's time-out
+ *
+ */
+void rt_hw_cpu_reset()
+{
+
+	/* enable watchdog */
+	*(RP)(RTC_CTR) = 0x02;
+
+	/*Enable watchdog reset*/
+	*(RP)(RTC_INT_EN) = 0x20;
+
+	/* Initialize watchdog timer count register */
+	*(RP)(RTC_WD_CNT) = 0x0001;
+
+	while(1);	/* loop forever and wait for reset to happen */
+
+	/* NEVER REACHED */
+}
+
+/**
+ *  shutdown CPU
+ *
+ */
+void rt_hw_cpu_shutdown()
+{
+	rt_uint32_t UNUSED level;
+	rt_kprintf("shutdown...\n");
+
+	level = rt_hw_interrupt_disable();
+
+	RT_ASSERT(RT_NULL);
+}
+
+/*@}*/

libcpu/arm/sep4020/interrupt.c

@@ -9,30 +9,30 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2006-08-23     Bernard      first version
- * 2010-03-17     zchong       SEP4020
+ * 2006-03-13     Bernard      first version
  */
 
 #include <rtthread.h>
-#include "sep4020.h"
+#include <sep4020.h>
 
 #define MAX_HANDLERS	32
 
-extern rt_uint32_t rt_interrupt_nest;
+extern rt_uint32_t rt_interrupt_nest;
 
-/* exception and interrupt handler table */
+/* exception and interrupt handler table */
 rt_isr_handler_t isr_table[MAX_HANDLERS];
 rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
 rt_uint32_t rt_thread_switch_interrput_flag;
 
 /**
- * @addtogroup SEP4020
+ * @addtogroup S3C24X0
  */
 /*@{*/
 
-void rt_hw_interrupt_handler(int vector)
+rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector)
 {
 	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+	return RT_NULL;
 }
 
 /**
@@ -42,16 +42,33 @@ void rt_hw_interrupt_init()
 {
 	register rt_uint32_t idx;
 
-    /* disable all interrupts */
-    INTC_IER = 0x0;
+	/*Make sure all intc registers in proper state*/
 
-    /* mask all interrupts */
-    INTC_IMR = 0xFFFFFFFF;
+	/*mask all the irq*/
+	*(RP)(INTC_IMR) = 0xFFFFFFFF;
+
+	/*enable all the irq*/
+	*(RP)(INTC_IER)	= 0XFFFFFFFF;
+
+	/*Dont use any forced irq*/
+	*(RP)(INTC_IFR) = 0x0;
+
+	/*Disable all the fiq*/
+	*(RP)(INTC_FIER) = 0x0;
+
+	/*Mask all the fiq*/
+	*(RP)(INTC_FIMR) = 0x0F;
+
+	/*Dont use forced fiq*/
+	*(RP)(INTC_FIFR) = 0x0;
+
+	/*Intrrupt priority register*/
+	*(RP)(INTC_IPLR) = 0x0;
 
-	/* init exceptions table */
-	for(idx=0; idx < MAX_HANDLERS; idx++)
-	{
-		isr_table[idx] = (rt_isr_handler_t)rt_hw_interrupt_handler;
+	/* init exceptions table */
+	for(idx=0; idx < MAX_HANDLERS; idx++)
+	{
+		isr_table[idx] = (rt_isr_handler_t)rt_hw_interrupt_handle;
 	}
 
 	/* init interrupt nest, and context in thread sp */
@@ -65,29 +82,25 @@ void rt_hw_interrupt_init()
  * This function will mask a interrupt.
  * @param vector the interrupt number
  */
-void rt_hw_interrupt_mask(int vector)
-{
-    INTC_IMR |= 1 << vector;
+void rt_hw_interrupt_mask(rt_uint32_t vector)
+{
+	*(RP)(INTC_IMR) |= 1 << vector;
 }
 
 /**
  * This function will un-mask a interrupt.
  * @param vector the interrupt number
  */
-void rt_hw_interrupt_umask(int vector)
+void rt_hw_interrupt_umask(rt_uint32_t vector)
 {
-	/* un-mask interrupt */
-	if ((vector == INT_NOTUSED0) || (vector == INT_NOTUSED16))
+	if(vector == 16)
 	{
 		rt_kprintf("Interrupt vec %d is not used!\n", vector);
-		// while(1);
 	}
-	else if (vector == INTGLOBAL)
-		INTC_IMR = 0x0;
 	else
-		INTC_IMR &= ~(1 << vector);
-
-}
+		*(RP)(INTC_IMR) &= ~(1 << vector);
+}
+
 
 /**
  * This function will install a interrupt service routine to a interrupt.
@@ -95,12 +108,14 @@ void rt_hw_interrupt_umask(int vector)
  * @param new_handler the interrupt service routine to be installed
  * @param old_handler the old interrupt service routine
  */
-void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
+void rt_hw_interrupt_install(rt_uint32_t vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
 {
-	if(vector >= 0 && vector < MAX_HANDLERS)
+	if(vector < MAX_HANDLERS)
 	{
-		if (*old_handler != RT_NULL) *old_handler = isr_table[vector];
-		if (new_handler != RT_NULL) isr_table[vector] = new_handler;
+		if (*old_handler != RT_NULL)
+			*old_handler = isr_table[vector];
+		if (new_handler != RT_NULL) 
+			isr_table[vector] = new_handler;
 	}
 }
 

libcpu/arm/sep4020/stack.c

@@ -9,14 +9,12 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2006-08-23     Bernard      the first version
+ * 2006-03-13     Bernard      the first version
  */
 #include <rtthread.h>
-
-#define SVCMODE				0x13
-
+#include <sep4020.h>
 /**
- * @addtogroup AT91SAM7
+ * @addtogroup S3C24X0
  */
 /*@{*/
 
@@ -24,7 +22,7 @@
  * This function will initialize thread stack
  *
  * @param tentry the entry of thread
- * @param parameter the parameter of entry
+ * @param parameter the parameter of entry 
  * @param stack_addr the beginning stack address
  * @param texit the function will be called when thread exit
  *
@@ -33,11 +31,11 @@
 rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
 	rt_uint8_t *stack_addr, void *texit)
 {
-	unsigned long *stk;
+	rt_uint32_t *stk;
 
-	stk 	 = (unsigned long *)stack_addr;
-	*(stk) 	 = (unsigned long)tentry;		/* entry point */
-	*(--stk) = (unsigned long)texit;		/* lr */
+	stk 	 = (rt_uint32_t*)stack_addr;
+	*(stk) 	 = (rt_uint32_t)tentry;			/* entry point */
+	*(--stk) = (rt_uint32_t)texit;			/* lr */
 	*(--stk) = 0;							/* r12 */
 	*(--stk) = 0;							/* r11 */
 	*(--stk) = 0;							/* r10 */
@@ -50,9 +48,9 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
 	*(--stk) = 0;							/* r3 */
 	*(--stk) = 0;							/* r2 */
 	*(--stk) = 0;							/* r1 */
-	*(--stk) = (unsigned long)parameter;	/* r0 : argument */
-	*(--stk) = SVCMODE;						/* cpsr */
-	*(--stk) = SVCMODE;						/* spsr */
+	*(--stk) = (rt_uint32_t)parameter;		/* r0 : argument */
+	*(--stk) = Mode_SVC;					/* cpsr */
+	*(--stk) = Mode_SVC;					/* spsr */
 
 	/* return task's current stack address */
 	return (rt_uint8_t *)stk;

libcpu/arm/sep4020/start_rvds.S

@@ -8,8 +8,6 @@
 ; 2010-03-17     zchong 
 ;=============================================================================================
 
-;
-
 PMU_PLTR        EQU     0x10001000     	; PLL的稳定过渡时间
 PMU_PMCR        EQU     0x10001004      ; 系统主时钟PLL的控制寄存器
 PMU_PUCR        EQU     0x10001008      ; USB时钟PLL的控制寄存器
@@ -51,42 +49,51 @@ MODE_SVC32		EQU		0x00000013
 ; Internal Memory Base Addresses
 FLASH_BASE      EQU     0x20000000   
 RAM_BASE        EQU     0x04000000
+SDRAM_BASE      EQU     0x30000000
 
 ; Stack
-UND_Stack_Size  EQU     0x00000000
-SVC_Stack_Size  EQU     0x00000400
-ABT_Stack_Size  EQU     0x00000000
-FIQ_Stack_Size  EQU     0x00000000
-IRQ_Stack_Size  EQU     0x00000100
-USR_Stack_Size  EQU     0x00000000
+Unused_Stack_Size  EQU     0x00000100
+Svc_Stack_Size  EQU     0x00001000
+Abt_Stack_Size  EQU     0x00000000
+Fiq_Stack_Size  EQU     0x00000000
+Irq_Stack_Size  EQU     0x00001000
+Usr_Stack_Size  EQU     0x00000000
+
+;SVC STACK
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Svc_Stack    	SPACE   Svc_Stack_Size
+__initial_sp
+Svc_Stack_Top
 
-ISR_Stack_Size  EQU     (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
-                         FIQ_Stack_Size + IRQ_Stack_Size)
+;IRQ STACK
+				AREA	STACK, NOINIT, READWRITE, ALIGN=3
+Irq_Stack		SPACE	Irq_Stack_Size
+Irq_Stack_Top
 
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+;UNUSED STACK
+				AREA	STACK, NOINIT, READWRITE, ALIGN=3
+Unused_Stack	SPACE	Unused_Stack_Size
+Unused_Stack_Top
 
-Stack_Mem       SPACE   USR_Stack_Size
-__initial_sp    SPACE   ISR_Stack_Size
-Stack_Top
 
 ; Heap
-Heap_Size       EQU     0x00000000
+Heap_Size       EQU     0x0000100
 
                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+				EXPORT	Heap_Mem
 __heap_base
 Heap_Mem        SPACE   Heap_Size
 __heap_limit
 
-
                 PRESERVE8
                 
-; Area Definition and Entry Point
+;  Area Definition and Entry Point
 ;  Startup Code must be linked first at Address at which it expects to run.
 
                 AREA    RESET, CODE, READONLY
                 ARM
 
-; Exception Vectors
+;  Exception Vectors
 ;  Mapped to Address 0.
 ;  Absolute addressing mode must be used.
 ;  Dummy Handlers are implemented as infinite loops which can be modified.
@@ -110,265 +117,268 @@ IRQ_Addr        DCD     IRQ_Handler
 FIQ_Addr        DCD     FIQ_Handler
 
 Undef_Handler   B       Undef_Handler
-SWI_Handler     B       SWI_Handler
-PAbt_Handler    B       PAbt_Handler
-DAbt_Handler    B       DAbt_Handler
+SWI_Handler     B		SWI_Handler
+PAbt_Handler    B       Abort_Handler
+DAbt_Handler    B       Abort_Handler
 FIQ_Handler     B       FIQ_Handler
 
+Abort_Handler	PROC
+				ARM
+				EXPORT	Abort_Handler
+DeadLoop	BHI	DeadLoop    ; Abort happened in irq mode, halt system.
+				ENDP
 
-; Reset Handler
 
+; Reset Handler
+				;IMPORT	__user_initial_stackheap
                 EXPORT  Reset_Handler
-Reset_Handler   
+Reset_Handler
 
 ;****************************************************************
-;* 关闭看门狗
+;* Shutdown watchdog
 ;****************************************************************
-		LDR		R0,=RTC_CTR	
-		LDR		R1,=0x0			
-		STR		R1,[R0]	
+				LDR		R0,=RTC_CTR	
+				LDR		R1,=0x0			
+				STR		R1,[R0]	
 
 ;****************************************************************
-;* 关中断
+;* shutdown interrupts
 ;****************************************************************	
-		MRS		R0, CPSR
-		BIC		R0, R0, #MASK_MODE
-		ORR		R0, R0, #MODE_SVC32
-		ORR 	R0, R0, #I_Bit
-		ORR 	R0, R0, #F_Bit
-		MSR		CPSR_c, r0
-	
-		LDR		R0,=INTC_IER			
-		LDR		R1,=0x0 	
-		STR		R1,[R0]
-		LDR		R0,=INTC_IMR
-		LDR		R1,=0xFFFFFFFF			
-		STR		R1,[R0]	
-	
-		LDR		R0,=INTC_FIER			
-		LDR		R1,=0x0 	
-		STR		R1,[R0]
-		LDR		R0,=INTC_FIMR
-		LDR		R1,=0x0F				
-		STR		R1,[R0]
+				MRS		R0, CPSR
+				BIC		R0, R0, #MASK_MODE
+				ORR		R0, R0, #MODE_SVC32
+				ORR 	R0, R0, #I_Bit
+				ORR 	R0, R0, #F_Bit
+				MSR		CPSR_c, r0
+			
+				LDR		R0,=INTC_IER			
+				LDR		R1,=0x0 	
+				STR		R1,[R0]
+				LDR		R0,=INTC_IMR
+				LDR		R1,=0xFFFFFFFF			
+				STR		R1,[R0]	
+			
+				LDR		R0,=INTC_FIER			
+				LDR		R1,=0x0 	
+				STR		R1,[R0]
+				LDR		R0,=INTC_FIMR
+				LDR		R1,=0x0F				
+				STR		R1,[R0]
 
 ;****************************************************************
-;* 初始化PMU模块, 配置系统时钟
+;* Initialize Stack Pointer
+;****************************************************************
+			
+			    LDR		SP, =Svc_Stack_Top	;init SP_svc
+				
+			    MOV		R4, #0xD2			;chmod to irq and init SP_irq
+			    MSR		cpsr_c, R4   
+			    LDR		SP, =Irq_Stack_Top
+				
+			    MOV		R4, #0XD1			;chomod to fiq and init SP_fiq
+			    MSR		cpsr_c, R4   
+			    LDR		SP, =Unused_Stack_Top  
+				
+			    MOV		R4, #0XD7			;chomod to abt and init SP_ABT
+			    MSR		cpsr_c, R4   
+			    LDR		SP, =Unused_Stack_Top 
+				
+			    MOV		R4, #0XDB			;chomod to undf and init SP_UNDF
+			    MSR		cpsr_c, R4   
+			    LDR		SP, =Unused_Stack_Top 	
+			    
+			                                ;chomod to abt and init SP_sys
+			    MOV 	R4, #0xDF           ;all interrupts disabled      
+			    MSR		cpsr_c, R4       ;SYSTEM mode, @32-bit code mode     
+			    LDR		SP, =Unused_Stack_Top   	
+			    
+			    MOV		R4, #0XD3           ;chmod to svc modle, CPSR IRQ bit  is disable
+			    MSR		cpsr_c, R4
+			
+			
+			
+;****************************************************************
+;* Initialize PMU & System Clock
 ;****************************************************************
-		LDR	   	R4,    =PMU_PCSR        ; 打开所有模块时钟
-		LDR    	R5,    =0x0001ffff                 
-  	  	STR    	R5,    [ R4 ] 
-
-		LDR    	R4,    =PMU_PLTR        ; 配置PLL稳定过度时间为保守值50us*100M.
-		LDR    	R5,    =0x00fa00fa
-		STR    	R5,    [ R4 ] 
-   
-    	LDR    	R4,    =PMU_PMDR        ; 由SLOW模式进入NORMAL模式
-	   	LDR    	R5,    =0x00000001                
-    	STR    	R5,    [ R4 ] 
-    
-    	LDR    	R4,    =PMU_PMCR        ; 配置系统时钟为72MHz 2*Fin*9=2*4*9=72MHz
-    	LDR    	R5,    =0x00004009      ; MFCN 0->1 trigger PLL to reconfigure event when mode isn''t SLOW        
-    	STR    	R5,    [ R4 ]
-    	LDR    	R4,    =PMU_PMCR        ; 
-    	LDR    	R5,    =0x0000c009                 
-    	STR    	R5,    [ R4 ]
-    
+			
+			    LDR    R4,    =PMU_PCSR         ; 打所有模块时钟
+			    LDR    R5,    =0x0001ffff                 
+			    STR    R5,    [ R4 ] 
+			
+			    LDR    R4,    =PMU_PLTR         ; 配置PLL稳定过度时间为保守值50us*100M.
+			    LDR    R5,    =0x00fa00fa
+			    STR    R5,    [ R4 ] 
+			   
+			    LDR    R4,    =PMU_PMDR         ; 由SLOW模式进入NORMAL模式
+			    LDR    R5,    =0x00000001                
+			    STR    R5,    [ R4 ] 
+			    
+			    LDR    R4,    =PMU_PMCR         ; 配置系统时钟为80MHz       
+			    LDR    R5,    =0x00004009       ; 400b -- 88M
+			    STR    R5,    [ R4 ] 
+			    
+			    ;PMU_PMCR寄存器第15位需要有从低到高的翻转，才能触发PLL的时钟配置
+			    LDR    R4,    =PMU_PMCR        
+			    LDR    R5,    =0x0000c009               
+			    STR    R5,    [ R4 ]
+			    
 ;****************************************************************
 ;* 初始化EMI
 ;****************************************************************
-;    	LDR    	R4,    =EMI_CSACONF     ; CSA片选时序参数配置
-;    	LDR    	R5,    =0x08a6a6a1                 
-;    	STR    	R5,    [ R4 ]     
- 
-;    	LDR    	R4,    =EMI_CSECONF     ; CSE片选时序参数配置,最保守配置
-;    	LDR    	R5,    =0x8cfffff1                 
-;    	STR    	R5,    [ R4 ]
- 
-;    	LDR    	R4,    =EMI_SDCONF1     ; SDRAM参数配置1
-;    	LDR    	R5,    =0x1E104177                 
-;    	STR    	R5,    [ R4 ] 
-
-;    	LDR    	R4,    =EMI_SDCONF2     ; SDRAM参数配置2
-;    	LDR   	R5,    =0x80001860                 
-;    	STR    	R5,    [ R4 ]
-
-
-; Copy Exception Vectors to Internal RAM
-
-	IF      :DEF:RAM_INTVEC
-		ADR     R8, 	Vectors         ; Source
-		LDR     R9, 	=RAM_BASE       ; Destination
-		LDMIA   R8!, 	{R0-R7}        	; Load Vectors 
-		STMIA   R9!, 	{R0-R7}        	; Store Vectors 
-		LDMIA   R8!, 	{R0-R7}        	; Load Handler Addresses 
-		STMIA   R9!, 	{R0-R7}        	; Store Handler Addresses
-	ENDIF
 
+				IF		:DEF:INIT_EMI
+
+		    	LDR    	R4,    =EMI_CSACONF     ; CSA片选时序参数配置
+		    	LDR    	R5,    =0x08a6a6a1                 
+		    	STR    	R5,    [ R4 ]     
+		 
+		    	LDR    	R4,    =EMI_CSECONF     ; CSE片选时序参数配置,最保守配置
+		    	LDR    	R5,    =0x8cfffff1                 
+		    	STR    	R5,    [ R4 ]
+		 
+		    	LDR    	R4,    =EMI_SDCONF1     ; SDRAM参数配置1
+		    	LDR    	R5,    =0x1E104177                 
+		    	STR    	R5,    [ R4 ] 
+		
+		    	LDR    	R4,    =EMI_SDCONF2     ; SDRAM参数配置2
+		    	LDR   	R5,    =0x80001860                 
+		    	STR    	R5,    [ R4 ]
+				 
+				ENDIF
+
+; Copy Exception Vectors to Internal RAM 
+
+				IF      :DEF:RAM_INTVEC
+
+				ADR     R8, 	Vectors         ; Source
+				LDR     R9, 	=RAM_BASE       ; Destination
+				LDMIA   R8!, 	{R0-R7}        	; Load Vectors 
+				STMIA   R9!, 	{R0-R7}        	; Store Vectors 
+				LDMIA   R8!, 	{R0-R7}        	; Load Handler Addresses 
+				STMIA   R9!, 	{R0-R7}        	; Store Handler Addresses
+
+				ENDIF
 
 ; Remap on-chip RAM to address 0
 
-	IF      :DEF:REMAP
-		LDR     R0, 	=EMI_REMAPCONF
-		MOV     R1, 	#0x80000000
-		STR     R1, 	[R0, #0]   ; Remap
-	ENDIF
-
-
-; Setup Stack for each mode
-
-		LDR     R0, 	=Stack_Top
-
-;  Enter Undefined Instruction Mode and set its Stack Pointer
-		MSR     CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
-		MOV     SP, 	R0
-		SUB     R0, R0, #UND_Stack_Size
-
-;  Enter Abort Mode and set its Stack Pointer
-		MSR     CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
-		MOV     SP, 	R0
-		SUB     R0, R0, #ABT_Stack_Size
-
-;  Enter FIQ Mode and set its Stack Pointer
-		MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
-		MOV     SP, 	R0
-		SUB     R0, R0, #FIQ_Stack_Size
+				IF      :DEF:REMAP
 
-;  Enter IRQ Mode and set its Stack Pointer
-		MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
-		MOV     SP, 	R0
-		SUB     R0, R0, #IRQ_Stack_Size
+				LDR     R0, 	=EMI_REMAPCONF
+				IF		:DEF:RAM_INTVEC
+				MOV     R1, 	#0x80000000
+				ELSE
+				MOV		R1,		#0x0000000b
+				ENDIF
+				STR     R1, 	[R0, #0]   ; Remap
 
-;  Enter Supervisor Mode and set its Stack Pointer
-		MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
-		MOV     SP, 	R0
-	 	SUB     R0, R0, #SVC_Stack_Size
+				ENDIF
 
-;  Enter User Mode and set its Stack Pointer
-	; MSR     CPSR_c, #Mode_USR
-	IF      :DEF:__MICROLIB
-
-		EXPORT __initial_sp
+;***************************************************************
+;* Open irq interrupt											 
+;***************************************************************
 	
-	ELSE
-
-	; No usr mode stack here.
-	;MOV     SP, R0
-	;SUB     SL, SP, #USR_Stack_Size
-
-	ENDIF
-
+			    MRS		R4, cpsr
+			    BIC		R4, R4, #0x80  		    ; set bit7 to zero
+			    MSR		cpsr_c, R4
 
 ; Enter the C code
-
-		IMPORT  __main
-		LDR     R0, 	=__main
-		BX      R0
-
-	IMPORT rt_interrupt_enter
-	IMPORT rt_interrupt_leave
-	IMPORT rt_thread_switch_interrput_flag
-	IMPORT rt_interrupt_from_thread
-	IMPORT rt_interrupt_to_thread
-	IMPORT rt_hw_trap_irq
-	IMPORT rt_hw_trap_abort
-	IMPORT rt_interrupt_nest
-
-Abort_Handler	PROC
-		EXPORT	Abort_Handler
-		STMFD	SP!, 	{R0-R12,LR}
-		LDR		R0, 	=rt_interrupt_nest
-		LDR		R1, 	[R0]
-		CMP		R1, 	#0
-DeadLoop	BHI	DeadLoop    ; Abort happened in irq mode, halt system.
-		BL		rt_interrupt_enter
-		BL		rt_hw_trap_abort
-		BL		rt_interrupt_leave
-		B		SWITCH
-				ENDP
-				
-IRQ_Handler		PROC
-		EXPORT IRQ_Handler
-		STMFD	SP!,	{R0-R12,LR}
-		BL		rt_interrupt_enter
-		BL		rt_hw_trap_irq
-		BL		rt_interrupt_leave
-
-				; if rt_thread_switch_interrput_flag set, jump to
-				; rt_hw_context_switch_interrupt_do and don't return
-SWITCH			
-		LDR		R0, 	=rt_thread_switch_interrput_flag
-		LDR		R1, 	[R0]
-		CMP		R1, 	#1
-		BEQ		rt_hw_context_switch_interrupt_do
-
-		LDMFD	SP!, 	{R0-R12,LR}
-		SUBS	PC, 	LR, #4
-	ENDP
+				IMPORT  __main
+				LDR		R0,=__main
+				BX		R0
+
+
+                IMPORT rt_interrupt_enter
+                IMPORT rt_interrupt_leave
+                IMPORT rt_thread_switch_interrput_flag
+                IMPORT rt_interrupt_from_thread
+                IMPORT rt_interrupt_to_thread
+                IMPORT rt_hw_trap_irq
+
+IRQ_Handler     PROC
+                EXPORT IRQ_Handler
+                STMFD   sp!, {r0-r12,lr}
+                BL  rt_interrupt_enter
+                BL  rt_hw_trap_irq
+                BL  rt_interrupt_leave
+
+                ; if rt_thread_switch_interrput_flag set, jump to
+                ; rt_hw_context_switch_interrupt_do and don't return
+                LDR r0, =rt_thread_switch_interrput_flag
+                LDR r1, [r0]
+                CMP r1, #1
+                BEQ rt_hw_context_switch_interrupt_do
+
+                LDMFD   sp!, {r0-r12,lr}
+                SUBS    pc, lr, #4
+                ENDP
 
 ; /*
 ; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
 ; */
-rt_hw_context_switch_interrupt_do	PROC
-		EXPORT rt_hw_context_switch_interrupt_do
-		MOV		r1,  #0			; clear flag
-		STR		r1,  [r0]
-
-		LDMFD	sp!, {r0-r12,lr}; reload saved registers
-		STMFD	sp!, {r0-r3}	; save r0-r3
-		MOV		r1,  sp
-		ADD		sp,  sp, #16	; restore sp
-		SUB		r2,  lr, #4		; save old task's pc to r2
-
-		MRS		r3,  spsr		; get cpsr of interrupt thread
-
-		; switch to SVC mode and no interrupt
-		MSR     cpsr_c, #I_Bit:OR:F_Bit:OR:Mode_SVC
-
-		STMFD	sp!, {r2}		; push old task's pc
-		STMFD	sp!, {r4-r12,lr}; push old task's lr,r12-r4
-		MOV		r4,  r1			; Special optimised code below
-		MOV		r5,  r3
-		LDMFD	r4!, {r0-r3}
-		STMFD	sp!, {r0-r3}	; push old task's r3-r0
-		STMFD	sp!, {r5}		; push old task's cpsr
-		MRS		r4,  spsr
-		STMFD	sp!, {r4}		; push old task's spsr
-
-		LDR		r4,  =rt_interrupt_from_thread
-		LDR		r5,  [r4]
-		STR		sp,  [r5]		; store sp in preempted tasks's TCB
-
-		LDR		r6,  =rt_interrupt_to_thread
-		LDR		r6,  [r6]
-		LDR		sp,  [r6]		; get new task's stack pointer
-			
-		LDMFD	sp!, {r4}		; pop new task's spsr
-		MSR		spsr_cxsf, r4
-		LDMFD	sp!, {r4}		; pop new task's psr
-		MSR		cpsr_cxsf, r4
- 	
-		LDMFD	sp!, {r0-r12,lr,pc}	; pop new task's r0-r12,lr & pc
-		ENDP
-
-	IF      :DEF:__MICROLIB
-
-		EXPORT  __heap_base
-		EXPORT  __heap_limit
-
-	ELSE
+rt_hw_context_switch_interrupt_do   PROC
+                EXPORT rt_hw_context_switch_interrupt_do
+                MOV     r1,  #0         ; clear flag
+                STR     r1,  [r0]
+
+                LDMFD   sp!, {r0-r12,lr}; reload saved registers
+                STMFD   sp!, {r0-r3}    ; save r0-r3
+                MOV     r1,  sp
+                ADD     sp,  sp, #16    ; restore sp
+                SUB     r2,  lr, #4     ; save old task's pc to r2
+
+                MRS     r3,  spsr       ; get cpsr of interrupt thread
+
+                ; switch to SVC mode and no interrupt
+                MSR     cpsr_c, #I_Bit :OR F_Bit :OR Mode_SVC
+
+                STMFD   sp!, {r2}       ; push old task's pc
+                STMFD   sp!, {r4-r12,lr}; push old task's lr,r12-r4
+                MOV     r4,  r1         ; Special optimised code below
+                MOV     r5,  r3
+                LDMFD   r4!, {r0-r3}
+                STMFD   sp!, {r0-r3}    ; push old task's r3-r0
+                STMFD   sp!, {r5}       ; push old task's cpsr
+                MRS     r4,  spsr
+                STMFD   sp!, {r4}       ; push old task's spsr
+
+                LDR     r4,  =rt_interrupt_from_thread
+                LDR     r5,  [r4]
+                STR     sp,  [r5]       ; store sp in preempted tasks's TCB
+
+                LDR     r6,  =rt_interrupt_to_thread
+                LDR     r6,  [r6]
+                LDR     sp,  [r6]       ; get new task's stack pointer
+
+                LDMFD   sp!, {r4}       ; pop new task's spsr
+                MSR     spsr_cxsf, r4
+                LDMFD   sp!, {r4}       ; pop new task's psr
+                MSR     cpsr_cxsf, r4
+
+                LDMFD   sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc
+                ENDP
+
+
+
+				ALIGN		
+				IF      :DEF:__MICROLIB
+		
+				EXPORT  __heap_base
+				EXPORT  __heap_limit
+				EXPORT __initial_sp
+		
+				ELSE	;__MICROLIB 
 ; User Initial Stack & Heap
-		AREA    |.text|, CODE, READONLY
-
-		IMPORT  __use_two_region_memory
-		EXPORT  __user_initial_stackheap
+				AREA    |.text|, CODE, READONLY
+		
+				IMPORT  __use_two_region_memory
+				EXPORT  __user_initial_stackheap
 __user_initial_stackheap
-
-		LDR     R0, =  Heap_Mem
-		LDR     R1, = (Stack_Mem + IRQ_Stack_Size)
-		LDR     R2, = (Heap_Mem +      Heap_Size)
-		LDR     R3, = Stack_Mem
-		BX      LR
-	ENDIF
-
-	END
+		
+				LDR     R0, =  Heap_Mem
+				LDR     R1, = (Svc_Stack + 	   Svc_Stack_Size)
+				LDR     R2, = (Heap_Mem +      Heap_Size)
+				LDR     R3, = Svc_Stack
+				BX      LR
+				ALIGN
+				ENDIF
+				END

libcpu/arm/sep4020/trap.c

@@ -9,58 +9,155 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2006-08-25     Bernard      first version
- * 2010-03-18     zchong       for sep4020
+ * 2006-03-13     Bernard      first version
+ * 2006-05-27     Bernard      add skyeye support
+ * 2007-11-19     Yi.Qiu       fix rt_hw_trap_irq function
  */
 
 #include <rtthread.h>
 #include <rthw.h>
 
-#include "sep4020.h"
+#include <sep4020.h>
 
 /**
- * @addtogroup SEP4020
+ * @addtogroup S3C24X0
  */
 /*@{*/
 
-extern rt_isr_handler_t isr_table[];
-
-void rt_hw_trap_irq()
-{
-	rt_uint32_t intstat,intnum;
-    rt_uint8_t i = 0;
+extern struct rt_thread *rt_current_thread;
+
+/**
+ * this function will show registers of CPU
+ *
+ * @param regs the registers point
+ */
+
+void rt_hw_show_register (struct rt_hw_register *regs)
+{
+	rt_kprintf("Execption:\n");
+	rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+	rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+	rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+	rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+	rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+	rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+}
+
+/**
+ * When ARM7TDMI comes across an instruction which it cannot handle,
+ * it takes the undefined instruction trap.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_udef(struct rt_hw_register *regs)
+{
+	rt_hw_show_register(regs);
+
+	rt_kprintf("undefined instruction\n");
+	rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+	rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry);
+
+	rt_hw_cpu_shutdown();
+}
+
+/**
+ * The software interrupt instruction (SWI) is used for entering
+ * Supervisor mode, usually to request a particular supervisor
+ * function.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_swi(struct rt_hw_register *regs)
+{
+	rt_hw_show_register(regs);
+
+	rt_kprintf("software interrupt\n");
+	rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during an instruction prefetch.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_pabt(struct rt_hw_register *regs)
+{
+	rt_hw_show_register(regs);
+
+	rt_kprintf("prefetch abort\n");
+	rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+	rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry);
+
+	rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during a data access.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_dabt(struct rt_hw_register *regs)
+{
+	rt_hw_show_register(regs);
+
+	rt_kprintf("data abort\n");
+	rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+	rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry);
+
+	rt_hw_cpu_shutdown();
+}
+
+/**
+ * Normally, system will never reach here
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_resv(struct rt_hw_register *regs)
+{
+	rt_kprintf("not used\n");
+	rt_hw_show_register(regs);
+	rt_hw_cpu_shutdown();
+}
+
+extern rt_isr_handler_t isr_table[];
+
+void rt_hw_trap_irq()
+{
+	unsigned long intstat;
+	rt_uint32_t i = 0;
 	rt_isr_handler_t isr_func;
-    
-    /* get interrupt source */
-	intstat = INTC_IFSR;
-
-	intnum = intstat;
-    if (intstat == INTGLOBAL) return;
-
-	while(intnum != 0x00000001)
+
+	/*Get the final intrrupt source*/
+	intstat = *(RP)(INTC_IFSR);;
+
+	/*Shift to get the intrrupt number*/
+ 	while(intstat != 1)
 	{
-		intnum = intnum>>1;
+		intstat = intstat >> 1;
 		i++;
-	}
-	/* get interrupt service routine */
-	isr_func = isr_table[i];
-
-	/* turn to interrupt service routine */
-	isr_func(intstat);
-
+	} 
+	/* get interrupt service routine */
+	isr_func = isr_table[i];
+
+	/* turn to interrupt service routine */
+	isr_func(i);
 }
 
 void rt_hw_trap_fiq()
 {
-    rt_kprintf("fast interrupt request\n");
-}
-
-extern struct rt_thread* rt_current_thread;
-void rt_hw_trap_abort()
-{
-	rt_kprintf("Abort occured!!! Thread [%s] suspended.\n",rt_current_thread->name);
-	rt_thread_suspend(rt_current_thread);
-	rt_schedule();
-
+	rt_kprintf("fast interrupt request\n");
 }
+
 /*@}*/