add support for SmartFusion2 family FPGA

bsp/smartfusion2/CMSIS/core_cm3.c

+/**************************************************************************//**
+ * @file     core_cm3.c
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Source File
+ * @version  V1.30
+ * @date     30. October 2009
+ *
+ * @note
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+/*******************************************************************************
+ * Microsemi SoC Products Group SVN revision number for the purpose of tracking
+ * changes done to original file supplied by ARM:
+ * SVN $Revision: 6671 $
+ * SVN $Date: 2014-07-04 12:15:22 +0100 (Fri, 04 Jul 2014) $
+ ******************************************************************************/
+
+#include <stdint.h>
+
+/* define compiler specific symbols */
+#if defined ( __CC_ARM   )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined   (  __GNUC__  )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined   (  __TASKING__  )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+
+#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+__ASM uint32_t __get_PSP(void)
+{
+  mrs r0, psp
+  bx lr
+}
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP 
+ * (process stack pointer) Cortex processor register
+ */
+__ASM void __set_PSP(uint32_t topOfProcStack)
+{
+  msr psp, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+__ASM uint32_t __get_MSP(void)
+{
+  mrs r0, msp
+  bx lr
+}
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP 
+ * (main stack pointer) Cortex processor register
+ */
+__ASM void __set_MSP(uint32_t mainStackPointer)
+{
+  msr msp, r0
+  bx lr
+}
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param   value  value to reverse
+ * @return         reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+__ASM uint32_t __REV16(uint16_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+
+/**
+ * @brief  Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param   value  value to reverse
+ * @return         reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+__ASM int32_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+
+
+#if (__ARMCC_VERSION < 400000)
+
+/**
+ * @brief  Remove the exclusive lock created by ldrex
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+__ASM void __CLREX(void)
+{
+  clrex
+}
+
+/**
+ * @brief  Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+__ASM uint32_t  __get_BASEPRI(void)
+{
+  mrs r0, basepri
+  bx lr
+}
+
+/**
+ * @brief  Set the Base Priority value
+ *
+ * @param  basePri  BasePriority
+ *
+ * Set the base priority register
+ */
+__ASM void __set_BASEPRI(uint32_t basePri)
+{
+  msr basepri, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+__ASM uint32_t __get_PRIMASK(void)
+{
+  mrs r0, primask
+  bx lr
+}
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param  priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+__ASM void __set_PRIMASK(uint32_t priMask)
+{
+  msr primask, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+__ASM uint32_t  __get_FAULTMASK(void)
+{
+  mrs r0, faultmask
+  bx lr
+}
+
+/**
+ * @brief  Set the Fault Mask value
+ *
+ * @param  faultMask  faultMask value
+ *
+ * Set the fault mask register
+ */
+__ASM void __set_FAULTMASK(uint32_t faultMask)
+{
+  msr faultmask, r0
+  bx lr
+}
+
+/**
+ * @brief  Return the Control Register value
+ * 
+ * @return Control value
+ *
+ * Return the content of the control register
+ */
+__ASM uint32_t __get_CONTROL(void)
+{
+  mrs r0, control
+  bx lr
+}
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+__ASM void __set_CONTROL(uint32_t control)
+{
+  msr control, r0
+  bx lr
+}
+
+#endif /* __ARMCC_VERSION  */ 
+
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+#pragma diag_suppress=Pe940
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+#if (__VER__ < 6020000)
+uint32_t __get_PSP(void)
+{
+  __ASM("mrs r0, psp");
+  __ASM("bx lr");
+}
+#endif
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP 
+ * (process stack pointer) Cortex processor register
+ */
+#if (__VER__ < 6020000)
+void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM("msr psp, r0");
+  __ASM("bx lr");
+}
+#endif
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+#if (__VER__ < 6020000)
+uint32_t __get_MSP(void)
+{
+  __ASM("mrs r0, msp");
+  __ASM("bx lr");
+}
+#endif
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP 
+ * (main stack pointer) Cortex processor register
+ */
+#if (__VER__ < 6020000)
+void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM("msr msp, r0");
+  __ASM("bx lr");
+}
+#endif
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+#if (__VER__ < 6020000)
+uint32_t __REV16(uint16_t value)
+{
+  __ASM("rev16 r0, r0");
+  __ASM("bx lr");
+}
+#endif
+
+/**
+ * @brief  Reverse bit order of value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse bit order of value
+ */
+#if (__VER__ < 6020000)
+uint32_t __RBIT(uint32_t value)
+{
+  __ASM("rbit r0, r0");
+  __ASM("bx lr");
+}
+#endif
+
+/**
+ * @brief  LDR Exclusive (8 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 8 bit values)
+ */
+#if (__VER__ < 6020000)
+uint8_t __LDREXB(uint8_t *addr)
+{
+  __ASM("ldrexb r0, [r0]");
+  __ASM("bx lr"); 
+}
+#endif
+
+/**
+ * @brief  LDR Exclusive (16 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+#if (__VER__ < 6020000)
+uint16_t __LDREXH(uint16_t *addr)
+{
+  __ASM("ldrexh r0, [r0]");
+  __ASM("bx lr");
+}
+#endif
+
+/**
+ * @brief  LDR Exclusive (32 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+  __ASM("ldrex r0, [r0]");
+  __ASM("bx lr");
+}
+
+/**
+ * @brief  STR Exclusive (8 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+#if (__VER__ < 6020000)
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+  __ASM("strexb r0, r0, [r1]");
+  __ASM("bx lr");
+}
+#endif
+
+/**
+ * @brief  STR Exclusive (16 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+#if (__VER__ < 6020000)
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+  __ASM("strexh r0, r0, [r1]");
+  __ASM("bx lr");
+}
+#endif
+
+/**
+ * @brief  STR Exclusive (32 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+  __ASM("strex r0, r0, [r1]");
+  __ASM("bx lr");
+}
+
+#pragma diag_default=Pe940
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/**
+ * @brief  Return the Process Stack Pointer
+ *
+ * @return ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void) __attribute__( ( naked ) );
+uint32_t __get_PSP(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, psp\n\t" 
+                  "MOV r0, %0 \n\t"
+                  "BX  lr     \n\t"  : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Process Stack Pointer
+ *
+ * @param  topOfProcStack  Process Stack Pointer
+ *
+ * Assign the value ProcessStackPointer to the MSP 
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack) __attribute__( ( naked ) );
+void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n\t"
+                  "BX  lr     \n\t" : : "r" (topOfProcStack) );
+}
+
+/**
+ * @brief  Return the Main Stack Pointer
+ *
+ * @return Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void) __attribute__( ( naked ) );
+uint32_t __get_MSP(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, msp\n\t" 
+                  "MOV r0, %0 \n\t"
+                  "BX  lr     \n\t"  : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Main Stack Pointer
+ *
+ * @param  topOfMainStack  Main Stack Pointer
+ *
+ * Assign the value mainStackPointer to the MSP 
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack) __attribute__( ( naked ) );
+void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n\t"
+                  "BX  lr     \n\t" : : "r" (topOfMainStack) );
+}
+
+/**
+ * @brief  Return the Base Priority value
+ *
+ * @return BasePriority
+ *
+ * Return the content of the base priority register
+ */
+uint32_t __get_BASEPRI(void)
+{
+  uint32_t result=0;
+  
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Base Priority value
+ *
+ * @param  basePri  BasePriority
+ *
+ * Set the base priority register
+ */
+void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+/**
+ * @brief  Return the Priority Mask value
+ *
+ * @return PriMask
+ *
+ * Return state of the priority mask bit from the priority mask register
+ */
+uint32_t __get_PRIMASK(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Priority Mask value
+ *
+ * @param  priMask  PriMask
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+/**
+ * @brief  Return the Fault Mask value
+ *
+ * @return FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result=0;
+  
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Fault Mask value
+ *
+ * @param  faultMask  faultMask value
+ *
+ * Set the fault mask register
+ */
+void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+/**
+ * @brief  Return the Control Register value
+* 
+*  @return Control value
+ *
+ * Return the content of the control register
+ */
+uint32_t __get_CONTROL(void)
+{
+  uint32_t result=0;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+/**
+ * @brief  Set the Control Register value
+ *
+ * @param  control  Control value
+ *
+ * Set the control register
+ */
+void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/**
+ * @brief  Reverse byte order in integer value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in integer value
+ */
+uint32_t __REV(uint32_t value)
+{
+  uint32_t result=0;
+  
+  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+/**
+ * @brief  Reverse byte order in unsigned short value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+  uint32_t result=0;
+  
+  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+/**
+ * @brief  Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+int32_t __REVSH(int16_t value)
+{
+  uint32_t result=0;
+  
+  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+/**
+ * @brief  Reverse bit order of value
+ *
+ * @param  value  value to reverse
+ * @return        reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result=0;
+  
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+/**
+ * @brief  LDR Exclusive (8 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 8 bit value
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+    uint8_t result=0;
+  
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+/**
+ * @brief  LDR Exclusive (16 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 16 bit values
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+    uint16_t result=0;
+  
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+/**
+ * @brief  LDR Exclusive (32 bit)
+ *
+ * @param  *addr  address pointer
+ * @return        value of (*address)
+ *
+ * Exclusive LDR command for 32 bit values
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+    uint32_t result=0;
+  
+   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+/**
+ * @brief  STR Exclusive (8 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 8 bit values
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+   uint32_t result=0;
+  
+   __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+/**
+ * @brief  STR Exclusive (16 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 16 bit values
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+   uint32_t result=0;
+  
+   __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+/**
+ * @brief  STR Exclusive (32 bit)
+ *
+ * @param  value  value to store
+ * @param  *addr  address pointer
+ * @return        successful / failed
+ *
+ * Exclusive STR command for 32 bit values
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+   uint32_t result=0;
+  
+   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif

bsp/smartfusion2/CMSIS/hw_reg_io.h

+/*******************************************************************************
+ * (c) Copyright 2011-2013 Microsemi SoC Products Group. All rights reserved.
+ *
+ *  SmartFusion2 Cortex Microcontroller Software Interface - Peripheral
+ *  Access Layer.
+ *
+ *  This file provides interfaces to perform register and register bit level 
+ *  read / write operations. These interfaces support bit-banding in case of 
+ *  Cortex-M3 CPU.
+ *
+ * SVN $Revision: 5263 $
+ * SVN $Date: 2013-03-21 14:44:58 +0000 (Thu, 21 Mar 2013) $
+ */
+
+#ifndef HW_REG_IO_H_
+#define HW_REG_IO_H_
+
+#include <stdint.h>                       /* Include standard types */
+
+#if defined ( __CC_ARM   )
+  #define __INLINE         __inline       /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __INLINE        inline          /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined   (  __GNUC__  )
+  #define __INLINE        inline          /*!< inline keyword for GNU Compiler       */
+#endif
+
+/*****************************************************************************************
+ * Definitions for register access
+ */
+
+#define HW_REG(addr)            (*((volatile uint32_t *) (addr)))
+
+static __INLINE void write_reg32(volatile uint32_t * reg, uint32_t val)
+{
+    HW_REG(reg) = val;
+}
+static __INLINE void write_reg16(volatile uint16_t * reg, uint16_t val)
+{
+    HW_REG(reg) = val;
+}
+static __INLINE void write_reg8(volatile uint8_t * reg, uint8_t val)
+{
+    HW_REG(reg) = val;
+}
+
+static __INLINE uint32_t read_reg32(volatile uint32_t * reg)
+{
+    return ( HW_REG(reg) );
+}
+static __INLINE uint16_t read_reg16(volatile uint16_t * reg)
+{
+    return ( HW_REG(reg) );
+}
+static __INLINE uint8_t read_reg8(volatile uint8_t * reg)
+{
+    return ( HW_REG(reg) );
+}
+/*****************************************************************************************
+ * Definitions for register bits access using bit-band aliases for Cortex-M3 
+ */
+#define BITBAND(addr,bitnum)    (((uint32_t)addr & 0xF0000000)+0x02000000+(((uint32_t)addr & 0xFFFFF)<<5)+(bitnum<<2))
+#define HW_REG_BIT(reg,bitnum)  (*(volatile unsigned int *)((BITBAND(reg,bitnum))))
+
+/*****************************************************************************************
+ * Functions to set a bit field in Cortex-M3 
+ */
+static __INLINE void set_bit_reg32(volatile uint32_t * reg, uint8_t bit)
+{
+    HW_REG_BIT(reg,bit) = 0x1;
+}
+static __INLINE void set_bit_reg16(volatile uint16_t * reg, uint8_t bit)
+{
+    HW_REG_BIT(reg,bit) = 0x1;
+}
+static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
+{
+    HW_REG_BIT(reg,bit) = 0x1;
+}
+/*****************************************************************************************
+ * Functions to clear a bit field in Cortex-M3
+ */
+static __INLINE void clear_bit_reg32(volatile uint32_t * reg, uint8_t bit)
+{
+    HW_REG_BIT(reg,bit) = 0x0;
+}
+static __INLINE void clear_bit_reg16(volatile uint16_t * reg, uint8_t bit)
+{
+    HW_REG_BIT(reg,bit) = 0x0;
+}
+static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
+{
+    HW_REG_BIT(reg,bit) = 0x0;
+}
+/*****************************************************************************************
+ * Functions to read a bit field in Cortex-M3
+ */
+static __INLINE uint8_t read_bit_reg32(volatile uint32_t * reg, uint8_t bit)
+{
+    return (HW_REG_BIT(reg,bit));
+}
+static __INLINE uint8_t read_bit_reg16(volatile uint16_t * reg, uint8_t bit)
+{
+    return (HW_REG_BIT(reg,bit));
+}
+static __INLINE uint8_t read_bit_reg8(volatile uint8_t * reg, uint8_t bit)
+{
+    return (HW_REG_BIT(reg,bit));
+}
+
+#endif /* HW_REG_IO_H_ */

bsp/smartfusion2/CMSIS/mss_assert.h

+/*******************************************************************************
+ * (c) Copyright 2009-2013 Microsemi SoC Products Group. All rights reserved.
+ * 
+ * Assertion implementation.
+ *
+ * This file provides the implementation of the ASSERT macro. This file can be
+ * modified to cater for project specific requirements regarding the way
+ * assertions are handled.
+ *
+ * SVN $Revision: 6422 $
+ * SVN $Date: 2014-05-14 14:37:56 +0100 (Wed, 14 May 2014) $
+ */
+#ifndef __MSS_ASSERT_H_
+#define __MSS_ASSERT_H_
+
+#if defined(NDEBUG)
+
+#define ASSERT(CHECK)
+
+#else   /* NDEBUG */
+
+#include <assert.h>
+
+#if defined ( __GNUC__   )
+
+/*
+ * SoftConsole assertion handling
+ */
+#define ASSERT(CHECK)  \
+    do { \
+        if (!(CHECK)) \
+        { \
+            __asm volatile ("BKPT\n\t"); \
+        } \
+    } while (0);
+    
+#elif defined ( __ICCARM__ )
+/*
+ * IAR Embedded Workbench assertion handling.
+ * Call C library assert function which should result in error message
+ * displayed in debugger.
+ */
+#define ASSERT(X)   assert(X)
+
+#else
+/*
+ * Keil assertion handling.
+ * Call C library assert function which should result in error message
+ * displayed in debugger.
+ */
+
+#ifndef __MICROLIB
+  #define ASSERT(X)   assert(X)
+#else
+  #define ASSERT(X)
+#endif
+
+#endif  /* Tool Chain */
+
+#endif  /* NDEBUG */
+
+#endif  /* __MSS_ASSERT_H_ */

bsp/smartfusion2/CMSIS/startup_arm/low_level_init.c

+/*******************************************************************************
+ * (c) Copyright 2014 Microsemi SoC Products Group. All rights reserved.
+ *
+ *  Keil-MDK specific system initialization.
+ *
+ * SVN $Revision: 7375 $
+ * SVN $Date: 2015-05-01 14:57:40 +0100 (Fri, 01 May 2015) $
+ */
+#ifdef MSCC_NO_RELATIVE_PATHS
+#include "m2sxxx.h"
+#else
+#include "..\m2sxxx.h"
+#endif
+
+#define ENVM_BASE_ADDRESS       0x60000000U
+#define MDDR_BASE_ADDRESS       0xA0000000U
+
+//extern unsigned int Image$$ER_RW$$Base;
+//extern unsigned int Image$$ER_RO$$Base;
+
+/*==============================================================================
+ * The __low_level_init() function is called after SystemInit. Therefore, the
+ * external RAM should be configured at this stage if it is used.
+ */
+/* void low_level_init(void)
+{
+    volatile unsigned int rw_region_base;
+    volatile unsigned int readonly_region_base;
+    
+    rw_region_base = (unsigned int)&Image$$ER_RW$$Base;
+    if (rw_region_base >= MDDR_BASE_ADDRESS)
+    {
+        / --------------------------------------------------------------------------
+         * Remap MDDR to address 0x00000000.
+         /
+        SYSREG->ESRAM_CR = 0u;
+        SYSREG->ENVM_REMAP_BASE_CR = 0u;
+        SYSREG->DDR_CR = 1u;
+    }
+    
+    readonly_region_base = (unsigned int)&Image$$ER_RO$$Base;
+    SCB->VTOR = readonly_region_base;
+}  */
+

bsp/smartfusion2/CMSIS/startup_arm/retarget.c

+/*******************************************************************************
+ * (c) Copyright 2013 Microsemi SoC Products Group.  All rights reserved.
+ *
+ * Redirection of the standard library I/O to one of the SmartFusion2
+ * MMUART.
+ *
+ * SVN $Revision: 7375 $
+ * SVN $Date: 2015-05-01 14:57:40 +0100 (Fri, 01 May 2015) $
+ */
+
+/*==============================================================================
+ * The content of this source file will only be compiled if either one of the
+ * following two defined symbols are defined in the project settings:
+ *  - MICROSEMI_STDIO_THRU_MMUART0
+ *  - MICROSEMI_STDIO_THRU_MMUART1
+ *
+ */
+#ifdef MICROSEMI_STDIO_THRU_MMUART0
+#ifndef MICROSEMI_STDIO_THRU_UART
+#define MICROSEMI_STDIO_THRU_UART
+#endif
+#endif  /* MICROSEMI_STDIO_THRU_MMUART0 */
+
+#ifdef MICROSEMI_STDIO_THRU_MMUART1
+#ifndef MICROSEMI_STDIO_THRU_UART
+#define MICROSEMI_STDIO_THRU_UART
+#endif
+#endif  /* MICROSEMI_STDIO_THRU_MMUART1 */
+
+/*==============================================================================
+ * Actual implementation.
+ */
+#ifdef MICROSEMI_STDIO_THRU_UART
+
+#include <stdio.h>
+#include <rt_misc.h>
+
+#include "m2sxxx.h"
+#include "mss_uart.h"
+#include "core_uart_apb.h"
+
+
+/*
+ * The baud rate will default to 57600 baud if no baud rate is specified though the
+ * MICROSEMI_STDIO_BAUD_RATE define.
+ */
+#ifndef MICROSEMI_STDIO_BAUD_RATE
+#define MICROSEMI_STDIO_BAUD_RATE  MSS_UART_115200_BAUD
+#endif
+
+#ifdef MICROSEMI_STDIO_THRU_MMUART0
+static mss_uart_instance_t * const gp_my_uart = &g_mss_uart0;
+#else
+static mss_uart_instance_t * const gp_my_uart = &g_mss_uart1;
+#endif
+
+/*==============================================================================
+ * Flag used to indicate if the UART driver needs to be initialized.
+ */
+static int g_stdio_uart_init_done = 0;
+
+
+#define LSR_THRE_MASK   0x20u
+
+/*
+ * Disable semihosting apis
+ */
+#pragma import(__use_no_semihosting_swi)
+
+/*==============================================================================
+ * sendchar()
+ */
+int sendchar(int ch)  
+{
+    uint32_t tx_ready;
+	//第一次调用时，初始化串口
+    if(!g_stdio_uart_init_done)
+    {
+        MSS_UART_init(gp_my_uart,
+                      MICROSEMI_STDIO_BAUD_RATE,
+                      MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY);
+        g_stdio_uart_init_done = 1;
+    }
+    do {
+        tx_ready = gp_my_uart->hw_reg->LSR & LSR_THRE_MASK;
+    } while(!tx_ready);
+    gp_my_uart->hw_reg->THR = ch;
+    return (ch);
+}
+
+/*==============================================================================
+ * 
+ */
+struct __FILE { int handle; /* Add whatever you need here */ };
+FILE __stdout;
+FILE __stdin;
+
+
+/*==============================================================================
+ * fputc()
+ */
+int fputc(int ch, FILE *f)
+{
+  return (sendchar(ch));
+}
+
+/*==============================================================================
+ * fgetc()
+ */
+int fgetc(FILE *f)
+{
+    uint8_t rx_size;
+    uint8_t rx_byte;
+    
+    do {
+        rx_size = MSS_UART_get_rx(gp_my_uart, &rx_byte, 1);
+    } while(0u == rx_size);
+
+    return rx_byte;
+}
+
+/*==============================================================================
+ * ferror()
+ */
+int ferror(FILE *f)
+{
+  /* Your implementation of ferror */
+  return EOF;
+}
+
+/*==============================================================================
+ * _ttywrch()
+ */
+void _ttywrch(int ch)
+{
+  sendchar(ch);
+}
+
+/*==============================================================================
+ * _sys_exit()
+ */
+void _sys_exit(int return_code)
+{
+    for(;;)
+    {
+        ;  /* endless loop */
+    }
+}
+
+#endif  /* MICROSEMI_STDIO_THRU_UART */

bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_esram_debug.sct

+;*******************************************************************************
+;  (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
+;  SmartFusion2 scatter file for debugging code executing in internal eSRAM.
+; 
+;  SVN $Revision: 7419 $
+;  SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
+;
+; * Some current (April 2015) dev kit memory map possibilities are
+; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
+; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
+; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
+; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
+; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
+; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
+; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
+; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
+; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
+; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
+; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
+; * --Some older physical memory map possibilities are
+; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
+; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
+; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
+;
+;  Example linker scripts use lowest practicl values so will work accross dev kits
+;  eNVM=256KB  eRAM=64KB  External memory = 64MB  
+
+RAM_LOAD 0x20000000 0x10000
+{
+    ;   First half of RAM allocated to RO Execute and data
+    ER_RO 0x20000000 0x8000
+    {
+       *.o (RESET, +First)
+        *(InRoot$$Sections)
+        .ANY (+RO)
+    }
+    ;   Heap size is defined in startup_m2sxxx.s
+    ;   Heap will be added after RW data in ER_RW unless explicitly 
+    ;   allocated a meemory region in .sct file
+    ;   Stack size is defined in startup_m2sxxx.s
+    ;   Stack will be added after heap in ER_RW unless explicitly 
+    ;   allocated a memory region in .sct file
+    ;   Second half of RAM allocated to RW data, heap and stack
+    ER_RW 0x20008000 0x8000
+    {
+        .ANY (+RW +ZI)
+    }
+}
+

bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_execute_in_place.sct

+;*******************************************************************************
+;  (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
+;  SmartFusion2 scatter file for executing code in internal eNVM.
+; 
+;  SVN $Revision: 7419 $
+;  SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
+;
+; * Some current (April 2015) dev kit memory map possibilities are
+; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
+; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
+; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
+; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
+; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
+; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
+; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
+; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
+; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
+; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
+; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
+; * --Some older physical memory map possibilities are
+; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
+; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
+; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
+;
+;  Example linker scripts use lowest practicl values so will work accross dev kits
+;  eNVM=256KB  eRAM=64KB  External memory = 64MB  
+
+FLASH_LOAD 0x00000000 0x40000		
+{
+;   All R only code/data is located in ENVM
+    ER_RO 0x00000000 0x40000
+    {
+       	*.o (RESET, +First)
+        *(InRoot$$Sections)
+        .ANY (+RO)
+    }
+;   Heap size is defined in startup_m2sxxx.s
+;   Heap will be added after RW data in ER_RW unless explicitly 
+;   allocated a meemory region in .sct file
+;   Stack size is defined in startup_m2sxxx.s
+;   Stack will be added after heap in ER_RW unless explicitly 
+;   allocated a memory region in .sct file
+    ER_RW 0x20000000 0x10000
+    {
+        .ANY (+RW +ZI)
+    }
+}
+

bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_mddr_debug.sct

+;*******************************************************************************
+;  (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
+;  SmartFusion2 scatter file for debugging code executing in external MDDR.
+; 
+;  SVN $Revision: 7419 $
+;  SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
+;
+; * Some current (April 2015) dev kit memory map possibilities are
+; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
+; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
+; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
+; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
+; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
+; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
+; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
+; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
+; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
+; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
+; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
+; * --Some older physical memory map possibilities are
+; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
+; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
+; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
+;
+;  Example linker scripts use lowest practicl values so will work accross dev kits
+;  eNVM=256KB  eRAM=64KB  External memory = 64MB  
+
+; Extern RAM 64M in total
+; allocate 1/2 to progam, 1/2 to variable data
+RAM_LOAD 0x00000000 0x04000000
+{
+;   Total = 64MB (lowest common amount accross dev kits) 32MB - First half of external memory allocated to RO Code
+    ER_RO 0x00000000 0x02000000
+    {
+       *.o (RESET, +First)
+        *(InRoot$$Sections)
+        .ANY (+RO)
+    }
+    ;   Heap size is defined in startup_m2sxxx.s
+    ;   Heap will be added after RW data in ER_RW unless explicitly 
+    ;   allocated a meemory region in .sct file
+    ;   Stack size is defined in startup_m2sxxx.s
+    ;   Stack will be added after heap in ER_RW unless explicitly 
+    ;   allocated a memory region in .sct file as is the case below
+    STACKS 0x20000000 UNINIT
+    {
+        startup_m2sxxx.o (STACK)
+    }
+;   32 MB- Second half of external memory allocated to RW data
+    ER_RW 0xA2000000 0x02000000
+    {
+        .ANY (+RW +ZI)
+    }
+}

bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_relocate_to_external_ram.sct

+;*******************************************************************************
+;  (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
+;  SmartFusion2 scatter file for relocating code to external RAM.
+; 
+;  SVN $Revision: 7419 $
+;  SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
+;
+; * Some current (April 2015) dev kit memory map possibilities are
+; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
+; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
+; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
+; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
+; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
+; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
+; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
+; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
+; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
+; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
+; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
+; * --Some older physical memory map possibilities are
+; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
+; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
+; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
+;
+;  Example linker scripts use lowest practicl values so will work accross dev kits
+;  eNVM=256KB  eRAM=64KB  External memory = 64MB  
+
+FLASH_LOAD 0x60000000 0x40000
+{
+;   All code required on start-up located here before relocation has occured
+    ER_RO 0x60000000 0x40000
+    {
+        *.o (RESET, +First)
+        *(InRoot$$Sections)
+        startup_m2sxxx.o
+        system_m2sxxx.o
+        sys_config.o
+        low_level_init.o
+	sys_config_SERDESIF_?.o
+	mscc_post_hw_cfg_init.o			
+    	ecc_error_handler.o		
+    }
+    ;   MDDR_RAM 0xA0000000 0x4000000  	
+    ;   -MDDR is mapped to address space from 0 on startup
+    ;   This allows the use of cache which is restriced to this area.
+    ;   Code is copied to RAM_EXEC space on startup by boot code.
+    RAM_EXEC 0x00000000 0x00040000	
+    {
+        .ANY (+RO)
+    }
+    ;   Heap size is defined in startup_m2sxxx.s
+    ;   Heap will be added after RW data in ER_RW unless explicitly 
+    ;   allocated a meemory region in .sct file
+    ;   Stack size is defined in startup_m2sxxx.s
+    ;   Stack will be added after heap in ER_RW unless explicitly 
+    ;   allocated a memory region in .sct file as is the case below
+    STACKS 0x20000000 UNINIT
+    {
+        startup_m2sxxx.o (STACK)
+    }
+;    All internal RAM has been allocatd to the stack
+;    INTERNAL_RAM 0x20008000 0x10000
+;    {
+;        .ANY (+RW +ZI)
+;    }
+
+;    MDDR_RAM 0xA0000000 0x4000000  So use top half of this for RW data
+;    Bottom half has been assigned to R only code already
+    ER_RW 0xA2000000 0x2000000
+    {
+        .ANY (+RW +ZI)
+    }
+}
+

bsp/smartfusion2/CMSIS/sys_init_cfg_types.h

+/*******************************************************************************
+ * (c) Copyright 2012 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ *  
+ *
+ * SVN $Revision: 4410 $
+ * SVN $Date: 2012-07-16 14:36:17 +0100 (Mon, 16 Jul 2012) $
+ */
+ 
+#ifndef SYSTEM_INIT_CFG_TYPES_H_
+#define SYSTEM_INIT_CFG_TYPES_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+/*============================================================================*/
+/*                              DDR Configuration                             */
+/*============================================================================*/
+typedef struct
+{
+    /*--------------------------------------------------------------------------
+     * DDR Controller registers.
+     */
+    struct
+    {
+        uint16_t DYN_SOFT_RESET_CR;
+        uint16_t RESERVED0;
+        uint16_t DYN_REFRESH_1_CR;
+        uint16_t DYN_REFRESH_2_CR;
+        uint16_t DYN_POWERDOWN_CR;
+        uint16_t DYN_DEBUG_CR;
+        uint16_t MODE_CR;
+        uint16_t ADDR_MAP_BANK_CR;
+        uint16_t ECC_DATA_MASK_CR;
+        uint16_t ADDR_MAP_COL_1_CR;
+        uint16_t ADDR_MAP_COL_2_CR;
+        uint16_t ADDR_MAP_ROW_1_CR;
+        uint16_t ADDR_MAP_ROW_2_CR;
+        uint16_t INIT_1_CR;
+        uint16_t CKE_RSTN_CYCLES_1_CR;
+        uint16_t CKE_RSTN_CYCLES_2_CR;
+        uint16_t INIT_MR_CR;
+        uint16_t INIT_EMR_CR;
+        uint16_t INIT_EMR2_CR;
+        uint16_t INIT_EMR3_CR;
+        uint16_t DRAM_BANK_TIMING_PARAM_CR;
+        uint16_t DRAM_RD_WR_LATENCY_CR;
+        uint16_t DRAM_RD_WR_PRE_CR;
+        uint16_t DRAM_MR_TIMING_PARAM_CR;
+        uint16_t DRAM_RAS_TIMING_CR;
+        uint16_t DRAM_RD_WR_TRNARND_TIME_CR;
+        uint16_t DRAM_T_PD_CR;
+        uint16_t DRAM_BANK_ACT_TIMING_CR;
+        uint16_t ODT_PARAM_1_CR;
+        uint16_t ODT_PARAM_2_CR;
+        uint16_t ADDR_MAP_COL_3_CR;
+        uint16_t MODE_REG_RD_WR_CR;
+        uint16_t MODE_REG_DATA_CR;
+        uint16_t PWR_SAVE_1_CR;
+        uint16_t PWR_SAVE_2_CR;
+        uint16_t ZQ_LONG_TIME_CR;
+        uint16_t ZQ_SHORT_TIME_CR;
+        uint16_t ZQ_SHORT_INT_REFRESH_MARGIN_1_CR;
+        uint16_t ZQ_SHORT_INT_REFRESH_MARGIN_2_CR;
+        uint16_t PERF_PARAM_1_CR;
+        uint16_t HPR_QUEUE_PARAM_1_CR;
+        uint16_t HPR_QUEUE_PARAM_2_CR;
+        uint16_t LPR_QUEUE_PARAM_1_CR;
+        uint16_t LPR_QUEUE_PARAM_2_CR;
+        uint16_t WR_QUEUE_PARAM_CR;
+        uint16_t PERF_PARAM_2_CR;
+        uint16_t PERF_PARAM_3_CR;
+        uint16_t DFI_RDDATA_EN_CR;
+        uint16_t DFI_MIN_CTRLUPD_TIMING_CR;
+        uint16_t DFI_MAX_CTRLUPD_TIMING_CR;
+        uint16_t DFI_WR_LVL_CONTROL_1_CR;
+        uint16_t DFI_WR_LVL_CONTROL_2_CR;
+        uint16_t DFI_RD_LVL_CONTROL_1_CR;
+        uint16_t DFI_RD_LVL_CONTROL_2_CR;
+        uint16_t DFI_CTRLUPD_TIME_INTERVAL_CR;
+        uint16_t DYN_SOFT_RESET_CR2;
+        uint16_t AXI_FABRIC_PRI_ID_CR;
+    } ddrc;
+    
+    /*--------------------------------------------------------------------------
+     * DDR PHY configuration registers
+     */
+    struct 
+    {
+        uint16_t LOOPBACK_TEST_CR;
+        uint16_t BOARD_LOOPBACK_CR;
+        uint16_t CTRL_SLAVE_RATIO_CR;
+        uint16_t CTRL_SLAVE_FORCE_CR;
+        uint16_t CTRL_SLAVE_DELAY_CR;
+        uint16_t DATA_SLICE_IN_USE_CR;
+        uint16_t LVL_NUM_OF_DQ0_CR;
+        uint16_t DQ_OFFSET_1_CR;
+        uint16_t DQ_OFFSET_2_CR;
+        uint16_t DQ_OFFSET_3_CR;
+        uint16_t DIS_CALIB_RST_CR;
+        uint16_t DLL_LOCK_DIFF_CR;
+        uint16_t FIFO_WE_IN_DELAY_1_CR;
+        uint16_t FIFO_WE_IN_DELAY_2_CR;
+        uint16_t FIFO_WE_IN_DELAY_3_CR;
+        uint16_t FIFO_WE_IN_FORCE_CR;
+        uint16_t FIFO_WE_SLAVE_RATIO_1_CR;
+        uint16_t FIFO_WE_SLAVE_RATIO_2_CR;
+        uint16_t FIFO_WE_SLAVE_RATIO_3_CR;
+        uint16_t FIFO_WE_SLAVE_RATIO_4_CR;
+        uint16_t GATELVL_INIT_MODE_CR;
+        uint16_t GATELVL_INIT_RATIO_1_CR;
+        uint16_t GATELVL_INIT_RATIO_2_CR;
+        uint16_t GATELVL_INIT_RATIO_3_CR;
+        uint16_t GATELVL_INIT_RATIO_4_CR;
+        uint16_t LOCAL_ODT_CR;
+        uint16_t INVERT_CLKOUT_CR;
+        uint16_t RD_DQS_SLAVE_DELAY_1_CR;
+        uint16_t RD_DQS_SLAVE_DELAY_2_CR;
+        uint16_t RD_DQS_SLAVE_DELAY_3_CR;
+        uint16_t RD_DQS_SLAVE_FORCE_CR;
+        uint16_t RD_DQS_SLAVE_RATIO_1_CR;
+        uint16_t RD_DQS_SLAVE_RATIO_2_CR;
+        uint16_t RD_DQS_SLAVE_RATIO_3_CR;
+        uint16_t RD_DQS_SLAVE_RATIO_4_CR;
+        uint16_t WR_DQS_SLAVE_DELAY_1_CR;
+        uint16_t WR_DQS_SLAVE_DELAY_2_CR;
+        uint16_t WR_DQS_SLAVE_DELAY_3_CR;
+        uint16_t WR_DQS_SLAVE_FORCE_CR;
+        uint16_t WR_DQS_SLAVE_RATIO_1_CR;
+        uint16_t WR_DQS_SLAVE_RATIO_2_CR;
+        uint16_t WR_DQS_SLAVE_RATIO_3_CR;
+        uint16_t WR_DQS_SLAVE_RATIO_4_CR;
+        uint16_t WR_DATA_SLAVE_DELAY_1_CR;
+        uint16_t WR_DATA_SLAVE_DELAY_2_CR;
+        uint16_t WR_DATA_SLAVE_DELAY_3_CR;
+        uint16_t WR_DATA_SLAVE_FORCE_CR;
+        uint16_t WR_DATA_SLAVE_RATIO_1_CR;
+        uint16_t WR_DATA_SLAVE_RATIO_2_CR;
+        uint16_t WR_DATA_SLAVE_RATIO_3_CR;
+        uint16_t WR_DATA_SLAVE_RATIO_4_CR;
+        uint16_t WRLVL_INIT_MODE_CR;
+        uint16_t WRLVL_INIT_RATIO_1_CR;
+        uint16_t WRLVL_INIT_RATIO_2_CR;
+        uint16_t WRLVL_INIT_RATIO_3_CR;
+        uint16_t WRLVL_INIT_RATIO_4_CR;
+        uint16_t WR_RD_RL_CR;
+        uint16_t RDC_FIFO_RST_ERRCNTCLR_CR;
+        uint16_t RDC_WE_TO_RE_DELAY_CR;
+        uint16_t USE_FIXED_RE_CR;
+        uint16_t USE_RANK0_DELAYS_CR;
+        uint16_t USE_LVL_TRNG_LEVEL_CR;
+        uint16_t CONFIG_CR;
+        uint16_t RD_WR_GATE_LVL_CR;
+        uint16_t DYN_RESET_CR;
+    } phy;
+    
+    /*--------------------------------------------------------------------------
+     * FIC-64 registers
+     * These registers are 16-bit wide and 32-bit aligned.
+     */
+    struct 
+    {
+        uint16_t NB_ADDR_CR;
+        uint16_t NBRWB_SIZE_CR;
+        uint16_t WB_TIMEOUT_CR;
+        uint16_t HPD_SW_RW_EN_CR;
+        uint16_t HPD_SW_RW_INVAL_CR;
+        uint16_t SW_WR_ERCLR_CR;
+        uint16_t ERR_INT_ENABLE_CR;
+        uint16_t NUM_AHB_MASTERS_CR;
+        uint16_t LOCK_TIMEOUTVAL_1_CR;
+        uint16_t LOCK_TIMEOUTVAL_2_CR;
+        uint16_t LOCK_TIMEOUT_EN_CR;
+    } fic;
+} ddr_subsys_cfg_t;
+
+/*============================================================================*/
+/*                             FDDR Configuration                             */
+/*============================================================================*/
+
+typedef struct 
+{
+    uint16_t PLL_CONFIG_LOW_1;
+    uint16_t PLL_CONFIG_LOW_2;
+    uint16_t PLL_CONFIG_HIGH;
+    uint16_t FACC_CLK_EN;
+    uint16_t FACC_MUX_CONFIG;
+    uint16_t FACC_DIVISOR_RATIO;
+    uint16_t PLL_DELAY_LINE_SEL;
+    uint16_t SOFT_RESET; 
+    uint16_t IO_CALIB;
+    uint16_t INTERRUPT_ENABLE;
+    uint16_t AXI_AHB_MODE_SEL;
+    uint16_t PHY_SELF_REF_EN;
+} fddr_sysreg_t;
+
+/*============================================================================*/
+/*                 PCI Express Bridge IP Core configuration.                  */
+/*============================================================================*/
+
+typedef struct
+{
+    uint32_t * p_reg;
+    uint32_t value;
+} cfg_addr_value_pair_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_INIT_CFG_TYPES_H_ */

bsp/smartfusion2/CMSIS/system_m2sxxx.h

+/*******************************************************************************
+ * (c) Copyright 2012-2013 Microsemi SoC Products Group. All rights reserved.
+ * 
+ *  SmartFusion2 CMSIS system initialization.
+ *
+ * SVN $Revision: 5280 $
+ * SVN $Date: 2013-03-22 20:51:50 +0000 (Fri, 22 Mar 2013) $
+ */
+
+#ifndef SYSTEM_M2SXXX_H
+#define SYSTEM_M2SXXX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+/* Standard CMSIS global variables. */
+extern uint32_t SystemCoreClock;    /*!< System Clock Frequency (Core Clock) */
+
+/* SmartFusion2 specific clocks. */
+extern uint32_t g_FrequencyPCLK0;   /*!< Clock frequency of APB bus 0. */  
+extern uint32_t g_FrequencyPCLK1;   /*!< Clock frequency of APB bus 1. */
+extern uint32_t g_FrequencyPCLK2;   /*!< Clock frequency of APB bus 2. */
+extern uint32_t g_FrequencyFIC0;    /*!< Clock frequecny of FPGA fabric interface controller 1. */
+extern uint32_t g_FrequencyFIC1;    /*!< Clock frequecny of FPGA fabric inteface controller 2. */
+extern uint32_t g_FrequencyFIC64;   /*!< Clock frequecny of 64-bit FPGA fabric interface controller. */
+
+
+/***************************************************************************//**
+ * The SystemInit() is a standard CMSIS function called during system startup.
+ * It is meant to perform low level hardware setup such as configuring DDR and
+ * SERDES controllers.
+ */
+void SystemInit(void);
+
+/***************************************************************************//**
+ * The SystemCoreClockUpdate() is a standard CMSIS function which can be called
+ * by the application in order to ensure that the SystemCoreClock global
+ * variable contains the up to date Cortex-M3 core frequency. Calling this
+ * function also updates the global variables containing the frequencies of the
+ * APB busses connecting the peripherals.
+ */
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/smartfusion2/README.md

+## 移植RT-Thread到Microsemi SmartFusion2系列FPGA芯片
+
+### 1. BSP简介
+
+移植 RT-Thread 操作系统到 一款 **FPGA 芯片——M2S010** 上，该芯片属于 [Microsemi](https://www.microsemi.com/)（现Microchip）SmartFusion2系列，是一款**智能混合型FPGA**，片上除了 FPGA Fabric 逻辑部分，还包括一个 ARM® Cortex™-M3 内核的 MCU，主频最高 166MHz ，256KB eNVM，64KB eSRAM，集成GPIO、UART、I2C、SPI、CAN、USB等基本外设。
+
+> 关于 Microsemi，第三大 FPGA 厂商，原 Actel 半导体，2010 年，Microsemi 收购 Actel，2018 年， Microchip 收购 Microsemi。
+
+SmartFusion2 内部框图
+
+![](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/Microsemi_Smartfusion2_BD.jpg)
+
+### 2. 使用说明
+
+#### 2.1 FPGA 工程设计 
+
+FPGA 部分使用 SmartDesign 图形化设计，不需要写 HDL 代码，时钟来自外部 50M 晶体输入，PLL 倍频 100M 提供给 MCU 使用，顶层配置如下图所示：
+
+![](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/2020-06-02_114736.jpg)
+
+MSS 部分仅使用到了GPIO 和UART0，其他外设未启用，两个 GPIO 配置成输出模式：
+
+![](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/2020-06-02_114816.jpg)
+
+配置完成的 FPGA 工程文件下载：[fpga_project.rar](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/fpga_project.rar)
+
+#### 2.2 ARM 程序设计
+
+ARM 程序使用 Keil MDK 5.26 开发，需要安装 M2S 系列芯片支持包：[Microsemi.M2Sxxx.1.0.64.pack](http://www.actel-ip.com/repositories/CMSIS-Pack/Microsemi.M2Sxxx.1.0.64.pack)
+
+如果官网下载失败，可以到以下地址下载：[Microsemi.M2Sxxx.1.0.64.pack](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/Microsemi.M2Sxxx.1.0.64.pack)
+
+在官方生成的示例工程目录下，添加 RT-Thread 相关组件，并实现一些对接函数，最终的文件结构：
+
+![](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/2020-06-04_213532.png)
+
+### 3. 下载和运行
+
+为了能使用 ARM 调试器连接到 ARM 内核，而不是 FPGA，需要把 JTAG_SEL 引脚置为低电平。使用 ARM 调试器，如 JLink，对应连接 JTAG 口的 TMS、TCK、GND 引脚，如果连接正常，可以检测到 ARM 芯片，如下图所示：
+
+![](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/2020-06-02_115130.jpg)
+
+配置对应的 Flash 编程算法：
+
+![](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/2020-06-02_115115.jpg)
+
+下载完成：
+
+![](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/2020-06-02_115216.jpg)
+
+如果编译 & 烧写无误，下载完成或者按下复位按键之后，会在串口上看到 RT-Thread 的启动 LOG 信息：
+
+
+```c
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.3 build Jun  2 2020
+ 2006 - 2020 Copyright by rt-thread team
+msh >
+```
+
+![](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/2020-06-02_115305.jpg)
+
+### 4. 外设支持
+
+目前仅移植了 RT-Thread 内核，支持线程调度、线程间同步和通信等，支持 Finsh 组件，PIN、Serial 等设备驱动将会在以后添加。
+
+### 5. 资料下载
+
+独立的工程文件下载：
+
+- FPGA 工程下载：[fpga_project.rar](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/fpga_project.rar)
+- ARM 工程下载：[smartfusion_rtt-master-4.0.3.rar](https://wcc-blog.oss-cn-beijing.aliyuncs.com/Libero/RT-Thread/smartfusion_rtt-master-4.0.3.rar)
+
+### 6. 注意事项
+
+- FPGA 开发环境基于 Libero V11.8.2.4，向上兼容，不支持低版本 IDE。
+- ARM 开发环境基于 Keil MDK 5.26，如果使用SoftConsole IDE ，需要修改 `libcpu` 内的文件。
+- 调试内部 ARM 核，需要把 JTAG_SEL 拉低，否则调试器连接不上。 
+- 使用 SoftConsole 开发环境可以直接使用官方的 Flash Pro 调试器进行 ARM 程序的调试。
+- 内核时钟需要和 FPGA 中 MSS 配置的对应，Libero 自动生成的时钟文件，可以直接替换`bsp\smartfusion2\libraries\sys_config`文件夹下的文件 。
+
+### 7. 参考资料
+
+- [学习路线 - RT-Thread 文档中心](https://www.rt-thread.org/document/site/)
+- [Microsemi Libero系列中文教程](https://blog.csdn.net/whik1194/article/details/102901710)
+
+### 8. 联系我
+
+- 邮箱：wangchao149@foxmail.com
+- 主页：www.wangchaochao.top
+- 微信：wcc149

bsp/smartfusion2/del_obj_file.bat

+%删除obj目录下的多余文件%
+del *.lnp /s
+::del *.opt /s  ::不允许删除JLINK的设置
+del *.__i /s
+del *.crf /s
+del *.o /s
+del *.d /s
+del *.htm /s
+
+%删除USER目录下的多余文件%
+del *.map /s
+del *.lst /s
+del *.dep /s
+del *.build_log.htm /s
+del *.bak
+
+echo 编译产生的其他文件已经删除

bsp/smartfusion2/hal/CortexM3/Keil/cpu_types.h

+/*******************************************************************************
+ * (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
+ * 
+ * SVN $Revision: 5258 $
+ * SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $
+ */
+#ifndef __CPU_TYPES_H
+#define __CPU_TYPES_H   1
+
+#include <stdint.h>
+
+/*------------------------------------------------------------------------------
+ */
+typedef unsigned int size_t;
+
+/*------------------------------------------------------------------------------
+ * addr_t: address type.
+ * Used to specify the address of peripherals present in the processor's memory
+ * map.
+ */
+typedef unsigned int addr_t;
+
+/*------------------------------------------------------------------------------
+ * psr_t: processor state register.
+ * Used by HAL_disable_interrupts() and HAL_restore_interrupts() to store the
+ * processor's state between disabling and restoring interrupts.
+ */
+typedef unsigned int psr_t;
+
+#endif  /* __CPU_TYPES_H */

bsp/smartfusion2/hal/CortexM3/Keil/hal.s

+;-------------------------------------------------------------------------------
+; (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
+; 
+; Interrupt disabling/restoration for critical section protection.
+;
+; SVN $Revision: 5261 $
+; SVN $Date: 2013-03-21 19:52:41 +0530 (Thu, 21 Mar 2013) $
+;
+    AREA    |.text|, CODE, READONLY
+    EXPORT HAL_disable_interrupts
+    EXPORT HAL_restore_interrupts
+
+;-------------------------------------------------------------------------------
+; 
+;
+HAL_disable_interrupts \
+    PROC
+    mrs r0, PRIMASK
+    cpsid I
+    bx lr
+    ENDP
+
+;-------------------------------------------------------------------------------
+;
+;
+HAL_restore_interrupts \
+    PROC
+    msr PRIMASK, r0
+    bx lr
+    ENDP
+
+    END

bsp/smartfusion2/hal/CortexM3/Keil/hw_macros.h

+/*******************************************************************************
+ * (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
+ * 
+ *  Hardware registers access macros.
+ * 
+ *  THE MACROS DEFINED IN THIS FILE ARE DEPRECATED. DO NOT USED FOR NEW 
+ *  DEVELOPMENT.
+ *
+ * These macros are used to access peripheral's registers. They allow access to
+ * 8, 16 and 32 bit wide registers. All accesses to peripheral registers should
+ * be done through these macros in order to ease porting accross different 
+ * processors/bus architectures.
+ * 
+ * Some of these macros also allow to access a specific register field.
+ * 
+ * SVN $Revision: 5258 $
+ * SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $
+ */
+#ifndef __HW_REGISTER_MACROS_H
+#define __HW_REGISTER_MACROS_H  1
+
+/*------------------------------------------------------------------------------
+ * 32 bits registers access:
+ */
+#define HW_get_uint32_reg(BASE_ADDR, REG_OFFSET) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
+
+#define HW_set_uint32_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
+
+#define HW_set_uint32_reg_field(BASE_ADDR, FIELD, VALUE) \
+            (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) =  \
+                ( \
+                    (uint32_t) \
+                    ( \
+                    (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
+                    (uint32_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
+                ) \
+            )
+
+#define HW_get_uint32_reg_field( BASE_ADDR, FIELD ) \
+            (( (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
+
+/*------------------------------------------------------------------------------
+ * 32 bits memory access:
+ */
+#define HW_get_uint32(BASE_ADDR) (*((uint32_t volatile *)(BASE_ADDR)))
+
+#define HW_set_uint32(BASE_ADDR, VALUE) (*((uint32_t volatile *)(BASE_ADDR)) = (VALUE))
+
+/*------------------------------------------------------------------------------
+ * 16 bits registers access:
+ */
+#define HW_get_uint16_reg(BASE_ADDR, REG_OFFSET) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
+
+#define HW_set_uint16_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
+
+#define HW_set_uint16_reg_field(BASE_ADDR, FIELD, VALUE) \
+            (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) =  \
+                ( \
+                    (uint16_t) \
+                    ( \
+                    (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
+                    (uint16_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
+                ) \
+            )
+
+#define HW_get_uint16_reg_field( BASE_ADDR, FIELD ) \
+            (( (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
+
+/*------------------------------------------------------------------------------
+ * 8 bits registers access:
+ */
+#define HW_get_uint8_reg(BASE_ADDR, REG_OFFSET) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
+
+#define HW_set_uint8_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
+ 
+#define HW_set_uint8_reg_field(BASE_ADDR, FIELD, VALUE) \
+            (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) =  \
+                ( \
+                    (uint8_t) \
+                    ( \
+                    (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
+                    (uint8_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
+                ) \
+            )
+
+#define HW_get_uint8_reg_field( BASE_ADDR, FIELD ) \
+            (( (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
+
+/*------------------------------------------------------------------------------
+ * 8 bits memory access:
+ */
+#define HW_get_uint8(BASE_ADDR) (*((uint8_t volatile *)(BASE_ADDR)))
+
+#define HW_set_uint8(BASE_ADDR, VALUE) (*((uint8_t volatile *)(BASE_ADDR)) = (VALUE))
+ 
+#endif  /* __HW_REGISTER_MACROS_H */

bsp/smartfusion2/hal/CortexM3/Keil/hw_reg_access.s

+;******************************************************************************
+; (c) Copyright 2008-2013 Microsemi SoC Products Group. All rights reserved.
+; 
+; SVN $Revision: 5258 $
+; SVN $Date: 2013-03-21 18:11:02 +0530 (Thu, 21 Mar 2013) $
+;
+
+    AREA    |.text|, CODE, READONLY
+    EXPORT HW_set_32bit_reg
+    EXPORT HW_get_32bit_reg
+    EXPORT HW_set_32bit_reg_field
+    EXPORT HW_get_32bit_reg_field
+    EXPORT HW_set_16bit_reg
+    EXPORT HW_get_16bit_reg
+    EXPORT HW_set_16bit_reg_field
+    EXPORT HW_get_16bit_reg_field
+    EXPORT HW_set_8bit_reg
+    EXPORT HW_get_8bit_reg
+    EXPORT HW_set_8bit_reg_field
+    EXPORT HW_get_8bit_reg_field
+
+;------------------------------------------------------------------------------
+; R0:   addr_t reg_addr
+; R1:   uint32_t value
+;
+HW_set_32bit_reg \
+    PROC
+    STR R1, [R0]
+    BX LR
+    ENDP
+
+;------------------------------------------------------------------------------
+; R0:   addr_t reg_addr
+;      
+HW_get_32bit_reg \
+    PROC
+    LDR R0, [R0]
+    BX LR
+    ENDP
+
+;------------------------------------------------------------------------------
+; R0:   addr_t reg_addr
+; R1:   int_fast8_t shift
+; R2:   uint32_t mask
+; R3:   uint32_t value
+;
+HW_set_32bit_reg_field \
+    PROC
+    PUSH {R1,R2,R3,LR}
+    LSL.W R3, R3, R1
+    AND.W R3, R3, R2
+    LDR R1, [R0]
+    MVN.W R2, R2
+    AND.W R1, R1, R2
+    ORR.W R1, R1, R3
+    STR R1, [R0]
+    POP {R1,R2,R3,PC}
+    ENDP
+
+;------------------------------------------------------------------------------
+; R0:   addr_t reg_addr
+; R1:   int_fast8_t shift
+; R2:   uint32_t mask
+;
+HW_get_32bit_reg_field \
+    PROC
+    LDR R0, [R0]
+    AND.W R0, R0, R2
+    LSR.W R0, R0, R1
+    BX LR
+    ENDP
+
+;------------------------------------------------------------------------------
+; R0:   addr_t reg_addr
+; R1:   uint_fast16_t value
+;
+HW_set_16bit_reg \
+    PROC
+    STRH R1, [R0]
+    BX LR
+    ENDP
+        
+;------------------------------------------------------------------------------
+; R0:   addr_t reg_addr
+;
+HW_get_16bit_reg \
+    PROC
+    LDRH R0, [R0]
+    BX LR
+    ENDP
+
+;------------------------------------------------------------------------------
+; R0:   addr_t reg_addr
+; R1:   int_fast8_t shift
+; R2:   uint_fast16_t mask
+; R3:   uint_fast16_t value
+;
+HW_set_16bit_reg_field \
+    PROC
+    PUSH {R1,R2,R3,LR}
+    LSL.W R3, R3, R1
+    AND.W R3, R3, R2
+    LDRH R1, [R0]
+    MVN.W R2, R2
+    AND.W R1, R1, R2
+    ORR.W R1, R1, R3
+    STRH R1, [R0]
+    POP {R1,R2,R3,PC}
+    ENDP
+
+;------------------------------------------------------------------------------
+; R0:   addr_t reg_addr
+; R1:   int_fast8_t shift
+; R2:   uint_fast16_t mask
+;
+HW_get_16bit_reg_field \
+    PROC
+    LDRH R0, [R0]
+    AND.W R0, R0, R2
+    LSR.W R0, R0, R1
+    BX LR
+    ENDP
+
+;------------------------------------------------------------------------------
+; R0:   addr_t reg_addr
+; R1:   uint_fast8_t value
+;
+HW_set_8bit_reg \
+    PROC
+    STRB R1, [R0]
+    BX LR
+    ENDP
+        
+;------------------------------------------------------------------------------
+; R0:   addr_t reg_addr
+;
+HW_get_8bit_reg \
+    PROC
+    LDRB R0, [R0]
+    BX LR
+    ENDP
+
+;------------------------------------------------------------------------------
+; R0:   addr_t reg_addr,
+; R1:   int_fast8_t shift
+; R2:   uint_fast8_t mask
+; R3:   uint_fast8_t value
+;
+HW_set_8bit_reg_field \
+    PROC
+    PUSH {R1,R2,R3,LR}
+    LSL.W R3, R3, R1
+    AND.W R3, R3, R2
+    LDRB R1, [R0]
+    MVN.W R2, R2
+    AND.W R1, R1, R2
+    ORR.W R1, R1, R3
+    STRB R1, [R0]
+    POP {R1,R2,R3,PC}
+    ENDP
+
+;------------------------------------------------------------------------------
+; R0:   addr_t reg_addr
+; R1:   int_fast8_t shift
+; R2:   uint_fast8_t mask
+;
+HW_get_8bit_reg_field \
+    PROC
+    LDRB R0, [R0]
+    AND.W R0, R0, R2
+    LSR.W R0, R0, R1
+    BX LR
+    ENDP
+
+    END

bsp/smartfusion2/hal/CortexM3/cortex_nvic.c

+/*******************************************************************************
+ * (c) Copyright 2007-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * Legacy Actel HAL Cortex NVIC control functions.
+ * The use of these functions should be replaced by calls to the equivalent
+ * CMSIS function in your application code.
+ *
+ * SVN $Revision: 7375 $
+ * SVN $Date: 2015-05-01 19:27:40 +0530 (Fri, 01 May 2015) $
+ */
+#include "cortex_nvic.h"
+#ifdef MSCC_NO_RELATIVE_PATHS
+#include "mss_assert.h"
+#else
+#include "../../CMSIS/mss_assert.h"
+#endif
+
+
+/***************************************************************************//**
+ * 
+ */
+void NVIC_init( void )
+{
+    /*
+     * Please use the NVIC control functions provided by the SmartFusion2 CMSIS
+     * Hardware Abstraction Layer. The use of the Actel HAL NVIC control
+     * functions is obsolete on SmartFusion2 devices.
+     *
+     * Simply remove the call to NVIC_init() from your application code.
+     */
+    ASSERT(0);
+}
+
+/***************************************************************************//**
+ * 
+ */
+void NVIC_set_handler
+(
+    uint32_t interrupt_number,
+    hal_nvic_irq_handler_t handler
+)
+{
+    /*
+     * Please use the NVIC control functions provided by the SmartFusion2 CMSIS
+     * Hardware Abstraction Layer. The use of the Actel HAL NVIC control
+     * functions is obsolete on SmartFusion2 devices.
+     *
+     * Please remove the call to NVIC_set_handler() from your application code
+     * and provide a function using one of the following function prototypes to
+     * handle interrupts from peripherals implemeted in the SmartFusion2 FPGA
+     * fabric:
+     *      - void FabricIrq0_IRQHandler(void)
+     *      - void FabricIrq1_IRQHandler(void)
+     *      - void FabricIrq2_IRQHandler(void)
+     *      - void FabricIrq3_IRQHandler(void)
+     *      - void FabricIrq4_IRQHandler(void)
+     *      - void FabricIrq5_IRQHandler(void)
+     *      - void FabricIrq6_IRQHandler(void)
+     *      - void FabricIrq7_IRQHandler(void)
+     *      - void FabricIrq8_IRQHandler(void)
+     *      - void FabricIrq9_IRQHandler(void)
+     *      - void FabricIrq10_IRQHandler(void)
+     *      - void FabricIrq11_IRQHandler(void)
+     *      - void FabricIrq12_IRQHandler(void)
+     *      - void FabricIrq13_IRQHandler(void)
+     *      - void FabricIrq14_IRQHandler(void)
+     *      - void FabricIrq15_IRQHandler(void)
+     * The function to implement depends on which MSS_INT_F2M[n] signal is used
+     * in your Libero design to connect the interrupt signal of the peripheral
+     * generating the interrupt.
+     */
+    ASSERT(0);
+}
+
+/***************************************************************************//**
+ * 
+ */
+void NVIC_set_priority
+(
+    uint32_t interrupt_number,
+    uint8_t priority_level
+)
+{
+    /*
+     * Please use the NVIC control functions provided by the SmartFusion2 CMSIS
+     * Hardware Abstraction Layer. The use of the Actel HAL NVIC control
+     * functions is obsolete on SmartFusion2 devices.
+     *
+     * Please replace calls to NVIC_set_priority() with a call to the CMSIS
+     * void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) function where
+     * IRQn is one of the following values:
+     *      - FabricIrq0_IRQn
+     *      - FabricIrq1_IRQn
+     *      - FabricIrq2_IRQn
+     *      - FabricIrq3_IRQn
+     *      - FabricIrq4_IRQn
+     *      - FabricIrq5_IRQn
+     *      - FabricIrq6_IRQn
+     *      - FabricIrq7_IRQn
+     *      - FabricIrq8_IRQn
+     *      - FabricIrq9_IRQn
+     *      - FabricIrq10_IRQn
+     *      - FabricIrq11_IRQn
+     *      - FabricIrq12_IRQn
+     *      - FabricIrq13_IRQn
+     *      - FabricIrq14_IRQn
+     *      - FabricIrq15_IRQn
+     */
+    ASSERT(0);
+}
+
+/***************************************************************************//**
+ * 
+ */
+void NVIC_enable_interrupt( uint32_t interrupt_number )
+{
+    /*
+     * Please use the NVIC control functions provided by the SmartFusion2 CMSIS
+     * Hardware Abstraction Layer. The use of the Actel HAL NVIC control
+     * functions is obsolete on SmartFusion2 devices.
+     *
+     * Please replace calls to NVIC_enable_interrupt() with a call to the CMSIS
+     * void NVIC_EnableIRQ(IRQn_Type IRQn) function where IRQn is one of the
+     * following values:
+     *      - FabricIrq0_IRQn
+     *      - FabricIrq1_IRQn
+     *      - FabricIrq2_IRQn
+     *      - FabricIrq3_IRQn
+     *      - FabricIrq4_IRQn
+     *      - FabricIrq5_IRQn
+     *      - FabricIrq6_IRQn
+     *      - FabricIrq7_IRQn
+     *      - FabricIrq8_IRQn
+     *      - FabricIrq9_IRQn
+     *      - FabricIrq10_IRQn
+     *      - FabricIrq11_IRQn
+     *      - FabricIrq12_IRQn
+     *      - FabricIrq13_IRQn
+     *      - FabricIrq14_IRQn
+     *      - FabricIrq15_IRQn
+     */
+    ASSERT(0);
+}
+
+/***************************************************************************//**
+ * 
+ */
+void NVIC_disable_interrupt( uint32_t interrupt_number )
+{
+    /*
+     * Please use the NVIC control functions provided by the SmartFusion2 CMSIS
+     * Hardware Abstraction Layer. The use of the Actel HAL NVIC control
+     * functions is obsolete on SmartFusion2 devices.
+     *
+     * Please replace calls to NVIC_disable_interrupt() with a call to the CMSIS
+     * void NVIC_DisableIRQ(IRQn_Type IRQn) function where IRQn is one of the
+     * following values:
+     *      - FabricIrq0_IRQn
+     *      - FabricIrq1_IRQn
+     *      - FabricIrq2_IRQn
+     *      - FabricIrq3_IRQn
+     *      - FabricIrq4_IRQn
+     *      - FabricIrq5_IRQn
+     *      - FabricIrq6_IRQn
+     *      - FabricIrq7_IRQn
+     *      - FabricIrq8_IRQn
+     *      - FabricIrq9_IRQn
+     *      - FabricIrq10_IRQn
+     *      - FabricIrq11_IRQn
+     *      - FabricIrq12_IRQn
+     *      - FabricIrq13_IRQn
+     *      - FabricIrq14_IRQn
+     *      - FabricIrq15_IRQn
+     */
+    ASSERT(0);
+}
+
+/***************************************************************************//**
+ * 
+ */
+void NVIC_clear_interrupt( uint32_t interrupt_number )
+{
+    /*
+     * Please use the NVIC control functions provided by the SmartFusion2 CMSIS
+     * Hardware Abstraction Layer. The use of the Actel HAL NVIC control
+     * functions is obsolete on SmartFusion2 devices.
+     *
+     * Please replace calls to NVIC_clear_interrupt() with a call to the CMSIS
+     * void NVIC_ClearPendingIRQ(IRQn_Type IRQn) function where IRQn is one of the
+     * following values:
+     *      - FabricIrq0_IRQn
+     *      - FabricIrq1_IRQn
+     *      - FabricIrq2_IRQn
+     *      - FabricIrq3_IRQn
+     *      - FabricIrq4_IRQn
+     *      - FabricIrq5_IRQn
+     *      - FabricIrq6_IRQn
+     *      - FabricIrq7_IRQn
+     *      - FabricIrq8_IRQn
+     *      - FabricIrq9_IRQn
+     *      - FabricIrq10_IRQn
+     *      - FabricIrq11_IRQn
+     *      - FabricIrq12_IRQn
+     *      - FabricIrq13_IRQn
+     *      - FabricIrq14_IRQn
+     *      - FabricIrq15_IRQn
+     */
+    ASSERT(0);
+}

bsp/smartfusion2/hal/CortexM3/cortex_nvic.h

+/*******************************************************************************
+ * (c) Copyright 2007-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * Legacy Actel HAL Cortex NVIC control functions.
+ * The use of these functions should be replaced by calls to the equivalent
+ * CMSIS function in your application code.
+ *
+ * SVN $Revision: 5257 $
+ * SVN $Date: 2013-03-21 17:54:10 +0530 (Thu, 21 Mar 2013) $
+ */
+#ifndef CORTEX_NVIC_H_
+#define CORTEX_NVIC_H_
+
+#include <stdint.h>
+
+typedef void (*hal_nvic_irq_handler_t)(void);
+
+/*------------------------------------------------------------------------------
+ * 
+ */
+void NVIC_init( void );
+
+/*------------------------------------------------------------------------------
+ * 
+ */
+void NVIC_set_handler
+(
+    uint32_t interrupt_number,
+    hal_nvic_irq_handler_t handler
+);
+
+/*------------------------------------------------------------------------------
+ * 
+ */
+void NVIC_set_priority
+(
+    uint32_t interrupt_number,
+    uint8_t priority_level
+);
+
+/*------------------------------------------------------------------------------
+ * 
+ */
+void NVIC_enable_interrupt( uint32_t interrupt_number );
+
+/*------------------------------------------------------------------------------
+ * 
+ */
+void NVIC_disable_interrupt( uint32_t interrupt_number );
+
+/*------------------------------------------------------------------------------
+ * 
+ */
+void NVIC_clear_interrupt( uint32_t interrupt_number );
+
+#endif /*CORTEX_NVIC_H_*/

bsp/smartfusion2/hal/hal_assert.h

+/*******************************************************************************
+ * (c) Copyright 2008-2013 Microsemi SoC Products Group. All rights reserved.
+ * 
+ * SVN $Revision: 7375 $
+ * SVN $Date: 2015-05-01 19:27:40 +0530 (Fri, 01 May 2015) $
+ */
+#ifndef HAL_ASSERT_HEADER
+#define HAL_ASSERT_HEADER
+
+#ifdef MSCC_NO_RELATIVE_PATHS
+#include "mss_assert.h"
+#else
+#include "../CMSIS/mss_assert.h"
+#endif
+
+#if defined(NDEBUG)
+/***************************************************************************//**
+ * HAL_ASSERT() is defined out when the NDEBUG symbol is used.
+ ******************************************************************************/
+#define HAL_ASSERT(CHECK)
+
+#else
+/***************************************************************************//**
+ * Default behaviour for HAL_ASSERT() macro:
+ *------------------------------------------------------------------------------
+ * Using the HAL_ASSERT() macro is the same as directly using the SmartFusion2
+ * CMSIS ASSERT() macro. The behaviour is toolchain specific and project
+ * setting specific.
+ ******************************************************************************/
+#define HAL_ASSERT(CHECK)     ASSERT(CHECK);
+
+#endif  /* NDEBUG */
+
+#endif  /* HAL_ASSERT_HEADER */

bsp/smartfusion2/libraries/mss_sys_services/mss_comblk.h

+/*******************************************************************************
+ * (c) Copyright 2012-2016 Microsemi SoC Products Group.  All rights reserved.
+ *
+ * SmartFusion2 COMBLK access functions.
+ *
+ * SVN $Revision: 8345 $
+ * SVN $Date: 2016-03-23 11:53:04 +0530 (Wed, 23 Mar 2016) $
+ */
+#ifndef __MSS_COMBLK_H_
+#define __MSS_COMBLK_H_ 1
+
+#include "../../CMSIS/m2sxxx.h"
+#include "mss_comblk_page_handler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  
+/*------------------------------------------------------------------------------
+ *
+ */
+typedef void(*comblk_completion_handler_t)(uint8_t * p_response, uint16_t response_size);
+
+typedef void (*comblk_async_event_handler_t)(uint8_t event_opcode);
+
+/*------------------------------------------------------------------------------
+ *
+ */
+void MSS_COMBLK_init
+(
+    comblk_async_event_handler_t async_event_handler, 
+    uint8_t* p_response
+);
+
+/*------------------------------------------------------------------------------
+ *
+ */
+void MSS_COMBLK_send_cmd_with_ptr
+(
+    uint8_t cmd_opcode,
+    uint32_t cmd_params_ptr,
+    uint8_t * p_response,
+    uint16_t response_size,
+    comblk_completion_handler_t completion_handler
+);
+
+/*------------------------------------------------------------------------------
+ *
+ */
+void MSS_COMBLK_send_cmd
+(
+    const uint8_t * p_cmd,
+    uint16_t cmd_size,
+    const uint8_t * p_data,
+    uint32_t data_size,
+    uint8_t * p_response,
+    uint16_t response_size,
+    comblk_completion_handler_t completion_handler
+);
+
+/*------------------------------------------------------------------------------
+ *
+ */
+void MSS_COMBLK_read
+(
+    const uint8_t * p_data,
+    uint16_t cmd_size,
+    uint8_t * p_response,
+    uint16_t response_size,
+    comblk_completion_handler_t completion_handler
+);
+
+/*------------------------------------------------------------------------------
+ *
+ */
+void MSS_COMBLK_send_paged_cmd
+(
+    const uint8_t * p_cmd,
+    uint16_t cmd_size,
+    uint8_t * p_response,
+    uint16_t response_size,
+    comblk_page_handler_t page_read_handler,
+    comblk_completion_handler_t completion_handler
+);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MSS_COMBLK_H_ */

bsp/smartfusion2/libraries/mss_sys_services/mss_comblk_page_handler.h

+/*******************************************************************************
+ * (c) Copyright 2012-2016 Microsemi SoC Products Group.  All rights reserved.
+ *
+ * SmartFusion2 MSS COM block driver, page handler callback function prototype.
+ *
+ * SVN $Revision: 8345 $
+ * SVN $Date: 2016-03-23 11:53:04 +0530 (Wed, 23 Mar 2016) $
+ */
+
+#ifndef __MSS_COMBLK_PAGE_HANDLER_H_
+#define __MSS_COMBLK_PAGE_HANDLER_H_ 1
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-------------------------------------------------------------------------*//**
+  The comblk_page_handler_t typedef specifies the function prototype of a COMBLK
+  page handler callback function. This callback is used by the system services
+  and COMBLK drivers as part of in-system programming (ISP) to retrieve the next
+  page of programming information to send to the SmartFusion2 System Controller
+  via the COMBLK.
+  The COMBLK page handler must be implemented by the application layer to return
+  the address of the next page of programming data to be sent to the
+  SmartFusion2 system controller. It must return the number of bytes contained
+  in the next page. Returning a value of zero indicates that all programming
+  data has been passed to the system services/COMBLK drivers.
+  
+  @code
+    #define PAGE_LENGTH 512
+    
+    uint8_t programming_data[PROG_DATA_LENGTH];
+    uint32_t prog_data_index = 0;
+    
+    uint32_t page_read_handler
+    (
+        uint8_t const ** pp_next_page
+    )
+    {
+        uint32_t returned_page_length;
+        uint32_t remaining_length;
+
+        *pp_next_page = &programming_data[prog_data_index];
+        remaining_length = PROG_DATA_LENGTH - prog_data_index
+        if(remaining_length > PAGE_LENGTH)
+        {
+            returned_page_length = PAGE_LENGTH;
+        }
+        else
+        {
+            returned_page_length = remaining_length;
+            prog_data_index = PROG_DATA_LENGTH;
+        }
+        
+        return returned_page_length;
+    }
+
+  @endcode
+ */
+typedef uint32_t (*comblk_page_handler_t)(uint8_t const ** pp_next_page);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __MSS_COMBLK_PAGE_HANDLER_H_ */

bsp/smartfusion2/user/README.txt

+