Skip to content
体验新版
项目
组织
正在加载...
登录
切换导航
打开侧边栏
机器未来
Paddle
提交
7ab0e336
P
Paddle
项目概览
机器未来
/
Paddle
与 Fork 源项目一致
Fork自
PaddlePaddle / Paddle
通知
1
Star
1
Fork
0
代码
文件
提交
分支
Tags
贡献者
分支图
Diff
Issue
1
列表
看板
标记
里程碑
合并请求
0
Wiki
0
Wiki
分析
仓库
DevOps
项目成员
Pages
P
Paddle
项目概览
项目概览
详情
发布
仓库
仓库
文件
提交
分支
标签
贡献者
分支图
比较
Issue
1
Issue
1
列表
看板
标记
里程碑
合并请求
0
合并请求
0
Pages
分析
分析
仓库分析
DevOps
Wiki
0
Wiki
成员
成员
收起侧边栏
关闭侧边栏
动态
分支图
创建新Issue
提交
Issue看板
未验证
提交
7ab0e336
编写于
7月 21, 2022
作者:
C
Chenxiao Niu
提交者:
GitHub
7月 21, 2022
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
[MLU] transpose avg_pool2d to NHWC for better performance. (#44475)
上级
c3ba8056
变更
1
隐藏空白更改
内联
并排
Showing
1 changed file
with
34 addition
and
32 deletion
+34
-32
paddle/fluid/operators/pool_op_mlu.cc
paddle/fluid/operators/pool_op_mlu.cc
+34
-32
未找到文件。
paddle/fluid/operators/pool_op_mlu.cc
浏览文件 @
7ab0e336
...
...
@@ -100,6 +100,25 @@ class MLUPoolOpKernel : public framework::OpKernel<T> {
cnnlPoolingMode_t
pool_mode
=
ToCnnlPoolingMode
(
pooling_type
,
exclusive
,
adaptive
);
// transpose NCHW to NHWC since cnnl pool2d has worse performance in that
// layout.
framework
::
Tensor
trans_in_x
;
framework
::
Tensor
trans_out
;
if
(
channel_last
)
{
trans_in_x
=
*
in_x
;
trans_out
=
*
out
;
}
else
{
std
::
vector
<
int
>
perm
{
0
,
2
,
3
,
1
};
TransposeFromMLUTensor
<
T
>
(
ctx
,
perm
,
in_x
,
&
trans_in_x
,
true
/*need_reshape_or_alloc*/
);
trans_out
=
ctx
.
AllocateTmpTensor
<
T
,
MLUDeviceContext
>
(
{
out_dims
[
0
],
out_dims
[
2
],
out_dims
[
3
],
out_dims
[
1
]},
dev_ctx
);
}
MLUCnnlTensorDesc
trans_in_x_desc
(
trans_in_x
,
CNNL_LAYOUT_NHWC
,
ToCnnlDataType
<
T
>
());
MLUCnnlTensorDesc
trans_out_desc
(
trans_out
,
CNNL_LAYOUT_NHWC
,
ToCnnlDataType
<
T
>
());
if
(
!
adaptive
)
{
MLUCnnlPoolingDesc
pool_desc
(
pool_mode
,
CNNL_NOT_PROPAGATE_NAN
,
...
...
@@ -128,8 +147,8 @@ class MLUPoolOpKernel : public framework::OpKernel<T> {
{
static_cast
<
int64_t
>
(
extra_input_size
)},
cpu_ctx
);
cnnlInitPoolingExtraInput
(
handle
,
pool_desc
.
get
(),
in_x_desc
.
get
(),
out_desc
.
get
(),
trans_
in_x_desc
.
get
(),
trans_
out_desc
.
get
(),
GetBasePtr
(
&
extra_host_tensor
));
framework
::
Tensor
extra_device_tensor
=
ctx
.
AllocateTmpTensor
<
int8_t
,
MLUDeviceContext
>
(
...
...
@@ -151,12 +170,12 @@ class MLUPoolOpKernel : public framework::OpKernel<T> {
out_w
,
pool_desc
.
get
(),
nullptr
/*alpha*/
,
in_x_desc
.
get
(),
GetBasePtr
(
in_x
),
trans_
in_x_desc
.
get
(),
GetBasePtr
(
&
trans_
in_x
),
nullptr
/*beta*/
,
GetBasePtr
(
&
extra_device_tensor
)
/*params_shape_ptr*/
,
out_desc
.
get
(),
GetBasePtr
(
out
));
trans_
out_desc
.
get
(),
GetBasePtr
(
&
trans_
out
));
}
else
{
MLUCnnl
::
PoolingForward
(
ctx
,
pool_mode
,
...
...
@@ -164,31 +183,14 @@ class MLUPoolOpKernel : public framework::OpKernel<T> {
out_w
,
pool_desc
.
get
(),
nullptr
/*alpha*/
,
in_x_desc
.
get
(),
GetBasePtr
(
in_x
),
trans_
in_x_desc
.
get
(),
GetBasePtr
(
&
trans_
in_x
),
nullptr
/*beta*/
,
nullptr
/*params_shape_ptr*/
,
out_desc
.
get
(),
GetBasePtr
(
out
));
trans_
out_desc
.
get
(),
GetBasePtr
(
&
trans_
out
));
}
}
else
{
// cnnl Adaptive pooling only support NHWC layout
framework
::
Tensor
trans_in_x
;
framework
::
Tensor
trans_out
;
if
(
channel_last
)
{
trans_in_x
=
*
in_x
;
trans_out
=
*
out
;
}
else
{
std
::
vector
<
int
>
perm
{
0
,
2
,
3
,
1
};
TransposeFromMLUTensor
<
T
>
(
ctx
,
perm
,
in_x
,
&
trans_in_x
,
true
/*need_reshape_or_alloc*/
);
trans_out
=
ctx
.
AllocateTmpTensor
<
T
,
MLUDeviceContext
>
(
{
out_dims
[
0
],
out_dims
[
2
],
out_dims
[
3
],
out_dims
[
1
]},
dev_ctx
);
}
MLUCnnlTensorDesc
trans_in_x_desc
(
trans_in_x
,
CNNL_LAYOUT_NHWC
,
ToCnnlDataType
<
T
>
());
MLUCnnlTensorDesc
trans_out_desc
(
trans_out
,
CNNL_LAYOUT_NHWC
,
ToCnnlDataType
<
T
>
());
MLUCnnl
::
AdaptivePoolingForward
(
ctx
,
pool_mode
,
trans_in_x_desc
.
get
(),
...
...
@@ -197,11 +199,11 @@ class MLUPoolOpKernel : public framework::OpKernel<T> {
GetBasePtr
(
&
trans_out
),
nullptr
,
nullptr
);
if
(
!
channel_last
)
{
std
::
vector
<
int
>
perm
{
0
,
3
,
1
,
2
};
TransposeFromMLUTensor
<
T
>
(
ctx
,
perm
,
&
trans_out
,
out
,
false
/*need_reshape_or_alloc*/
);
}
}
if
(
!
channel_last
)
{
std
::
vector
<
int
>
perm
{
0
,
3
,
1
,
2
};
TransposeFromMLUTensor
<
T
>
(
ctx
,
perm
,
&
trans_out
,
out
,
false
/*need_reshape_or_alloc*/
);
}
}
};
...
...
编辑
预览
Markdown
is supported
0%
请重试
或
添加新附件
.
添加附件
取消
You are about to add
0
people
to the discussion. Proceed with caution.
先完成此消息的编辑!
取消
想要评论请
注册
或
登录