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体验新版 GitCode,发现更多精彩内容 >>
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e6600dbf
编写于
3月 13, 2020
作者:
B
bigmagic
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电子邮件补丁
差异文件
remove cortex-a53 from libcpu/arm
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f6a13de0
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隐藏空白更改
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Showing
5 changed file
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and
651 deletion
+0
-651
libcpu/arm/cortex-a53/cp15.h
libcpu/arm/cortex-a53/cp15.h
+0
-168
libcpu/arm/cortex-a53/cpu.c
libcpu/arm/cortex-a53/cpu.c
+0
-91
libcpu/arm/cortex-a53/interrupt.c
libcpu/arm/cortex-a53/interrupt.c
+0
-186
libcpu/arm/cortex-a53/interrupt.h
libcpu/arm/cortex-a53/interrupt.h
+0
-18
libcpu/arm/cortex-a53/mmu.c
libcpu/arm/cortex-a53/mmu.c
+0
-188
未找到文件。
libcpu/arm/cortex-a53/cp15.h
已删除
100644 → 0
浏览文件 @
f6a13de0
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-09-15 Bernard first version
*/
#include "raspi.h"
#ifndef __CP15_H__
#define __CP15_H__
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
#endif
#define __WFI() __asm__ volatile ("wfi":::"memory")
#define __WFE() __asm__ volatile ("wfe":::"memory")
#define __SEV() __asm__ volatile ("sev")
__STATIC_FORCEINLINE
void
__ISB
(
void
)
{
__asm__
volatile
(
"isb 0xF"
:::
"memory"
);
}
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__STATIC_FORCEINLINE
void
__DSB
(
void
)
{
__asm__
volatile
(
"dsb 0xF"
:::
"memory"
);
}
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__STATIC_FORCEINLINE
void
__DMB
(
void
)
{
__asm__
volatile
(
"dmb 0xF"
:::
"memory"
);
}
#ifdef RT_USING_SMP
static
inline
void
send_ipi_msg
(
int
cpu
,
int
ipi_vector
)
{
IPI_MAILBOX_SET
(
cpu
)
=
1
<<
ipi_vector
;
}
static
inline
void
setup_bootstrap_addr
(
int
cpu
,
int
addr
)
{
CORE_MAILBOX3_SET
(
cpu
)
=
addr
;
}
static
inline
void
enable_cpu_ipi_intr
(
int
cpu
)
{
COREMB_INTCTL
(
cpu
)
=
IPI_MAILBOX_INT_MASK
;
}
static
inline
void
enable_cpu_timer_intr
(
int
cpu
)
{
CORETIMER_INTCTL
(
cpu
)
=
0x8
;
}
static
inline
void
enable_cntv
(
void
)
{
rt_uint32_t
cntv_ctl
;
cntv_ctl
=
1
;
asm
volatile
(
"mcr p15, 0, %0, c14, c3, 1"
::
"r"
(
cntv_ctl
));
// write CNTV_CTL
}
static
inline
void
disable_cntv
(
void
)
{
rt_uint32_t
cntv_ctl
;
cntv_ctl
=
0
;
asm
volatile
(
"mcr p15, 0, %0, c14, c3, 1"
::
"r"
(
cntv_ctl
));
// write CNTV_CTL
}
static
inline
void
mask_cntv
(
void
)
{
rt_uint32_t
cntv_ctl
;
cntv_ctl
=
2
;
asm
volatile
(
"mcr p15, 0, %0, c14, c3, 1"
::
"r"
(
cntv_ctl
));
// write CNTV_CTL
}
static
inline
void
unmask_cntv
(
void
)
{
rt_uint32_t
cntv_ctl
;
cntv_ctl
=
1
;
asm
volatile
(
"mcr p15, 0, %0, c14, c3, 1"
::
"r"
(
cntv_ctl
));
// write CNTV_CTL
}
static
inline
rt_uint64_t
read_cntvct
(
void
)
{
rt_uint32_t
val
,
val1
;
asm
volatile
(
"mrrc p15, 1, %0, %1, c14"
:
"=r"
(
val
),
"=r"
(
val1
));
return
(
val
);
}
static
inline
rt_uint64_t
read_cntvoff
(
void
)
{
rt_uint64_t
val
;
asm
volatile
(
"mrrc p15, 4, %Q0, %R0, c14"
:
"=r"
(
val
));
return
(
val
);
}
static
inline
rt_uint32_t
read_cntv_tval
(
void
)
{
rt_uint32_t
val
;
asm
volatile
(
"mrc p15, 0, %0, c14, c3, 0"
:
"=r"
(
val
));
return
val
;
}
static
inline
void
write_cntv_tval
(
rt_uint32_t
val
)
{
asm
volatile
(
"mcr p15, 0, %0, c14, c3, 0"
::
"r"
(
val
));
return
;
}
static
inline
rt_uint32_t
read_cntfrq
(
void
)
{
rt_uint32_t
val
;
asm
volatile
(
"mrc p15, 0, %0, c14, c0, 0"
:
"=r"
(
val
));
return
val
;
}
static
inline
rt_uint32_t
read_cntctrl
(
void
)
{
rt_uint32_t
val
;
asm
volatile
(
"mrc p15, 0, %0, c14, c1, 0"
:
"=r"
(
val
));
return
val
;
}
static
inline
uint32_t
write_cntctrl
(
uint32_t
val
)
{
asm
volatile
(
"mcr p15, 0, %0, c14, c1, 0"
:
:
"r"
(
val
));
return
val
;
}
#endif
unsigned
long
rt_cpu_get_smp_id
(
void
);
void
rt_cpu_mmu_disable
(
void
);
void
rt_cpu_mmu_enable
(
void
);
void
rt_cpu_tlb_set
(
volatile
unsigned
long
*
);
void
rt_cpu_dcache_clean_flush
(
void
);
void
rt_cpu_icache_flush
(
void
);
void
rt_cpu_vector_set_base
(
unsigned
int
addr
);
void
rt_hw_mmu_init
(
void
);
void
rt_hw_vector_init
(
void
);
void
set_timer_counter
(
unsigned
int
counter
);
void
set_timer_control
(
unsigned
int
control
);
#endif
libcpu/arm/cortex-a53/cpu.c
已删除
100644 → 0
浏览文件 @
f6a13de0
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2011-09-15 Bernard first version
* 2019-07-28 zdzn add smp support
*/
#include <rthw.h>
#include <rtthread.h>
#include <board.h>
#include "cp15.h"
int
rt_hw_cpu_id
(
void
)
{
int
cpu_id
;
__asm__
volatile
(
"mrc p15, 0, %0, c0, c0, 5"
:
"=r"
(
cpu_id
)
);
cpu_id
&=
0xf
;
return
cpu_id
;
};
#ifdef RT_USING_SMP
void
rt_hw_spin_lock_init
(
rt_hw_spinlock_t
*
lock
)
{
lock
->
slock
=
0
;
}
void
rt_hw_spin_lock
(
rt_hw_spinlock_t
*
lock
)
{
unsigned
long
tmp
;
unsigned
long
newval
;
rt_hw_spinlock_t
lockval
;
__asm__
__volatile__
(
"pld [%0]"
::
"r"
(
&
lock
->
slock
)
);
__asm__
__volatile__
(
"1: ldrex %0, [%3]
\n
"
" add %1, %0, %4
\n
"
" strex %2, %1, [%3]
\n
"
" teq %2, #0
\n
"
" bne 1b"
:
"=&r"
(
lockval
),
"=&r"
(
newval
),
"=&r"
(
tmp
)
:
"r"
(
&
lock
->
slock
),
"I"
(
1
<<
16
)
:
"cc"
);
while
(
lockval
.
tickets
.
next
!=
lockval
.
tickets
.
owner
)
{
__WFE
();
lockval
.
tickets
.
owner
=
*
(
volatile
unsigned
short
*
)(
&
lock
->
tickets
.
owner
);
}
__DMB
();
}
void
rt_hw_spin_unlock
(
rt_hw_spinlock_t
*
lock
)
{
__DMB
();
lock
->
tickets
.
owner
++
;
__DSB
();
__SEV
();
}
#endif
/*RT_USING_SMP*/
/**
* @addtogroup ARM CPU
*/
/*@{*/
/** shutdown CPU */
void
rt_hw_cpu_shutdown
()
{
rt_uint32_t
level
;
rt_kprintf
(
"shutdown...
\n
"
);
level
=
rt_hw_interrupt_disable
();
while
(
level
)
{
RT_ASSERT
(
0
);
}
}
/*@}*/
libcpu/arm/cortex-a53/interrupt.c
已删除
100644 → 0
浏览文件 @
f6a13de0
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018/5/3 Bernard first version
* 2019-07-28 zdzn add smp support
* 2019-08-09 zhangjun fixup the problem of smp startup and scheduling issues,
* write addr to mailbox3 to startup smp, and we use mailbox0 for ipi
*/
#include <rthw.h>
#include <rtthread.h>
#include "cp15.h"
#include <board.h>
#define MAX_HANDLERS 72
#ifdef RT_USING_SMP
#define rt_interrupt_nest rt_cpu_self()->irq_nest
#else
extern
volatile
rt_uint8_t
rt_interrupt_nest
;
#endif
const
unsigned
int
VECTOR_BASE
=
0x00
;
extern
void
rt_cpu_vector_set_base
(
unsigned
int
addr
);
extern
int
system_vectors
;
void
rt_hw_vector_init
(
void
)
{
rt_cpu_vector_set_base
((
unsigned
int
)
&
system_vectors
);
}
/* exception and interrupt handler table */
struct
rt_irq_desc
isr_table
[
MAX_HANDLERS
];
rt_uint32_t
rt_interrupt_from_thread
;
rt_uint32_t
rt_interrupt_to_thread
;
rt_uint32_t
rt_thread_switch_interrupt_flag
;
extern
int
system_vectors
;
static
void
default_isr_handler
(
int
vector
,
void
*
param
)
{
#ifdef RT_USING_SMP
rt_kprintf
(
"cpu %d unhandled irq: %d
\n
"
,
rt_hw_cpu_id
(),
vector
);
#else
rt_kprintf
(
"unhandled irq: %d
\n
"
,
vector
);
#endif
}
/**
* This function will initialize hardware interrupt
*/
void
rt_hw_interrupt_init
(
void
)
{
rt_uint32_t
index
;
/* mask all of interrupts */
IRQ_DISABLE_BASIC
=
0x000000ff
;
IRQ_DISABLE1
=
0xffffffff
;
IRQ_DISABLE2
=
0xffffffff
;
for
(
index
=
0
;
index
<
MAX_HANDLERS
;
index
++
)
{
isr_table
[
index
].
handler
=
default_isr_handler
;
isr_table
[
index
].
param
=
NULL
;
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy
(
isr_table
[
index
].
name
,
"unknown"
,
RT_NAME_MAX
);
isr_table
[
index
].
counter
=
0
;
#endif
}
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest
=
0
;
rt_interrupt_from_thread
=
0
;
rt_interrupt_to_thread
=
0
;
rt_thread_switch_interrupt_flag
=
0
;
}
/**
* This function will mask a interrupt.
* @param vector the interrupt number
*/
void
rt_hw_interrupt_mask
(
int
vector
)
{
if
(
vector
<
32
)
{
IRQ_DISABLE1
=
(
1
<<
vector
);
}
else
if
(
vector
<
64
)
{
vector
=
vector
%
32
;
IRQ_DISABLE2
=
(
1
<<
vector
);
}
else
{
vector
=
vector
-
64
;
IRQ_DISABLE_BASIC
=
(
1
<<
vector
);
}
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void
rt_hw_interrupt_umask
(
int
vector
)
{
if
(
vector
<
32
)
{
IRQ_ENABLE1
=
(
1
<<
vector
);
}
else
if
(
vector
<
64
)
{
vector
=
vector
%
32
;
IRQ_ENABLE2
=
(
1
<<
vector
);
}
else
{
vector
=
vector
-
64
;
IRQ_ENABLE_BASIC
=
(
1
<<
vector
);
}
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param new_handler the interrupt service routine to be installed
* @param old_handler the old interrupt service routine
*/
rt_isr_handler_t
rt_hw_interrupt_install
(
int
vector
,
rt_isr_handler_t
handler
,
void
*
param
,
const
char
*
name
)
{
rt_isr_handler_t
old_handler
=
RT_NULL
;
if
(
vector
<
MAX_HANDLERS
)
{
old_handler
=
isr_table
[
vector
].
handler
;
if
(
handler
!=
RT_NULL
)
{
#ifdef RT_USING_INTERRUPT_INFO
rt_strncpy
(
isr_table
[
vector
].
name
,
name
,
RT_NAME_MAX
);
#endif
/* RT_USING_INTERRUPT_INFO */
isr_table
[
vector
].
handler
=
handler
;
isr_table
[
vector
].
param
=
param
;
}
}
return
old_handler
;
}
#ifdef RT_USING_SMP
void
rt_hw_ipi_send
(
int
ipi_vector
,
unsigned
int
cpu_mask
)
{
__DSB
();
if
(
cpu_mask
&
0x1
)
{
send_ipi_msg
(
0
,
ipi_vector
);
}
if
(
cpu_mask
&
0x2
)
{
send_ipi_msg
(
1
,
ipi_vector
);
}
if
(
cpu_mask
&
0x4
)
{
send_ipi_msg
(
2
,
ipi_vector
);
}
if
(
cpu_mask
&
0x8
)
{
send_ipi_msg
(
3
,
ipi_vector
);
}
__DSB
();
}
#endif
#ifdef RT_USING_SMP
void
rt_hw_ipi_handler_install
(
int
ipi_vector
,
rt_isr_handler_t
ipi_isr_handler
)
{
/* note: ipi_vector maybe different with irq_vector */
rt_hw_interrupt_install
(
ipi_vector
,
ipi_isr_handler
,
0
,
"IPI_HANDLER"
);
}
#endif
libcpu/arm/cortex-a53/interrupt.h
已删除
100644 → 0
浏览文件 @
f6a13de0
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
#include <rthw.h>
#include <board.h>
#define INT_IRQ 0x00
#define INT_FIQ 0x01
void
rt_hw_interrupt_init
(
void
);
void
rt_hw_interrupt_mask
(
int
vector
);
void
rt_hw_interrupt_umask
(
int
vector
);
rt_isr_handler_t
rt_hw_interrupt_install
(
int
vector
,
rt_isr_handler_t
handler
,
void
*
param
,
const
char
*
name
);
#endif
libcpu/arm/cortex-a53/mmu.c
已删除
100644 → 0
浏览文件 @
f6a13de0
/*
* Copyright (c) 2006-2019, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2012-01-10 bernard porting to AM1808
* 2019-07-28 zdzn add smp support
*/
#include "mmu.h"
/* dump 2nd level page table */
void
rt_hw_cpu_dump_page_table_2nd
(
rt_uint32_t
*
ptb
)
{
int
i
;
int
fcnt
=
0
;
for
(
i
=
0
;
i
<
256
;
i
++
)
{
rt_uint32_t
pte2
=
ptb
[
i
];
if
((
pte2
&
0x3
)
==
0
)
{
if
(
fcnt
==
0
)
rt_kprintf
(
" "
);
rt_kprintf
(
"%04x: "
,
i
);
fcnt
++
;
if
(
fcnt
==
16
)
{
rt_kprintf
(
"fault
\n
"
);
fcnt
=
0
;
}
continue
;
}
if
(
fcnt
!=
0
)
{
rt_kprintf
(
"fault
\n
"
);
fcnt
=
0
;
}
rt_kprintf
(
" %04x: %x: "
,
i
,
pte2
);
if
((
pte2
&
0x3
)
==
0x1
)
{
rt_kprintf
(
"L,ap:%x,xn:%d,texcb:%02x
\n
"
,
((
pte2
>>
7
)
|
(
pte2
>>
4
))
&
0xf
,
(
pte2
>>
15
)
&
0x1
,
((
pte2
>>
10
)
|
(
pte2
>>
2
))
&
0x1f
);
}
else
{
rt_kprintf
(
"S,ap:%x,xn:%d,texcb:%02x
\n
"
,
((
pte2
>>
7
)
|
(
pte2
>>
4
))
&
0xf
,
pte2
&
0x1
,
((
pte2
>>
4
)
|
(
pte2
>>
2
))
&
0x1f
);
}
}
}
void
rt_hw_cpu_dump_page_table
(
rt_uint32_t
*
ptb
)
{
int
i
;
int
fcnt
=
0
;
rt_kprintf
(
"page table@%p
\n
"
,
ptb
);
for
(
i
=
0
;
i
<
1024
*
4
;
i
++
)
{
rt_uint32_t
pte1
=
ptb
[
i
];
if
((
pte1
&
0x3
)
==
0
)
{
rt_kprintf
(
"%03x: "
,
i
);
fcnt
++
;
if
(
fcnt
==
16
)
{
rt_kprintf
(
"fault
\n
"
);
fcnt
=
0
;
}
continue
;
}
if
(
fcnt
!=
0
)
{
rt_kprintf
(
"fault
\n
"
);
fcnt
=
0
;
}
rt_kprintf
(
"%03x: %08x: "
,
i
,
pte1
);
if
((
pte1
&
0x3
)
==
0x3
)
{
rt_kprintf
(
"LPAE
\n
"
);
}
else
if
((
pte1
&
0x3
)
==
0x1
)
{
rt_kprintf
(
"pte,ns:%d,domain:%d
\n
"
,
(
pte1
>>
3
)
&
0x1
,
(
pte1
>>
5
)
&
0xf
);
/*
*rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
* - 0x80000000 + 0xC0000000));
*/
}
else
if
(
pte1
&
(
1
<<
18
))
{
rt_kprintf
(
"super section,ns:%d,ap:%x,xn:%d,texcb:%02x
\n
"
,
(
pte1
>>
19
)
&
0x1
,
((
pte1
>>
13
)
|
(
pte1
>>
10
))
&
0xf
,
(
pte1
>>
4
)
&
0x1
,
((
pte1
>>
10
)
|
(
pte1
>>
2
))
&
0x1f
);
}
else
{
rt_kprintf
(
"section,ns:%d,ap:%x,"
"xn:%d,texcb:%02x,domain:%d
\n
"
,
(
pte1
>>
19
)
&
0x1
,
((
pte1
>>
13
)
|
(
pte1
>>
10
))
&
0xf
,
(
pte1
>>
4
)
&
0x1
,
(((
pte1
&
(
0x7
<<
12
))
>>
10
)
|
((
pte1
&
0x0c
)
>>
2
))
&
0x1f
,
(
pte1
>>
5
)
&
0xf
);
}
}
}
/* level1 page table, each entry for 1MB memory. */
volatile
static
unsigned
long
MMUTable
[
4
*
1024
]
__attribute__
((
aligned
(
16
*
1024
)));
void
rt_hw_mmu_setmtt
(
rt_uint32_t
vaddrStart
,
rt_uint32_t
vaddrEnd
,
rt_uint32_t
paddrStart
,
rt_uint32_t
attr
)
{
volatile
rt_uint32_t
*
pTT
;
volatile
int
i
,
nSec
;
pTT
=
(
rt_uint32_t
*
)
MMUTable
+
(
vaddrStart
>>
20
);
nSec
=
(
vaddrEnd
>>
20
)
-
(
vaddrStart
>>
20
);
for
(
i
=
0
;
i
<=
nSec
;
i
++
)
{
*
pTT
=
attr
|
(((
paddrStart
>>
20
)
+
i
)
<<
20
);
pTT
++
;
}
}
unsigned
long
rt_hw_set_domain_register
(
unsigned
long
domain_val
)
{
unsigned
long
old_domain
;
asm
volatile
(
"mrc p15, 0, %0, c3, c0
\n
"
:
"=r"
(
old_domain
));
asm
volatile
(
"mcr p15, 0, %0, c3, c0
\n
"
:
:
"r"
(
domain_val
)
:
"memory"
);
return
old_domain
;
}
void
rt_hw_init_mmu_table
()
{
/* set page table */
/* 4G 1:1 memory */
rt_hw_mmu_setmtt
(
0x00000000
,
0x3effffff
,
0x00000000
,
NORMAL_MEM
);
/* IO memory region */
rt_hw_mmu_setmtt
(
0x3f000000
,
0x40010000
,
0x3f000000
,
DEVICE_MEM
);
}
void
rt_hw_change_mmu_table
(
rt_uint32_t
vaddrStart
,
rt_uint32_t
size
,
rt_uint32_t
paddrStart
,
rt_uint32_t
attr
)
{
rt_hw_mmu_setmtt
(
vaddrStart
,
vaddrStart
+
size
-
1
,
paddrStart
,
attr
);
#ifndef RT_USING_SMP
rt_cpu_dcache_clean_flush
();
rt_cpu_icache_flush
();
#endif
}
void
rt_hw_mmu_init
(
void
)
{
rt_cpu_dcache_clean_flush
();
rt_cpu_icache_flush
();
rt_hw_cpu_dcache_disable
();
rt_hw_cpu_icache_disable
();
rt_cpu_mmu_disable
();
/*rt_hw_cpu_dump_page_table(MMUTable);*/
rt_hw_set_domain_register
(
0x55555555
);
rt_cpu_tlb_set
(
MMUTable
);
rt_cpu_mmu_enable
();
rt_hw_cpu_icache_enable
();
rt_hw_cpu_dcache_enable
();
}
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